CN109918230A - A kind of business board abnormal restoring method and system - Google Patents
A kind of business board abnormal restoring method and system Download PDFInfo
- Publication number
- CN109918230A CN109918230A CN201910124873.6A CN201910124873A CN109918230A CN 109918230 A CN109918230 A CN 109918230A CN 201910124873 A CN201910124873 A CN 201910124873A CN 109918230 A CN109918230 A CN 109918230A
- Authority
- CN
- China
- Prior art keywords
- business board
- visited
- fpga
- master control
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The application provides a kind of business board abnormal restoring method and system.A kind of business board abnormal restoring method include: on master control board card CPU to FPGA send access request message；FPGA receives access request message, parse the PCIe bus address space address for the business board to be visited that access request message carries, according to the PCIe bus address space address of business board to be visited, access request message is issued to business board to be visited, judge whether to receive the response data that business board to be visited returns, if not, determine business board access failure to be visited, CPU reports abnormal interrupt on master control board card, and the PCIe bus address space address of business board to be visited is stored in caching；CPU reads the PCIe bus address space address of business board to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card, determines the business board to be visited being abnormal, and sends reset or instruction of restarting to FPGA.
Description
Technical field
This application involves field of communication technology more particularly to a kind of business board abnormal restoring method and systems.
Background technique
In centralized control frame type equipment, the management control of all business boards is unified to be responsible for by CPU on master control board card,
Pass through PCIe (Peripheral Component Interconnect express, high speed between business board and master control board card
Serial computer expansion bus standard) bus is attached, the high-speed transfer efficiency that PCIe bus has by it and business board
The mode that card can exclusively enjoy broadband is widely used.But with the increase and extension of centralized control frame type equipment function, master control
The CPU business board to be managed is also more and more on board, since channel link and centralized control frame type equipment itself are hard
The situation of the reason of part, business board exception happen occasionally, if business board cannot be handled timely extremely, having can
It can lead to centralized control frame type equipment delay machine.
Existing technical solution is to be handled extremely by way of soft or hard combination business board: on master control board card
CPU is by PCIe bus access business board, when the message long-term receipt that CPU is sent to business board on master control board card is less than industry
When the response of business board, CPU will judge that business board is abnormal on master control board card, at this moment by CPU internal proprietary on master control board card
Register set, subsequent applications program determine the business board being abnormal after detecting corresponding register set, will
The business board resets, and can so prevent from leading to entire centralized control frame type equipment delay machine situation extremely because of single business board
Generation.
But existing technical solution is mainly realized by the detection of CPU built-in command and register, and integrated phase is needed inside CPU
Function is answered, hardware cost can be greatly improved in this way.
Summary of the invention
In view of this, the application provides a kind of business board abnormal restoring method and system.
Specifically, the application is achieved by the following technical solution:
A kind of business board abnormal restoring method, which is characterized in that be applied to centralized control frame type equipment, the concentration control
Frame type equipment processed includes master control board card, FPGA and at least one business board, the FPGA respectively with the master control board card,
At least one described business board card is attached, which comprises
In the preparation stage: CPU is each business board point according to PCIe bus address space configuration information on master control board card
With corresponding PCIe bus address space, by the address range foundation for the PCIe bus address space distributed for each business board
Board distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, parses the business board to be visited that the access request message carries
PCIe bus address space address；
FPGA, will be under the access request message according to the PCIe bus address space address of the business board to be visited
It is sent to corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and
It will be in the PCIe bus address space address deposit caching of the business board to be visited；
CPU reads the industry to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of business board, the address with the PCIe bus address space for being in advance the distribution of each business board
Range is matched, and determines the business board to be visited being abnormal；
CPU is sent to FPGA on master control board card resets perhaps instruction of restarting so that FPGA is according to reset or instruction of restarting
Reset or reboot operation are executed to the business board to be visited being abnormal.
A kind of business board abnormal restoring system, which is characterized in that be applied to centralized control frame type equipment, the concentration control
Frame type equipment processed includes master control board card, FPGA and at least one business board, the FPGA respectively with the master control board card,
At least one described business board card is attached, the system comprises:
In the preparation stage: CPU is each business board point according to PCIe bus address space configuration information on master control board card
With corresponding PCIe bus address space, by the address range foundation for the PCIe bus address space distributed for each business board
Board distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, parses the business board to be visited that the access request message carries
PCIe bus address space address；
FPGA, will be under the access request message according to the PCIe bus address space address of the business board to be visited
It is sent to corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and
It will be in the PCIe bus address space address deposit caching of the business board to be visited；
CPU reads the industry to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of business board, the address with the PCIe bus address space for being in advance the distribution of each business board
Range is matched, and determines the business board to be visited being abnormal；
CPU is sent to FPGA on master control board card resets perhaps instruction of restarting so that FPGA is according to reset or instruction of restarting
Reset or reboot operation are executed to the business board to be visited being abnormal.
Using technical solution provided by the present application, without being realized by the detection of CPU built-in command and register, without in CPU
Portion integrates corresponding function, greatly reduces hardware cost.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to required attached in embodiment description
Figure is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments as described in this application, for
For those of ordinary skill in the art, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the hardware connection diagram shown in one exemplary embodiment of the application；
Fig. 2 is another hardware connection diagram shown in one exemplary embodiment of the application；
Fig. 3 is the interaction flow schematic diagram of the business board abnormal restoring method shown in one exemplary embodiment of the application；
Fig. 4 is the board distributed topology figure shown in one exemplary embodiment of the application.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they are only and the application
The consistent device and method of some aspects example.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not departing from
In the case where the application range, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determination ".
A kind of business board abnormal restoring method provided by the embodiments of the present application is illustrated first, is applied to concentrate control
Frame type equipment processed, the centralized control frame type equipment include master control board card, FPGA and at least one business board, described
FPGA is attached with the master control board card, at least one described business board card, and this method specifically includes that
Preparation stage: CPU is the distribution of each business board according to PCIe bus address space configuration information on master control board card
Corresponding PCIe bus address space, by the address range for the PCIe bus address space distributed for each business board according to plate
Card distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, parses the business board to be visited that the access request message carries
PCIe bus address space address；
FPGA, will be under the access request message according to the PCIe bus address space address of the business board to be visited
It is sent to corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and
It will be in the PCIe bus address space address deposit caching of the business board to be visited；
CPU reads the industry to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of business board, the address with the PCIe bus address space for being in advance the distribution of each business board
Range is matched, and determines the business board to be visited being abnormal；
CPU is sent to FPGA on master control board card resets perhaps instruction of restarting so that FPGA is according to reset or instruction of restarting
Reset or reboot operation are executed to the business board to be visited being abnormal.
An example hardware connection schematic diagram stated in the background, as shown in Figure 1, CPU passes through on master control board card
PCIe bus access business board, when the message long-term receipt that CPU is sent to business board on master control board card is less than business board
Response when, CPU will judge that business board is abnormal on master control board card, at this moment by the register of CPU internal proprietary on master control board card
Set, subsequent applications program determine the business board being abnormal, by the business after detecting corresponding register set
Board resets, and can so prevent the hair for leading to entire centralized control frame type equipment delay machine situation extremely because of single business board
It is raw.Although the occurrence of leading to entire centralized control frame type equipment delay machine extremely because of single business board so can be prevented,
But mainly realized at present by the detection of CPU built-in command and register, integrated corresponding function is needed inside CPU, it in this way can be significantly
Improve hardware cost.
The embodiment of the present application provides a kind of technical solution, example hardware connection schematic diagram as shown in Figure 2, FPGA thus
It is attached respectively with CPU, business board on master control borad, in the case where FPGA is determined and is accessed business board card crash to be visited,
In the PCIe bus address space address deposit of corresponding business board to be visited being cached (in memory as shown in Figure 2),
And CPU reports abnormal interrupt on master control borad, CPU is postponed after receiving the abnormal interrupt that FPGA is reported on master control board card
The middle PCIe bus address space address for reading business board to be visited is deposited, it is total with the PCIe in advance for the distribution of each business board
The address range of line address space is matched, and determines the business board to be visited that is abnormal, on subsequent master control board card CPU to
FPGA send reset perhaps instruction of restarting so that FPGA according to reset or instruction of restarting to the business board to be visited being abnormal
Card executes reset or reboot operation.In this way, can equally be prevented using technical solution provided by the present application because of single industry
Business board the occurrence of leading to entire centralized control frame type equipment delay machine extremely, and without by the detection of CPU built-in command and
Register is realized, is internally integrated corresponding function without CPU, is greatly reduced hardware cost.In order to be further illustrated to the application,
The following example is provided:
As shown in figure 3, being a kind of interaction flow schematic diagram of the embodiment of the present application business board abnormal restoring method, the party
Method may comprise steps of:
In the preparation stage:
S301, CPU is that the distribution of each business board corresponds to according to PCIe bus address space configuration information on master control board card
PCIe bus address space, by the address range of the PCIe bus address space distributed for each business board according to board point
Cloth topological diagram is stored；
In this application, CPU is that each business board distributes corresponding PCIe bus address space in advance on master control board card,
And store the address range for the PCIe bus address space distributed for each business board according to board distributed topology figure,
The corresponding relationship of storage service board and PCIe bus address space is distinguished on master control borad and FPGA, the board distribution is opened up
Figure is flutterred as shown in figure 4, being similar to device tree, it is meant that by the address for the PCIe bus address space distributed for each business board
Range is stored according to tree structure.
Wherein, on master control board card CPU previously according to PCIe bus address space configuration information be each business board distribute
Corresponding PCIe bus address space, the PCIe bus address space configuration information are that the PCIe according to needed for each business board is total
Line address space obtains.Such as CPU is business board previously according to PCIe bus address space configuration information on master control board card
1 distribution 6MPCIe bus address space, distributes 5MPCIe bus address space for business board 2, distributes for business board 3
10MPCIe bus address space ..., by the address range foundation for the PCIe bus address space distributed for each business board
Board distributed topology figure is stored.
Preferably, after distributing corresponding PCIe bus address space for each business board, CPU can on master control board card
To scan corresponding PCIe device on each business board of centralized control frame type equipment using recursive fashion, and according to the original of depth-first
Then, the PCIe bus address space for being based upon each business board distribution is that the PCIe device scanned distributes corresponding PCIe bus
Address space, and the address information of the PCIe bus address space of distribution is stored.For example, being distributed for business board 1
6MPCIe bus address space, CPU can scan each business board of centralized control frame type equipment using recursive fashion on master control board card
Corresponding PCIe device on card, and according to the principle of depth-first, the 6MPCIe bus address for being based upon the distribution of business board 1 is empty
Between, corresponding 2MPCIe bus address space is distributed for the PCIe device 1 that scans, and by the PCIe bus address space of distribution
Address information is stored.
In addition, CPU opens up a certain size space, such as the memory headroom of 4byte in the buffer in advance on master control board card,
Dedicated for the write-back of the PCIe bus address space address of business board to be visited, and the first address of this section of spatial cache is deposited
Enter in FPGA register, such as FPGA special register SMB Cache Addr, in order to which CPU is read on master control board card.
In processing stage:
S302, CPU sends access request message to FPGA on master control board card；
When CPU accesses business board on master control board card or on business board when some PCIe device, sent out to FPGA
Access request message is sent, so that the access request message is issued to some on corresponding business board or business board by FPGA
PCIe device.
S303, FPGA receive the access request message, parse the business board to be visited that the access request message carries
The PCIe bus address space address of card；
S304, FPGA are according to the PCIe bus address space address of the business board to be visited, by the access request
Message is issued to corresponding business board to be visited；
FPGA receives the access request message that CPU is issued on master control borad, parses the business board to be visited of its carrying
PCIe bus address space address, such as CPU will access business board 1 on master control borad, then parse and take in access request message
The 1 corresponding PCIe bus address space address of business board of band.FPGA can be corresponding according to the business board to be visited
The corresponding relationship for the business board and PCIe bus address space being locally stored is inquired, by this in PCIe bus address space address
Access request message is issued to corresponding business board to be visited, such as the access request message is issued to business board 1.
S305, FPGA judge whether to receive the response data that business board to be visited returns；
Timer is set inside FPGA, after which is issued to corresponding business board to be visited, is sentenced
The disconnected response data for whether receiving business board to be visited within a preset time period and returning, if within a preset time period not
Receive the response data that business board to be visited returns, it is determined that access business board card crash to be visited, otherwise real-time reception
The response data that business board to be visited returns.
S306, if it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU is reported in exception on master control board card
It is disconnected, and will be in the PCIe bus address space address of the business board to be visited deposit caching；
If not receiving the response data that business board to be visited returns, it is determined that business board card crash to be visited is accessed,
Preferably, if not receiving the response data that business board to be visited returns within a preset time period, FPGA is according to default
Access request message transmission times, the access request message is constantly issued to corresponding business board, if FPGA is according to pre-
If access request message transmission times, during the access request message is constantly issued to corresponding business board, according to
The response data of business board to be visited is not received so, it is determined that access business board card crash to be visited.
For example, if not receiving the response data that business board to be visited returns within a preset time period, FPGA root
According to preset access request message transmission times (5 times), the access request message is constantly issued to corresponding business board, often
It sends and once judges whether to receive the response data that business board to be visited returns, if the access request message is continuous
During being issued to corresponding business board, the response data of business board to be visited is not received still, it is determined that access wait visit
Ask business board card crash.
In the case where determining access business board card crash to be visited, FPGA, which stops sending to business board to be visited, to be accessed
Request message, CPU reports abnormal interrupt on master control board card, and by the PCIe bus address space of the business board to be visited
In the caching that address deposit is opened up in advance.
Preferably, CPU is abnormal because business board time-out to be visited is accessed on master control board card in order to prevent, and FPGA is true
Surely in the case where accessing business board card crash to be visited, CPU on master control board card is back to from group null response data.
S307, CPU is read described wait visit after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of asking business board, with the PCIe bus address space for being in advance the distribution of each business board
Address range is matched, and determines the business board to be visited being abnormal；
CPU reads business board to be visited in caching after receiving the abnormal interrupt that FPGA is reported on master control board card
PCIe bus address space address, in advance for each business board distribution PCIe bus address space address range into
Row matching, can determine the business board to be visited being abnormal, can further determine and send out on business board to be visited
Raw abnormal PCIe device.
CPU stops in the case where determining the business board to be visited being abnormal to business to be visited on master control board card
The access of board.
S308, CPU is sent to FPGA on master control board card resets perhaps instruction of restarting so that FPGA is according to resetting or restart
It instructs and reset or reboot operation is executed to the business board to be visited being abnormal.
CPU is in the case where determining the business board to be visited being abnormal on master control board card, to being abnormal wait visit
Ask that business board executes and reset perhaps that reboot operation is specifically: CPU is sent to FPGA on master control board card resets or restarts finger
It enabling, FPGA executes reset or reboot operation to the business board to be visited being abnormal according to reset or instruction of restarting, after
CPU sends initialization directive to FPGA on continuous master control board card, and FPGA is according to initialization directive to the business to be visited being abnormal
Board executes initialization operation.
By the description above to technical solution provided by the present application, is determined in FPGA and access business board card crash to be visited
In the case where, it can be by the PCIe bus address space address deposit caching of corresponding business board to be visited, and to master control borad
Upper CPU reports abnormal interrupt, on master control board card CPU after receiving the abnormal interrupt that FPGA is reported, from caching read to
The PCIe bus address space address of access business board, in advance be each business board distribution PCIe bus address space
Address range matched, determine the business board to be visited that is abnormal, CPU is sent multiple to FPGA on subsequent master control board card
Position perhaps instruction of restarting so that FPGA according to reset or instruction of restarting reset is executed to the business board to be visited being abnormal
Or reboot operation.In this way, can equally be prevented using technical solution provided by the present application because single business board is abnormal
The occurrence of leading to entire centralized control frame type equipment delay machine, and without being realized by the detection of CPU built-in command and register,
It is internally integrated corresponding function without CPU, greatly reduces hardware cost.
In addition, CPU can again visit business board card to be visited on master control board card after by above-mentioned steps
It asks, if the business board to be visited after resetting or restarting still remains problem, to the business board to be visited being abnormal
Reset or reboot operation are executed, if problem cannot still solve, CPU executes business board card to be visited on master control board card
Power operation (specifically sends cut-offing instruction to FPGA, FPGA executes power-off to business board card to be visited according to the cut-offing instruction
Operation), prompt maintenance personal to handle.
Corresponding with the embodiment of above-mentioned business board abnormal restoring method, present invention also provides business board is extremely extensive
The embodiment of complex system, be applied to centralized control frame type equipment, the centralized control frame type equipment include master control board card, FPGA,
And at least one business board, the FPGA are attached with the master control board card, at least one described business board card respectively,
The system comprises:
In the preparation stage: CPU is each business board point according to PCIe bus address space configuration information on master control board card
With corresponding PCIe bus address space, by the address range foundation for the PCIe bus address space distributed for each business board
Board distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, parses the business board to be visited that the access request message carries
PCIe bus address space address；
FPGA, will be under the access request message according to the PCIe bus address space address of the business board to be visited
It is sent to corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and
It will be in the PCIe bus address space address deposit caching of the business board to be visited；
CPU reads the industry to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of business board, the address with the PCIe bus address space for being in advance the distribution of each business board
Range is matched, and determines the business board to be visited being abnormal；
CPU is sent to FPGA on master control board card resets perhaps instruction of restarting so that FPGA is according to reset or instruction of restarting
Reset or reboot operation are executed to the business board to be visited being abnormal.
Above system realizes that process is specifically detailed in the realization process that step is corresponded in the above method, and details are not described herein.
By the above-mentioned description to technical solution provided by the embodiments of the present application, is determined in FPGA and access business board to be visited
In the case where card crash, the PCIe bus address space address of corresponding business board to be visited can be stored in caching, and to
CPU reports abnormal interrupt on master control borad, and CPU is after receiving the abnormal interrupt that FPGA is reported on master control board card, from caching
The PCIe bus address space address of reading business board to be visited, and is in advance the PCIe bus of each business board distribution
The address range in location space is matched, and determines the business board to be visited that is abnormal, and CPU is to FPGA on subsequent master control board card
It sends and resets perhaps instruction of restarting so that FPGA holds the business board to be visited being abnormal according to reset or instruction of restarting
Row resets or reboot operation.In this way, can equally be prevented using technical solution provided by the present application because of single business board
The occurrence of card exception leads to entire centralized control frame type equipment delay machine, and without being detected and being deposited by CPU built-in command
Device is realized, is internally integrated corresponding function without CPU, is greatly reduced hardware cost.
For system embodiments, since it corresponds essentially to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.System embodiment described above is only schematical, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize application scheme.Those of ordinary skill in the art are not paying
Out in the case where creative work, it can understand and implement.
The present invention can be in the general described in the text, such as program up and down of calculated value executable instruction performed by computer
Module.Generally, program module includes routines performing specific tasks or implementing specific abstract data types, programs, objects, group
Part, data structure etc..The present invention can also be practiced in a distributed computing environment, in these distributed computing environments, by
Task is executed by the connected remote processing devices of communication network.In a distributed computing environment, program module can be with
In the local and remote computer storage media including storage equipment.
The above is only a specific embodiment of the invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of business board abnormal restoring method, which is characterized in that be applied to centralized control frame type equipment, the centralized control
Frame type equipment includes master control board card, FPGA and at least one business board, the FPGA respectively with the master control board card, institute
At least one business board card is stated to be attached, which comprises
In the preparation stage: CPU is the distribution pair of each business board according to PCIe bus address space configuration information on master control board card
The PCIe bus address space answered, by the address range for the PCIe bus address space distributed for each business board according to board
Distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, and the PCIe for parsing the business board to be visited that the access request message carries is total
Line address space address；
The access request message is issued to by FPGA according to the PCIe bus address space address of the business board to be visited
Corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and by institute
It states in the PCIe bus address space address deposit caching of business board to be visited；
CPU reads the business board to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of card, with the address range for being in advance the PCIe bus address space that each business board distributes
It is matched, determines the business board to be visited being abnormal；
On master control board card CPU to FPGA send reset perhaps instruction of restarting so that FPGA according to reset or instruction of restarting to hair
Raw abnormal business board to be visited executes reset or reboot operation.
2. the method according to claim 1, wherein the FPGA judges whether to receive business board to be visited
The response data of return, comprising:
Whether FPGA judgement receives the response data that business board to be visited returns within a preset time period.
3. according to the method described in claim 2, it is characterized in that, described if it is not, FPGA, which is then determined, accesses business board to be visited
Card crash, comprising:
If not receiving the response data that business board to be visited returns within a preset time period, FPGA is according to preset visit
It asks request message transmission times, the access request message is constantly issued to corresponding business board；
If the access request message is constantly being issued to corresponding industry according to preset access request message transmission times by FPGA
It is engaged in not receiving the response data of business board to be visited still during board, it is determined that access business board to be visited and lose
It loses.
4. the method according to claim 1, wherein the method also includes:
CPU stops in the case where determining the business board to be visited being abnormal to business board card to be visited on master control board card
Access.
5. method according to any one of claims 1 to 4, which is characterized in that the method also includes:
FPGA is back on master control board card in the case where determining access business board card crash to be visited from group null response data
CPU, so that CPU will not be abnormal because of access time-out on master control board card.
6. a kind of business board abnormal restoring system, which is characterized in that be applied to centralized control frame type equipment, the centralized control
Frame type equipment includes master control board card, FPGA and at least one business board, the FPGA respectively with the master control board card, institute
At least one business board card is stated to be attached, the system comprises:
In the preparation stage: CPU is the distribution pair of each business board according to PCIe bus address space configuration information on master control board card
The PCIe bus address space answered, by the address range for the PCIe bus address space distributed for each business board according to board
Distributed topology figure is stored；
In processing stage: CPU sends access request message to FPGA on master control board card；
FPGA receives the access request message, and the PCIe for parsing the business board to be visited that the access request message carries is total
Line address space address；
The access request message is issued to by FPGA according to the PCIe bus address space address of the business board to be visited
Corresponding business board to be visited；
FPGA judges whether to receive the response data that business board to be visited returns；
If it is not, FPGA, which is then determined, accesses business board card crash to be visited, CPU reports abnormal interrupt on master control board card, and by institute
It states in the PCIe bus address space address deposit caching of business board to be visited；
CPU reads the business board to be visited after receiving the abnormal interrupt that FPGA is reported from caching on master control board card
The PCIe bus address space address of card, with the address range for being in advance the PCIe bus address space that each business board distributes
It is matched, determines the business board to be visited being abnormal；
On master control board card CPU to FPGA send reset perhaps instruction of restarting so that FPGA according to reset or instruction of restarting to hair
Raw abnormal business board to be visited executes reset or reboot operation.
7. system according to claim 6, which is characterized in that described to state FPGA and judge whether to connect especially by following manner
Receive the response data that business board to be visited returns:
Whether FPGA judgement receives the response data that business board to be visited returns within a preset time period.
8. system according to claim 7, which is characterized in that the FPGA is accessed especially by following manner determination wait visit
Ask business board card crash:
If not receiving the response data that business board to be visited returns within a preset time period, FPGA is according to preset visit
It asks request message transmission times, the access request message is constantly issued to corresponding business board；
If the access request message is constantly being issued to corresponding industry according to preset access request message transmission times by FPGA
It is engaged in not receiving the response data of business board to be visited still during board, it is determined that access business board to be visited and lose
It loses.
9. system according to claim 6, which is characterized in that the system also includes:
CPU stops in the case where determining the business board to be visited being abnormal to business board card to be visited on master control board card
Access.
10. according to the described in any item systems of claim 6 to 9, which is characterized in that the system also includes:
FPGA is back on master control board card in the case where determining access business board card crash to be visited from group null response data
CPU, so that CPU will not be abnormal because of access time-out on master control board card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910124873.6A CN109918230B (en) | 2019-02-20 | 2019-02-20 | Method and system for recovering abnormity of service board card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910124873.6A CN109918230B (en) | 2019-02-20 | 2019-02-20 | Method and system for recovering abnormity of service board card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109918230A true CN109918230A (en) | 2019-06-21 |
| CN109918230B CN109918230B (en) | 2021-01-26 |
Family
ID=66961802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910124873.6A Active CN109918230B (en) | 2019-02-20 | 2019-02-20 | Method and system for recovering abnormity of service board card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109918230B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110519098A (en) * | 2019-08-30 | 2019-11-29 | 新华三信息安全技术有限公司 | A kind of processing method and processing device of abnormal single-board |
| CN111338700A (en) * | 2020-02-24 | 2020-06-26 | 杭州迪普科技股份有限公司 | Method and device for loading FPGA version and storage medium |
| CN111682991A (en) * | 2020-05-28 | 2020-09-18 | 杭州迪普科技股份有限公司 | Bus error message processing method and device |
| CN111885431A (en) * | 2020-08-03 | 2020-11-03 | 北京环境特性研究所 | Communication control method and device |
| CN113836058A (en) * | 2021-09-13 | 2021-12-24 | 南京南瑞继保电气有限公司 | Method, device, equipment and storage medium for data exchange between board cards |
| CN114356622A (en) * | 2021-12-10 | 2022-04-15 | 国电南瑞科技股份有限公司 | Abnormal chain breaking self-recovery method and system for PCIe bus of power secondary equipment |
| CN116841358A (en) * | 2023-06-09 | 2023-10-03 | 启朔(深圳)科技有限公司 | Server refreshing method, refreshing structure, system, computer equipment and medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467420A (en) * | 2010-11-15 | 2012-05-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for storing and restoring configuration information of external board card |
| CN103513994A (en) * | 2012-06-19 | 2014-01-15 | 记忆科技(深圳)有限公司 | Method and system for carrying out FPGA on-line upgrading through PCIE |
| WO2014059617A1 (en) * | 2012-10-17 | 2014-04-24 | 华为技术有限公司 | Port configuration method and device for high-speed peripheral component interconnect express |
| US20160092328A1 (en) * | 2014-09-30 | 2016-03-31 | Neosem Inc. | Memory device test apparatus and method |
| CN105991481A (en) * | 2015-05-19 | 2016-10-05 | 杭州迪普科技有限公司 | Message forwarding method and message forwarding apparatus |
| CN107632865A (en) * | 2017-10-24 | 2018-01-26 | 新华三技术有限公司 | A kind of FPGA configuration upgrade methods and device |
| CN108874441A (en) * | 2018-06-20 | 2018-11-23 | 上海思源弘瑞自动化有限公司 | A kind of board configuration method, device, server and storage medium |
| US20180349310A1 (en) * | 2017-05-31 | 2018-12-06 | Hewlett Packard Enterprise Development Lp | HOT PLUGGING PERIPHERAL CONNECTED INTERFACE EXPRESS (PCIe) CARDS |
| CN109286537A (en) * | 2018-10-23 | 2019-01-29 | 智强通达科技（北京）有限公司 | A kind of board management system and management method for frame multi-service board |
-
2019
- 2019-02-20 CN CN201910124873.6A patent/CN109918230B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467420A (en) * | 2010-11-15 | 2012-05-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for storing and restoring configuration information of external board card |
| CN103513994A (en) * | 2012-06-19 | 2014-01-15 | 记忆科技(深圳)有限公司 | Method and system for carrying out FPGA on-line upgrading through PCIE |
| WO2014059617A1 (en) * | 2012-10-17 | 2014-04-24 | 华为技术有限公司 | Port configuration method and device for high-speed peripheral component interconnect express |
| US20160092328A1 (en) * | 2014-09-30 | 2016-03-31 | Neosem Inc. | Memory device test apparatus and method |
| CN105991481A (en) * | 2015-05-19 | 2016-10-05 | 杭州迪普科技有限公司 | Message forwarding method and message forwarding apparatus |
| US20180349310A1 (en) * | 2017-05-31 | 2018-12-06 | Hewlett Packard Enterprise Development Lp | HOT PLUGGING PERIPHERAL CONNECTED INTERFACE EXPRESS (PCIe) CARDS |
| CN107632865A (en) * | 2017-10-24 | 2018-01-26 | 新华三技术有限公司 | A kind of FPGA configuration upgrade methods and device |
| CN108874441A (en) * | 2018-06-20 | 2018-11-23 | 上海思源弘瑞自动化有限公司 | A kind of board configuration method, device, server and storage medium |
| CN109286537A (en) * | 2018-10-23 | 2019-01-29 | 智强通达科技（北京）有限公司 | A kind of board management system and management method for frame multi-service board |
Non-Patent Citations (1)
| Title |
|---|
| 陈冉: "基于RTDS的配电网分布式测试系统设计", 《计算机科学与探索》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110519098A (en) * | 2019-08-30 | 2019-11-29 | 新华三信息安全技术有限公司 | A kind of processing method and processing device of abnormal single-board |
| CN110519098B (en) * | 2019-08-30 | 2022-06-21 | 新华三信息安全技术有限公司 | Method and device for processing abnormal single board |
| CN111338700A (en) * | 2020-02-24 | 2020-06-26 | 杭州迪普科技股份有限公司 | Method and device for loading FPGA version and storage medium |
| CN111338700B (en) * | 2020-02-24 | 2022-11-25 | 杭州迪普科技股份有限公司 | Method and device for loading FPGA version and storage medium |
| CN111682991A (en) * | 2020-05-28 | 2020-09-18 | 杭州迪普科技股份有限公司 | Bus error message processing method and device |
| CN111682991B (en) * | 2020-05-28 | 2022-08-12 | 杭州迪普科技股份有限公司 | Bus error message processing method and device |
| CN111885431A (en) * | 2020-08-03 | 2020-11-03 | 北京环境特性研究所 | Communication control method and device |
| CN113836058A (en) * | 2021-09-13 | 2021-12-24 | 南京南瑞继保电气有限公司 | Method, device, equipment and storage medium for data exchange between board cards |
| CN114356622A (en) * | 2021-12-10 | 2022-04-15 | 国电南瑞科技股份有限公司 | Abnormal chain breaking self-recovery method and system for PCIe bus of power secondary equipment |
| CN114356622B (en) * | 2021-12-10 | 2024-05-24 | 国电南瑞科技股份有限公司 | Power secondary device PCIe bus abnormal broken link self-recovery method and system |
| CN116841358A (en) * | 2023-06-09 | 2023-10-03 | 启朔(深圳)科技有限公司 | Server refreshing method, refreshing structure, system, computer equipment and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109918230B (en) | 2021-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109918230A (en) | A kind of business board abnormal restoring method and system | |
| US7028218B2 (en) | Redundant multi-processor and logical processor configuration for a file server | |
| CN103199972B (en) | The two-node cluster hot backup changing method realized based on SOA, RS485 bus and hot backup system | |
| CN1648842B (en) | Storage systems and data access method of the storage system | |
| US5121486A (en) | Network control system for dynamically switching a logical connection between an identified terminal device and an indicated processing unit | |
| US5784617A (en) | Resource-capability-based method and system for handling service processor requests | |
| US6505241B2 (en) | Network intermediate node cache serving as proxy to client node to request missing data from server | |
| DE69907776T2 (en) | Method and device for identifying vulnerable components in a system with redundant components | |
| WO2006019512B1 (en) | Apparatus and method for supporting connection establishment in an offload of network protocol processing | |
| CN105610972A (en) | Clustered task dispatching system | |
| JP2000259502A (en) | Method and device for transferring write cache data for data storage and data processing system | |
| US8612973B2 (en) | Method and system for handling interrupts within computer system during hardware resource migration | |
| KR20000005691A (en) | Performance enhancements for threaded servers | |
| CN107682460A (en) | A kind of distributed storage trunked data communication method and system | |
| US7043603B2 (en) | Storage device control unit and method of controlling the same | |
| CN109684257B (en) | Remote memory expansion management system | |
| US20090089787A1 (en) | Method and System for Migrating Critical Resources Within Computer Systems | |
| US7853713B2 (en) | Communication interface device and communication method | |
| US7302607B2 (en) | Two node virtual shared disk cluster recovery | |
| CN109445984A (en) | A kind of service restoration method, device, arbitrating server and storage system | |
| US7137029B2 (en) | Information processor | |
| JPH0675887A (en) | Polling interval determining system | |
| US20090019259A1 (en) | Multiprocessing method and multiprocessor system | |
| US20050022056A1 (en) | Access by distributed computers to a same hardware resource | |
| KR100771915B1 (en) | Digital protection relay and communication duplex method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |