WO2014048349A1 - 一种传输数据的方法和设备 - Google Patents

一种传输数据的方法和设备 Download PDF

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Publication number
WO2014048349A1
WO2014048349A1 PCT/CN2013/084355 CN2013084355W WO2014048349A1 WO 2014048349 A1 WO2014048349 A1 WO 2014048349A1 CN 2013084355 W CN2013084355 W CN 2013084355W WO 2014048349 A1 WO2014048349 A1 WO 2014048349A1
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WIPO (PCT)
Prior art keywords
data
channel
transmission
arbitration unit
arbitration
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PCT/CN2013/084355
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English (en)
French (fr)
Inventor
廖洲
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中兴通讯股份有限公司
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to US14/431,445 priority Critical patent/US9697153B2/en
Priority to EP13841870.2A priority patent/EP2902914B1/en
Publication of WO2014048349A1 publication Critical patent/WO2014048349A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot

Definitions

  • the present invention relates to the field of data transmission, and in particular, to a method and device for transmitting data. Background technique
  • the arbitration unit implements arbitration for each DMA (Direct Memory Access) channel by round-robin.
  • the first hardware module sends a DMA request including the transmission data information to the DMA arbitration unit through the first channel of the DMA (for example, transmitting the data of the address A to the address B, the data volume is 90 megabytes)
  • the second hardware module sends a DMA request including the transmission data information to the DMA arbitration unit through the second channel of the DMA (for example, transmitting the data of the address C to the address D, the data amount is 100 megabytes).
  • the DMA arbitration unit uses the polling from top to bottom in real time, starting polling from the first channel, determining the data corresponding to the first channel, and transmitting the corresponding channel to the bus command generator.
  • the data command when polling the second channel, determines to transmit the data corresponding to the second channel, and sends a command for transmitting the data corresponding to the second channel to the bus command generator, when polling the fifth channel, if the CPU (Central Processing Unit)
  • the DMA request containing the transmission data information is transmitted to the DMA arbitration unit through the third channel of the DMA, and the arbitration unit does not immediately respond to the CPU DMA request, but in the next round of polling, the DMA arbitration.
  • the unit polls the third channel, it sends a command to transmit the data of the third channel to the bus command generator.
  • the bus command generator After receiving the command for transmitting the data of the first channel from the arbitration unit of the DMA (the arbitration unit of the DMA transmits the command for transmitting the data of the first channel to the bus command generator for the first time), the bus command generator determines the source address and the destination. Address and the size of the data corresponding to the first channel to be transmitted (for the first channel, address A is the source address, and address B is The destination address) is cached in the bus command queue. After receiving the transfer data command from the bus command queue, the bus controller sends a data acquisition command to the data path unit to indicate the data path unit. The data corresponding to the data identifier is obtained from the source address, and after receiving the data from the data path unit, the acquired data is written into the destination address, where the bus command queue is a FIFO (first in first out) data buffer.
  • FIFO first in first out
  • the data transmission rate corresponding to the first channel, the second channel, and the third channel is relatively small.
  • the bus jam occurs, so when other hardware modules pass the fourth channel.
  • the DMA arbitration unit suspends the processing of the DMA request, resulting in relatively low data transmission efficiency and poor DMA performance.
  • the current DMA arbitration unit implements arbitration for each DMA channel by round-robin (polling).
  • the method of transmitting data according to the arbitration result results in relatively low data transmission efficiency and poor DMA performance.
  • the method and device for transmitting data provided by the embodiment of the present invention are used to solve the problem that the arbitrating of each DMA channel is implemented by the round-robin method in the prior art, and the data is transmitted according to the arbitration result.
  • the transmission efficiency is relatively low, and the DMA performance is relatively poor.
  • the data is transmitted according to the priorities of the at least two arbitration units.
  • An apparatus for transmitting data includes: Determining a module, configured to target a direct memory access DMA channel, and determining an arbitration unit corresponding to the channel from the plurality of arbitration units according to the transmission performance corresponding to the data of the channel;
  • the processing module is configured to determine, when the data corresponding to the at least two arbitration units has data to be transmitted, determine the data to be transmitted according to the priorities of the at least two arbitration units.
  • a plurality of arbitration units are used, and for a direct memory access DMA channel, the arbitration unit corresponding to the channel is determined from the plurality of arbitration units according to the transmission performance corresponding to the data of the channel;
  • the data is transmitted according to the priority of the at least two arbitration units.
  • the transmission performance corresponding to the data of the channel is better for one channel, and the data corresponding to the channel is transmitted earlier. Therefore, the data corresponding to the channel with good transmission performance corresponding to the data of the channel is transmitted first, and the application of the priority level keeps the bus unblocked, thereby improving the efficiency of data transmission and the performance of DMA.
  • Figure 1 is an arbitration structure in the prior art
  • FIG. 2 is a schematic flowchart of a method for transmitting data according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a detailed method for transmitting data according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present invention. detailed description
  • a plurality of arbitration units are used, and for a direct memory access DMA channel, an arbitration unit corresponding to the channel is determined from a plurality of arbitration units according to a transmission performance corresponding to the data of the channel; and at least two arbitration units are determined.
  • the data is transmitted according to the priority of the at least two arbitration units. Since the transmission performance corresponding to the data of the channel is better for one channel, the data corresponding to the channel is transmitted earlier, thereby achieving the first transmission. The data corresponding to the channel with good performance is transmitted. Through this priority application, the bus is kept clear, thereby improving the efficiency of data transmission and the performance of DMA.
  • the method for transmitting data in the embodiment of the present invention includes the following steps:
  • Step 201 Determine, according to a transmission performance corresponding to the data of the channel, a arbitration unit corresponding to the channel according to a direct memory access DMA channel;
  • Step 202 When it is determined that the channels corresponding to the at least two arbitration units have data to be transmitted, the data is transmitted according to the priorities of the at least two arbitration units.
  • step 201 for a direct memory access DMA channel, before transmitting the data corresponding to the channel, the method further includes:
  • the hardware module sends a DMA request to the arbitration unit through the channel to request data transmission.
  • the hardware module can be any hardware module involved in data transmission, such as CPU, RAM, etc. As for the specific hardware module, it can be configured as needed.
  • each hardware module sends a DMA request to the arbitration unit 1 through its corresponding channel, requesting data transmission;
  • the first hardware module can send a DMA request to the arbitration unit 1 through any multiple channels, for example, sending a DMA request to the arbitration unit 1 through the first channel, and sending a DMA request to the arbitration unit 1 through the first channel and the second channel. .
  • the first hardware module, the second hardware module, the third hardware module, the fourth hardware module, and the fifth hardware module are used to send a DMA request to the arbitration unit 1 as an example.
  • the first A hardware module, a second hardware module, a third hardware module, a fourth hardware module, and a fifth hardware module may also send a DMA request to other arbitration units, and specifically to which arbitration unit to send a DMA request may be set as needed.
  • the arbitration unit may determine, by a fixed priority or a round-robin manner, which channel corresponds to the data, and send an instruction for transmitting data corresponding to the channel, wherein the arbitration unit determines the transmission by a fixed priority or a round-robin manner.
  • the arbitration unit determines which channel corresponds to the data transmitted by the round-robin method. Referring to the background art of the present invention, the arbitration unit determines the channel corresponding to the data transmitted by the fixed priority method. : ⁇ wiki.cnki.com.cn/HotWord/237347 l.htm.
  • the arbitration unit sends an instruction for transmitting the data corresponding to the channel to the bus command generator corresponding to the arbitration unit.
  • the arbitration unit 1 if the arbitration unit 1 receives the DMA request from the first hardware module and the second hardware module within the set time, the arbitration unit 1 first determines that the first channel has data to transmit by polling. Determining that the data corresponding to the first channel is transmitted first, and transmitting an instruction for transmitting data corresponding to the first channel to the bus command generator 1; the arbitration unit 1 continues to poll, determining that the second channel has data to be transmitted, and the bus command generator 1 transmitting an instruction for transmitting data corresponding to the second channel; the arbitration unit 1 continues to poll, determining that the third channel has no data to transmit, the fifth hardware module sends a DMA request to the arbitration unit 1 through the fifth channel, and the arbitration unit 1 does not Immediately processing the DMA request from the fifth hardware module, but continuing to poll, determining that the fourth channel has no data to transmit, continuing to poll, determining that the fifth channel has data to transmit, and transmitting the transmission to the bus command generator 1. Five channels of data corresponding to the instructions.
  • the channel that has obtained the arbitration is marked, and the arbitration unit is instructed to determine whether the channel has been arbitrated according to the mark.
  • the channel that obtains the arbitration of different times may be marked differently, and the arbitration unit is instructed to The tag determines how many arbitrations have been made to the channel.
  • the flag may be any flag that the arbitration unit is capable of determining whether the channel has been arbitrated based on the flag and/or the arbitration unit is capable of determining how many times the channel has been arbitrated based on the tag, such as a digital tag or a letter tag.
  • the source address corresponding to the channel is determined according to the received instruction from the arbitration unit, The destination address corresponding to the channel and the data identifier corresponding to the channel.
  • the bus command generator corresponding to the arbitration unit may receive an instruction from the arbitration unit.
  • the data corresponding to the data identifier may be a part of data in the data requested for transmission in the DMA request.
  • the arbitration unit 1 if the arbitration unit 1 receives the DMA request from the first hardware module and the second hardware module within the set time, the arbitration unit 1 first determines that the first channel has data to transmit by polling. Determining that the data corresponding to the first channel is transmitted first, and the instruction for transmitting the data corresponding to the first channel is sent to the bus command generator 1, and the bus command generator 1 receives the instruction from the arbitration unit 1 to determine the source corresponding to the first channel.
  • the address, the destination address corresponding to the first channel, and the data identifier corresponding to the first channel are used to indicate that the data corresponding to the data identifier in the source address is obtained, and the obtained data is transmitted to the destination address.
  • the data corresponding to the data identifier may be 20 megabytes of data in the source address corresponding to the first channel.
  • the arbitration unit 1 first determines that the second channel has data to be transmitted by polling, determines that the data corresponding to the second channel is transmitted first, and sends an instruction for transmitting the data corresponding to the second channel to the bus command generator 1, the bus command generator 1 Receiving an instruction from the arbitration unit 1, determining a source address corresponding to the second channel, a destination address corresponding to the second channel, and a data identifier corresponding to the second channel, for indicating the data corresponding to the data identifier in the source address, and The acquired data is transferred to the destination address.
  • the source address corresponding to the channel, the destination address corresponding to the channel, and the data identifier corresponding to the channel are determined.
  • a plurality of instructions from the arbitration unit are received, and the source address corresponding to the plurality of groups of channels, the destination address corresponding to the channel, and the information of the data identifier corresponding to the channel are determined.
  • the arbitration unit 1 if within the set time, the arbitration unit 1 is receiving the first hardware module. And the DMA request from the second hardware module, the arbitration unit 1 first determines that the first channel has data to be transmitted by polling, determines that the data corresponding to the first channel is transmitted first, and transmits the corresponding channel corresponding to the first command to the bus command generator 1 The instruction of the data, the bus command generator 1 receives the instruction from the arbitration unit 1, determines the source address corresponding to the first channel, the destination address corresponding to the first channel, and the data identifier corresponding to the first channel; the arbitration unit 1 polls Determining that the second channel has data to be transmitted, determining to transmit data corresponding to the second channel, and transmitting an instruction for transmitting data corresponding to the second channel to the bus command generator 1, and the bus command generator 1 receives the instruction from the arbitration unit 1, The source address corresponding to the second channel, the destination address corresponding to the second channel, and the data identifier corresponding to the second channel are determined.
  • the bus command queue is used to store the source address corresponding to the determined plurality of channels, the destination address corresponding to the channel, and the information of the data identifier corresponding to the channel.
  • the bus command queue can be any storage device, such as a FIFO data buffer.
  • determining a source address corresponding to a group of channels, a destination address corresponding to the channel, and a data identifier corresponding to the channel, that is, determining a transmission data instruction and the bus command queue is sent to the bus controller in a first-in, first-out manner. Transfer data instructions.
  • transmitting data corresponding to the channel includes:
  • the data corresponding to the transmission performance of the channel is a transmission time of transmitting data corresponding to the channel or a rate of transmitting data corresponding to the channel.
  • the performance determining module determines the transmission performance corresponding to the data of the channel.
  • the transmission performance corresponding to the data of each channel may be different, that is, the transmission time of the data corresponding to the transmission channel may be different for each channel;
  • the rate of data corresponding to the transmission channel may be different for each channel.
  • Embodiment 1 The performance determining module determines a transmission time of transmitting data corresponding to the channel. After receiving the data transfer instruction, the bus controller determines the source address, the destination address, and the data identifier, and sends a data acquisition instruction to the data path, instructing the data path to obtain the data corresponding to the data identifier in the source address, and corresponding to the acquired data identifier. The data is sent to the bus controller, and the bus controller transmits the data corresponding to the acquired data identifier to the destination address.
  • the transmission time refers to a time period during which the bus controller issues a data acquisition instruction to the data path to receive the data corresponding to the acquired data identifier returned by the data path.
  • the acquisition time can be obtained by setting a timer, and the timer is started when the bus controller issues a data acquisition command to the data path, and the timer is turned off when receiving the data corresponding to the acquired data identifier returned by the data path.
  • Embodiment 2 The performance determining module determines a rate at which data corresponding to the channel is transmitted.
  • determining a rate of transmitting data corresponding to the channel includes:
  • the transmission time of the data corresponding to the transmission of the channel determined by the performance determining module is the same as the transmission time of the data corresponding to the transmission of the channel determined in step S1.
  • the transmission capacity refers to the size of the data amount corresponding to the data identifier.
  • step S2 determining, according to the transmission time and the transmission capacity, a rate of transmitting data corresponding to the channel includes:
  • the ratio of the transmission capacity to the transmission time can be determined as the rate at which the data corresponding to the channel is transmitted.
  • the bus command queue sends a transmission data command including a source address corresponding to the first channel, a destination address corresponding to the first channel, and a data identifier corresponding to the first channel to the bus controller
  • the source corresponding to the first channel The address is the accumulator ACC
  • the destination address corresponding to the first channel is the program counter PC
  • the bus controller sends the acquired data including the ACC and the M1 to the data path.
  • the performance determining module sends an open command to instruct the timer in the performance determining module to start timing; after receiving the data command, the data path acquires the data corresponding to M1 in the ACC, and sends the acquired delayed data to the bus controller, the bus.
  • the controller When receiving the delay data from the data path, the controller immediately sends a shutdown instruction to the performance determination module, indicating that the timer in the performance determination module stops timing;
  • integrating the performance determination module into the bus controller reduces the error in transmission time.
  • determining, according to the transmission performance corresponding to the data of the channel, the arbitration unit corresponding to the channel from the plurality of arbitration units comprises:
  • the arbitration unit determines, by the arbitration unit, a threshold range in which the transmission performance corresponding to the data of the channel is located, and determines, according to the correspondence between the arbitration unit and the threshold range, an arbitration unit corresponding to a threshold range in which the transmission performance corresponding to the data of the channel is located, And determining that the arbitration unit corresponding to the threshold range is an arbitration unit corresponding to the channel.
  • the method further includes:
  • the arbitration unit determines that the module receives the transmission performance corresponding to the data of the channel from the performance determination module.
  • the correspondence between the arbitration unit and the threshold range may be stored in the arbitration unit determining module, or may be stored in other storage entities, and the arbitration unit determines that the module needs to use the correspondence between the arbitration unit and the threshold range.
  • the following is an example of the transmission performance corresponding to the data of the channel for transmitting the data corresponding to the channel.
  • the transmission performance corresponding to the data of the channel is the implementation of the transmission time of the data corresponding to the channel and the embodiment of the present invention.
  • the implementation of the data corresponding to the data of the channel is similar to the rate of the data corresponding to the channel, and details are not described herein.
  • the transmission performance corresponding to the data of the channel is the rate of the data corresponding to the channel, and the threshold range is the threshold range of the rate.
  • the transmission performance corresponding to the data of the channel is the transmission time of the data corresponding to the channel, the threshold.
  • the range is the threshold range of the transmission time.
  • the correspondence between the arbitration unit and the threshold range is: if the rate of the data corresponding to the transmission channel is less than 50 bps, the corresponding arbitration unit 3; Corresponding data rate is between 50 bps and 90 bps, corresponding to arbitration unit 2; if the rate of data corresponding to the transmission channel is greater than 90 bps, corresponding to arbitration unit 1;
  • the arbitration unit determines that the rate at which the data corresponding to the channel is transmitted is in the range of 50 bps to 90 bps, and determines the arbitration unit corresponding to the channel as the arbitration unit 2 according to the correspondence between the arbitration unit and the threshold range.
  • the correspondence between the arbitration unit and the threshold range may be set according to a specific application scenario.
  • the threshold range can be determined by weighting the rate of data corresponding to each channel.
  • the rate of data corresponding to the first channel is 20 bps
  • the rate of data corresponding to the second channel is 40 bps
  • the rate of data corresponding to the third channel is 60 bps
  • the fourth channel is transmitted.
  • the corresponding data rate is 50 bps
  • the rate of data corresponding to the fifth channel is 60 bps
  • the weight of the data corresponding to each channel is 46 bps.
  • the correspondence between the cutting unit and the threshold range is: if the rate of the data corresponding to the transmission channel is less than 46 bps, corresponding to the arbitration unit 2; if the rate of the data corresponding to the transmission channel is greater than 46 bps, the arbitration unit 2 is corresponding.
  • the priority of the multiple arbitration units may be divided. The higher the rate of transmitting the data corresponding to the channel, the higher the priority of the arbitration unit corresponding to the data corresponding to the channel is transmitted. The smaller the transmission time of the data corresponding to the channel is. The higher the priority of the arbitration unit corresponding to the data corresponding to the transmission of the channel.
  • step 202 it is determined that the channel corresponding to the at least two arbitration units has data to be transmitted before:
  • an arbitration unit of multiple arbitration units it may be determined by fixed priority or round-robin manner which channel of the channel corresponding to the arbitration unit is transmitted, and may also be determined by transmitting the rate of the data of the channel corresponding to the arbitration unit. The data of which channel in the channel corresponding to the arbitration unit is transmitted.
  • the rate of data corresponding to the first channel is 20 bps
  • the rate of data corresponding to the second channel is 40 bps
  • the rate of data corresponding to the third channel is 65 bps
  • the fourth channel is transmitted.
  • the rate of the corresponding data is 50 bps
  • the rate of data corresponding to the fifth channel is 60 bps
  • the first channel and the second channel correspond to the arbitration unit 3
  • the fourth channel corresponds to the arbitration unit 2
  • the third channel corresponds to the fifth channel.
  • Arbitration unit 1 because the rate of data corresponding to the second channel is greater than the rate of data corresponding to the first channel, the arbitration unit 3 determines to transmit part of the data in the data corresponding to the second channel. Then, part of the data in the data corresponding to the first channel is transmitted, and then part of the data in the data corresponding to the second channel is transmitted, and the cycle is alternated.
  • the instruction interaction between the arbitration unit 1, the bus command generator 1 and the bus command queue 1 is between the arbitration unit, the bus command generator and the bus command queue mentioned above.
  • the instruction interaction is similar, the instruction interaction between the arbitration unit 2, the bus command generator 2, and the bus command queue 2 is similar to the instruction interaction between the arbitration unit, the bus command generator, and the bus command queue mentioned above, the arbitration unit 3,
  • the instruction interaction between the bus command generator 3 and the bus command queue 3 is similar to the instruction interaction between the arbitration unit, the bus command generator, and the bus command queue mentioned above, and will not be described herein.
  • the bus command queue storage capacity is also different for different priority arbitration units.
  • the higher the arbitration unit priority the larger the bus command queue storage capacity and the higher the data transmission efficiency.
  • determining that the channel corresponding to the at least two arbitration units has data to be transmitted includes multiple manners, for example, after receiving the transmission data instruction corresponding to the at least two arbitration units within the set time period, determining at least The channels corresponding to the two arbitration units have data to be transmitted, or transmission instructions from at least two arbitration units received within a set period of time, and it is determined that the channels corresponding to at least two arbitration units have data to be transmitted.
  • Manner 1 After receiving the transmission data command corresponding to the at least two arbitration units in the set time period, determining that the channel corresponding to the at least two arbitration units has data to be transmitted;
  • the transmission data instruction corresponding to each arbitration unit is different.
  • the set time period can be any time period, such as 1ms (milliseconds), 100us (microseconds), which can be set as needed.
  • the transmission data instruction includes a source address, a destination address, and a data identifier; each of the arbitration unit corresponding to the transmission data instruction differently includes one or more of the following:
  • the source address in the transmission data instruction corresponding to each arbitration unit is different;
  • the source address corresponding to the first channel is ROM, and the data identifier corresponding to the first channel is Al
  • the second channel The source address corresponding to the channel is PC
  • the data identifier corresponding to the second channel is A2
  • the destination addresses corresponding to the first channel and the second channel are all ACC
  • the transmission data instructions corresponding to the arbitration unit 1 include ROM, ACC, and Al
  • the arbitration The transmission data instruction corresponding to unit 2 includes PC, ACC, and A2.
  • the destination address in the transmission data instruction corresponding to each arbitration unit is different;
  • the source address corresponding to the first channel and the second channel is a PC
  • the data identifier corresponding to the first channel is Al, the first channel.
  • the corresponding destination address is ROM
  • the destination address corresponding to the second channel is ACC
  • the data identifier corresponding to the second channel is Al
  • the transmission data command corresponding to the arbitration unit 1 includes PC, ROM, and Al
  • the transmission data corresponding to the arbitration unit 2 The instruction includes the PC, the ACC, and the A1, and the bus controller receives the transmission data instruction corresponding to the arbitration unit 1 and the transmission data instruction corresponding to the arbitration unit 2 within the set time, and determines that the channel corresponding to the at least two arbitration units has data. To be transmitted; wherein the destination address in the transfer data instruction corresponding to each arbitration unit is different.
  • the data identifier in the transmission data instruction corresponding to each arbitration unit is different.
  • the source address corresponding to the first channel and the second channel is a PC
  • the corresponding destination address corresponding to the first channel and the second channel For the ROM, the data corresponding to the first channel is identified as A1, and the data corresponding to the second channel is identified as A2.
  • the data transfer instruction corresponding to the arbitration unit 1 includes the PC, the ROM, and the Al.
  • the transmission data command corresponding to the arbitration unit 2 includes the PC.
  • the bus controller receives the transmission data instruction corresponding to the arbitration unit 1 and the transmission data instruction corresponding to the arbitration unit 2 within the set time, and determines that the channel corresponding to the at least two arbitration units has data to be transmitted; The data identifier in the transmission data instruction corresponding to each arbitration unit is different.
  • Method 2 A transmission instruction received from at least two arbitration units within a set time period, It is determined that the channel corresponding to at least two arbitration units has data to be transmitted.
  • the set time period can be any time period, such as lms (milliseconds), 100 us (microseconds), which can be set as needed.
  • the arbitration unit sends a transmission instruction for notifying the bus controller that the channel corresponding to the arbitration unit has data to be transmitted.
  • transmitting data according to the priority of the at least two arbitration units comprises: first processing a transmission data instruction corresponding to the arbitration unit with a higher priority, that is, first transmitting data of a channel corresponding to the arbitration unit with a higher priority.
  • the priority of the arbitration unit does not need to be determined, and the data of the channel corresponding to the arbitration unit is directly transmitted.
  • the priority of the arbitration unit may be stored by the bus controller or by other storage entities. When the priority of the arbitration unit is needed, the bus controller calls to other storage entities.
  • the embodiment of the present invention is described by taking three arbitrating units and five DMA channels as an example. It should be noted that the embodiment of the present invention is not limited to three arbitrating units and five DMA channels, which are required for different applications.
  • the other embodiments are also applicable to the embodiments of the present invention, and the implementation manners of the other embodiments are similar to the implementation manners of the embodiments of the present invention, and details are not described herein again.
  • Step 401 The first hardware module sends a DMA request to the arbitration unit 1 through the first channel, requesting to transfer the data M from the address A to the address B.
  • the third hardware module sends a DMA request to the arbitration unit 1 through the third channel, requesting the data.
  • N is transferred from address C to address D;
  • fourth hardware The module sends a DMA request to the arbitration unit 1 through the fourth channel, requesting that the data 0 be transmitted from the address E to the address F;
  • the DMA request sent by all the hardware modules to which arbitration unit can be set as needed for example, the DMA request is sent to the arbitration unit 1 at the same time.
  • the first hardware module may send a DMA request to the arbitration unit 1 through the first channel, requesting to transfer the data M from the address A to the address B; the first hardware module may also send a DMA request to the arbitration unit 1 through the first channel, The data M is requested to be transmitted from the address A to the address B; the DMA request is sent to the arbitration unit 1 through the second channel, and the data N is requested to be transmitted from the address A to the address B, which can be set as needed.
  • Step 402 When receiving the DMA request from the hardware module, the arbitration unit 1 determines, by a fixed priority or a round-robin method, which channel corresponds to the data, and sends and transmits the channel corresponding to the bus command generator 1
  • the instruction of the data indicates that the bus command generator 1 determines the source address corresponding to the channel, the destination address corresponding to the channel, and the data identifier corresponding to the channel;
  • the implementation manner in which the arbitration unit 1 determines which channel corresponds to the data by using the fixed priority or the round-robin manner is the same as the implementation manner in which the arbitration unit in FIG. 2 determines which channel corresponds to the data by the fixed priority or the round-robin manner. , will not repeat them here.
  • Step 403 The bus command generator 1 determines, according to the received instruction from the arbitration unit 1, a source address corresponding to the channel, a destination address corresponding to the channel, and a data identifier corresponding to the channel.
  • Step 404 for the first hardware module, The DMA request of the third hardware module and the fourth hardware module, the arbitration unit 1 sends three instructions for transmitting data corresponding to the channel according to a fixed priority or a round-robin manner, and the bus command generator 1 determines a source address corresponding to the plurality of groups of channels, The destination address corresponding to the channel and the data identifier corresponding to the channel;
  • Step 405 After determining the source address corresponding to the group of channels, the destination address corresponding to the channel, and the data identifier corresponding to the channel, the bus command generator 1 sends the determined source address and channel corresponding to the determined group of channels to the bus command queue 1.
  • Step 406 The bus command queue 1 stores the source address corresponding to the received multiple groups of channels, the destination address corresponding to the channel, and the data identifier corresponding to the channel; the corresponding destination address and the data corresponding to the channel Logo.
  • Step 407 The bus command queue 1 determines, in a first-in first-out manner, a source address corresponding to the stored plurality of groups of channels, a destination address corresponding to the channel, and a group of data identifiers corresponding to the channel as a transmission data instruction, and controls the bus to the bus.
  • the transmission data instruction includes a source address, a destination address, and a data identifier, and indicates that the data corresponding to the data identifier in the source address is obtained and transmitted to the destination address.
  • Step 408 After receiving the transmission data instruction from the bus command queue 1, the bus controller determines the source address, the destination address, and the data identifier, and sends an acquisition data instruction including the determined source address and the data identifier to the data path.
  • Step 409 The bus controller sends an instruction to the performance determining module to issue a timer to start the timing set in the performance determining module.
  • Step 410 Obtain data corresponding to the data identifier from the data path to the source address, and send the data to the bus controller.
  • Step 411 The bus controller sends an instruction to the performance determining module, indicating the timer stop timing set in the performance determining module, and transmitting the data amount of the received data to the performance determining module, while receiving the data from the data path.
  • Step 412 The bus controller transmits the data received from the data path to the destination address.
  • Step 413 The performance determining module determines a transmission time and a transmission capacity of the data corresponding to the channel, and calculates a rate of transmitting the data corresponding to the channel. ;
  • Step 414 The performance determining module sends the calculated rate of transmitting data corresponding to the channel. Determining a module to the arbitration unit;
  • Step 415 The arbitration unit determining module determines a threshold range in which the rate of the data corresponding to the channel is transmitted, and determines, according to the correspondence between the arbitration unit and the threshold range, the arbitration corresponding to the threshold range in which the rate of the data corresponding to the channel is transmitted. Unit, and determining that the arbitration unit corresponding to the threshold range is an arbitration unit corresponding to the channel;
  • Step 416 For each arbitration unit, the arbitration unit determines, according to the received DMA request, that the channel corresponding to the arbitration unit has data to be transmitted;
  • step 402 For the interaction of the arbitration unit, the bus command generator, and the bus command queue, refer to step 402 to step 407;
  • Step 417 When the bus controller determines that the channel corresponding to the at least two arbitration units has data to be transmitted, the data is transmitted according to the priority of the at least two arbitration units.
  • step 417 is shown in the embodiment of FIG. 2 of the present invention.
  • an embodiment of the present invention provides a device for transmitting data, and a receiving device.
  • the principle of the device is similar to the method of the embodiment of the present invention. Therefore, the implementation of the device may refer to the implementation of the method. The repetitions are not repeated here.
  • FIG. 5 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present invention. As shown in the figure, an apparatus for transmitting data according to an embodiment of the present invention includes:
  • the determining module 501 is configured to determine, according to the transmission performance corresponding to the data of the channel, an arbitration unit corresponding to the channel according to the transmission performance corresponding to the data of the channel; the processing module 502 is configured to determine at least two arbitrations.
  • the data to be transmitted is determined according to the priorities of the at least two arbitration units.
  • the data corresponding to the transmission performance of the channel is the transmission time of the data corresponding to the channel or the rate of the data corresponding to the channel; the determining module 501 is configured to determine the transmission.
  • the transmission time of the data corresponding to the channel or the rate at which the data corresponding to the channel is transmitted.
  • the transmission performance corresponding to the data of the channel is to transmit data corresponding to the channel.
  • the determining module 501 is configured to determine a transmission time and a transmission capacity of the data corresponding to the transmission of the channel, and determine a transmission corresponding to the data of the channel according to the transmission time and the transmission capacity.
  • the determining module 501 is configured to determine a threshold range in which the transmission performance corresponding to the data of the channel is located, and determine, according to the correspondence between the arbitration unit and the threshold range, the arbitration corresponding to the threshold range in which the data corresponding to the channel is located. a unit, and determining that the arbitration unit corresponding to the threshold range is an arbitration unit corresponding to the channel.
  • the processing module 502 is configured to: after receiving the transmission data instruction corresponding to the at least two arbitration units within the set time period, determine that the channel corresponding to the at least two arbitration units has data to be transmitted, where each arbitration unit The corresponding transfer data instructions are different.
  • the transmission data instruction includes a source address, a destination address, and a data identifier; each of the arbitration unit corresponding to the transmission data instruction differently includes one or more of the following: each of the arbitration unit corresponding to the transmission data instruction The source addresses are different; the destination addresses in the transmission data instructions corresponding to each arbitration unit are different; the data identifiers in the transmission data instructions corresponding to each arbitration unit are different.
  • the determining module 501 is equivalent to the arbitration unit determining module in the arbitration structure (see FIG. 3) of the embodiment of the present invention, and the processing module 502 is equivalent to the arbitration structure of the embodiment of the present invention.
  • the determining module 501 is configured to determine a transmission time and a transmission capacity of the data corresponding to the channel, and determine a transmission performance corresponding to the data of the channel according to the transmission time and the transmission capacity, and the determining module 501 further It is equivalent to the performance determination module in the arbitration structure of the embodiment of the present invention.
  • the determining module 501 and the processing module 502 may be configured by a central processing unit (CPU), a processor (MPU, a Micro Processing Unit), and a digital signal processor (DSP). Or programmable logic array (FPGA, Field - Programmable Gate Array) implementation.
  • CPU central processing unit
  • MPU Micro Processing Unit
  • DSP digital signal processor
  • FPGA programmable logic array
  • the embodiment of the present invention further includes a DMA channel and a bus command generated as shown in FIG.
  • the implementation of the hardware module, DMA channel, bus command generator, bus command queue, and data path unit for transmitting DMA requests, etc., is described in detail in the implementation of FIG. 2 of the present invention and the implementation of FIG. 4 of the present invention.
  • the foregoing is an example in which a finite number of DMA channels, an arbitration unit determination module, an arbitration unit, a bus command generator, and a bus command queue are introduced.
  • the DMA channel, the arbitration unit determination module, the arbitration unit, and the bus command generator are implemented.
  • the number of bus command queues can be as needed, but it needs to be satisfied:
  • the number of DMA channels, arbitration unit determination module, arbitration unit, bus command generator, and bus command queue are the same.
  • embodiments of the present invention can be provided as a method, system, or computer program product.
  • the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware.
  • embodiments of the invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) in which computer usable program code is embodied.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本发明实施例涉及数据传输领域，特别涉及一种传输数据的方法和设备，用以解决通过round-robin方式实现对各个DMA通道的仲裁，根据仲裁结果对数据进行传输的方法导致数据传输效率比较低，DMA性能比较差的问题。本发明实施例提供的方法包括：针对一个直接内存存取DMA通道，根据该通道的数据对应的传输性能，从多个仲裁单元中确定该通道对应的仲裁单元；确定至少两个仲裁单元对应的通道有数据要传输时，根据所述至少两个仲裁单元的优先级传输数据。本发明实施例实现了先对通道的数据对应的传输性能好的通道对应的数据的进行传输，保持总线畅通，进而提高了数据传输的效率，提高了DMA的性能。

Description

一种传输数据的方法和设备 技术领域
本发明涉及数据传输领域， 特别涉及一种传输数据的方法和设备。 背景技术
现有技术中，仲裁单元通过 round-robin(轮询）的方式实现对各个 DMA ( Direct Memory Access, 直接内存存取）通道的仲裁。 如图 1所示， 第一 硬件模块通过 DMA的第一通道向 DMA的仲裁单元发送包含传输数据信息 的 DMA请求（比如，将地址 A的数据传输到地址 B，数据量为 90兆字节）， 第二硬件模块通过 DMA的第二通道向 DMA的仲裁单元发送包含传输数据 信息的 DMA请求（比如， 将地址 C的数据传输到地址 D， 数据量为 100 兆字节）。 DMA 的仲裁单元实时采用从上到下轮询的方式， 从第一通道开 始轮询， 确定传输第一通道对应的数据， 并向 bus command generator (总线 命令产生器）发送传输第一通道对应的数据的命令， 当轮询到第二通道时， 确定传输第二通道对应的数据， 并向 bus command generator发送传输第二 通道对应的数据的命令， 当轮询到第五通道的时候，若 CPU (中央处理器） 通过 DMA的第三通道向 DMA的仲裁单元发送包含传输数据信息的 DMA 请求， 则仲裁单元不会立即响应 CPU的 DMA请求， 而是在下一轮的轮询 中， DMA的仲裁单元轮询到第三通道时， 会向 bus command generator发送 传输第三通道的数据的命令。
针对接收到的来自 DMA 的仲裁单元的传输第一通道的数据的命令 ( DMA的仲裁单元第一次向 bus command generator发送传输第一通道的数 据的命令）后， bus command generator确定源地址、 目的地址以及要传输的 第一通道对应的数据的大小 （针对第一通道， 地址 A为源地址， 地址 B为 目的地址），并緩存在 bus command queue (总线命令队列）中， bus controller (总线控制器 )在收到来自 bus command queue的传输数据指令后， 向数据 通路单元发送获取数据指令， 指示数据通路单元到源地址中获取数据标识 对应的数据， 在接收到来自数据通路单元的数据后， 将获取的数据写入到 目的地址中， 其中， bus command queue是一个 FIFO (先进先出 )数据緩存 器。
以上过程中， 假设第一通道、 第二通道以及第三通道对应的数据传输 速率比较小， 当数据通路单元达到处理上限时， 就会造成总线堵塞， 因此 当其它硬件模块通过第四通道、第五通道或者第六通道向 DMA的仲裁单元 发送 DMA请求时， DMA的仲裁单元会暂停对 DMA请求的处理， 导致数 据传输效率比较低， DMA性能比较差。
综上所述， 目前 DMA的仲裁单元通过 round-robin (轮询）的方式实现 对各个 DMA通道的仲裁，根据仲裁结果对数据进行传输的方法导致数据传 输效率比较低， DMA性能比较差。 发明内容
本发明实施例提供的一种传输数据的方法和设备， 用以解决现有技术 中存在的通过 round-robin方式实现对各个 DMA通道的仲裁， 才艮据仲裁结 果对数据进行传输的方法导致数据传输效率比较低， DMA性能比较差的问 题。
本发明实施例提供的一种传输数据的方法， 包括：
针对一个直接内存存取 DMA通道，根据该通道的数据对应的传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元；
确定至少两个仲裁单元对应的通道有数据要传输时， 根据所述至少两 个仲裁单元的优先级传输数据。
本发明实施例提供的一种传输数据的设备， 包括： 确定模块， 配置为针对一个直接内存存取 DMA通道，根据该通道的数 据对应的传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元；
处理模块， 配置为确定至少两个仲裁单元对应的通道有数据要传输时， 根据所述至少两个仲裁单元的优先级确定进行传输的数据。
在本发明实施例中， 采用多个仲裁单元， 针对一个直接内存存取 DMA 通道， 根据该通道的数据对应的传输性能， 从多个仲裁单元中确定该通道 对应的仲裁单元； 确定至少两个仲裁单元对应的通道有数据要传输时， 根 据所述至少两个仲裁单元的优先级传输数据， 由于针对一个通道， 该通道 的数据对应的传输性能越好， 越在先传输该通道对应的数据， 从而实现了 先对通道的数据对应的传输性能好的通道对应的数据的进行传输， 通过这 种优先级的应用，保持总线畅通，进而提高了数据传输的效率与 DMA的性 6匕
Fit！。 附图说明
图 1为现有技术中的仲裁结构；
图 2为本发明实施例传输数据的方法流程示意图；
图 3为本发明实施例的仲裁结构；
图 4为本发明实施例传输数据的详细方法流程示意图；
图 5为本发明实施例传输数据的设备结构示意图。 具体实施方式
本发明实施例，采用多个仲裁单元，针对一个直接内存存取 DMA通道， 根据该通道的数据对应的传输性能， 从多个仲裁单元中确定该通道对应的 仲裁单元； 确定至少两个仲裁单元对应的通道有数据要传输时， 根据所述 至少两个仲裁单元的优先级传输数据。 由于针对一个通道， 该通道的数据 对应的传输性能越好， 越在先传输该通道对应的数据， 从而实现了先对传 输性能好的通道对应的数据的进行传输， 通过这种优先级的应用， 保持总 线畅通， 进而提高了数据传输的效率与 DMA的性能。
下面结合说明书附图对本发明实施例作进一步详细描述。
如图 2所示， 本发明实施例传输数据的方法包括下列步骤：
步骤 201、 针对一个直接内存存取 DMA通道， 根据该通道的数据对应 的传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元；
步骤 202、确定至少两个仲裁单元对应的通道有数据要传输时， 根据所 述至少两个仲裁单元的优先级传输数据。
较佳地， 步骤 201中， 针对一个直接内存存取 DMA通道， 传输该通道 对应的数据之前还包括：
硬件模块通过所述该通道向仲裁单元发送 DMA请求，请求进行数据传 输。
其中， 所有的硬件模块第一次发送 DMA请求时，要通过各自的通道向 同一个仲裁单元发送 DMA请求。
实施中， 硬件模块可以是参与数据传输的任何硬件模块， 比如 CPU， RAM等， 至于具体是哪种硬件模块， 可以根据需要进行配置。
以图 3 为例， 各个硬件模块通过各自对应的通道向仲裁单元 1 发送 DMA请求， 请求进行数据传输；
实施中， 第一硬件模块可以通过任意多个通道向仲裁单元 1发送 DMA 请求， 比如通过第一通道向仲裁单元 1发送 DMA请求，可以通过第一通道 和第二通道向仲裁单元 1发送 DMA请求。
其中， 在本发明实施例中， 以第一硬件模块、 第二硬件模块、 第三硬 件模块、第四硬件模块和第五硬件模块向仲裁单元 1发送 DMA请求为例进 行介绍， 优选地， 第一硬件模块、 第二硬件模块、 第三硬件模块、 第四硬 件模块和第五硬件模块还可以向其它仲裁单元发送 DMA请求，具体向哪个 仲裁单元发送 DMA请求可以根据需要设定。 较佳地， 仲裁单元可以通过固定优先级或者 round-robin方式确定传输 哪个通道对应的数据， 并发送传输该通道对应的数据的指令， 其中， 仲裁 单元通过固定优先级或者 round-robin方式确定传输哪个通道对应的数据是 现有技术， 仲裁单元通过 round-robin方式确定传输哪个通道对应的数据具 体参见本发明的背景技术， 仲裁单元通过固定优先级方式确定传输哪个通 道对应的数据具体参见网址 http：〃 wiki.cnki.com.cn/HotWord/237347 l.htm。
其中， 仲裁单元向该仲裁单元对应的总线命令产生器发送传输该通道 对应的数据的指令。
以图 3为例， 若在设定时间内， 仲裁单元 1在收到来自第一硬件模块 和来自第二硬件模块的 DMA请求，仲裁单元 1通过轮询先确定第一通道有 数据要传输， 确定在先传输第一通道对应的数据， 向总线命令产生器 1 发 送传输第一通道对应的数据的指令； 仲裁单元 1 继续进行轮询， 确定第二 通道有数据要传输， 向总线命令产生器 1 发送传输第二通道对应的数据的 指令； 仲裁单元 1 继续进行轮询， 确定第三通道没有数据要传输时， 第五 硬件模块通过第五通道向仲裁单元 1发送 DMA请求，仲裁单元 1不立即处 理来自第五硬件模块的 DMA请求， 而是继续进行轮询，确定第四通道没有 数据要传输， 继续进行轮询， 确定第五通道有数据要传输， 向总线命令产 生器 1发送传输第五通道对应的数据的指令。
实施中， 对已经获得仲裁的通道做上标记， 指示仲裁单元根据标记确 定是否已经对该通道进行了仲裁， 较佳地， 可以对获得不同次数仲裁的通 道做上不同的标记， 指示仲裁单元根据标记确定已经对该通道进行了多少 次仲裁。
其中， 标记可以是仲裁单元能够根据标记确定是否已经对该通道进行 了仲裁和 /或仲裁单元能够根据标记确定已经对该通道进行了多少次仲裁的 任何标记， 比如数字标记或者字母标记。
较佳地，根据收到的来自仲裁单元的指令，确定该通道对应的源地址、 该通道对应的目的地址以及该通道对应的数据标识。
其中， 可以是仲裁单元对应的总线命令产生器收到来自该仲裁单元的 指令。
实施中，该通道对应的源地址中，数据标识对应的数据可以是 DMA请 求中请求进行传输的数据中的一部分数据。
以图 3为例， 若在设定时间内， 仲裁单元 1在收到来自第一硬件模块 和来自第二硬件模块的 DMA请求，仲裁单元 1通过轮询先确定第一通道有 数据要传输， 确定在先传输第一通道对应的数据， 向总线命令产生器 1 发 送传输第一通道对应的数据的指令， 总线命令产生器 1 在收到来自仲裁单 元 1 的指令， 确定第一通道对应的源地址、 第一通道对应的目的地址以及 第一通道对应的数据标识， 用于指示获取源地址中数据标识对应的数据， 并将获取的数据传输到目的地址。
实施中，若第一硬件模块发送 DMA请求传输第一通道对应的源地址中 的 100 兆字节的数据， 数据标识对应的数据可以是第一通道对应的源地址 中的 20兆字节的数据，仲裁单元 1通过轮询先确定第二通道有数据要传输， 确定在先传输第二通道对应的数据， 向总线命令产生器 1 发送传输第二通 道对应的数据的指令， 总线命令产生器 1在收到来自仲裁单元 1 的指令， 确定第二通道对应的源地址、 第二通道对应的目的地址以及第二通道对应 的数据标识， 用于指示获取源地址中数据标识对应的数据， 并将获取的数 据传输到目的地址。
较佳地， 针对收到的来自仲裁单元的多条指令， 确定该通道对应的源 地址、 该通道对应的目的地址以及该通道对应的数据标识。
较佳地， 针对多个 DMA请求， 将会收到来自仲裁单元的多条指令， 确 定多组通道对应的源地址、 通道对应的目的地址以及通道对应的数据标识 的信息。
以图 3为例， 若在设定时间内， 仲裁单元 1在收到来自第一硬件模块 和来自第二硬件模块的 DMA请求，仲裁单元 1通过轮询先确定第一通道有 数据要传输， 确定在先传输第一通道对应的数据， 向总线命令产生器 1 发 送传输第一通道对应的数据的指令， 总线命令产生器 1 在收到来自仲裁单 元 1 的指令， 确定第一通道对应的源地址、 第一通道对应的目的地址以及 第一通道对应的数据标识； 仲裁单元 1 通过轮询确定第二通道有数据要传 输， 确定传输第二通道对应的数据， 向总线命令产生器 1 发送传输第二通 道对应的数据的指令， 总线命令产生器 1在收到来自仲裁单元 1 的指令， 确定第二通道对应的源地址、 第二通道对应的目的地址以及第二通道对应 的数据标识。
具体实施中， 采用总线命令队列存储确定的多组通道对应的源地址、 通道对应的目的地址以及通道对应的数据标识的信息。
其中， 总线命令队列可以是任何存储设备， 比如 FIFO数据緩存器。 其中， 针对一个通道， 确定一组通道对应的源地址、 通道对应的目的 地址以及通道对应的数据标识的信息， 即确定一条传输数据指令， 总线命 令队列采用先入先出的方式向总线控制器发送传输数据指令。
较佳地， 针对一个 DMA通道， 传输该通道对应的数据包括：
确定该通道对应的源地址、 该通道对应的目的地址以及该通道对应的 数据标识；
获取所述源地址中所述数据标识对应的数据， 并将所述数据传输到所 述目的地址。
较佳地， 步骤 201中， 针对一个 DMA通道， 该通道的数据对应的传输 性能为传输该通道对应的数据的传输时间或传输该通道对应的数据的速率。
实施中， 由性能确定模块确定该通道的数据对应的传输性能。
其中， 各个通道的数据对应的传输性能可能不同， 即针对各个通道， 传输通道对应的数据的传输时间可能不同； 或
针对各个通道， 传输通道对应的数据的速率可能不同。 实施例一、 性能确定模块确定传输该通道对应的数据的传输时间。 总线控制器收到传输数据指令后， 确定源地址、 目的地址以及数据标 识， 并向数据通路发送获取数据指令， 指示数据通路到源地址中获取数据 标识对应的数据， 并将获取的数据标识对应的数据发送给总线控制器， 总 线控制器将获取的数据标识对应的数据传输到目的地址。
其中， 传输时间是指总线控制器向数据通路发出获取数据指令到接收 到数据通路返回的获取的数据标识对应的数据的时间段。
较佳地， 可以通过设定定时器实现获取传输时间， 在总线控制器向数 据通路发出获取数据指令时开始开启定时器， 在接收到数据通路返回的获 取的数据标识对应的数据时关闭定时器。
实施例二、 性能确定模块确定传输该通道对应的数据的速率。
较佳地， 确定传输该通道对应的数据的速率包括：
S1、 确定传输该通道对应的数据的传输时间和传输容量；
S2、根据所述传输时间和传输容量确定传输该通道对应的数据的速率。 其中， 实施例一中， 性能确定模块确定的传输该通道对应的数据的传 输时间与步骤 S1中确定的传输该通道对应的数据的传输时间相同。
其中， 传输容量是指数据标识对应的数据量的大小。
步骤 S2中， 根据所述传输时间和传输容量确定传输该通道对应的数据 的速率包括：
可以将传输容量与传输时间的比值确定为传输该通道对应的数据的速 率。
以图 3 为例， 若总线命令队列向总线控制器发送包含第一通道对应的 源地址、 第一通道对应的目的地址以及第一通道对应的数据标识的传输数 据指令， 第一通道对应的源地址为累加器 ACC， 第一通道对应的目的地址 为程序计数器 PC，第一通道对应的数据标识 Ml对应的数据为延时数据时， 则总线控制器向数据通路发出包含 ACC 和 Ml的获取数据指令，并立即向 性能确定模块发送开启指令， 指示性能确定模块中的定时器启动计时； 数据通路在收到数据指令后， 到 ACC中获取 Ml对应的数据， 并将获 取的延时数据发送给总线控制器， 总线控制器在接收到来自数据通路的延 时数据时， 立即向性能确定模块发送关闭指令， 指示性能确定模块中的定 时器停止计时；
若性能确定模块根据定时器的计时确定传输时间为 1 S (秒）， 根据来 自总线控制器的延时数据确定传输容量为 10字节 B， 则将传输容量与传输 时间的比值（ 10/1 = 10 bps字节每秒）确定为传输该通道对应的数据的速率。
较佳地， 将性能确定模块集成到总线控制器中， 可以减小传输时间的 误差。
较佳地， 步骤 201 中， 根据该通道的数据对应的传输性能， 从多个仲 裁单元中确定该通道对应的仲裁单元包括：
Z1、 确定该通道的数据对应的传输性能所在的阈值范围；
Z2、 根据仲裁单元与阈值范围的对应关系， 确定该通道的数据对应的 传输性能所在的阈值范围对应的仲裁单元， 并将确定所述阈值范围对应的 仲裁单元为该通道对应的仲裁单元。
实施中， 由仲裁单元确定模块确定该通道的数据对应的传输性能所在 的阈值范围， 根据仲裁单元与阈值范围的对应关系， 确定该通道的数据对 应的传输性能所在的阈值范围对应的仲裁单元， 并确定阈值范围对应的仲 裁单元为该通道对应的仲裁单元。
较佳地， 在步骤 Z1之前还包括：
仲裁单元确定模块接收来自性能确定模块的该通道的数据对应的传输 性能。
较佳地， 在步骤 Z2中， 仲裁单元与阈值范围的对应关系可以存储在仲 裁单元确定模块中， 也可以存储在其它存储实体里， 当仲裁单元确定模块 需要用到仲裁单元与阈值范围的对应关系时， 到其它存储实体里调取。 下面以该通道的数据对应的传输性能为传输该通道对应的数据的速率 为例进行介绍， 该通道的数据对应的传输性能为传输该通道对应的数据的 传输时间的实施情况与本发明实施例该通道的数据对应的传输性能为传输 该通道对应的数据的速率的实施情况类似， 在此不再赘述。
确定传输该通道对应的数据的速率所在的阈值范围；
根据仲裁单元与阈值范围的对应关系， 确定传输该通道对应的数据的 速率所在的阈值范围对应的仲裁单元， 并将确定所述阈值范围对应的仲裁 单元为该通道对应的仲裁单元；
其中， 针对该通道的数据对应的传输性能为传输该通道对应的数据的 速率， 阈值范围为速率的阈值范围； 针对该通道的数据对应的传输性能为 传输该通道对应的数据的传输时间， 阈值范围为传输时间的阈值范围。
以图 3为例，若传输该通道对应的数据的速率为 58 bps,仲裁单元与阈 值范围的对应关系为： 若传输通道对应的数据的速率小于 50 bps,则对应仲 裁单元 3; 若传输通道对应的数据的速率在 50 bps〜 90 bps, 则对应仲裁单 元 2; 若传输通道对应的数据的速率大于 90 bps, 则对应仲裁单元 1 ;
则仲裁单元确定模块确定传输该通道对应的数据的速率所在的阈值范 围为 50 bps〜 90 bps， 才艮据仲裁单元与阈值范围的对应关系， 确定该通道对 应的仲裁单元为仲裁单元 2。
具体实施中， 仲裁单元与阈值范围的对应关系可以根据具体的应用场 景进行设定。
其中， 针对存在两个仲裁单元的情况， 可以通过对传输各个通道对应 的数据的速率的加权确定阈值范围。
以图 3为例，若传输第一通道对应的数据的速率为 20 bps,传输第二通 道对应的数据的速率为 40 bps， 传输第三通道对应的数据的速率为 60 bps， 传输第四通道对应的数据的速率为 50 bps，传输第五通道对应的数据的速率 为 60 bps, 则传输各个通道对应的数据的速率的加权值为 46 bps, 则确定仲 裁单元与阈值范围的对应关系为：若传输通道对应的数据的速率小于 46 bps, 则对应仲裁单元 2; 若传输通道对应的数据的速率大于 46 bps, 则对应仲裁 单元 2。
上述是以存在三个仲裁单元为例进行介绍， 实施中， 总裁单元有多少 个可以根据需要而定， 仲裁单元设置的个数越多， 传输数据的效率越高。
其中， 可以给多个仲裁单元划分优先级， 传输该通道对应的数据的速 率越大， 传输该通道对应的数据对应的仲裁单元的优先级越高； 传输该通 道对应的数据的传输时间越小， 传输该通道对应的数据对应的仲裁单元的 优先级越高。
较佳地， 步骤 202 中， 确定至少两个仲裁单元对应的通道有数据要传 输之前还包括：
针对多个仲裁单元的一个仲裁单元， 可以通过固定优先级或者 round-robin方式确定传输该仲裁单元对应的通道中的哪个通道的数据， 还 可以通过传输该仲裁单元对应的通道的数据的速率确定传输该仲裁单元对 应的通道中的哪个通道的数据。
以图 3为例，若传输第一通道对应的数据的速率为 20 bps,传输第二通 道对应的数据的速率为 40 bps， 传输第三通道对应的数据的速率为 65 bps， 传输第四通道对应的数据的速率为 50 bps，传输第五通道对应的数据的速率 为 60 bps，第一通道和第二通道对应仲裁单元 3，第四通道对应仲裁单元 2， 第三通道和第五通道对应仲裁单元 1， 由于仲裁单元 3对应的通道中， 传输 第二通道对应的数据的速率大于传输第一通道对应的数据的速率， 则仲裁 单元 3确定先传输第二通道对应的数据中的部分数据， 再传输第一通道对 应的数据中的部分数据， 再传输第二通道对应的数据中的部分数据， 如此 循环交替进行。
较佳地， 仲裁单元 1、 总线命令产生器 1 以及总线命令队列 1之间的指 令交互与上述提及的仲裁单元、 总线命令产生器以及总线命令队列之间的 指令交互类似， 仲裁单元 2、 总线命令产生器 2以及总线命令队列 2之间的 指令交互与上述提及的仲裁单元、 总线命令产生器以及总线命令队列之间 的指令交互类似， 仲裁单元 3、 总线命令产生器 3以及总线命令队列 3之间 的指令交互与上述提及的仲裁单元、 总线命令产生器以及总线命令队列之 间的指令交互类似， 在此不再赘述。
其中， 针对不同优先级的仲裁单元， 总线命令队列存储容量也不同， 较佳地， 仲裁单元优先级越高， 总线命令队列存储容量越大， 数据传输效 率越高。
较佳地， 步骤 202 中， 确定至少两个仲裁单元对应的通道有数据要传 输包括有多种方式， 比如在设定时间段内接收到至少两个仲裁单元对应的 传输数据指令后， 确定至少两个仲裁单元对应的通道有数据要传输， 或者 在设定时间段内收到的来自至少两个仲裁单元的传输指令， 确定至少两个 仲裁单元对应的通道有数据要传输。
方式一、 在设定时间段内接收到至少两个仲裁单元对应的传输数据指 令后， 确定至少两个仲裁单元对应的通道有数据要传输；
其中， 每个仲裁单元对应的传输数据指令不同。
其中，设定时间段可以是任何时间段，比如 1ms (毫秒）， 100us(微秒）， 可以根据需要设定。
当设定时间段的值为 0 时， 即在同时接收到至少两个仲裁单元对应的 传输数据指令后， 确定至少两个仲裁单元对应的通道有数据要传输的情况 同样适用于本发明实施例。
较佳地， 所述传输数据指令包括源地址、 目的地址以及数据标识； 每 个仲裁单元对应的传输数据指令不同包括下列中的一种或多种：
一、 每个仲裁单元对应的传输数据指令中的源地址不同；
以图 3为例， 若第一通道对应仲裁单元 1， 第二通道对应仲裁单元 2， 第一通道对应的源地址为 ROM, 第一通道对应的数据标识为 Al， 第二通 道对应的源地址为 PC， 第二通道对应的数据标识为 A2， 第一通道和第二 通道对应的目的地址均为 ACC， 则仲裁单元 1 对应的传输数据指令包括 ROM, ACC以及 Al， 仲裁单元 2对应的传输数据指令包括 PC、 ACC以及 A2, 在设定时间内， 总线控制器收到来自仲裁单元 1对应的传输数据指令 以及仲裁单元 2对应的传输数据指令， 则确定至少两个仲裁单元对应的通 道有数据要传输； 其中， 每个仲裁单元对应的传输数据指令中的源地址不 同。
二、 每个仲裁单元对应的传输数据指令中的目的地址不同；
以图 3为例， 若第一通道对应仲裁单元 1， 第二通道对应仲裁单元 2， 第一通道和第二通道对应的源地址为 PC，第一通道对应的数据标识为 Al， 第一通道对应的目的地址为 ROM,第二通道对应的目的地址为 ACC， 第二 通道对应的数据标识为 Al， 则仲裁单元 1对应的传输数据指令包括 PC、 ROM以及 Al， 仲裁单元 2对应的传输数据指令包括 PC、 ACC以及 Al， 在设定时间内， 总线控制器收到来自仲裁单元 1 对应的传输数据指令以及 仲裁单元 2对应的传输数据指令， 则确定至少两个仲裁单元对应的通道有 数据要传输；其中，每个仲裁单元对应的传输数据指令中的目的地址不同。
三、 每个仲裁单元对应的传输数据指令中的数据标识不同。
以图 3为例， 若第一通道对应仲裁单元 1， 第二通道对应仲裁单元 2， 第一通道和第二通道对应的源地址为 PC， 第一通道和第二通道对应的对应 的目的地址为 ROM, 第一通道对应的数据标识为 Al， 第二通道对应的数 据标识为 A2，则仲裁单元 1对应的传输数据指令包括 PC、 ROM以及 Al， 仲裁单元 2对应的传输数据指令包括 PC、 ROM以及 A2， 在设定时间内， 总线控制器收到来自仲裁单元 1对应的传输数据指令以及仲裁单元 2对应 的传输数据指令， 则确定至少两个仲裁单元对应的通道有数据要传输； 其 中， 每个仲裁单元对应的传输数据指令中的数据标识不同。
方式二、 在设定时间段内收到的来自至少两个仲裁单元的传输指令， 确定至少两个仲裁单元对应的通道有数据要传输。
其中，设定时间段可以是任何时间段，比如 lms (毫秒）， 100us(微秒）， 可以根据需要设定。
当设定时间段的值为 0 时， 即在同时接收到至少两个仲裁单元对应的 传输数据指令后， 确定至少两个仲裁单元对应的通道有数据要传输的情况 同样适用于本发明实施例。
其中， 仲裁单元发送传输指令， 用于通知总线控制器该仲裁单元对应 的通道有数据要进行传输。
较佳地， 根据所述至少两个仲裁单元的优先级传输数据包括： 先处理优先级高的仲裁单元对应的传输数据指令， 即先传输优先级高 的仲裁单元对应的通道的数据。
其中， 仲裁单元的优先级越高， 传输仲裁单元对应的通道的数据的速 率越大。
其中， 如果在设定时间段内收到来自一个仲裁单元的传输指令， 则无 需判断该仲裁单元的优先级， 直接传输该仲裁单元对应的通道的数据。
其中， 仲裁单元的优先级可以有总线控制器进行存储， 也可以由其它 存储实体进行存储， 当需要用到仲裁单元的优先级时， 总线控制器到其它 存储实体调取。
本发明实施例是以存在三个仲裁单元， 五个 DMA通道为例进行说明， 需要说明的是， 本发明实施例并不局限于三个仲裁单元， 五个 DMA通道， 针对不同的应用需求， 其他情况也适用本发明实施例， 针对其他情况的实 施方式与本发明实施例的实施方式类似， 在此不再赘述。
步骤 401、 第一硬件模块通过第一通道向仲裁单元 1发送 DMA请求， 请求将数据 M从地址 A传输到地址 B; 第三硬件模块通过第三通道向仲裁 单元 1发送 DMA请求， 请求将数据 N从地址 C传输到地址 D; 第四硬件 模块通过第四通道向仲裁单元 1发送 DMA请求， 请求将数据 0从地址 E 传输到地址 F;
其中， 所有的硬件模块第一次发送 DMA请求时，要通过各自的通道向 同一个仲裁单元发送 DMA请求。
实施中，所有的硬件模块同时向哪个仲裁单元发送 DMA请求可以根据 需要设定， 比如同时向仲裁单元 1发送 DMA请求。
实施中，第一硬件模块可以通过第一通道向仲裁单元 1发送 DMA请求， 请求将数据 M从地址 A传输到地址 B; 第一硬件模块也可以通过第一通道 向仲裁单元 1发送 DMA请求， 请求将数据 M从地址 A传输到地址 B; 通 过第二通道向仲裁单元 1发送 DMA请求， 请求将数据 N从地址 A传输到 地址 B， 具体可以根据需要设定。
步骤 402、 仲裁单元 1在收到来自硬件模块的 DMA请求时， 通过固定 优先级或者 round-robin (轮询） 方式确定传输哪个通道对应的数据， 并向 总线命令产生器 1 发送传输该通道对应的数据的指令， 指示总线命令产生 器 1 确定该通道对应的源地址、 该通道对应的目的地址以及该通道对应的 数据标识；
其中， 仲裁单元 1通过固定优先级或者 round-robin方式确定传输哪个 通道对应的数据的实施方式与图 2 中仲裁单元通过固定优先级或者 round-robin方式确定传输哪个通道对应的数据的实施方式相同， 在此不再 赘述。
步骤 403、 总线命令产生器 1根据收到的来自仲裁单元 1的指令， 确定 该通道对应的源地址、 该通道对应的目的地址以及该通道对应的数据标识； 步骤 404、针对第一硬件模块、第三硬件模块以及第四硬件模块的 DMA 请求， 仲裁单元 1根据固定优先级或者 round-robin方式发送三条传输该通 道对应的数据的指令， 总线命令产生器 1 确定多组通道对应的源地址、 通 道对应的目的地址以及通道对应的数据标识； 步骤 405、在确定一组通道对应的源地址、通道对应的目的地址以及通 道对应的数据标识后， 总线命令产生器 1会向总线命令队列 1发送确定的 一组通道对应的源地址、 通道对应的目的地址以及通道对应的数据标识； 步骤 406、 总线命令队列 1存储接收到的多组通道对应的源地址、通道 对应的目的地址以及通道对应的数据标识； 对应的目的地址以及通道对应的数据标识。
步骤 407、总线命令队列 1采用先入先出的方式将存储的多组通道对应 的源地址、 通道对应的目的地址以及通道对应的数据标识中的一组确定为 一条传输数据指令， 并向总线控制器发送；
其中， 传输数据指令包含源地址、 目的地址以及数据标识， 指示获取 源地址中数据标识对应的数据， 并传输到目的地址。
步骤 408、 总线控制器接收到来自总线命令队列 1的传输数据指令后， 确定源地址、 目的地址以及数据标识， 并向数据通路发送包含确定的源地 址以及数据标识的获取数据指令；
步骤 409、 总线控制器在发出获取数据指令的同时， 向性能确定模块发 送指令， 指示性能确定模块中设定的定时器开始定时；
步骤 410、数据通路到源地址中获取数据标识对应的数据， 并将数据发 送给总线控制器；
步骤 411、 总线控制器在收到来自数据通路的数据的同时， 向性能确定 模块发送指令， 指示性能确定模块中设定的定时器停止定时， 并向性能确 定模块发送收到的数据的数据量信息；
步骤 412、 总线控制器将收到来自数据通路的数据传输到目的地址； 步骤 413、性能确定模块确定传输该通道对应的数据的传输时间和传输 容量， 并计算出传输该通道对应的数据的速率；
步骤 414、性能确定模块将计算出的传输该通道对应的数据的速率发送 给仲裁单元确定模块；
步骤 415、仲裁单元确定模块确定收到的传输该通道对应的数据的速率 所在的阈值范围， 根据仲裁单元与阈值范围的对应关系， 确定传输该通道 对应的数据的速率所在的阈值范围对应的仲裁单元， 并确定阈值范围对应 的仲裁单元为该通道对应的仲裁单元；
步骤 416、 针对每个仲裁单元， 仲裁单元根据收到的 DMA请求确定该 仲裁单元对应的通道有数据要进行传输；
针对仲裁单元、 总线命令产生器以及总线命令队列的交互， 参见执行 步骤 402〜步骤 407;
步骤 417、总线控制器确定至少两个仲裁单元对应的通道有数据要传输 时， 根据所述至少两个仲裁单元的优先级传输数据。
其中， 步骤 417的实施方式见本发明图 2的实施方式。
基于同一发明构思， 本发明实施例中还提供了一种传输数据的设备、 接收设备， 由于该设备解决问题的原理与本发明实施例的方法相似， 因此 该设备的实施可以参见方法的实施， 重复之处不再赘述。
图 5 为本发明实施例传输数据的设备结构示意图， 如图所示， 本发明 实施例的传输数据的设备包括：
确定模块 501， 配置为针对一个直接内存存取 DMA通道， 根据该通道 的数据对应的传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元； 处理模块 502，配置为确定至少两个仲裁单元对应的通道有数据要传输 时， 根据所述至少两个仲裁单元的优先级确定进行传输的数据。
较佳地，针对一个直接内存存取 DMA通道，该通道的数据对应的传输 性能为传输该通道对应的数据的传输时间或传输该通道对应的数据的速率； 确定模块 501，配置为确定传输该通道对应的数据的传输时间或传输该 通道对应的数据的速率。
较佳地， 针对该通道的数据对应的传输性能为传输该通道对应的数据 的速率； 确定模块 501， 配置为确定传输该通道对应的数据的传输时间和传 输容量， 并根据所述传输时间和传输容量确定该通道的数据对应的传输性 6
Fi匕t！。
较佳地， 确定模块 501， 配置为确定该通道的数据对应的传输性能所在 的阈值范围， 根据仲裁单元与阈值范围的对应关系， 确定该通道的数据对 应的传输性能所在的阈值范围对应的仲裁单元， 并将确定所述阈值范围对 应的仲裁单元为该通道对应的仲裁单元。
较佳地， 处理模块 502， 配置为在设定时间段内接收到至少两个仲裁单 元对应的传输数据指令后， 确定至少两个仲裁单元对应的通道有数据要传 输， 其中， 每个仲裁单元对应的传输数据指令不同。
较佳地， 所述传输数据指令包括源地址、 目的地址以及数据标识； 每 个仲裁单元对应的传输数据指令不同包括下列中的一种或多种： 每个仲裁 单元对应的传输数据指令中的源地址不同； 每个仲裁单元对应的传输数据 指令中的目的地址不同； 每个仲裁单元对应的传输数据指令中的数据标识 不同。
其中， 本发明传输数据的设备的实施例中， 确定模块 501 相当于本发 明实施例的仲裁结构（见图 3 )中的仲裁单元确定模块， 处理模块 502相当 于本发明实施例的仲裁结构中的总线控制器； 在确定模块 501， 配置为确定 传输该通道对应的数据的传输时间和传输容量， 并根据所述传输时间和传 输容量确定该通道的数据对应的传输性能时， 确定模块 501 还相当于本发 明实施例的仲裁结构中的性能确定模块。
另外， 所述确定模块 501、处理模块 502均可由所述设备中的中央处理 器（ CPU， Central Processing Unit )、 处理器（ MPU, Micro Processing Unit )、 数字信号处理器（ DSP, Digital Signal Processor )或可编程逻辑阵列（ FPGA， Field - Programmable Gate Array ) 实现。
较佳地，本发明实施例还包括如图 3所示的 DMA通道、总线命令产生 器以及总线命令队列等， 发送 DMA请求的硬件模块、 DMA通道、 总线命 令产生器、 总线命令队列以及数据通路单元等的实施方式详见本发明图 2 的实施和本发明图 4的实施。
其中，上述是以存在有限个 DMA通道、仲裁单元确定模块、仲裁单元、 总线命令产生器、 总线命令队列为例进行介绍， 实施中， DMA通道、 仲 裁单元确定模块、 仲裁单元、 总线命令产生器、 总线命令队列的数量可以 根据需要而定， 然而需要满足： DMA通道、 仲裁单元确定模块、 仲裁单 元、 总线命令产生器、 总线命令队列的数量相同。
本领域内的技术人员应明白， 本发明的实施例可提供为方法、 系统、 或计算机程序产品。 因此， 本发明可采用完全硬件实施例、 完全软件实施 例、 或结合软件和硬件方面的实施例的形式。 而且， 本发明实施例可采用 在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质 (包 括但不限于磁盘存储器、 CD-ROM、 光学存储器等）上实施的计算机程序 产品的形式。
本发明是参照根据本发明实施例的方法、 设备（系统）、 和计算机程序 产品的流程图和 /或方框图来描述的。 应理解可由计算机程序指令实现流 程图和 /或方框图中的每一流程和 /或方框、 以及流程图和 /或方框图中 的流程和 /或方框的结合。 可提供这些计算机程序指令到通用计算机、 专 用计算机、 嵌入式处理机或其他可编程数据处理设备的处理器以产生一个 机器， 使得通过计算机或其他可编程数据处理设备的处理器执行的指令产 生用于实现在流程图一个流程或多个流程和 /或方框图一个方框或多个方 框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理 设备以特定方式工作的计算机可读存储器中， 使得存储在该计算机可读存 储器中的指令产生包括指令装置的制造品， 该指令装置实现在流程图一个 流程或多个流程和 /或方框图一个方框或多个方框中指定的功能。 这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上， 使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现 的处理， 从而在计算机或其他可编程设备上执行的指令提供用于实现在流 程图一个流程或多个流程和 /或方框图一个方框或多个方框中指定的功能 的步骤。
尽管已描述了本发明的优选实施例， 但本领域内的技术人员一旦得知 了基本创造性概念， 则可对这些实施例作出另外的变更和修改。 所以， 所 附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和 修改。 本发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权 利要求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在 内。

Claims

权利要求书
1、 一种传输数据的方法， 该方法包括：
针对一个直接内存存取 DMA通道，根据该通道的数据对应的传输性 能， 从多个仲裁单元中确定该通道对应的仲裁单元；
确定至少两个仲裁单元对应的通道有数据要传输时， 根据所述至少 两个仲裁单元的优先级传输数据。
2、 如权利要求 1所述的方法， 其中， 所述该通道的数据对应的传输 性能为传输该通道对应的数据的传输时间或传输该通道对应的数据的速 率。
3、 如权利要求 2所述的方法， 其中， 所述该通道的数据对应的传输 性能为传输该通道对应的数据的速率， 确定该通道的数据对应的传输性 能包括：
确定传输该通道对应的数据的传输时间和传输容量；
根据所述传输时间和传输容量确定该通道的数据对应的数据的速率。
4、 如权利要求 1所述的方法， 其中， 所述根据该通道的数据对应的 传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元包括：
确定该通道的数据对应的传输性能所在的阈值范围；
根据仲裁单元与阈值范围的对应关系， 确定该通道的数据对应的传 输性能所在的阈值范围对应的仲裁单元， 并将确定所述阈值范围对应的 仲裁单元为该通道对应的仲裁单元。
5、 如权利要求 1所述的方法， 其中， 所述确定至少两个仲裁单元对 应的通道有数据要传输包括：
在设定时间段内接收到至少两个仲裁单元对应的传输数据指令后， 确定至少两个仲裁单元对应的通道有数据要传输；
其中， 每个仲裁单元对应的传输数据指令不同。
6、如权利要求 5所述的方法，其中，所述传输数据指令包括源地址、 目的地址以及数据标识；
每个仲裁单元对应的传输数据指令不同包括下列中的一种或多种： 每个仲裁单元对应的传输数据指令中的源地址不同；
每个仲裁单元对应的传输数据指令中的目的地址不同；
每个仲裁单元对应的传输数据指令中的数据标识不同。
7、 一种传输数据的设备， 该设备包括：
确定模块， 配置为针对一个直接内存存取 DMA通道，根据该通道的 数据对应的传输性能， 从多个仲裁单元中确定该通道对应的仲裁单元； 处理模块， 配置为确定至少两个仲裁单元对应的通道有数据要传输 时， 根据所述至少两个仲裁单元的优先级确定进行传输的数据。
8、 如权利要求 7所述的设备， 其中， 该通道的数据对应的传输性能 为传输该通道对应的数据的传输时间或传输该通道对应的数据的速率； 所述确定模块， 配置为确定传输该通道对应的数据的传输时间或传 输该通道对应的数据的速率。
9、 如权利要求 8所述的设备， 其中， 所述该通道的数据对应的传输 性能为传输该通道对应的数据的速率；
所述确定模块， 配置为确定传输该通道对应的数据的传输时间和传 输容量， 并根据所述传输时间和传输容量确定该通道的数据对应的传输 性能。
10、 如权利要求 7 所述的设备， 其中， 所述确定模块， 配置为确定 该通道的数据对应的传输性能所在的阈值范围， 根据仲裁单元与阈值范 围的对应关系， 确定该通道的数据对应的传输性能所在的阈值范围对应 的仲裁单元， 并将确定所述阈值范围对应的仲裁单元为该通道对应的仲 裁单元。
11、 如权利要求 7所述的设备， 其中， 所述处理模块， 配置为在设定 时间段内接收到至少两个仲裁单元对应的传输数据指令后， 确定至少两 个仲裁单元对应的通道有数据要传输， 其中， 每个仲裁单元对应的传输 数据指令不同。
12、 如权利要求 11所述的设备， 其中， 所述传输数据指令包括源地 址、 目的地址以及数据标识； 每个仲裁单元对应的传输数据指令不同包 括下列中的一种或多种： 每个仲裁单元对应的传输数据指令中的源地址 不同； 每个仲裁单元对应的传输数据指令中的目的地址不同； 每个仲裁 单元对应的传输数据指令中的数据标识不同。
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