WO2014048269A1 - Communication circuit for automatically performing transceiving control on rs485 - Google Patents

Communication circuit for automatically performing transceiving control on rs485 Download PDF

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Publication number
WO2014048269A1
WO2014048269A1 PCT/CN2013/083799 CN2013083799W WO2014048269A1 WO 2014048269 A1 WO2014048269 A1 WO 2014048269A1 CN 2013083799 W CN2013083799 W CN 2013083799W WO 2014048269 A1 WO2014048269 A1 WO 2014048269A1
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terminal
data
communication chip
enable
data input
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PCT/CN2013/083799
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French (fr)
Chinese (zh)
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方晓云
廖松荣
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广东易事特电源股份有限公司
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Publication of WO2014048269A1 publication Critical patent/WO2014048269A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Definitions

  • RS-485 interface has good anti-noise, long transmission distance and multi-station transmission capability
  • An object of the present invention is to provide an automatic transmission and reception control RS485 communication circuit capable of effectively eliminating an interference signal generated by a data delay when a communication chip RS485 is changed in transmission and reception state by avoiding the above-mentioned deficiencies in the prior art.
  • An automatic transmission and reception control RS485 communication circuit which includes a TTL level signal output terminal Rx that outputs a TTL level, a TTL level signal input terminal Tx that receives an external TTL level, and a transmission/reception control signal.
  • the enable terminal /RE of the terminal R0 and the enable terminal DE of the data input terminal DI of the communication chip RS48 are connected to the transceiver control signal terminal ,, and the connection between the enable terminal / RE and the enable terminal DE is enabled.
  • the hopping signal of the energy terminal/RE is delayed by the falling edge delay circuit of the hopping signal of the enabling terminal DE.
  • the falling edge delay circuit includes a storage capacitor Cl, a discharge resistor R1, and an isolation diode D1 that isolates the enable terminal /RE and the enable terminal DE when the energy storage capacitor C1 is released.
  • a transient voltage suppression diode D3 is connected between the data input/output terminal A and the data input/output terminal B of the communication chip RS485, and a transient voltage suppression diode is connected between the data input/output terminal A and the power ground.
  • D4 a transient voltage suppression diode D2 is connected between the data input/output terminal B and the power ground.
  • the process of enabling the threshold of the enable terminal/RE from the high level to the low level is delayed due to the presence of the delay circuit On the enable side DE, That is, there is a time slot between the transmission state and the reception state of the communication chip RS485. In this time slot, the enable terminal /RE is at a high level, the enable terminal DE is at a low level, and the communication chip RS485 is neither transmitting.
  • the state is not in the receiving state, so that the data to be sent is smoothly sent out from its input and output terminals, ensuring that the data input and output data of the data chip is the data to be received when the communication chip RS485 is turned into the receiving state, instead of staying in the data due to the delay.
  • the data to be sent at the input and output end effectively avoids the delay of the data transmission due to the delay of the data transmission when the communication chip RS485 changes from the transmitting state to the receiving state, so that the communication chip RS485 receives a small amount of data to be transmitted, and generates an interference signal.
  • the circuit has a simple structure, requires fewer components, and has low cost. At the same time, the effect is obvious and is not affected by the data frequency.
  • Figure 1 is a circuit diagram of the prior art.
  • FIG. 2 is a circuit diagram of an embodiment of an automatic transmission and reception control RS485 communication circuit of the present invention. detailed description
  • a specific implementation manner of an automatic transceiver control RS485 communication circuit includes: a TTL level signal output terminal Rx that outputs a TTL level, and a TTL level signal input terminal that receives an external TTL level.
  • the data output terminal R0 of the communication chip RS48 is connected to the TTL level signal output terminal Rx, and the data input terminal DI and the TTL battery are connected to the receiving/transmitting control signal terminal ⁇ and the communication chip RS485.
  • the process of enabling the threshold of the enable terminal/RE from the high level to the low level is delayed by DE due to the presence of the delay circuit.
  • the level change process of the enable/RE-enable terminal DE changes from high-high to high-low, then to low-low, and the prior art enable/RE-enable DE
  • the flat change process is directly changed from high-high to low-low; it can be seen that in the embodiment, the communication chip RS485 has a time slot during the transition from the transmission state to the reception state, in which the enable terminal/RE is high.
  • Level, enable terminal DE is low level
  • communication chip RS485 is neither in the transmitting state nor in the receiving state, so that the smooth data of the data to be transmitted is sent from its input and output terminal A and data input and output terminal B, ensuring that When the communication chip RS485 is turned into the receiving state, the data of the data input/output terminal A and the data input/output terminal B is the data to be received, and the data to be transmitted which stays at the data input/output terminal A and the data input/output terminal B due to the delay.
  • the output of the E terminal of the receive/transmit control signal changes from low level to high level, even if the low level of the enable terminal /RE is maintained for a short period of time, the enable terminal DE is already high level.
  • the communication chip RS485 operates in the transmission state as long as the enable terminal DE is at the high level. Therefore, when the output of the E terminal of the receiving/transmitting control signal is changed from the low level to the high level, the input/output terminal A and the data input/output terminal B will not receive the signal just sent out. Therefore, the circuit can effectively avoid the communication chip RS485 receiving a small period of data to be transmitted due to the delay of the data transmission when the communication chip RS485 changes from the transmission state to the reception state, and generates an interference signal.
  • the circuit has a simple structure, requires fewer components, and has low cost. At the same time, the effect is obvious and is not affected by the data frequency.
  • the falling edge delay circuit 1 includes a storage capacitor C1, a discharge resistor R1, and an isolation diode D1 that isolates the enable terminal /RE and the enable terminal DE when the storage capacitor C1 is released.
  • the charging and discharging of the storage capacitor can delay the level of the enabling terminal/RE.
  • the transition diode D1 can isolate the delay signal when the enable terminal /RE changes from high level to low level, that is, when the storage capacitor C1 discharges the discharge, so that the level of the enable terminal / RE There is a delay between the signal and the level signal of the enable terminal DE.
  • a transient voltage suppression diode D3 is connected between the data input/output terminal A and the data input/output terminal B of the communication chip RS485, and a transient voltage suppression diode is connected between the data input/output terminal A and the power ground.
  • D4 a transient voltage suppression diode D2 is connected between the data input/output terminal B and the power ground.

Abstract

The present invention relates to the technical field of communications circuits, and in particular to a communication circuit for automatically performing transceiving control on RS485. The circuit comprises a communication chip RS485, an enable end /RE of a data output end RO of the communication chip RS485 and an enable end DE of a data input end DI of the communication chip RS485 being connected to a transceiving control signal end E, and a delay circuit being connected between the enable end /RE and the enable end DE, wherein the delay circuit enables a transition signal of the enable end /RE to delay to a falling edge of a transition signal of the enable end DE. Therefore, when the communication chip RS485 is converted from the sending state to the receiving state, the technical solution of the present invention effectively avoids the condition that the communication chip RS485 receives a bit of data to be sent due to data transmission delay and an interference signal is generated. The circuit has a simple structure, needs few components, and has a low cost; and moreover, achieves an obvious effect without being affected by the data frequency.

Description

一种自动收发控制 RS485通信电路 技术领域 本发明涉及通信电路技术领域， 特别涉及一种自动收发控制 RS485通信电 路。 背景技术 说  TECHNICAL FIELD The present invention relates to the field of communication circuit technologies, and in particular, to an automatic transmission and reception control RS485 communication circuit. Background art
RS-485接口由于具有良好的抗噪音干扰性， 传输距离长及多站传输能力等 书 RS-485 interface has good anti-noise, long transmission distance and multi-station transmission capability
优点， 因此其成为首选的串行接口。 其接口的最大传输距离可达 1200 米， 可 组成半双工或全双工网络， 采用屏蔽双绞线传输， 接口连接器采用 DB-9 的 9 芯插头座。允许连接多达 256 个节点数。常见的 RS485通信芯片具有如下管脚： 数据输出端 R0、 数据输入端 DI， R0的使能端/ RE、 DI的使能端 DE以及数据 输入输出端 A和 B, 同时 RS485芯片采用发送优先原则，只要 DE端为高电平， 那么无论/ RE端电平状态如何， RS485芯片都工作在发送状态，只有当 DE和/ RE 两端都为低电平时， 芯片才工作在接收状态。 现有技术中，通常将 /RE端和 DE端两引脚连接在一起并同时与一个收发控 制信号连接， 如图 1所示， 当收发控制信号为高电平时， DE有效， 芯片处于发 送状态， 当控制器向这两端输入低电平时， /RE 有效， 芯片处于接收状态。 从 原理上讲这种接法简单可行。但在实际应用中， 当 DE和/ RE两端同时由高电平 转为低电平时， 芯片会立刻由发送状态转为接收状态， 由于数据传输会有延时， 此时发送出去的数据还在 A、 B两端甚至还在芯片内， 所以 RS485芯片会接收 到一小段刚发送出去的电平信号， 成为一段干扰信号。 要滤除这个干扰信号采 用一般的电容滤波效果不太显， 往往需要采用一些三极管、 光耦之类的器件， 不仅大大增加了成本， 而且当需要传输的数据频率较高时还会受到光耦和三极 管开关速度的限制。 The advantage, therefore it becomes the preferred serial interface. The interface has a maximum transmission distance of 1200 meters and can be used as a half-duplex or full-duplex network. It is shielded and twisted-pair. The interface connector uses a DB-9 9-pin connector. Allows connection of up to 256 nodes. The common RS485 communication chip has the following pins: data output terminal R0, data input terminal DI, R0 enable terminal / RE, DI enable terminal DE and data input and output terminals A and B, while RS485 chip adopts the transmission priority principle. As long as the DE terminal is high, the RS485 chip operates in the transmit state regardless of the state of the /RE terminal. The chip operates in the receive state only when both DE and /RE are low. In the prior art, the two pins of the /RE terminal and the DE terminal are usually connected together and simultaneously connected with a transceiver control signal. As shown in FIG. 1, when the transceiver control signal is at a high level, DE is valid, and the chip is in a transmitting state. When the controller inputs a low level to both ends, /RE is valid and the chip is in the receiving state. In principle, this connection is simple and feasible. However, in practical applications, when both ends of DE and /RE turn from high level to low level at the same time, the chip will immediately change from the transmitting state to the receiving state. Since the data transmission will have a delay, the data sent at this time is still At both ends of A and B, even in the chip, the RS485 chip will receive a small level of signal that has just been sent out, becoming an interference signal. To filter out this interference signal, the general capacitance filtering effect is not obvious, and it is often necessary to use some devices such as a triode or an optocoupler. Not only does it add significant cost, but it is also limited by the optocoupler and triode switching speeds when the frequency of data that needs to be transmitted is high.
发明内容 Summary of the invention
本发明的目的在于避免上述现有技术中的不足之处而提供一种能够有效消 除通信芯片 RS485收发状态改变时由于数据延时产生的干扰信号的自动收发控 制 RS485通信电路。  SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic transmission and reception control RS485 communication circuit capable of effectively eliminating an interference signal generated by a data delay when a communication chip RS485 is changed in transmission and reception state by avoiding the above-mentioned deficiencies in the prior art.
本发明的目的通过以下技术方案实现：  The object of the invention is achieved by the following technical solutions:
提供了一种自动收发控制 RS485通信电路，包括向外输出 TTL电平的 TTL 电平信号输出端 Rx、 接收外部 TTL电平的 TTL电平信号输入端 Tx、 发送收 / 发控制信号的收 /发控制信号端 Ε以及通信芯片 RS485, 所述通信芯片 RS48的 数据输出端 R0 与 TTL电平信号输出端 Rx连接， 所述数据输入端 DI 与 TTL 电平信号输入端 Tx连接， 所述数据输出端 R0 的使能端/ RE和所述通信芯片 RS48的数据输入端 DI的使能端 DE与收发控制信号端 Ε连接，所述使能端/ RE 与使能端 DE之间连接有使使能端 /RE的跳变信号延迟于使能端 DE的跳变信号 的下降沿延时电路。  An automatic transmission and reception control RS485 communication circuit is provided, which includes a TTL level signal output terminal Rx that outputs a TTL level, a TTL level signal input terminal Tx that receives an external TTL level, and a transmission/reception control signal. a control signal terminal Ε and a communication chip RS485, wherein the data output terminal R0 of the communication chip RS48 is connected to the TTL level signal output terminal Rx, and the data input terminal DI is connected to the TTL level signal input terminal Tx, the data output The enable terminal /RE of the terminal R0 and the enable terminal DE of the data input terminal DI of the communication chip RS48 are connected to the transceiver control signal terminal ,, and the connection between the enable terminal / RE and the enable terminal DE is enabled. The hopping signal of the energy terminal/RE is delayed by the falling edge delay circuit of the hopping signal of the enabling terminal DE.
其中， 所述下降沿延时电路包括储能电容 Cl、 释能电阻 R1以及在储能电 容 C1释能时隔离使能端/ RE和使能端 DE的隔离二极管 Dl。  The falling edge delay circuit includes a storage capacitor Cl, a discharge resistor R1, and an isolation diode D1 that isolates the enable terminal /RE and the enable terminal DE when the energy storage capacitor C1 is released.
其中，在所述通信芯片 RS485的数据输入输出端 A和数据输入输出端 B之 间连接有瞬态电压抑制二极管 D3 ,所述数据输入输出端 A与电源地之间连接有 瞬态电压抑制二极管 D4,所述数据输入输出端 B与电源地之间连接有瞬态电压 抑制二极管 D2。  A transient voltage suppression diode D3 is connected between the data input/output terminal A and the data input/output terminal B of the communication chip RS485, and a transient voltage suppression diode is connected between the data input/output terminal A and the power ground. D4, a transient voltage suppression diode D2 is connected between the data input/output terminal B and the power ground.
本发明的有益效果： 在收发控制信号端 E由高电平转为低电平时， 由于延 时电路的存在，使能端/ RE由高电平降到低电平的阀值的过程延后于使能端 DE， 即通信芯片 RS485由发送状态转为接收状态之间存在一段时隙， 在该时隙中， 使能端 /RE为高电平， 使能端 DE为低电平， 通信芯片 RS485既不处于发送状 态也不处于接收状态， 使其待发送数据顺利从其输入输出端发送出去， 保证在 通信芯片 RS485转为接收状态时数据输入输出端的数据为需要接收的数据而非 由于延时而停留在数据输入输出端的待发送数据， 有效避免了通信芯片 RS485 从发送状态转为接收状态时由于数据传输存在延时导致通信芯片 RS485会接收 到一小段待发送数据， 产生一段干扰信号。 本电路结构简单， 所需元件少， 成 本低。 同时效果明显， 不受数据频率影响。 Advantageous Effects of the Invention: When the transceiving control signal terminal E changes from a high level to a low level, the process of enabling the threshold of the enable terminal/RE from the high level to the low level is delayed due to the presence of the delay circuit On the enable side DE, That is, there is a time slot between the transmission state and the reception state of the communication chip RS485. In this time slot, the enable terminal /RE is at a high level, the enable terminal DE is at a low level, and the communication chip RS485 is neither transmitting. The state is not in the receiving state, so that the data to be sent is smoothly sent out from its input and output terminals, ensuring that the data input and output data of the data chip is the data to be received when the communication chip RS485 is turned into the receiving state, instead of staying in the data due to the delay. The data to be sent at the input and output end effectively avoids the delay of the data transmission due to the delay of the data transmission when the communication chip RS485 changes from the transmitting state to the receiving state, so that the communication chip RS485 receives a small amount of data to be transmitted, and generates an interference signal. The circuit has a simple structure, requires fewer components, and has low cost. At the same time, the effect is obvious and is not affected by the data frequency.
附图说明 DRAWINGS
利用附图对本发明作进一歩说明， 但附图中的实施例不构成对本发明的任 何限制， 对于本领域的普通技术人员， 在不付出创造性劳动的前提下， 还可以 根据以下附图获得其它的附图。  The present invention will be further described with reference to the drawings, but the embodiments in the drawings do not constitute any limitation to the present invention. For those skilled in the art, other work can be obtained according to the following drawings without any creative work. The drawing.
图 1是现有技术的电路图。  Figure 1 is a circuit diagram of the prior art.
图 2是本发明一种自动收发控制 RS485通信电路的实施例的电路图。 具体实施方式  2 is a circuit diagram of an embodiment of an automatic transmission and reception control RS485 communication circuit of the present invention. detailed description
结合以下实施例对本发明作进一歩描述。  The present invention will be further described in conjunction with the following examples.
本发明一种自动收发控制 RS485通信电路的具体实施方式， 如图 2所示， 包括： 向外输出 TTL电平的 TTL电平信号输出端 Rx、 接收外部 TTL电平的 TTL电平信号输入端 Tx、 发送收 /发控制信号的收 /发控制信号端 Ε以及通信芯 片 RS485, 所述通信芯片 RS48的数据输出端 R0 与 TTL电平信号输出端 Rx 连接， 所述数据输入端 DI 与 TTL电平信号输入端 Tx连接， 所述数据输出端 R0的使能端/ RE和所述通信芯片 RS48的数据输入端 DI的使能端 DE与收 /发控 制信号端 E连接，所述使能端/ RE与使能端 DE之间连接有使使能端 /RE的跳变 信号延迟于使能端 DE的跳变信号的下降沿延时电路 1。 A specific implementation manner of an automatic transceiver control RS485 communication circuit, as shown in FIG. 2, includes: a TTL level signal output terminal Rx that outputs a TTL level, and a TTL level signal input terminal that receives an external TTL level. The data output terminal R0 of the communication chip RS48 is connected to the TTL level signal output terminal Rx, and the data input terminal DI and the TTL battery are connected to the receiving/transmitting control signal terminal Ε and the communication chip RS485. The flat signal input terminal Tx is connected, the enable end of the data output terminal R0 / RE and the enable terminal DE of the data input terminal DI of the communication chip RS48 and the receiving/transmitting control The signal terminal E is connected, and a falling edge delay circuit 1 for delaying the hopping signal of the enable terminal/RE to the hopping signal of the enable terminal DE is connected between the enable terminal/RE and the enable terminal DE.
在收 /发控制信号端 E由高电平转为低电平时， 由于延时电路的存在， 使能 端/ RE 由高电平降到低电平的阀值的过程延后于 DE， 即及使能端/ RE-使能端 DE的电平变化过程为由高 -高转变为高 -低， 再转变为低 -低， 而现有技术使能端 /RE-使能端 DE的电平变化过程为由高-高直接转变为低 -低； 可见本实施例中通 信芯片 RS485在由发送状态转为接收状态期间存在一段时隙， 在该时隙中， 使 能端/ RE为高电平， 使能端 DE为低电平， 通信芯片 RS485既不处于发送状态 也不处于接收状态， 使其待发送数据顺利数据从其输入输出端 A和数据输入输 出端 B发送出去，保证在通信芯片 RS485转为接收状态时数据输入输出端 A和 数据输入输出端 B的数据为需要接收的数据而非由于延时而停留在数据输入输 出端 A和数据输入输出端 B 的待发送数据。 另一方面， 当收 /发控制信号端 E 端输出由低电平转为高电平时， 即使使能端 /RE 的低电平会维持一小段时间， 但使能端 DE早已为高电平， 根据发送优先的原则， 不管使能端 /RE电平状态如 何， 只要使能端 DE为高电平， 则通信芯片 RS485工作在发送状态。 所以， 当收 /发控制信号端 E端输出由低电平转为高电平时，输入输出端 A和数据输入输出 端 B 也不会接收到刚发送出去的信号。 因此本电路能够有效避免了通信芯片 RS485从发送状态转为接收状态时由于数据传输存在延时导致通信芯片 RS485 会接收到一小段待发送数据， 产生一段干扰信号。 本电路结构简单， 所需元件 少， 成本低。 同时效果明显， 不受数据频率影响。  When the receiving/transmitting control signal terminal E changes from a high level to a low level, the process of enabling the threshold of the enable terminal/RE from the high level to the low level is delayed by DE due to the presence of the delay circuit. And the level change process of the enable/RE-enable terminal DE changes from high-high to high-low, then to low-low, and the prior art enable/RE-enable DE The flat change process is directly changed from high-high to low-low; it can be seen that in the embodiment, the communication chip RS485 has a time slot during the transition from the transmission state to the reception state, in which the enable terminal/RE is high. Level, enable terminal DE is low level, communication chip RS485 is neither in the transmitting state nor in the receiving state, so that the smooth data of the data to be transmitted is sent from its input and output terminal A and data input and output terminal B, ensuring that When the communication chip RS485 is turned into the receiving state, the data of the data input/output terminal A and the data input/output terminal B is the data to be received, and the data to be transmitted which stays at the data input/output terminal A and the data input/output terminal B due to the delay. On the other hand, when the output of the E terminal of the receive/transmit control signal changes from low level to high level, even if the low level of the enable terminal /RE is maintained for a short period of time, the enable terminal DE is already high level. According to the principle of transmission priority, regardless of the state of the enable/RE level, the communication chip RS485 operates in the transmission state as long as the enable terminal DE is at the high level. Therefore, when the output of the E terminal of the receiving/transmitting control signal is changed from the low level to the high level, the input/output terminal A and the data input/output terminal B will not receive the signal just sent out. Therefore, the circuit can effectively avoid the communication chip RS485 receiving a small period of data to be transmitted due to the delay of the data transmission when the communication chip RS485 changes from the transmission state to the reception state, and generates an interference signal. The circuit has a simple structure, requires fewer components, and has low cost. At the same time, the effect is obvious and is not affected by the data frequency.
其中， 所述下降沿延时电路 1包括储能电容 Cl、 释能电阻 R1以及在储能 电容 C1释能时隔离使能端/ RE和使能端 DE的隔离二极管 Dl。 在收 /发控制信 号端 E的电平产生跳变时， 储能电容的充放电能够使对使能端 /RE的电平延迟 跳变， 同时隔离二极管 Dl能够在使能端 /RE由高电平逐歩变为低电平时， 即储 能电容 C1放电释能时隔离该延时信号， 使使能端/ RE的电平信号和使能端 DE 的电平信号之间存在延时。 The falling edge delay circuit 1 includes a storage capacitor C1, a discharge resistor R1, and an isolation diode D1 that isolates the enable terminal /RE and the enable terminal DE when the storage capacitor C1 is released. When the level of the receiving/transmitting control signal terminal E is changed, the charging and discharging of the storage capacitor can delay the level of the enabling terminal/RE. The transition diode D1 can isolate the delay signal when the enable terminal /RE changes from high level to low level, that is, when the storage capacitor C1 discharges the discharge, so that the level of the enable terminal / RE There is a delay between the signal and the level signal of the enable terminal DE.
其中，在所述通信芯片 RS485的数据输入输出端 A和数据输入输出端 B之 间连接有瞬态电压抑制二极管 D3 ,所述数据输入输出端 A与电源地之间连接有 瞬态电压抑制二极管 D4,所述数据输入输出端 B与电源地之间连接有瞬态电压 抑制二极管 D2。 本部分电路加强了通信芯片 RS485的数据输入输出端 A和数 据输入输出端 B的抗干扰能力， 改善电路的总体通信效果。 同时也保护了本电 路的电子元件。  A transient voltage suppression diode D3 is connected between the data input/output terminal A and the data input/output terminal B of the communication chip RS485, and a transient voltage suppression diode is connected between the data input/output terminal A and the power ground. D4, a transient voltage suppression diode D2 is connected between the data input/output terminal B and the power ground. This part of the circuit enhances the anti-interference ability of the data input/output terminal A and the data input/output terminal B of the communication chip RS485, and improves the overall communication effect of the circuit. It also protects the electronic components of the circuit.
最后应当说明的是， 以上实施例仅用以说明本发明的技术方案， 而非对本 发明保护范围的限制， 尽管参照较佳实施例对本发明作了详细地说明， 本领域 的普通技术人员应当理解， 可以对本发明的技术方案进行修改或者等同替换， 而不脱离本发明技术方案的实质和范围。  It should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention, and are not intended to limit the scope of the present invention. Although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art should understand The technical solutions of the present invention may be modified or equivalently substituted without departing from the spirit and scope of the technical solutions of the present invention.

Claims

权 利 要 求 书 Claim
1.一种自动收发控制 RS485通信电路， 包括向外输出 TTL电平的 TTL电 平信号输出端 Rx、 接收外部 TTL电平的 TTL电平信号输入端 Tx、 发送收 /发 控制信号的收 /发控制信号端 Ε以及通信芯片 RS485, 所述通信芯片 RS48的数 据输出端 R0 与 TTL电平信号输出端 Rx连接， 所述数据输入端 DI 与 TTL电 平信号输入端 Tx连接，所述数据输出端 R0的使能端/ RE和所述通信芯片 RS48 的数据输入端 DI的使能端 DE与收发控制信号端 Ε连接， 其特征在于： 所述使 能端/ RE与使能端 DE之间连接有使使能端 /RE的跳变信号延迟于使能端 DE的 跳变信号的下降沿延时电路 （1 )。  1. An automatic transmission and reception control RS485 communication circuit, comprising a TTL level signal output terminal Rx that outputs a TTL level, a TTL level signal input terminal Tx that receives an external TTL level, and a transmission/reception control signal. a control signal terminal Ε and a communication chip RS485, wherein the data output terminal R0 of the communication chip RS48 is connected to the TTL level signal output terminal Rx, and the data input terminal DI is connected to the TTL level signal input terminal Tx, the data output The enable terminal /RE of the terminal R0 and the enable terminal DE of the data input terminal DI of the communication chip RS48 are connected to the transceiver control signal terminal ,, characterized in that: between the enable terminal / RE and the enable terminal DE A falling edge delay circuit (1) having a hopping signal that delays the hopping signal of the enable terminal/RE to the enable terminal DE is connected.
2.如权利要求 1所述的一种自动收发控制 RS485通信电路， 其特征在于： 所述下降沿延时电路 （1 ) 包括储能电容 Cl、 释能电阻 R1 以及在储能电容 C1 释能时隔离使能端/ RE和使能端 DE的隔离二极管 D1。  2 . The automatic transmission and reception control RS485 communication circuit according to claim 1 , wherein: the falling edge delay circuit ( 1 ) comprises a storage capacitor C1, a discharge resistor R1, and an energy storage capacitor C1. The isolation diode D1 is isolated from the enable terminal / RE and the enable terminal DE.
3.如权利要求 1所述的一种自动收发控制 RS485通信电路， 其特征在于： 在所述通信芯片 RS485的数据输入输出端 A和数据输入输出端 B之间连接有瞬 态电压抑制二极管 D3 ,所述数据输入输出端 A与电源地之间连接有瞬态电压抑 制二极管 D4,所述数据输入输出端 B与电源地之间连接有瞬态电压抑制二极管 D2 o  3. The automatic transmission and reception control RS485 communication circuit according to claim 1, wherein: a transient voltage suppression diode D3 is connected between the data input/output terminal A and the data input/output terminal B of the communication chip RS485. A transient voltage suppression diode D4 is connected between the data input/output terminal A and the power ground, and a transient voltage suppression diode D2 is connected between the data input/output terminal B and the power ground.
PCT/CN2013/083799 2012-09-27 2013-09-18 Communication circuit for automatically performing transceiving control on rs485 WO2014048269A1 (en)

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