CN104009902A - Automatic transceiving circuit - Google Patents
Automatic transceiving circuit Download PDFInfo
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- CN104009902A CN104009902A CN201410206818.9A CN201410206818A CN104009902A CN 104009902 A CN104009902 A CN 104009902A CN 201410206818 A CN201410206818 A CN 201410206818A CN 104009902 A CN104009902 A CN 104009902A
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Abstract
The invention discloses an automatic transceiving circuit. The automatic transceiving circuit comprises an RS-485 transceiver and a not gate logic device, wherein the RS-485 transceiver is used for automatically receiving and transmitting data, and the not gate logic device is used for conducting not gate negation on transmitted signals. The input end of the not gate logic device is used for receiving the transmitted signals, and the output end of the not gate logic device is connected with the receiving enabling end and the transmitting enabling end of the RS-485 transceiver. The RS-485 transceiver further comprises a transmitting data end, a receiving data end, an end A and an end B, wherein the transmitting data end is used for receiving the transmitted signals, the receiving data end is used for transmitting receipt signals, and the end A and the end B are used for receiving or transmitting differential signals. According to the automatic transceiving circuit, the RS-485 transceiver is controlled through the not gate logic device, automatic transceiving of communication signals can be achieved without an MCU, expenditure for the MCU can be saved, abnormity of an RS-485 circuit is avoided, the communication baud rate is changed freely, the structure of the circuit is concise, and the area of a circuit board is reduced.
Description
Technical field
The present invention relates to circuit engineering field, particularly relate to a kind of automatic transceiving circuit.
Background technology
At present RS-485 preferred circuit due to allow in dual-wire bus a main equipment drive maximum 32 from equipment, can be applicable to a large amount of telecommunication circuits.Yet because RS-485 is the communication that adopts half-duplex mode, within the some time, it can only carry out a kind of operation (receive or send out), can not carry out two kinds of operations of transmitting-receiving simultaneously.Normally, a pin that utilizes MCU drives the sending/receiving of chip to enable pin to RS-485 and controls, or uses 74HC123 trigger to enable pin to sending/receiving and control.
But the first RS-485 telecommunication circuit, by MCU programming Control sending/receiving enable pin, need to write strict program and guarantee the sequential of switching, and easily causes RS-485 communication abnormality (as being easily placed in normal transmission state).The second RS-485 telecommunication circuit, its logical circuit is more complicated, and is difficult for change baud rate.
Summary of the invention
Based on this, be necessary for above-mentioned RS-485 telecommunication circuit, easily cause the problem of RS-485 communication abnormality, difficult change baud rate, a kind of automatic transceiving circuit is provided.
A kind of automatic transceiving circuit, comprise for the RS-485 transceiver of automatic transceiving data with for transmitted signal being carried out to the not gate logical device of not gate negate, the input of described not gate logical device receives transmitted signal, the reception Enable Pin of output and described RS-485 transceiver with send Enable Pin and be connected, described RS-485 transceiver also comprises transmission data terminal for receiving described transmitted signal, for sending, receives the reception data terminal of signal and hold with B for receiving or send the A end of differential signal.
Above-mentioned automatic transceiving circuit, controls RS-485 by not gate logical device, without MCU, can realize automatic transceiving signal of communication, can save the expense of MCU, avoid RS-485 circuit abnormality, arbitrarily change communication baud rate, and circuit structure is succinct, save board area.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of automatic transceiving circuit the first execution mode of the present invention;
Fig. 2 is the circuit diagram of automatic transceiving circuit the second execution mode of the present invention;
Fig. 3 is the first schematic diagram of receiving and transmitting signal in automatic transceiving circuit of the present invention;
Fig. 4 is the second schematic diagram of receiving and transmitting signal in automatic transceiving circuit of the present invention.
Embodiment
Refer to Fig. 1, Fig. 1 is the circuit diagram of automatic transceiving circuit the first execution mode of the present invention.
The described automatic transceiving circuit of present embodiment comprises for the RS-485 transceiver 100 of automatic transceiving data with for transmitted signal being carried out to the not gate logical device 200 of not gate negate, the input of not gate logical device 200 receives transmitted signal, the reception Enable Pin RXEN of output and RS-485 transceiver 100 with send Enable Pin TXEN and be connected, RS-485 transceiver 100 also comprises transmission data terminal TXD for receiving described transmitted signal, for sending, receives the reception data terminal RXD of signal and hold with B for receiving or send the A end of differential signal.
Automatic transceiving circuit described in present embodiment, controls RS-485 by not gate logical device, without MCU, can realize automatic transceiving signal of communication, can save the expense of MCU, avoid RS-485 circuit abnormality, arbitrarily change communication baud rate, and circuit structure is succinct, save board area.
Wherein, for not gate logical device 200, preferably, can be the combination of a plurality of lists " not gate ", can be also the distortion of non-conjunction.
Preferably, not gate logical device 200 can comprise NAND gate logical circuit, described NAND gate logical circuit comprises for accept first input end and second input of described transmitted signal simultaneously, the reception Enable Pin RXEN of the output of described NAND gate logical circuit and RS-485 transceiver 100 with send Enable Pin TXEN and be connected.Use NAND gate logical circuit can reduce the complexity of circuit as not gate logical device 200.
In the concrete transmitting-receiving process of automatic transceiving circuit of the present invention, described transmitted signal, through 200 negates of not gate logical device, is then transferred to and receives Enable Pin RXEN and send Enable Pin TXEN, to control the transmitting-receiving of RS-485 transceiver.Preferably, when described transmitted signal is high level, after not gate logical device 200, becoming low level transfers to reception Enable Pin RXEN and sends Enable Pin TXEN, RS-485 transceiver 100 receives and enables, by sending data terminal TXD, receive described transmitted signal, and send differential signal by side a and b.When described transmitted signal is low level, after not gate logical device 200, become high level, RS-485 transceiver 100 sends and enables, and by side a and b, receives differential signal, by receiving data terminal RXD, sends described reception signal.
In one embodiment, as shown in Figure 3, described transmitted signal TXD can be time series data, when time series data is 0, TXD makes to receive Enable Pin RXEN and sends Enable Pin TXEN and is set to 1 (high level) after not gate logical device 200, send and enable (reception is forbidden) state, data 0 can be sent to the differential signal line that side a and b is corresponding; When time series data is 1, TXD makes to receive Enable Pin RXEN and sends Enable Pin TXEN and is set to 0 (low level) after not gate logical device 200, send and forbid (reception enables) state, but now receiving terminal is not received ETX end mark position, still in accepting state, can read the data-signal that A end or B hold pull-up resistor on corresponding holding wire and pull down resistor to form " 1 ", receiving terminal can be received the data of " 1 ".
As shown in Figure 4, for DRP data reception process, when TXD transmission data are complete or while not starting to send data, TXD is " 1 ", it is high level state, TXD makes to receive Enable Pin RXEN and sends Enable Pin TXEN and is set to " 0 " (low level) after not gate logical device 200, sends and forbids (reception enables) state, and RXD signal end can intactly receive the data-signal of side a and b.
For RS-485 transceiver 100, be preferably the device that meets RS-485 standard.RS-485 transceiver 100 NAND gate logical devices 200 connect the power supply that supply power voltage is identical.
Preferably, automatic transceiving circuit of the present invention also can comprise that supply power voltage is the power supply of 3.3V, and the output of described power supply is connected with the power end of not gate logical device 200 with RS-485 transceiver 100 respectively.
In other embodiments, the supply power voltage of described power supply also can be 5V or other magnitudes of voltage.
In one embodiment, automatic transceiving circuit of the present invention also can comprise anti-overvoltage circuit, is connected respectively with described A end with described B end.
The automatic transceiving circuit of the present embodiment can prevent that voltage is excessive, avoids circuit to cause damage.
Preferably; described anti-overvoltage circuit comprises anti-overvoltage diode, pull-up resistor, pull down resistor, the first protective resistance and the second protective resistance; the input termination power of described anti-overvoltage diode; output meets described A by described pull-up resistor and holds; described B end is by described pull down resistor ground connection; described the first protective resistance connects described A end, and described the second protective resistance connects described B end.
In another embodiment, automatic transceiving circuit of the present invention also can comprise anti-static circuit, is connected respectively with described A end with described B end.
The automatic transceiving circuit of the present embodiment can antistatic, avoids producing electrostatic hazard.
Preferably, described anti-static circuit comprises a TVS pipe, the 2nd TVS pipe, the 3rd TVS pipe and build-out resistor, A end described in the input termination of a described TVS pipe, output head grounding, B end described in the input termination of described the 2nd TVS pipe, output head grounding, B end described in A end, another termination described in a termination of described the 3rd TVS pipe, described build-out resistor is managed in parallel with described the 3rd TVS.
Referring to Fig. 2, is the circuit diagram of automatic transceiving circuit the second execution mode of the present invention shown in Fig. 2.
Automatic transceiving circuit described in present embodiment and the difference of the first execution mode are: also can comprise anti-static circuit and anti-overvoltage circuit, described A end is connected with described anti-static circuit by described anti-overvoltage circuit with described B end.
Automatic transceiving circuit described in present embodiment, can protect signal of communication, prevents overvoltage and static.
Preferably, RS-485 transceiver 100 can comprise half-duplex RS-485 transceiver U4, half-duplex RS-485 transceiver U4 comprises receiver R and driver D, and receiver R comprises for sending the output RO of described reception signal and for receiving the input Enable Pin of the output signal of not gate logical device 200
, driver D comprises for receiving the input DI of described transmitted signal and for receiving the output enable end DE of the output signal of not gate logical device 200.
Further, the model of half-duplex RS-485 transceiver U4 can be IL83072EIBZA, by VCC termination 3.3V power supply, by GND, holds ground connection.
In one embodiment, described anti-overvoltage circuit comprises anti-overvoltage diode D15, pull-up resistor R589, pull down resistor R595, the first protective resistance R590 and the second protective resistance R594, described anti-static circuit comprises a TVS pipe D16, the 2nd TVS pipe D18, the 3rd TVS pipe D17 and build-out resistor R591, the input termination power of anti-overvoltage diode D15, output meets described A by pull-up resistor R589 and holds, described B end is by pull down resistor R595 ground connection, A end described in a termination of the first protective resistance R590, the other end is by a TVS pipe D16 ground connection, a termination B end of the second protective resistance R594, the other end is by the 2nd TVS pipe D18 ground connection, one end of the 3rd TVS pipe D17 meets described A by the first protective resistance R590 and holds, the other end meets described B by the second protective resistance R594 and holds, build-out resistor R591 is in parallel with the 3rd TVS pipe D17.
Wherein, the resistance value of pull-up resistor R589 and pull down resistor R595 is preferably 680 ohm, and the resistance value of the first protective resistance R590 and the second protective resistance R594 is preferably 10 ohm, and the resistance value of build-out resistor R591 is preferably 150 ohm.
Preferably, the model of overvoltage diode D15 is IN4148, and the model of a TVS pipe D16, the 2nd TVS pipe D18 and the 3rd TVS pipe D17 is UDD32C05L01.
Further, A end or B hold corresponding holding wire to be respectively the communication line between M_HOST_RM_A to A end, the communication line between M_HOST_RM_B to B end.
In another embodiment, NAND gate logical circuit comprises NAND gate device U5, and its first input end 1 and the second input 2 receive described transmitted signal simultaneously, and GND holds ground connection, VCC termination 3.3V power supply, and output Y connects input Enable Pin
with output enable end DE.
Preferably, the model of not gate device U5 is SN74LVC1G00DBV.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an automatic transceiving circuit, it is characterized in that, comprise for the RS-485 transceiver of automatic transceiving data with for transmitted signal being carried out to the not gate logical device of not gate negate, the input of described not gate logical device receives transmitted signal, the reception Enable Pin of output and described RS-485 transceiver with send Enable Pin and be connected, described RS-485 transceiver also comprises transmission data terminal for receiving described transmitted signal, for sending, receives the reception data terminal of signal and hold with B for receiving or send the A end of differential signal.
2. automatic transceiving circuit according to claim 1, it is characterized in that, described not gate logical device comprises NAND gate logical circuit, described NAND gate logical circuit comprises for accept first input end and second input of described transmitted signal simultaneously, the output of described NAND gate logical circuit respectively with the reception Enable Pin of described RS-485 transceiver with send Enable Pin and be connected.
3. automatic transceiving circuit according to claim 1, is characterized in that, also comprises anti-overvoltage circuit, is connected respectively with described A end with described B end.
4. automatic transceiving circuit according to claim 3; it is characterized in that; described anti-overvoltage circuit comprises anti-overvoltage diode, pull-up resistor, pull down resistor, the first protective resistance and the second protective resistance; the input termination power of described anti-overvoltage diode; output meets described A by described pull-up resistor and holds; described B end is by described pull down resistor ground connection, and described the first protective resistance connects described A end, and described the second protective resistance connects described B end.
5. automatic transceiving circuit according to claim 1, is characterized in that, also comprises anti-static circuit, is connected respectively with described A end with described B end.
6. automatic transceiving circuit according to claim 5, it is characterized in that, described anti-static circuit comprises a TVS pipe, the 2nd TVS pipe, the 3rd TVS pipe and build-out resistor, A end described in the input termination of a described TVS pipe, output head grounding, B end described in the input termination of described the 2nd TVS pipe, output head grounding, B end described in A end, another termination described in one termination of described the 3rd TVS pipe, described build-out resistor is in parallel with described the 3rd TVS pipe.
7. automatic transceiving circuit according to claim 1, is characterized in that, also comprises anti-static circuit and anti-overvoltage circuit, and described A end is connected with described anti-static circuit by described anti-overvoltage circuit respectively with described B end.
8. automatic transceiving circuit according to claim 7, it is characterized in that, described anti-overvoltage circuit comprises anti-overvoltage diode, pull-up resistor, pull down resistor, the first protective resistance and the second protective resistance, described anti-static circuit comprises a TVS pipe, the 2nd TVS pipe, the 3rd TVS pipe and build-out resistor, the input termination power of described anti-overvoltage diode, output meets described A by described pull-up resistor and holds, described B end is by described pull down resistor ground connection, A end described in one termination of described the first protective resistance, the other end is by a described TVS pipe ground connection, B end described in one termination of described the second protective resistance, the other end is by described the 2nd TVS pipe ground connection, one end of described the 3rd TVS pipe meets described A by described the first protective resistance and holds, the other end meets described B by described the second protective resistance and holds, described build-out resistor is in parallel with described the 3rd TVS pipe.
9. automatic transceiving circuit according to claim 1, is characterized in that, also comprises that supply power voltage is the power supply of 3.3V, and the output of described power supply is connected with the power end of described not gate logical device with described RS-485 transceiver respectively.
10. according to the automatic transceiving circuit described in any one in claim 1 to 9, it is characterized in that, described RS-485 transceiver comprises half-duplex RS-485 transceiver, described half-duplex RS-485 transceiver comprises receiver and driver, described receiver comprises for sending the output of described reception signal and for receiving the input Enable Pin of the output signal of described not gate logical device, and described driver comprises for receiving the input of described transmitted signal and for receiving the output enable end of the output signal of described not gate logical device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410206818.9A CN104009902A (en) | 2014-05-15 | 2014-05-15 | Automatic transceiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410206818.9A CN104009902A (en) | 2014-05-15 | 2014-05-15 | Automatic transceiving circuit |
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| CN104009902A true CN104009902A (en) | 2014-08-27 |
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| CN201410206818.9A Pending CN104009902A (en) | 2014-05-15 | 2014-05-15 | Automatic transceiving circuit |
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Citations (6)
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| CN201434881Y (en) * | 2009-06-10 | 2010-03-31 | 许继集团有限公司 | RS485 interface circuit and electric energy meter employing same |
| CN101719112A (en) * | 2009-11-19 | 2010-06-02 | 北京东方信联科技有限公司 | Half-duplex automatic receiving-transmitting switching circuit of RS485 |
| CN201557127U (en) * | 2009-11-19 | 2010-08-18 | 北京东方信联科技有限公司 | RS485 half-duplex transmit-receive automatic switch circuit |
| CN201789517U (en) * | 2010-09-10 | 2011-04-06 | 河南辉煌科技股份有限公司 | Automatic transceiving control 485 communication circuit with short delay |
| CN102868424A (en) * | 2012-09-27 | 2013-01-09 | 广东易事特电源股份有限公司 | Automatic transceiving control RS 485 communication circuit |
| CN103219986A (en) * | 2013-03-04 | 2013-07-24 | 海信科龙电器股份有限公司 | Polarity insensitive transmit-receive unit and RS-485 communication circuit |
-
2014
- 2014-05-15 CN CN201410206818.9A patent/CN104009902A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201434881Y (en) * | 2009-06-10 | 2010-03-31 | 许继集团有限公司 | RS485 interface circuit and electric energy meter employing same |
| CN101719112A (en) * | 2009-11-19 | 2010-06-02 | 北京东方信联科技有限公司 | Half-duplex automatic receiving-transmitting switching circuit of RS485 |
| CN201557127U (en) * | 2009-11-19 | 2010-08-18 | 北京东方信联科技有限公司 | RS485 half-duplex transmit-receive automatic switch circuit |
| CN201789517U (en) * | 2010-09-10 | 2011-04-06 | 河南辉煌科技股份有限公司 | Automatic transceiving control 485 communication circuit with short delay |
| CN102868424A (en) * | 2012-09-27 | 2013-01-09 | 广东易事特电源股份有限公司 | Automatic transceiving control RS 485 communication circuit |
| CN103219986A (en) * | 2013-03-04 | 2013-07-24 | 海信科龙电器股份有限公司 | Polarity insensitive transmit-receive unit and RS-485 communication circuit |
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Application publication date: 20140827 |