CN214311733U - RS485 circuit capable of automatically controlling receiving and transmitting - Google Patents
RS485 circuit capable of automatically controlling receiving and transmitting Download PDFInfo
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Abstract
The utility model is suitable for a communication field provides a receiving and dispatching automatic control's RS485 circuit, include: the output port of the trigger circuit is electrically connected with the sending signal control end and the receiving signal control end of the RS485 chip, and is used for controlling the RS485 chip to switch between a sending state and a receiving state by enabling the sending signal control end and the receiving signal control end of the RS485 chip, and controlling the RS485 chip to be in the sending state all the time and completely output a sending signal TXD when triggered by a sending signal TXD and controlled in a sending period. The utility model provides a RS485 circuit adopts trigger circuit to receive and dispatch automatic control, and this trigger circuit is in the transmission state through controlling the RS485 chip always in the transmission cycle, no matter like this send signal be 0 level or 1 level can both be exported by the RS485 chip is complete, and the integrality of assurance signal has reduced the trouble of communicating, and communication quality also obtains promoting.
Description
Technical Field
The utility model belongs to the communication field especially relates to a receiving and dispatching automatic control's RS485 circuit.
Background
RS485 is a standard defined to balance the electrical characteristics of drivers and receivers in digital multipoint systems, which is defined by the telecommunications industry association and the electronics industry consortium. The digital communication network using the standard can effectively transmit signals under long-distance conditions and in environments with large electronic noise. RS-485 enables the configuration of connecting local networks and multi-drop communication links.
Because the RS-485 technology is based on a half-duplex communication mode, an MCU is usually required to control the receiving and transmitting of signals by the RS-485 circuit. In order to save the I/O resource of the MCU and in some occasions where the transceiving state is inconvenient to control, the RS485 circuit for automatically controlling transceiving is produced.
The existing RS485 circuit capable of automatically controlling transmitting and receiving is realized by using a transmitting and receiving control pin which controls an RS485 chip after a transmitting signal TXD is conditioned. Different conditioning control modes produce different effects, and the currently used modes mainly include two types: one is that the TXD directly controls the receiving and transmitting control pin of the RS485 chip after passing through the phase inverter, the TXD signal is directly connected with the D pin of the RS485 chip, and the other is that the TXD signal is connected with the receiving and transmitting control pin after passing through the phase inverter, but the TXD signal is grounded.
As a result of the two ways, the 1-level signal of the RS485 signal is not output from the chip, but the 1-level signal is realized by the a-port pull-up and the B-port pull-down. It is easy to understand that when the TXD signal is not grounded, the RX485 chip is in a receiving state due to the fact that the tx signal passes through the inverter to control the transceiver control pin, so that a valid 1-level signal cannot be output.
In the whole sending process, if the RX485 chip cannot directly output the 1 level signal, the integrity of the signal cannot be ensured, which may cause communication failure and cannot ensure the communication quality.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve for how let RX485 chip can direct complete output send signal in whole sending process to guarantee the integrality of signal, reduce communication fault, promote communication quality.
In order to solve the above technical problem, the utility model relates to a realize like this, a receiving and dispatching automatic control's RS485 circuit, include:
the RS485 chip is provided with a signal sending input end, a signal receiving output end, a signal sending control end, a signal receiving control end and two bus data ports for transmitting differential signals, and can be switched between a sending state and a receiving state;
and the output port of the trigger circuit is electrically connected with the transmitting signal control end and the receiving signal control end of the RS485 chip, and is used for controlling the RS485 chip to switch between a transmitting state and a receiving state by enabling the transmitting signal control end and the receiving signal control end of the RS485 chip, and controlling the RS485 chip to be in the transmitting state all the time and completely output the transmitting signal TXD under the trigger of the transmitting signal TXD.
Further, the trigger circuit comprises an RC charging circuit, configured to charge for a preset duration when the tx signal is at 1 level, where the preset duration is greater than a duration for transmitting one frame of data; the trigger circuit directly controls the RS485 chip to be in a sending state when the sending signal TXD is in a 0 level, and the trigger circuit delays the conversion from the RS485 chip to a receiving state through the charging signal of the RC charging circuit when the sending signal TXD is in a 1 level, so that the RS485 chip can also be in the sending state when the sending signal TXD is in a 1 level.
Further, the trigger circuit includes: a capacitor C2 having a first terminal connected to ground; the RS + D flip-flop with the model of CD4013 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective high level, a reset port R with effective high level, a positive signal output port Q and a negative signal output port
The data input port D and the reset port R are grounded; the set port S is connected with the second end of the capacitor C2 and is also connected with the inverse signal output port through a resistor R7
The capacitor C2 and the resistor R7 form the RC charging circuit; the inverse signal output port
The receiving signal output end and the sending signal control end of the RS485 chip are connected at the same time; an inverter to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2; a reset diode D1 to the cathode of which the transmit signal TXD is input and the anode of which is connected to the set port S; a reset diode D2, the anode of which is connected to the first end of the capacitor C2, and the cathode of which is connected to the inverse signal output port
And (4) connecting.
Further, the transmitting signal TXD is input to the cathode of the reset diode D1 through a current limiting resistor R3.
Further, the cathode of the reset diode D2 passes through a current limiting resistor R4 and the inverse signal output port
And (4) connecting.
Further, the trigger circuit includes: a capacitor C2, the first end of which is connected with VCC power supply; the RS + D flip-flop with the model 74HC74 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective low level, a reset port R with effective low level, a positive signal output port Q and a negative signal output port
The above-mentionedThe set port S and the data input port D are both connected with a VCC power supply, the reset port R is connected with the second end of the capacitor C2, and the reset port R also passes through a resistor R7 and the inverse signal output port
The capacitor C2 and the resistor R7 form the RC charging circuit; the positive signal output port Q is simultaneously connected with a receiving signal output end and a sending signal control end of the RS485 chip; an inverter to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2; a reset diode D1 having an anode connected to the output terminal of the inverter and an anode connected to the reset port R; a reset diode D2 having its anode connected to the inverse signal output port
The cathode of which is connected to the reset port R.
Further, the output terminal of the inverter is input to the anode of the reset diode D1 through a current limiting resistor R3.
Further, the cathode of the reset diode D2 is connected to the reset port R through a current limiting resistor R4.
Further, the VCC power supply is grounded through a filter capacitor C1.
Further, a receiving signal output end of the RS485 chip outputs a receiving signal through a matching resistor R1; the two bus data ports for transmitting the differential signals comprise a port A and a port B, and the RS485 is also provided with a power supply terminal VCC for connecting a VCC power supply and a grounding terminal GND for grounding; the power supply terminal VCC is connected to a positive signal port 485A + of the RS485 chip through a pull-up resistor R11, and the port A is connected to a positive signal port 485A + of the RS485 chip through a matching resistor R6; the ground end GND is connected to a negative signal port 485A-of the RS485 chip through a pull-down resistor R12, and the port B is connected to a negative signal port 485A-of the RS485 chip through a matching resistor R5.
The utility model provides a RS485 circuit adopts trigger circuit to receive and dispatch automatic control, and this trigger circuit is in the transmission state through controlling the RS485 chip always in the transmission cycle, no matter like this send signal be 0 level or 1 level can both be exported by the RS485 chip is complete, and the integrality of assurance signal has reduced the trouble of communicating, and communication quality also obtains promoting.
Drawings
Fig. 1 is a block diagram of an RS485 circuit for automatic control of transceiving provided by the present invention;
fig. 2 is a specific circuit diagram of the RS485 circuit for automatic control of transceiving provided by the present invention;
fig. 3 is another specific circuit diagram of the RS485 circuit for automatic control of transceiving provided by the present invention;
fig. 4 is a timing diagram of the RS485 circuit shown in fig. 2 and fig. 3 provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the utility model provides a receiving and dispatching automatic control's RS485 circuit includes trigger circuit 11 and RS485 chip 12, and wherein, RS485 chip 12 has send signal input part, received signal output part, send signal control end, received signal control end and two bus data ports that are used for transmitting differential signal, and RS485 chip 12 can switch over work between sending the state and receiving the state.
When the RS485 chip 12 operates in the receiving state, the RS485 chip 12 outputs the receiving signals input from the bus data ports a and B from the receiving signal output terminal RXD, and when the RS485 chip 12 operates in the transmitting state, the RS485 chip 12 outputs the signaling signals input from the transmitting terminal signal TXD from the bus data ports a and B.
The working state of the RS485 chip 12 is controlled by the trigger circuit 11, and specifically, an output port of the trigger circuit 11 is electrically connected to a transmitting signal control terminal and a receiving signal control terminal of the RS485 chip 12, and is configured to control the RS485 chip 12 to switch between a transmitting state and a receiving state by enabling the transmitting signal control terminal and the receiving signal control terminal of the RS485 chip 12. And is triggered by the transmitting signal TXD to control the RS485 chip 12 to be in a transmitting state all the time in the transmitting period so as to completely output the transmitting signal TXD.
It is visible, be different from the state that direct adoption sent signal TXD or the sending signal TXD after the antiphase controlled RS485 chip 12 among the prior art, the utility model discloses an adopt special trigger circuit 11 at the operating condition of whole sending cycle control RS485 chip 12 for RS485 chip 12 can both keep sending state at whole sending cycle always, thereby make no matter send signal be 0 level or 1 level can both be exported by the RS485 chip is complete, the integrality has been guaranteed, reduce the trouble of communicating, communication quality also obtains promoting.
Further, the trigger circuit 11 includes an RC charging circuit, and the RC charging circuit is configured to perform charging for a preset time period when the transmitting signal TXD is at 1 level, and the preset time period is longer than the time period for transmitting one frame of data, for example, the preset time period may be set to a time period required for charging the charging circuit to 2/3 power voltage.
The trigger circuit 11 directly controls the RS485 chip 12 to be in a transmitting state when the transmitting signal TXD is at a 0 level, and the trigger circuit 11 delays and controls the RS485 chip 11 to be switched to a receiving state through the charging signal of the RC charging circuit when the transmitting signal TXD is at a 1 level, so that the RS485 chip 12 can also be in the transmitting state when the transmitting signal TXD is at a 1 level.
Based on the above principle, the utility model provides two kinds of embodiments realize above-mentioned RS485 circuits, describe respectively below. For the RS485 chip 12, RO represents a receiving signal output terminal, RE represents a receiving signal control terminal, DE represents a sending signal control terminal, DI represents a sending signal input terminal, VCC represents a power supply terminal, GND represents a ground terminal, a and B are RS485 bus data ports, and differential signals are transmitted on a and B.
Example one
Referring to fig. 2, the trigger circuit in this embodiment is implemented based on an RS + D flip-flop, and specifically includes: the circuit comprises a capacitor C2, an RS + D trigger with the model number of CD4013, an inverter U1, a reset diode D1 and a reset diode D2. The inverter U1 can adopt an inverter device with the model 74HC14, and the inverter device is a high-speed CMOS device compatible with a TTL device pin, so that the power consumption is low, and the speed is high.
The specific circuit connection relationship is as follows:
a capacitor C2 having a first terminal connected to ground;
the RS + D flip-flop with the model of CD4013 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective high level, a reset port R with effective high level, a positive signal output port Q and a negative signal output port
The data input port D and the reset port R are grounded; the set port S is connected with the second end of the capacitor C2 and is also connected with the inverted signal output port through a resistor R7
The capacitor C2 and the resistor R7 form an RC charging circuit; inverse signal output port
Simultaneously connecting a receiving signal output end and a sending signal control end of the RS485 chip;
an inverter U1 to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2;
a reset diode D1 to the cathode of which the transmit signal TXD is input and the anode of which is connected to the set port S;
a reset diode D2, whose anode is connected to the first end of the capacitor C2, and whose cathode is connected to the inverse signal output port
And (4) connecting.
Further, the transmitting signal TXD is inputted to the cathode of the reset diode D1 through the current limiting resistor R3, and the cathode of the reset diode D2 is turned onReverse signal output port of over-current limiting resistor R4 and RS485 chip 12
And (4) connecting.
Example two
Referring to fig. 3, the trigger circuit in this embodiment is also implemented based on an RS + D flip-flop, and specifically includes: the circuit comprises a capacitor C2, an RS + D trigger with the model number of 74HC74, an inverter U1, a reset diode D1 and a reset diode D2. Inverter U1 may also be implemented as an inverting device model 74HC 14.
The specific circuit connection relationship is as follows:
a capacitor C2, the first end of which is connected with VCC power supply;
the RS + D flip-flop with the model 74HC74 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective low level, a reset port R with effective low level, a positive signal output port Q and a negative signal output port
The set port S and the data input port D are both connected with a VCC power supply, the reset port R is connected with the second end of the capacitor C2, and the reset port R is also connected with the inverse signal output port through a resistor R7
The capacitor C2 and the resistor R7 form an RC charging circuit; the positive signal output port Q is simultaneously connected with a receiving signal output end and a sending signal control end of the RS485 chip;
an inverter U1 to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2;
a reset diode D1 having an anode connected to the output terminal of the inverter U1 and an anode connected to the reset port R;
a reset diode D2 with its anode connected to the inverse signal output port
Its cathode and reset port R.
Further, the output terminal of the inverter U1 is input to the anode of the reset diode D1 through the current limiting resistor R3. The cathode of the reset diode D2 is connected to the reset port R of the RS485 chip 12 through a current limiting resistor R4.
The VCC power supply needs to be grounded through a filter capacitor C1 to filter and decouple the VCC power supply signal.
The core parts of the first and second embodiments are both RS + D flip-flops, and the transceiver control terminal (i.e., the transmit signal control terminal and the receive signal control terminal) of the RS485 chip 12 is enabled in the whole transmit period, so that the transceiver control terminal of the RS485 chip 12 is enabled to be in a transmit state, and during the receive process, the transceiver control terminal of the RS485 chip 12 is ensured to be in a low level, thereby ensuring that the RS485 chip 12 receives signals normally.
Referring to fig. 2 and 3 together, the receiving signal output end of the RS485 chip 12 outputs a receiving signal through the matching resistor R1; the two bus data ports for transmitting differential signals comprise a port A and a port B, and the RS485 circuit also needs a power supply terminal VCC for connecting a VCC power supply and a ground terminal GND for grounding; the power supply terminal VCC is connected to the positive signal port 485A + of the RS485 chip through a pull-up resistor R11, and the port A is connected to the positive signal port 485A + of the RS485 chip through a matching resistor R6; the ground terminal GND is connected to the negative signal port 485A-of the RS485 chip through a pull-down resistor R12, and the port B is connected to the negative signal port 485A-of the RS485 chip through a matching resistor R5.
For convenience of description and understanding, the operation of the RS485 circuit shown in fig. 2 and 3 will be described together as follows:
1. during the power-on process, since the R and S terminals of CD4013 are both low level, and the R and S terminals of 74HC74 are both high level, the flip-flop is in the hold state, and there may be 2 kinds of hold states for each flip-flop, which are:
output of the Q terminal of the CD4013 is low level (at this time, the RS485 chip 12 is in a receiving state): because the S end of the CD4013 is also at a low level, TXD is in a pull-up state, a diode D1 is reversely biased, and the C2 cannot be charged, the S end is kept at a low level, the chip is in a stable state, the Q end of the CD4013 outputs a high level, and the Q output is at a low level, so that the RS485 chip 12 is ensured to be in a receiving state;
secondly, the output of the Q end of the CD4013 is high level (at this time, the RS485 chip 12 is in a sending state): since the S terminal of the CD4013 is at low level, the Q charges the C2 through the R7 resistor, which causes the voltage of the S pin to rise slowly, when the voltage rises above the 2/3 power supply voltage, the output of the CD4013 is inverted, the output of the Q terminal is at low level, and the RS485 chip 12 is in a receiving state. When the output of the Q end is low level, the diode D2 is conducted, so that the capacitor C2 is rapidly discharged through the resistor R4, the CD4013 is ensured to be in a holding state, and the next RS485 sending state is waited to arrive.
③, the Q terminal of the 74HC74 is low (when the RS485 chip 12 is in the transmitting state): the C2 capacitor is charged through the R7 resistor, resulting in a slow drop in the R pin voltage, and when the voltage drops below the 1/3 supply voltage, the output of the 74HC74 flips, Q is high, and the Q output is low, leaving the RS485 chip 12 in the receive state. When the output of the Q end is high level, the diode D2 is conducted, the pin R of 74HC74 quickly returns to high level, 74HC74 is ensured to be in a holding state, and the next RS485 sending state is waited to arrive;
the Q terminal output of the 74HC74 is high (in this case, the RS485 chip 12 is in the receiving state): the Q directly pulls the R pin to high level through a D2 diode, so that the 74HC74 chip is ensured to be in a stable holding state and waits for the arrival of the next RS485 transmission state.
2. In the receive state, the TXD signal is pulled up to the power high, inverter U1 outputs a low, and flip-flop U2 is not triggered and is in a hold state. In the hold state, both the R and S terminals of CD4013 are low, and both the R and S terminals of 74HC74 are high. Through the adjustment of the power-on process or the adjustment of the transmission-reception process, at this time, the output of the Q terminal of the CD4013 is at a low level, and the output of the Q terminal of the 74HC74 is at a low level, so that the transceiving control terminal of the RS485 chip 12 is at a low level and is in a reception state, and the requirements are met.
3. A receiving-transmitting process: the TXD signal transitions from high to low producing a rising edge at the output of inverter U1. This rising edge causes the flip-flop to produce an output, the Q output of CD4013 is 1, the Q output of 74HC74 is also 1, and the RS485 chip 12 enters the transmit state.
4. Maintenance of transmission state:
first, when the TXD port sends a 0: the inverter output is 1. Thus, the S pin of the CD4013 is clamped to a low level by the TXD signal through the reset diode D1, so that the CD4013 output is maintained unchanged, and the transmitting state of the RS485 chip is also maintained unchanged. Since the output of the inverter U1 is 1, the R pin of the 74HC74 is also pulled up to a high level by the reset diode D1, thereby maintaining the 74HC74 output and the transmitting state of the RS485 chip 12.
Secondly, when the TXD port sends 1: the Q of CD4013 charges C2 through R7, the voltage on C2 rises slowly, and the time for charging to 2/3 power supply voltage formed by R7 and C2 is ensured to be longer than the time for transmitting 1 frame data. If the 1 level is always sent, after the C2 charging delay time is reached, the RS485 chip 12 will shift to the receiving state, and the level on the bus is determined by pulling up and down. This pull-up and pull-down state on the bus is also 1 level for the receiving end. Normally, since the transmission process has a state in which 0 and 1 alternate with each other, the case of completely transmitting 1 is almost none.
And thirdly, similarly, for the 74HC74 chip, when the TXD port transmits 1, Q charges C2 through R7, the voltage of the R pin continuously drops, and the time for the voltage of the R pin to drop to 1/3 power supply voltage is ensured to be longer than the time for transmitting 1 frame of data. If the 1 level is always sent, after the C2 charging delay time is reached, the RS485 chip 12 will shift to the receiving state, and the level on the bus is determined by pulling up and down. This pull-up and pull-down state on the bus is also 1 level for the receiving end. Normally, since the transmission process has a state in which 0 and 1 alternate with each other, the case of completely transmitting 1 is almost none.
5. The process of transmitting to receiving: when the transmission is complete, TXD goes high and the Q terminals of both flip-flops charge C2 through R7. After charging is finished, the output of the trigger is turned over, the RS485 chip 12 is controlled to enter a receiving state, after the receiving state, the Q end of the trigger controls the trigger to enter a stable state through the reset diode D2, and the next sending time is waited to arrive.
6. Function of other parts of the circuit: r3 and R4 are current limiting resistors during C2 discharge, and prevent overlarge impact, and R1 is a matching resistor of the signal receiving output end of the RS485 chip 12, and aims to reduce high-frequency spikes. Generally, in the transmitting mode, the R terminal is in a high impedance state, and needs to be pulled up to maintain, and this part of the circuit is placed near the MCU side, which is not described in detail here. R5 and R6 are RS485 bus output matching resistors and are recommended by chip specifications. R11 and R12 are bus pull-up and pull-down resistors, so that the output of the R end is high level in a receiving mode without signals, and the normal operation of the system is ensured.
7. The working time sequence of the whole RS485 circuit is shown in figure 4, wherein RS485-E is the waveform of the receiving and transmitting control end of the RS485 chip 12. In the output state of the RS485 chip 12, the waveform of the differential pressure between A and B is the same as that of TXD, which is not shown in FIG. 4. Because RS485-E is high level all the time, the output of A and B is effective and has very strong driving capability, and the defect that 1 level transmission is realized only by depending on pull-up and pull-down is avoided. In the input state, the control signals RS485-E are low, so that the signal output by the R pin has the same waveform as the differential pressure between A and B.
To sum up, the RS485 circuit realizes the defect that the RS485 signal cannot effectively send 1 level in the automatic sending process through the RS + D trigger and a simple peripheral circuit, improves the driving capability, enhances the anti-interference capability and improves the communication quality. In addition, on the basis of the RS485 circuit, an isolation device can be added on the input side to achieve safety regulation isolation, a protection circuit and an EMC filter circuit can be added on the output side to improve the anti-interference capability and enhance the working reliability of the circuit.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An RS485 circuit capable of automatically controlling receiving and transmitting, comprising:
the RS485 chip is provided with a signal sending input end, a signal receiving output end, a signal sending control end, a signal receiving control end and two bus data ports for transmitting differential signals, and can be switched between a sending state and a receiving state;
and the output port of the trigger circuit is electrically connected with the transmitting signal control end and the receiving signal control end of the RS485 chip, and is used for controlling the RS485 chip to switch between a transmitting state and a receiving state by enabling the transmitting signal control end and the receiving signal control end of the RS485 chip, and controlling the RS485 chip to be in the transmitting state all the time and completely output the transmitting signal TXD under the trigger of the transmitting signal TXD.
2. The RS485 circuit for automatic transmit/receive control according to claim 1, wherein the trigger circuit comprises an RC charging circuit for charging for a preset duration when the tx signal is at 1 level, and the preset duration is longer than a duration for transmitting one frame of data;
the trigger circuit directly controls the RS485 chip to be in a sending state when the sending signal TXD is in a 0 level, and the trigger circuit delays the conversion from the RS485 chip to a receiving state through the charging signal of the RC charging circuit when the sending signal TXD is in a 1 level, so that the RS485 chip can also be in the sending state when the sending signal TXD is in a 1 level.
3. The transceiver automatic control RS485 circuit of claim 2, wherein the trigger circuit comprises:
a capacitor C2 having a first terminal connected to ground;
the RS + D flip-flop with the model of CD4013 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective high level, a reset port R with effective high level, a positive signal output port Q and a negative signal output port
The data input port D and the reset port R are grounded; the set port S is connected with the capacitorC2, the set port S is connected with the inverse signal output port through a resistor R7
The capacitor C2 and the resistor R7 form the RC charging circuit; the inverse signal output port
The receiving signal output end and the sending signal control end of the RS485 chip are connected at the same time;
an inverter to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2;
a reset diode D1 to the cathode of which the transmit signal TXD is input and the anode of which is connected to the set port S;
a reset diode D2, the anode of which is connected to the first end of the capacitor C2, and the cathode of which is connected to the inverse signal output port
And (4) connecting.
4. The automatic transmit receive RS485 circuit of claim 3 wherein the transmit signal TXD is input to the cathode of the reset diode D1 through a current limiting resistor R3.
5. The RS485 circuit of claim 3, wherein the cathode of the reset diode D2 passes through a current limiting resistor R4 and the inverse signal output port
And (4) connecting.
6. The transceiver automatic control RS485 circuit of claim 2, wherein the trigger circuit comprises:
a capacitor C2, the first end of which is connected with VCC power supply;
the RS + D flip-flop with the model 74HC74 comprises a trigger signal input port C with effective rising edge, a data input port D, a set port S with effective low level, a reset port R with effective low level, a positive signal output port Q and a negative signal output port
The set port S and the data input port D are both connected with a VCC power supply, the reset port R is connected with the second end of the capacitor C2, and the reset port R also passes through a resistor R7 and the inverse signal output port
The capacitor C2 and the resistor R7 form the RC charging circuit; the positive signal output port Q is simultaneously connected with a receiving signal output end and a sending signal control end of the RS485 chip;
an inverter to which a transmission signal TXD is input, an output terminal of which is connected to the trigger signal input port C through a resistor R2;
a reset diode D1 having an anode connected to the output terminal of the inverter and an anode connected to the reset port R;
a reset diode D2 having its anode connected to the inverse signal output port
The cathode of which is connected to the reset port R.
7. The RS485 circuit of claim 6, wherein an output terminal of the inverter is inputted to an anode of the reset diode D1 through a current limiting resistor R3.
8. The RS485 circuit of claim 6, wherein the cathode of the reset diode D2 is connected to the reset port R through a current limiting resistor R4.
9. The transceiver automatic control RS485 circuit according to any of claims 6 to 8, wherein the VCC power supply is grounded through a filter capacitor C1.
10. The transceiver automatic control RS485 circuit according to any of claims 1 to 8, wherein the receive signal output terminal of the RS485 chip outputs a receive signal through a matching resistor R1; the two bus data ports for transmitting the differential signals comprise a port A and a port B, and the RS485 is also provided with a power supply terminal VCC for connecting a VCC power supply and a grounding terminal GND for grounding;
the power supply terminal VCC is connected to a positive signal port 485A + of the RS485 chip through a pull-up resistor R11, and the port A is connected to a positive signal port 485A + of the RS485 chip through a matching resistor R6; the ground end GND is connected to a negative signal port 485A-of the RS485 chip through a pull-down resistor R12, and the port B is connected to a negative signal port 485A-of the RS485 chip through a matching resistor R5.
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| CN202120632199.5U CN214311733U (en) | 2021-03-29 | 2021-03-29 | RS485 circuit capable of automatically controlling receiving and transmitting |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116232362A (en) * | 2022-08-30 | 2023-06-06 | 苏州派特纳智能科技有限公司 | Control circuit based on RS485 transceiver |
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2021
- 2021-03-29 CN CN202120632199.5U patent/CN214311733U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116232362A (en) * | 2022-08-30 | 2023-06-06 | 苏州派特纳智能科技有限公司 | Control circuit based on RS485 transceiver |
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