CN102868424B - Automatic transceiving control RS 485 communication circuit - Google Patents
Automatic transceiving control RS 485 communication circuit Download PDFInfo
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- CN102868424B CN102868424B CN201210365328.4A CN201210365328A CN102868424B CN 102868424 B CN102868424 B CN 102868424B CN 201210365328 A CN201210365328 A CN 201210365328A CN 102868424 B CN102868424 B CN 102868424B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
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Abstract
The invention relates to the technical field of communication circuits, in particular to an automatic transceiving control RS 485 communication circuit which comprises a communication chip RS 485, wherein the enabling end RE of the data output end R0 of the communication chip RS 485 and the enabling end DE of the data input end DI of the communication chip RS 485 are connected with a transceiving control signal end E, a delay circuit capable of leading jump signals of the enabling end RE to delay and jump signals of the enabling end DE to lower is connected between the enabling end RE and the enabling end DE, generation of a section of interference signals caused by the fact that the communication chip RS 485 receives a small section of data to be transmitted due to data transmission delay when the communication chip RS 485 is converted from the transmitting state to the receiving state is avoided. The automatic transceiving control RS 485 communication circuit is simple in structure and low in cost, needs few elements, simultaneously is obvious in effect and is not affected by data frequency.
Description
Technical field
The present invention relates to telecommunication circuit technical field, particularly a kind of automatic transceiving control RS485 telecommunication circuit.
Background technology
RS-485 interface is owing to having good noise resistance interference, and the advantages such as transmission range length and multistation transmittability, therefore it becomes first-selected serial line interface.The maximum transmission distance of its interface can reach 1200 meters, can form half-or full-duplex network, and adopt Shielded Twisted Pair transmission, interface connector adopts the 9 core plug seats of DB-9.Allow to connect nearly 256 nodes.Common RS485 communication chip has following pin: data output end R0, data input pin DI, the Enable Pin DE of the Enable Pin of R0/RE, DI and data input/output terminal A and B, RS485 chip adopts and sends priority principle simultaneously, as long as DE end is high level, so hold level state regardless of/RE, RS485 chip is all operated in transmission state, and only have when DE and/RE two ends are all low level, chip is just operated in accepting state.
In prior art, usual general/RE end is held two pins to link together with DE and is received and dispatched control signal with one simultaneously and is connected, as shown in Figure 1, when transmitting-receiving control signal is high level, DE is effective, and chip is in transmission state, when controller is to this two ends input low level, / RE is effective, and chip is in accepting state.This connection simple possible in principle.But in actual applications, when DE and/RE two ends transfer low level to by high level simultaneously, chip can transfer accepting state to by transmission state at once, because transfer of data has time delay, the data now sent also at A, B two ends even also in chip, so RS485 chip can receive a bit of level signal just sent, become one section of interference signal.This interference signal of filtering is wanted to adopt general capacitor filtering effect not too aobvious, often need the device adopting some triodes, optocoupler and so on, not only considerably increase cost, and also can be subject to the restriction of optocoupler and triode switch speed when needing the data frequency of transmission higher.
Summary of the invention
The object of the invention is to avoid above-mentioned weak point of the prior art and a kind of automatic transceiving control RS485 telecommunication circuit can effectively eliminated due to the interference signal of data delay generation when communication chip RS485 reiving/transmitting state changes is provided.
Object of the present invention is achieved through the following technical solutions:
Provide a kind of automatic transceiving control RS485 telecommunication circuit, comprise the Transistor-Transistor Logic level signal output part Rx outwards exporting Transistor-Transistor Logic level, receive the Transistor-Transistor Logic level signal input part Tx of outside Transistor-Transistor Logic level, send the receipts/control signal end E and communication chip RS485 receiving/send out control signal, the data output end R0 of described communication chip RS48 is connected with Transistor-Transistor Logic level signal output part Rx, described data input pin DI is connected with Transistor-Transistor Logic level signal input part Tx, Enable Pin/the RE of described data output end R0 is connected with transmitting-receiving control signal end E with the Enable Pin DE of the data input pin DI of described communication chip RS48, described Enable Pin/be connected with the trailing edge delay circuit making the skip signal of Enable Pin/RE postpone the skip signal in Enable Pin DE between RE and Enable Pin DE.
Wherein, described trailing edge delay circuit comprises storage capacitor C1, releases energy resistance R1 and isolates the isolating diode D1 of Enable Pin/RE and Enable Pin DE when storage capacitor C1 releases energy.
Wherein, transient voltage suppressor diode D3 is connected with between the data input/output terminal A and data input/output terminal B of described communication chip RS485, be connected with transient voltage suppressor diode D4 between described data input/output terminal A and power supply ground, between described data input/output terminal B and power supply ground, be connected with transient voltage suppressor diode D2.
Beneficial effect of the present invention: when receiving and dispatching control signal end E and transferring low level to by high level, due to the existence of delay circuit, the process that Enable Pin/RE drops to low level threshold values by high level is delayed in Enable Pin DE, namely communication chip RS485 transfers existence one section of time slot between accepting state to by the state of transmission, in this timeslot, Enable Pin/RE is high level, Enable Pin DE is low level, communication chip RS485 is neither in transmission state and is not also in accepting state, its data to be sent are sent from its input/output terminal smoothly, ensure that the data of the data input/output terminal when communication chip RS485 transfers accepting state to are the data that receive of needs but not rest on the data to be sent of data input/output terminal due to time delay, effectively prevent when communication chip RS485 transfers accepting state to from transmission state causes communication chip RS485 can receive a bit of data to be sent because transfer of data exists time delay, produce one section of interference signal.This circuit structure is simple, and required element is few, and cost is low.Successful, does not affect by data frequency simultaneously.
Accompanying drawing explanation
The invention will be further described to utilize accompanying drawing, but the embodiment in accompanying drawing does not form any limitation of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to the following drawings.
Fig. 1 is the circuit diagram of prior art.
Fig. 2 is the circuit diagram of the embodiment of a kind of automatic transceiving control of the present invention RS485 telecommunication circuit.
Embodiment
The invention will be further described with the following Examples.
The embodiment of a kind of automatic transceiving control of the present invention RS485 telecommunication circuit, as shown in Figure 2, comprise: the Transistor-Transistor Logic level signal output part Rx outwards exporting Transistor-Transistor Logic level, receive the Transistor-Transistor Logic level signal input part Tx of outside Transistor-Transistor Logic level, send the receipts/control signal end E and communication chip RS485 receiving/send out control signal, the data output end R0 of described communication chip RS48 is connected with Transistor-Transistor Logic level signal output part Rx, described data input pin DI is connected with Transistor-Transistor Logic level signal input part Tx, Enable Pin/the RE of described data output end R0 is connected with a receipts/control signal end E with the Enable Pin DE of the data input pin DI of described communication chip RS48, described Enable Pin/be connected with the trailing edge delay circuit 1 making the skip signal of Enable Pin/RE postpone the skip signal in Enable Pin DE between RE and Enable Pin DE.
When receiving/sending out control signal end E and transfer low level to by high level, due to the existence of delay circuit, the process that Enable Pin/RE drops to low level threshold values by high level is delayed in DE, namely and the level change procedure Wei You Gao-Gao of Enable Pin/RE-Enable Pin DE change height-low into, change into low-low again, and the level change procedure of prior art Enable Pin/RE-Enable Pin DE Wei You Gao-Gao directly change into low-low, in visible the present embodiment there is one section of time slot in communication chip RS485 during transferring accepting state to by transmission state, in this timeslot, Enable Pin/RE is high level, Enable Pin DE is low level, communication chip RS485 is neither in transmission state and is not also in accepting state, the smooth data of its data to be sent are sent from its input/output terminal A and data input/output terminal B, ensure that the data of data input/output terminal A and data input/output terminal B when communication chip RS485 transfers accepting state to are the data that receive of needs but not rest on the data to be sent of data input/output terminal A and data input/output terminal B due to time delay.On the other hand, when receiving/sending out control signal end E and hold output to transfer high level to by low level, even if the low level of Enable Pin/RE can maintain a bit of time, but Enable Pin DE is high level already, according to sending preferential principle, no matter Enable Pin/RE level state how, as long as Enable Pin DE is high level, then communication chip RS485 is operated in transmission state.So when receiving/sending out control signal end E and hold output to transfer high level to by low level, input/output terminal A and data input/output terminal B also can not receive the signal just sent.Therefore this circuit can effectively prevent when communication chip RS485 transfers accepting state to from transmission state and cause communication chip RS485 can receive a bit of data to be sent because transfer of data exists time delay, produces one section of interference signal.This circuit structure is simple, and required element is few, and cost is low.Successful, does not affect by data frequency simultaneously.
Wherein, described trailing edge delay circuit 1 comprises storage capacitor C1, releases energy resistance R1 and isolates the isolating diode D1 of Enable Pin/RE and Enable Pin DE when storage capacitor C1 releases energy.When the level receiving/send out control signal end E produces saltus step, the discharge and recharge of storage capacitor can make to postpone saltus step to the level of Enable Pin/RE, isolating diode D1 can when Enable Pin/RE progressively becomes low level from high level simultaneously, namely isolate this time delayed signal when energy is released in storage capacitor C1 electric discharge, make to there is time delay between the level signal of Enable Pin/RE and the level signal of Enable Pin DE.
Wherein, transient voltage suppressor diode D3 is connected with between the data input/output terminal A and data input/output terminal B of described communication chip RS485, be connected with transient voltage suppressor diode D4 between described data input/output terminal A and power supply ground, between described data input/output terminal B and power supply ground, be connected with transient voltage suppressor diode D2.This part circuit strengthens the data input/output terminal A of communication chip RS485 and the antijamming capability of data input/output terminal B, improves the overall communication effect of circuit.Also protect the electronic component of this circuit simultaneously.
Finally should be noted that; above embodiment is only in order to illustrate technical scheme of the present invention; but not limiting the scope of the invention; although done to explain to the present invention with reference to preferred embodiment; those of ordinary skill in the art is to be understood that; can modify to technical scheme of the present invention or equivalent replacement, and not depart from essence and the scope of technical solution of the present invention.
Claims (3)
1. an automatic transceiving control RS485 telecommunication circuit, comprise the Transistor-Transistor Logic level signal output part Rx outwards exporting Transistor-Transistor Logic level, receive the Transistor-Transistor Logic level signal input part Tx of outside Transistor-Transistor Logic level, send the receipts/control signal end E and communication chip RS485 receiving/send out control signal, the data output end R0 of described communication chip RS485 is connected with Transistor-Transistor Logic level signal output part Rx, the data input pin DI of described communication chip RS485 is connected with Transistor-Transistor Logic level signal input part Tx, Enable Pin/the RE of described data output end R0 is connected with transmitting-receiving control signal end E with the Enable Pin DE of the data input pin DI of described communication chip RS485, it is characterized in that: the trailing edge delay circuit (1) that described Enable Pin/be connected with between RE and Enable Pin DE makes the skip signal of Enable Pin/RE postpone in the skip signal of Enable Pin DE.
2. a kind of automatic transceiving control RS485 telecommunication circuit as claimed in claim 1, is characterized in that: described trailing edge delay circuit (1) comprises storage capacitor C1, releases energy resistance R1 and isolates the isolating diode D1 of Enable Pin/RE and Enable Pin DE when storage capacitor C1 releases energy.
3. a kind of automatic transceiving control RS485 telecommunication circuit as claimed in claim 1, it is characterized in that: between the data input/output terminal A and data input/output terminal B of described communication chip RS485, be connected with transient voltage suppressor diode D3, be connected with transient voltage suppressor diode D4 between described data input/output terminal A and power supply ground, between described data input/output terminal B and power supply ground, be connected with transient voltage suppressor diode D2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210365328.4A CN102868424B (en) | 2012-09-27 | 2012-09-27 | Automatic transceiving control RS 485 communication circuit |
| PCT/CN2013/083799 WO2014048269A1 (en) | 2012-09-27 | 2013-09-18 | Communication circuit for automatically performing transceiving control on rs485 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210365328.4A CN102868424B (en) | 2012-09-27 | 2012-09-27 | Automatic transceiving control RS 485 communication circuit |
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| Publication Number | Publication Date |
|---|---|
| CN102868424A CN102868424A (en) | 2013-01-09 |
| CN102868424B true CN102868424B (en) | 2015-03-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210365328.4A Active CN102868424B (en) | 2012-09-27 | 2012-09-27 | Automatic transceiving control RS 485 communication circuit |
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| CN (1) | CN102868424B (en) |
| WO (1) | WO2014048269A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868424B (en) * | 2012-09-27 | 2015-03-18 | 广东易事特电源股份有限公司 | Automatic transceiving control RS 485 communication circuit |
| CN103441780A (en) * | 2013-08-16 | 2013-12-11 | 北京汉柏科技有限公司 | Communication circuit capable of enabling direction of RS-485 chip to be automatically changed |
| CN103633985A (en) * | 2013-12-11 | 2014-03-12 | 济南诺辉节能技术开发有限公司 | RS485 communication circuit |
| CN104009902A (en) * | 2014-05-15 | 2014-08-27 | 京信通信系统（中国）有限公司 | Automatic transceiving circuit |
| CN106201940A (en) * | 2016-08-27 | 2016-12-07 | 谢怡涛 | A kind of control circuit for improving RS485 bus data transfer reliability |
| CN106950890B (en) * | 2017-04-28 | 2023-06-20 | 南京搜新智能科技有限公司 | Intelligent switch circuit based on double 485 communication |
| CN109302204A (en) * | 2018-12-03 | 2019-02-01 | 中国船舶重工集团公司第七0四研究所 | Adaptive transmitting-receiving RS485 circuit |
| CN109557859A (en) * | 2018-12-13 | 2019-04-02 | 珠海派诺科技股份有限公司 | Simple general use circuit based on RS-485 communication |
| CN112052212B (en) * | 2020-08-26 | 2023-03-03 | 天津津航计算技术研究所 | RS485 communication flow control isolation circuit |
| CN114650077B (en) * | 2020-12-17 | 2023-07-14 | 航天科工惯性技术有限公司 | Communication circuit of receiving and transmitting self-control RS485 interface |
| CN113141244B (en) * | 2021-04-16 | 2023-07-21 | 珠海格力电器股份有限公司 | Full duplex communication device, electrical appliance system and communication method thereof |
| CN113595581B (en) * | 2021-07-28 | 2023-01-06 | 深圳市永旭电气技术有限公司 | Safe receiving and transmitting state control method and circuit of half-duplex serial port communication circuit |
| CN113985851B (en) * | 2021-10-29 | 2024-03-08 | 雅迪科技集团有限公司 | Electric vehicle positioner communication circuit with bus protection and anti-interference functions |
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| CN102868424B (en) * | 2012-09-27 | 2015-03-18 | 广东易事特电源股份有限公司 | Automatic transceiving control RS 485 communication circuit |
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- 2012-09-27 CN CN201210365328.4A patent/CN102868424B/en active Active
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2013
- 2013-09-18 WO PCT/CN2013/083799 patent/WO2014048269A1/en active Application Filing
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| CN101026387A (en) * | 2007-02-13 | 2007-08-29 | 徐震 | Automatic stream control device, control method and its circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102868424A (en) | 2013-01-09 |
| WO2014048269A1 (en) | 2014-04-03 |
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