CN116232362A

CN116232362A - Control circuit based on RS485 transceiver

Info

Publication number: CN116232362A
Application number: CN202211049223.8A
Authority: CN
Inventors: 陈江疆; 朱金峰; 杨建�
Original assignee: Suzhou Petner Intelligent Technology Co ltd
Current assignee: Suzhou Petner Intelligent Technology Co ltd
Priority date: 2022-08-30
Filing date: 2022-08-30
Publication date: 2023-06-06

Abstract

The invention relates to a control circuit based on an RS485 transceiver, which comprises: the power supply circuit comprises an RS485 chip and a level reversing sub-circuit, wherein a GND1 pin of the chip is grounded, and a VCC pin is connected with a power supply; the RXD pins are connected with the receiving end of the main controller; the RE# pin and the DE pin are connected with the transmitting end of the main controller through a level reversing sub-circuit, and the level reversing sub-circuit is used for reversing the level received from the transmitting end; the TXD pin is grounded; the GND2 pin is grounded, and the VISOIN pin is connected with an isolation voltage; the pin A is connected with the end A of the RS485 bus, the pin B is connected with the end B, and a first resistor is connected in parallel between the pin A and the pin B; the Z pin is connected with the B pin, and the Y pin is connected with the A pin; the visout pin is grounded and is also connected to the visin pin. The control circuit of the invention ensures that one RS485 transceiver only occupies 2 pins of the main controller to save pin resources, and ensures that the RS485 transceiver realizes full duplex communication of self-adaptive receiving and transmitting mode switching.

Description

Control circuit based on RS485 transceiver

Technical Field

The invention mainly relates to the technical field of circuit design, in particular to a control circuit based on an RS485 transceiver.

Background

With the development of the age, various intelligent robots are moving into the lives of people. The main controller in the robot, namely the micro control unit (Microcontroller Unit, MCU) plays an important role, the MCU integrates peripheral interfaces such as a memory, a counter and the like and a driving circuit on a single chip to form a chip-level computer, and different combination control is performed for different application occasions. The communication between MCU and equipment is realized by using an RS485 transceiver interface, the RS485 transceiver is an integrated transceiver chip, the data transmission is performed by adopting a half-duplex mode, and the RS485 transceiver has the problem that the data can not be simultaneously transmitted and received.

Fig. 1 is a schematic diagram of a connection between a main controller and an RS485 transceiver in the prior art, and fig. 2 is a circuit connection diagram of a connection between a main controller and an RS485 transceiver in the prior art. For the RS485 transceiver interface commonly used in the robot system, the number of requirements is generally larger, and the resources of the MCU pins of the robot main control system are relatively short, generally, one RS485 transceiver interface needs to occupy 4 Input/Output (I/O) pins of the MCU, and referring to fig. 1, the I/O1 pin of the MCU is connected with the DE pin of the RS485 transceiver; the I/O2 pin of the MCU is connected with the RE pin of the RS485 transceiver; the TX pin of the MCU is connected with the TX pin of the RS485 transceiver; the RX pin of MCU is connected with the RX pin of RS485 transceiver. Similarly, referring to FIG. 2, for example, using an RS485 transceiver chip U1, model ADM2582EBRWZ, the MCU-RX pin of the MCU is connected to the RXD pin of the RS485 transceiver chip U1; the MCU-RE# pin of the MCU is connected with the RE# pin of the RS485 transceiver chip U1; the MCU-DE pin of the MCU is connected with the DE pin of the RS485 transceiver chip U1; the MCU-TX pin of the MCU is connected with the TXD pin of the RS485 transceiver chip U1. Under the condition of using a plurality of RS485 transceiver interfaces, the problem that MCU pins are not enough and pin resources are short exists.

In summary, in the prior art, the problem that the single RS485 transceiver occupies too many MCU pins, which makes MCU pin resources scarce, and the RS485 transceiver cannot transmit and receive data simultaneously exists.

Disclosure of Invention

The technical problem to be solved by the application is to provide a control circuit based on an RS485 transceiver, which enables an RS485 transceiver interface to occupy only 2 pins of an MCU, saves MCU pin resources, enables the RS485 transceiver to realize full duplex communication of self-adaptive receiving and transmitting mode switching, and can simultaneously receive and transmit data.

The technical scheme that this application adopted in order to solve above-mentioned technical problem is a control circuit based on RS485 transceiver, includes: the power supply circuit comprises an RS485 chip and a level reversing sub-circuit, wherein a GND1 pin of the RS485 chip is grounded, and a VCC pin is connected with a power supply; the RXD pin of the RS485 chip is connected with the receiving end of the main controller; the RE# pin and the DE pin of the RS485 chip are connected with the transmitting end of the main controller through a level reversing sub-circuit, and the level reversing sub-circuit is used for reversing the level received from the transmitting end; the TXD pin of the RS485 chip is grounded; the GND2 pin of the RS485 chip is grounded, and the VISOIN pin is connected with an isolation voltage; the A pin of the RS485 chip is connected with the A end of the RS485 bus, the B pin is connected with the B end of the RS485 bus, and a first resistor is connected in parallel between the A pin and the B pin; the Z pin of the RS485 chip is connected with the B pin, and the Y pin is connected with the A pin; the VISOOUT pin of the RS485 chip is grounded, and the VISOOUT pin is also connected with the VISOIN pin.

In an embodiment of the present application, pin a is further connected to an isolation voltage through a third resistor; the B pin is also grounded through a second resistor.

In one embodiment of the present application, the level reversing sub-circuit includes: the transistor comprises a triode, the emitting electrode of the triode is grounded, the collecting electrode of the triode is connected with the RE# pin and the DE pin, the base electrode of the triode is connected with the sending end of the main controller through a fourth resistor, the collecting electrode is also connected with a power supply through a fifth resistor, and a sixth resistor is further connected between one end of the fourth resistor connected with the sending end of the main controller and one end of the fifth resistor connected with the power supply.

In one embodiment of the present application, the level reversing sub-circuit includes: the transistor comprises an MOS tube, the source electrode of the MOS tube is grounded, the drain electrode of the MOS tube is connected with the RE# pin and the DE pin, the grid electrode of the MOS tube is connected with the transmitting end of the main controller through a fourth resistor, the drain electrode is also connected with a power supply through a fifth resistor, and a sixth resistor is further connected between one end of the fourth resistor connected with the transmitting end of the main controller and one end of the fifth resistor connected with the power supply.

In an embodiment of the present application, the RXD pin is further connected to a power supply through a seventh resistor.

In an embodiment of the application, the control circuit based on the RS485 transceiver further includes an overvoltage protection chip, the overvoltage protection chip includes a first end, a second end and a third end, the first end is connected to one end of the second resistor connected to the first resistor, the second end is connected to one end of the third resistor connected to the first resistor, and the third end is grounded.

In an embodiment of the present application, the VCC pin includes a first VCC pin and a second VCC pin, and the first VCC pin is further grounded through a third capacitor and a fourth capacitor connected in parallel; the second VCC pin is also grounded through the first and second capacitors in parallel.

In an embodiment of the present application, the GND2 pin includes a first GND2 pin, a second GND2 pin, a third GND2 pin, and a fourth GND2 pin, where the first GND2 pin is further connected to the visin pin through a seventh capacitor and an eighth capacitor that are connected in parallel; the fourth GND2 pin is also connected to the visout pin through a fifth capacitor and a sixth capacitor connected in parallel.

In an embodiment of the present application, the power source comprises 3.3V or 5V.

In one embodiment of the present application, the ground for the GND1 pin and the TXD pin is logic side ground, and the ground for the GND2 pin and the VISOOUT pin is bus side ground.

In an embodiment of the present application, when the main controller is in a transmitting state, the transmitting end of the main controller outputs a transmitting end signal with a high-low level change, when the transmitting end signal is in a low level, the transmitting end controls the re# pin and the DE pin to be in a high level through the level reversing sub-circuit, the RS485 chip is in a transmitting mode, the Y pin and the Z pin are controlled to be in a low level through the TXD pin, the a end is pulled down to be in a low level through the Y pin, the B end is pulled up to be in a high level through the Z pin, and the RS485 bus is in a logic low state; when the signal of the transmitting end is high, the transmitting end controls the RE# pin and the DE pin to be low through the level reversing sub-circuit, the RS485 chip is in a receiving mode, the Y pin and the Z pin are closed, the A end is pulled up to be high through the third resistor, the B end is pulled down to be low through the second resistor, and the RS485 bus is in a logic high state.

In an embodiment of the present application, when a main controller is in a receiving state, a receiving end of the main controller receives a receiving end signal with a high-low level change, a transmitting end of the main controller keeps transmitting the high-level signal, the transmitting end controls an re# pin and a DE pin to be low level through a level reversing sub-circuit, an RS485 chip is in a receiving mode, a Y pin and a Z pin are closed, a state of an RS485 bus is controlled by a slave device on the RS485 bus, wherein when an a end is pulled down to be low level by the slave device and a B end is pulled up to be high level, the RS485 bus is in a logic low state, and the receiving end signal is low level; when the A end is pulled high to high level by the slave device and the B end is pulled low to low level, the RS485 bus is in logic high state, and the signal of the receiving end is high level.

According to the control circuit based on the RS485 transceiver, the first resistor is connected in parallel between the pin A and the pin B of the RS485 chip, so that the stability and the reliability of RS485 communication can be effectively improved; the RXD pin of the RS485 chip is connected with the receiving end of the main controller, and the RS485 transceiver occupies the first pin of the main controller, so that the communication connection with the main controller is realized; the RE# pin and the DE pin of the RS485 chip are connected with the transmitting end of the main controller through the level reversing sub-circuit which can reverse the level received from the transmitting end of the MCU, the RS485 transceiver occupies the second pin of the main controller, the communication connection with the main controller is realized, and 2 pins of the MCU which are separately connected with the RE# pin and the DE pin of the RS485 chip in the past are saved. The control circuit of the application enables one RS485 transceiver interface to occupy only 2 pins of the MCU, saves MCU pin resources, enables the RS485 transceiver to realize full duplex communication of self-adaptive receiving and transmitting mode switching, and can simultaneously receive and transmit data.

Drawings

In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic diagram of a prior art master controller connected to an RS485 transceiver;

FIG. 2 is a circuit diagram of a prior art connection of a master controller to an RS485 transceiver;

FIG. 3 is a circuit diagram of an RS485 transceiver based control circuit according to an embodiment of the present application;

FIG. 4 is another circuit diagram of an RS485 transceiver based control circuit according to an embodiment of the application;

FIG. 5 is a truth table abbreviation schematic of an RS485 transceiver based control circuit according to an embodiment of the present application;

FIG. 6 is a truth-presented intent of the RS485 chip transmission status of an embodiment of the application;

FIG. 7 is a truth-presented intent of the RS485 chip to receive status in accordance with an embodiment of the present application;

FIG. 8 is a timing diagram of a control circuit of an RS485 transceiver with a master controller in a transmit state according to an embodiment of the present application;

fig. 9 is a timing diagram of a control circuit of the RS485 transceiver when the master controller is in a receiving state according to an embodiment of the present application.

Detailed Description

In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced otherwise than as described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the description of the present application, it should be understood that, where azimuth terms such as "front, rear, upper, lower, left, right", "transverse, vertical, horizontal", and "top, bottom", etc., indicate azimuth or positional relationships generally based on those shown in the drawings, only for convenience of description and simplification of the description, these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present application; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.

In addition, the terms "first", "second", etc. are used to define the components, and are merely for convenience of distinguishing the corresponding components, and unless otherwise stated, the terms have no special meaning, and thus should not be construed as limiting the scope of the present application. Furthermore, although terms used in the present application are selected from publicly known and commonly used terms, some terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present application be understood, not simply by the actual terms used but by the meaning of each term lying within.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The control circuit based on the RS485 transceiver is mainly applied to a control system of an intelligent robot so as to realize communication between a main controller MCU and the RS485 transceiver. Illustratively, the RS485 transceiver-based control circuit of the present application is applied in an instant location and mapping (Simultaneous Localization and Mapping, SLAM) controller. SLAM is a universal robot controller, is mainly used for chassis walking type robots, and the chassis robot with wheels starts to move from a position in an unknown environment, and positions itself according to the position and a map in the moving process, and builds an incremental map at the same time, so as to realize autonomous positioning and navigation. For example, the application may select an RS485 chip with a model number of ADM2582EBRWZ, and the application is not limited to the model number of the RS485 chip.

Fig. 2 is a circuit connection diagram of a main controller and an RS485 transceiver in the prior art, fig. 3 is a circuit connection diagram of a control circuit based on the RS485 transceiver according to an embodiment of the present application, and fig. 4 is another circuit connection diagram of a control circuit based on the RS485 transceiver according to an embodiment of the present application. It should be noted that, the difference between fig. 3 and fig. 4 is that specific parameters of each component in the circuit are not identified in fig. 3, and specific parameters selected by each component in the circuit are identified in fig. 4, but the numerical values of each parameter in fig. 4 are only examples and can be selected autonomously according to actual situations, which is not limited in this application; GND in fig. 3 and 4 represents a logic side ground, which may be also referred to as an internal power supply ground, and GND-485 in fig. 3 and 4 represents a bus side ground, which may be also referred to as an external isolation ground.

Referring to fig. 2 to 4, the functions of the respective pins in the RS485 chip U1 of the RS485 transceiver of the present application will be described herein with reference to the following table 1.

TABLE 1 Pin function description of RS485 chip U1

Referring to fig. 2, in the prior art, the RS485 chip U1 communicates with the MCUs to a pin interface end of 4 MCUs in total: receiving end MCU-RX, receiving enabling end MCU-RE#, transmitting enabling end MCU-DE, transmitting end MCU-TX. Communication working principle: when the MCU is in a receiving state, the MCU-RE# is in a low level and is enabled to receive, and at the moment, the MCU-DE is pulled down and the MCU-TX is in an idle state; when the MCU is in a transmitting state, the MCU-DE is pulled high, transmitting enable is achieved, at the moment, the MCU-RE# is pulled high, and the MCU-RX is in an idle state.

Next, the RS485 transceiver-based control circuit of the present application is described in detail.

Referring to fig. 3, the RS485 transceiver based control circuit of this embodiment includes: the power supply comprises an RS485 chip U1 and a level reversing sub-circuit, wherein GND1 pins (1, 3,9, 10) of the RS485 chip U1 are grounded GND, and VCC pins (2, 8) are connected with a power supply VCC; RXD pin 4 of RS485 chip U1 is connected with receiving end MCU-RX of main controller MCU; the RE# pin 5 and the DE pin 6 of the RS485 chip U1 are connected with a transmitting end MCU-TX of the main controller MCU through a level reversing sub-circuit, and the level reversing sub-circuit is used for reversing the level received from the transmitting end MCU-TX; the TXD pin 7 of the RS485 chip U1 is grounded to GND; the GND2 pin (11, 14, 16, 20) of the RS485 chip U1 is grounded GND-485, and the VISOIN pin 19 is connected with the isolation voltage VISO; an A pin 18 of the RS485 chip U1 is connected with an A end 485-A of the RS485 bus, a B pin 17 is connected with a B end 485-B of the RS485 bus, and a first resistor R1 is connected in parallel between the A pin 18 and the B pin 17; the Z pin 15 of the RS485 chip U1 is connected with the B pin 17, and the Y pin 13 is connected with the A pin 18; the VISOOUT pin 12 of the RS485 chip U1 is grounded GND-485, and the VISOOUT pin 12 is also connected to the VISOIN pin 19.

Referring to fig. 4, illustratively, GND1 pins (1, 3,9, 10) of the RS485 chip U1 are connected to the logic side ground GND, and VCC pins (2, 8) are connected to a 3.3v power supply; RXD pin 4 of RS485 chip U1 is connected with receiving end MCU-RX of main controller MCU; the RE# pin 5 and the DE pin 6 of the RS485 chip U1 are connected with the transmitting end MCU-TX of the main controller MCU through level reversing sub-circuits, and the level reversing sub-circuits can reverse the level received from the transmitting end MCU-TX, namely when the transmitting end MCU-TX of the main controller MCU transmits high level, the level received by the RE# pin 5 and the DE pin 6 can be reversed to low level through the level reversing sub-circuits; when the transmitting end MCU-TX of the main controller MCU transmits a low level, the level received by the RE# pin 5 and the DE pin 6 can be inverted to a high level through a level inverting sub-circuit.

Illustratively, TXD pin 7 of RS485 chip U1 is connected to logic side ground GND; the GND2 pin (11, 14, 16, 20) of the RS485 chip U1 is connected with the bus side ground GND-485, and the VISOIN pin 19 is connected with the isolation voltage VISO; the A pin 18 of the RS485 chip U1 is connected with the A end 485-A of the RS485 bus, the B pin 17 is connected with the B end 485-B of the RS485 bus, a first resistor R1 is connected in parallel between the A pin 18 and the B pin 17, the resistance value of the first resistor R1 can be set to 120 ohms, and the first resistor R1 is connected in parallel between the A pin 18 and the B pin 17, so that the stability and the reliability of RS485 communication can be effectively improved.

Illustratively, Z pin 15 of RS485 chip U1 is connected to B pin 17, Y pin 13 is connected to A pin 18; the VISOOUT pin 12 of the RS485 chip U1 is connected with the bus side ground GND-485, and the VISOOUT pin 12 is also connected with the VISOIN pin 19.

In some embodiments, referring to fig. 3, a pin 18 is also connected to an isolation voltage VISO through a third resistor R3; the B pin 17 is also connected to ground GND-485 through a second resistor R2.

Illustratively, referring to FIG. 4, the A pin 18 is also coupled to an isolation voltage VISO via a third resistor R3, wherein the third resistor R3 is set to 10 kiloohms; the B pin 17 is also connected to bus side ground GND-485 through a second resistor R2, wherein the second resistor R2 is set to 10 kilo-ohms. By the arrangement, the level states of the A end 485-A and the B end 485-B of the RS485 bus can be respectively controlled through the third resistor R3 and the second resistor R2 under the condition that the Y pin 13 and the Z pin 15 are closed.

In some embodiments, referring to fig. 3, the level reversing sub-circuit includes: the transistor comprises a triode Q1, the emitting electrode of the triode Q1 is grounded GND, the collecting electrode of the triode Q1 is connected with a RE# pin 5 and a DE pin 6, the base electrode of the triode Q1 is connected with the transmitting end MCU-TX of the main controller MCU through a fourth resistor R4, the collecting electrode is also connected with a power supply VCC through a fifth resistor R5, and a sixth resistor R6 is also connected between one end of the fourth resistor R4 connected with the transmitting end MCU-TX of the main controller MCU and one end of the fifth resistor R5 connected with the power supply VCC.

For example, referring to fig. 4, the emitter of the transistor Q1 is connected to the logic side ground GND, the base of the transistor Q1 is connected to the transmitting end MCU-TX of the main controller MCU through a fourth resistor R4, wherein the fourth resistor R4 is set to 1 kiloohm, the collector is further connected to the 3.3v power supply through a fifth resistor R5, wherein the fifth resistor R5 is set to 10 kiloohms, and a sixth resistor R6 is further connected between the end of the fourth resistor R4 connected to the transmitting end MCU-TX of the main controller MCU and the end of the fifth resistor R5 connected to the 3.3v power supply, wherein the sixth resistor R6 is set to 1 kiloohm.

The level inverting sub-circuit combines the transistor, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 to form a non-logic gate circuit with the resistor circuit, namely the transistor forms a level inverter. The level received from the transmitting end MCU-TX can be inverted by the level inverting sub-circuit to control the level states received at both re# pin 5 and DE pin 6.

In some embodiments, referring to fig. 3, the level reversing sub-circuit includes: the transistor comprises a MOS tube (not shown), the source electrode of the MOS tube is grounded GND, the drain electrode of the MOS tube is connected with RE# pin 5 and DE pin 6, the grid electrode of the MOS tube is connected with the transmitting end MCU-TX of the main controller MCU through a fourth resistor R4, the drain electrode is also connected with the power VCC through a fifth resistor R5, and a sixth resistor R6 is also connected between one end of the fourth resistor R4 connected with the transmitting end MCU-TX of the main controller MCU and one end of the fifth resistor R5 connected with the power VCC.

Typically, the selection of the transistor needs to support the transmission rate of the serial port 1M, and the selection of the transistor is not limited in the application.

In some embodiments, as shown with reference to fig. 3, RXD pin 4 is also connected to power supply VCC through a seventh resistor R7. Illustratively, referring to fig. 4, the RXD pin 4 is also connected to a 3.3v power supply through a seventh resistor R7, wherein the seventh resistor R7 is set to 4.7 kiloohms.

The RXD pin 4 is connected with a power supply VCC through a seventh resistor R7, and when the MCU is in a transmitting state, the receiving end MCU-RX of the main controller MCU is kept at a high level through the seventh resistor R7.

In some embodiments, referring to fig. 3 and 4, the control circuit based on the RS485 transceiver further includes an overvoltage protection chip U2, where the overvoltage protection chip U2 includes a first terminal 21, a second terminal 22, and a third terminal 23, the first terminal 21 is connected to a terminal of the second resistor R2 connected to the first resistor R1, the second terminal 22 is connected to a terminal of the third resistor R3 connected to the first resistor R1, the third terminal 23 is grounded GND-485, and the ground of the third terminal 23 is bus-side ground GND-485.

Normally, in the case of general industrial application, the overvoltage protection core U2 may not be provided, but in some special cases, for example, the voltage of the a-terminal 485-a and the B-terminal 485-B of the RS485 bus is high, and at this time, the overvoltage protection core U2 may be provided to protect the circuit.

In some embodiments, referring to fig. 3, the VCC pins (2, 8) include a first VCC pin 2 and a second VCC pin 8, the first VCC pin 2 also being grounded GND through a third capacitor C3 and a fourth capacitor C4 in parallel; the second VCC pin 8 is also grounded GND through the first capacitor C1 and the second capacitor C2 connected in parallel.

Illustratively, referring to fig. 4, the first VCC pin 2 is further connected to the logic side ground GND through a third capacitor C3 and a fourth capacitor C4 connected in parallel, wherein the third capacitor C3 is set to 10UF/10V and the fourth capacitor C4 is set to 100NF/50V; the second VCC pin 8 is also connected to the logic side ground GND through a first capacitor C1 and a second capacitor C2 which are connected in parallel, wherein the first capacitor C1 is set to 10UF/10V, and the second capacitor C2 is set to 100NF/50V.

In some embodiments, referring to fig. 3, GND2 pin (11, 14, 16, 20) includes first GND2 pin 20, second GND2 pin 16, third GND2 pin 14, and fourth GND2 pin 11, first GND2 pin 20 also being connected to visin pin 19 through seventh capacitor C7 and eighth capacitor C8 in parallel; the fourth GND2 pin 11 is also connected to the visout pin 12 through a fifth capacitor C5 and a sixth capacitor C6 connected in parallel.

Illustratively, referring to FIG. 4, the seventh capacitance C7 is set to 100NF/50V, the eighth capacitance C8 is set to 100NF/50V, the fifth capacitance C5 is set to 10UF/25V, and the sixth capacitance C6 is set to 100NF/50V. By arranging the parallel capacitors in the circuit, the two parallel capacitors can restrain noise and reduce ripple during the working process of the circuit.

In some embodiments, referring to fig. 3 and 4, the power source VCC includes 3.3V or 5V.

For example, in the practical application process, the voltage of the power supply can be selected according to the requirement of the main controller MCU, which is not limited in this application.

In some embodiments, as shown with reference to fig. 3, the ground of GND1 pin (1, 3,9, 10) and TXD pin 7 is logic side ground GND, the ground of GND2 pin (11, 14, 16, 20) and visout pin 12 is bus side ground GND-485, and logic side ground GND and bus side ground GND-485 are non-conductive to each other.

According to the universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) protocol, the state of the signal line is high when the bus is in an idle state, i.e., the state of the signal line is "1". Fig. 5 is a schematic diagram of a truth table of a control circuit based on an RS485 transceiver according to an embodiment of the present application, fig. 6 is a truth representation intention of a transmission state of an RS485 chip according to an embodiment of the present application, and fig. 7 is a truth representation intention of a reception state of an RS485 chip according to an embodiment of the present application. Note that DE, TXD, Y, Z in fig. 6 represents the DE pin, the TXD pin, the Y pin, and the Z pin of the RS485 chip, respectively. a-B in fig. 7 shows differential signals, i.e., the voltage difference between the a-terminal and the B-terminal on the RS485 bus; RE# and RXD respectively represent RE# pins and RXD pins of the RS485 chip, an input open circuit represents that the end A and the end B on the RS485 bus are not connected with slave equipment, and the slave equipment can be temperature chips, sensors, battery control modules, ultrasonic radars and other equipment; NC indicates unconnected.

Fig. 8 is a timing diagram of a control circuit of the RS485 transceiver when the main controller is in a transmitting state according to an embodiment of the present application, and fig. 9 is a timing diagram of a control circuit of the RS485 transceiver when the main controller is in a receiving state according to an embodiment of the present application. It should be noted that, in fig. 8 and fig. 9, CLOCK represents a CLOCK, and CLOCK rising edges 1 to 9 may represent complete CLOCK cycles in the RS485 bus data transmission process, for example, complete one data transmission in one CLOCK cycle (between CLOCK rising edge 1 and CLOCK rising edge 2); MCU-RX and MCU-TX represent the receiving end and transmitting end of the master controller MCU, RE# and DE represent RE# pin and DE pin of RS485 chip, 485-A and 485-B represent A end and B end of RS485 bus respectively; the shaded portion represents any one of the states that may be tri-stated (high or low or high resistive state) without concern for the state.

In some embodiments, referring to fig. 3, when the master controller MCU is in a transmitting state, the transmitting end MCU-TX of the master controller MCU outputs a transmitting end signal with a high-low level change, when the transmitting end signal is in a low level, the transmitting end MCU-TX controls the re# pin 5 and the DE pin 6 to be in a high level through a level inverting subcircuit, the RS485 chip U1 is in a transmitting mode, the Y pin 13 and the Z pin 15 are controlled to be in a low level through the TXD pin 7, the a end 485-a is pulled down to be in a low level through the Y pin 13, the B end 485-B is pulled up to be in a high level through the Z pin 15, and the RS485 bus is in a logic low state; when the signal of the transmitting end is in a high level, the transmitting end MCU-TX controls the RE# pin 5 and the DE pin 6 to be in a low level through the level reversing sub-circuit, the RS485 chip U1 is in a receiving mode, the Y pin 13 and the Z pin 15 are closed, the A end 485-A is pulled up to be in a high level through the third resistor R3, the B end 485-B is pulled down to be in a low level through the second resistor R2, and the RS485 bus is in a logic high state.

For example, referring to fig. 3 and 5 to 8, when the master controller MCU is in a transmitting state, the transmitting end MCU-TX of the master controller MCU outputs a transmitting end signal with a high-low level change, i.e., in fig. 8, the MCU-TX is in a state with a high-low level change at different clock cycle levels, while the MCU-RX is idle, and the MCU-RX is always in a high-level state.

Referring to fig. 8, for example, in one clock cycle (between clock rising edge 1 and clock rising edge 2), when the transmitting-side signal is low, the transmitting-side MCU-TX controls the re# pin 5 and the DE pin 6 to be high through the level inverting subcircuit, the RS485 chip U1 is in the transmitting mode, the Y pin 13 and the Z pin 15 are controlled to be low through the TXD pin 7, it can be seen in row 2 602 of the truth table shown in fig. 6 that the a-side 485-a is pulled low through the Y pin 13, the B-side 485-B is pulled high through the Z pin 15, and the RS485 bus is in the logic low state.

Referring to fig. 8, for example, in one clock cycle (between clock rising edge 2 and clock rising edge 3), when the transmitting end signal is at a high level, the transmitting end MCU-TX controls the re# pin 5 and the DE pin 6 to be at a low level through the level reversing sub-circuit, the RS485 chip U1 is in a receiving mode, the Y pin 13 and the Z pin 15 are turned off, the a end 485-a is pulled high to be at a high level through the third resistor R3, the B end 485-B is pulled low to be at a low level through the second resistor R2, and the RS485 bus is in a logic high state.

In some embodiments, referring to fig. 3, when the main controller MCU is in a receiving state, the receiving end MCU-RX of the main controller MCU receives a receiving end signal with a high-low level change, the transmitting end MCU-TX of the main controller MCU keeps transmitting a high-level signal, the transmitting end MCU-TX controls the re# pin 5 and the DE pin 6 to be low level through a level inverting sub-circuit, the RS485 chip U1 is in a receiving mode, the Y pin 13 and the Z pin 15 are closed, the state of the RS485 bus is controlled by a slave device (not shown) on the RS485 bus, wherein when the a end 485-a is pulled down to be low level by the slave device and the B end 485-B is pulled up to be high level, the RS485 bus is in a logic low state, and the receiving end signal is low level; when the A-terminal 485-A is pulled high from the device and the B-terminal 485-B is pulled low, the RS485 bus is in a logic high state and the receiving terminal signal is high.

For example, referring to fig. 3, 5 to 7 and 9, when the master controller MCU is in the receiving state, the receiving end MCU-RX of the master controller MCU receives the receiving end signal with a varying level, i.e., in fig. 9, the level received by the MCU-RX at different clock cycles is in a varying state. The transmitting end MCU-TX of the main controller MCU is in an idle state, the MCU-TX always keeps transmitting a high-level signal in the clock period (in rising edges 1 to 9) of data transmission, the transmitting end MCU-TX always keeps a low level in the clock period (in rising edges 1 to 9) of data transmission through a level reversing sub-circuit control RE# pin 5 and DE pin 6, an RS485 chip U1 is in a receiving mode, the Y pin 13 and the Z pin 15 can be seen to be closed in a 3 rd row 603 of a truth table shown in fig. 6, and the state of an RS485 bus is controlled by slave equipment (not shown) on the RS485 bus.

Referring to fig. 9, for example, in one clock cycle (between clock rising edge 1 and clock rising edge 2), when a-terminal 485-a is pulled low by the slave device and B-terminal 485-B is pulled high, the RS485 bus is in a logic low state and the receiving terminal signal is low.

Referring to fig. 9, for example, in one clock cycle (between clock rising edge 2 and clock rising edge 3), when a-terminal 485-a is pulled high from the device and B-terminal 485-B is pulled low, the RS485 bus is in a logic high state and the receiving terminal signal is high.

According to the control circuit based on the RS485 transceiver, each RS485 communication interface only occupies 2 pins of the MCU, and pin resources of the MCU can be saved. And full duplex communication of the hardware self-adaptive transceiving mode switching of the RS485 transceiver is realized through the innovative design of the RS485 transceiver chip circuit, and the transceiving working mode is switched without MCU software control, namely, logic control is performed without MCU software.

While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing application disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations of the present application may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this application, and are therefore within the spirit and scope of the exemplary embodiments of this application.

Some aspects of the present application may be performed entirely by hardware, entirely by software (including firmware, resident software, micro-code, etc.) or by a combination of hardware and software. The above hardware or software may be referred to as a "data block," module, "" engine, "" unit, "" component, "or" system. The processor may be one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital signal processing devices (DAPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or a combination thereof. Furthermore, aspects of the present application may take the form of a computer product, comprising computer-readable program code, embodied in one or more computer-readable media. For example, computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, tape … …), optical disk (e.g., compact disk CD, digital versatile disk DVD … …), smart card, and flash memory devices (e.g., card, stick, key drive … …).

The computer readable medium may comprise a propagated data signal with the computer program code embodied therein, for example, on a baseband or as part of a carrier wave. The propagated signal may take on a variety of forms, including electro-magnetic, optical, etc., or any suitable combination thereof. A computer readable medium can be any computer readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code located on a computer readable medium may be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signals, or the like, or a combination of any of the foregoing.

Meanwhile, the present application uses specific words to describe embodiments of the present application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present application may be combined as suitable.

In some embodiments, numbers describing the components, number of attributes are used, it being understood that such numbers being used in the description of embodiments are modified in some examples by the modifier "about," approximately, "or" substantially. Unless otherwise indicated, "about," "approximately," or "substantially" indicate that the number allows for a 20% variation. Accordingly, in some embodiments, numerical parameters set forth in the specification and claims are approximations that may vary depending upon the desired properties sought to be obtained by the individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and employ a method for preserving the general number of digits. Although the numerical ranges and parameters set forth herein are approximations that may be employed in some embodiments to confirm the breadth of the range, in particular embodiments, the setting of such numerical values is as precise as possible.

While the present application has been described with reference to the present specific embodiments, those of ordinary skill in the art will recognize that the above embodiments are for illustrative purposes only, and that various equivalent changes or substitutions can be made without departing from the spirit of the present application, and therefore, all changes and modifications to the embodiments described above are intended to be within the scope of the claims of the present application.

Claims

1. A control circuit based on an RS485 transceiver, comprising: RS485 chip and level reversing sub-circuit, wherein

The GND1 pin of the RS485 chip is grounded, and the VCC pin is connected with a power supply;

the RXD pin of the RS485 chip is connected with the receiving end of the main controller;

the RE# pin and the DE pin of the RS485 chip are connected with the transmitting end of the main controller through the level reversing sub-circuit, and the level reversing sub-circuit is used for reversing the level received from the transmitting end;

the TXD pin of the RS485 chip is grounded;

the GND2 pin of the RS485 chip is grounded, and the VISOIN pin is connected with an isolation voltage;

the A pin of the RS485 chip is connected with the A end of the RS485 bus, the B pin of the RS485 chip is connected with the B end of the RS485 bus, and a first resistor is connected in parallel between the A pin and the B pin;

the Z pin of the RS485 chip is connected with the B pin, and the Y pin is connected with the A pin;

the VISOOUT pin of the RS485 chip is grounded, and the VISOOUT pin is also connected with the VISOIN pin.

2. The control circuit of claim 1, wherein the a pin is further connected to the isolation voltage through a third resistor; the pin B is also grounded through a second resistor.

3. The control circuit of claim 1, wherein the level reversing sub-circuit comprises: the transistor comprises a triode, the emitting electrode of the triode is grounded, the collecting electrode of the triode is connected with the RE# pin and the DE pin, the base electrode of the triode is connected with the sending end of the main controller through a fourth resistor, the collecting electrode is also connected with the power supply through a fifth resistor, and a sixth resistor is also connected between one end of the fourth resistor connected with the sending end of the main controller and one end of the fifth resistor connected with the power supply.

4. The control circuit of claim 1, wherein the level reversing sub-circuit comprises: the MOS transistor comprises a MOS transistor, a source electrode of the MOS transistor is grounded, a drain electrode of the MOS transistor is connected with the RE# pin and the DE pin, a grid electrode of the MOS transistor is connected with a transmitting end of the main controller through a fourth resistor, the drain electrode is also connected with a power supply through a fifth resistor, and a sixth resistor is also connected between one end of the fourth resistor connected with the transmitting end of the main controller and one end of the fifth resistor connected with the power supply.

5. The control circuit according to claim 3 or 4, wherein the RXD pin is further connected to the power supply through a seventh resistor.

6. The control circuit of claim 2, further comprising an overvoltage protection chip comprising a first end, a second end, and a third end, the first end connected to an end of the second resistor connected to the first resistor, the second end connected to an end of the third resistor connected to the first resistor, the third end grounded.

7. The control circuit of claim 1, wherein the VCC pin comprises a first VCC pin and a second VCC pin, the first VCC pin further grounded through third and fourth capacitors connected in parallel; the second VCC pin is also grounded through a first capacitor and a second capacitor connected in parallel.

8. The control circuit of claim 1, wherein the GND2 pin comprises a first GND2 pin, a second GND2 pin, a third GND2 pin, and a fourth GND2 pin, the first GND2 pin further connected to the visin pin through a seventh capacitor and an eighth capacitor in parallel; the fourth GND2 pin is also connected with the VISOOUT pin through a fifth capacitor and a sixth capacitor which are connected in parallel.

9. The control circuit of claim 1, wherein the power source comprises 3.3V or 5V.

10. The control circuit of claim 1, wherein the ground for the GND1 pin and the TXD pin is a logic side ground and the ground for the GND2 pin and the visout pin is a bus side ground.

11. The control circuit of claim 2, wherein the transmitter of the main controller outputs a transmitter signal of varying high and low levels when the main controller is in a transmitting state,

when the signal of the transmitting end is low level, the transmitting end controls the RE# pin and the DE pin to be high level through the level reversing sub-circuit, the RS485 chip is in a transmitting mode, the Y pin and the Z pin are controlled to be low level through the TXD pin, the A end is pulled down to be low level through the Y pin, the B end is pulled up to be high level through the Z pin, and the RS485 bus is in a logic low state;

when the signal of the transmitting end is at a high level, the transmitting end controls the RE# pin and the DE pin to be at a low level through the level reversing sub-circuit, the RS485 chip is in a receiving mode, the Y pin and the Z pin are closed, the A end is pulled up to be at a high level through the third resistor, the B end is pulled down to be at a low level through the second resistor, and the RS485 bus is in a logic high state.

12. The control circuit of claim 2 wherein the receiving end of the master controller receives a receiving end signal of a high-low level change when the master controller is in a receiving state, the transmitting end of the master controller keeps transmitting a high-level signal, the transmitting end controls the RE# pin and the DE pin to be low level through the level reversing sub-circuit, the RS485 chip is in a receiving mode, the Y pin is closed with the Z pin, the state of the RS485 bus is controlled by a slave device on the RS485 bus,

when the A end is pulled down to be low level by the slave device and the B end is pulled up to be high level, the RS485 bus is in a logic low state, and the receiving end signal is low level;

when the A end is pulled up to be high level by the slave device and the B end is pulled down to be low level, the RS485 bus is in a logic high state, and the receiving end signal is high level.