WO2014048007A1 - 一种驱动电路、液晶显示装置及驱动方法 - Google Patents

一种驱动电路、液晶显示装置及驱动方法 Download PDF

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Publication number
WO2014048007A1
WO2014048007A1 PCT/CN2012/084091 CN2012084091W WO2014048007A1 WO 2014048007 A1 WO2014048007 A1 WO 2014048007A1 CN 2012084091 W CN2012084091 W CN 2012084091W WO 2014048007 A1 WO2014048007 A1 WO 2014048007A1
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Prior art keywords
controllable switch
turned
compensation line
liquid crystal
coupled
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PCT/CN2012/084091
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English (en)
French (fr)
Inventor
王念茂
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/703,027 priority Critical patent/US20140091995A1/en
Publication of WO2014048007A1 publication Critical patent/WO2014048007A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • Driving circuit liquid crystal display device and driving method
  • the present invention relates to the field of liquid crystal display, and more particularly to a driving circuit, a liquid crystal display device, and a driving method.
  • FIG. 1 is a schematic diagram of a driving structure of a multi-sub-pixel charge sharing liquid crystal panel
  • FIG. 2 is a schematic circuit diagram of the inside of the liquid crystal panel of FIG. 1 , that is, a low color shifting technology in a TFT-LCD panel.
  • Internal circuit architecture the principle of this architecture is to divide a pixel into a main area (Sub Area) and a sub area (Sub Area).
  • the main area and The sub-areas are all charged to the same voltage.
  • the pulse of the second scanning line G2 turns on the second line, the upper row of charge sharing switch CS is also turned on, and the voltage of the sub-area and the capacitances Cxi and Cx2 are used for charge sharing.
  • the pixel voltages corresponding to the main area (Sub Area) and the sub area (Sub Area) are different, and the brightness of the corresponding display is also different.
  • the pixel brightness becomes the middle of the mixed area between the main area and the sub area.
  • the LCS architecture requires an additional compensation line based on the original scanning line.
  • the G1 ⁇ G1080 lines are all scan lines, while the G1081 is the compensation line.
  • the gate driving chip is required to be driven regardless of the scan line or the data line, so that the number of output channels of the gate driving chip is required to be one more than the number of lines displayed by the LCD, as shown in FIG. 2, the gate The driver chip outputs a total of 1081 channels.
  • the number of output channels of common gate driver chips can be divisible by 1080, such as 270 channels, 360 channels, 540 channels with 4, 3, and 2 cascades can achieve 1080 channel output, but there is no way to support Figure 2
  • the last line of the LCS architecture The current practice is to drive 1081 rows with a gate driver chip with more output channels than the 1081 channel. The excess channel number will be discarded, but this will cause some channels to be wasted, and each of the cascades
  • the gate drive chip output channel is different, set the gate drive core
  • the setting of the relevant pin number of the chip output channel is high or low, and the setting is also complicated.
  • the technical problem to be solved by the present invention is to provide a driving circuit, a liquid crystal display device and a driving method for designing a cartridge and realizing compensation line control without occupying a gate driving chip channel.
  • a driving circuit of a multi-subpixel charge sharing type liquid crystal panel comprising a plurality of scanning lines directly driven by a gate driving chip, the driving circuit further comprising a compensation line, and a level conversion coupled with the compensation line
  • the module, the level conversion module outputs a control signal to drive the compensation line after the last scan of the scan line ends, before the start of the next frame scan.
  • the level conversion module includes a first controllable switch that is turned on at a high level, a second controllable switch that is turned on at a low level, and a second controllable switch that controls the first controllable switch and the second controllable switch a channel control unit; an input end of the first controllable switch is coupled to a reference high level signal, and an input end of the second controllable switch is coupled to a reference low level signal; the first controllable switch and An output of the second controllable switch is coupled to the compensation line, the control end of which is coupled to the channel control unit.
  • This is a circuit structure of a specific level conversion module. The action logic of the first controllable switch and the second controllable switch are opposite, which can effectively avoid malfunction.
  • the level conversion module further includes a third controllable switch, an input end of the third controllable switch is coupled to the compensation line, a discharge resistor is coupled to the output end, and a control end thereof is coupled to the channel a control unit; the third controllable switch is turned on after the first controllable switch is turned on, is turned off after the second controllable switch is turned on, and after the third controllable switch is turned on, the first controllable The switch is off. With the controllable switch, the discharge can be performed while the compensation line is in the high state, so that the voltage is gradually reduced, and then pulled down to the low level by the third controllable switch to form a chamfering waveform.
  • the driving circuit of the liquid crystal panel includes a timing control circuit, and the channel control unit of the level converting module receives the compensation line clock signal and the chamfering control signal output by the timing control circuit; the first controllable switch is compensated The rising edge of the line clock signal is turned on, and the falling edge of the chamfer control signal Turning off; the second controllable switch is turned on at the falling edge of the compensation line clock signal, and is turned off at the rising edge of the next compensation line clock signal; the third controllable switch is turned on at the falling edge of the chamfering control signal, in the compensation The falling edge of the line clock signal is turned off.
  • the timing control circuit controls the output signals of the scan lines and the data lines of the liquid crystal panel. Therefore, the compensation line clock signal and the chamfer control signal are provided by the timing control circuit, and the driving timing and waveform of the compensation line can be accurately controlled without additional design driving.
  • the circuit facilitates the tube and reduces the hardware cost.
  • a liquid crystal display device comprising the above-described driving circuit of a multi-sub-pixel charge sharing type liquid crystal panel.
  • the liquid crystal display device includes a panel and a control circuit board, wherein the panel is provided with a plurality of scan lines and a compensation line, the control circuit board includes a timing control circuit, and the electricity coupled with the timing control circuit Flat conversion module.
  • the level conversion module and the timing control circuit are integrated into the same control board, and the distance between the two is short, which is convenient for circuit design and can also reduce signal attenuation.
  • a driving method of a multi-sub-pixel charge-sharing liquid crystal panel comprising the step A: after the scanning of the last scanning line by the gate driving chip is finished, the compensation circuit for driving the liquid crystal panel is driven by the level conversion module before the start of the next frame scanning .
  • the level conversion module includes a first controllable switch and a second controllable switch coupled to the compensation line, and the step A includes:
  • A1 controlling the first controllable switch to be turned on at the rising edge of the compensation line clock signal; coupling a reference high level signal to the compensation line;
  • A2 The first controllable switch is turned off at the falling edge of the compensation line clock signal, and the second controllable switch is turned on to couple a reference low level signal to the compensation line.
  • This is a standard square wave control waveform, which is implemented in a single way, which helps to reduce the design and the corresponding hardware cost.
  • the level conversion module includes a first controllable switch, a second controllable switch, and a third controllable switch coupled to the compensation line, and the step A includes:
  • A1 controlling the first controllable switch to be turned on at the rising edge of the compensation line clock signal; coupling a reference high level signal to the compensation line;
  • A2 controlling the first controllable switch to be turned off at the falling edge of the chamfering control signal, and simultaneously turning on the third controllable switch; coupling the compensation line to a discharge resistor for discharging;
  • A3 The third controllable switch is turned off at the falling edge of the compensation line clock signal, and the second controllable switch is turned on to couple a reference low level signal to the compensation line.
  • This is another control waveform that can form a chamfer on the waveform of the standard square wave to form a chamfered waveform to improve the reliability of the control.
  • the compensation clock signal and the chamfer control signal are generated by a timing control circuit of the liquid crystal panel.
  • the timing control circuit controls the output signals of the scan lines and the data lines of the liquid crystal panel. Therefore, the compensation line clock signal and the chamfer control signal are provided by the timing control circuit, and the driving timing and waveform of the compensation line can be accurately controlled without additional design.
  • the drive circuit facilitates the tube and reduces the hardware cost.
  • the level conversion module since the level conversion module is separately used to drive the compensation line, after the end of the last scan line scan, a control signal is output to drive the compensation line before the start of the next frame scan, so that the drive of the compensation line does not need to occupy the gate drive.
  • the channel of the chip, the gate driver chip only needs to be configured according to the actual number of scan lines, which can reduce the waste of the channel and reduce the hardware cost. In addition, it does not need to consider the driving cooperation problem of the gate drive chip output channel number and the scan line and the compensation line.
  • the scan line driver can be designed as usual, and the level conversion module only needs to drive the compensation line, which is relatively independent of other drive circuits, which is beneficial to reduce the development difficulty and design a comparison.
  • FIG. 1 is a schematic diagram of a conventional multi-subpixel charge sharing liquid crystal display device
  • FIG. 2 is a schematic diagram of an internal circuit of the multi-subpixel charge sharing liquid crystal panel of FIG. 1;
  • 3 is a schematic diagram of multi-subpixel display synthesis
  • FIG. 4 is a schematic view of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the connection of a timing control circuit and a level conversion module according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of an internal circuit of a level conversion module according to an embodiment of the present invention.
  • Figure 7 is a schematic diagram of driving waveforms of an embodiment of the present invention. ⁇ detailed description ⁇
  • the invention discloses a liquid crystal display device comprising a multi-sub-pixel liquid crystal panel and a driving circuit thereof.
  • the liquid crystal panel comprises a plurality of scanning lines directly driven by the gate driving chip, and further comprises a compensation line and a compensation A line-coupled level shifting module, the compensation line is not coupled to the scan line, and the level shifting module outputs a control signal to drive the compensation line after the end of the last scan of the scan line before the start of the next frame scan.
  • the level conversion module since the level conversion module is separately used to drive the compensation line, after the end of the last scan line scan, a control signal is output to drive the compensation line before the start of the next frame scan, so that the drive of the compensation line does not need to occupy the gate drive.
  • the channel of the chip, the gate driver chip only needs to be configured according to the actual number of scan lines, which can reduce the waste of the channel and reduce the hardware cost. In addition, it does not need to consider the driving cooperation problem of the gate drive chip output channel number and the scan line and the compensation line.
  • the scan line driver can be designed as usual, and the level conversion module only needs to drive the compensation line, which is relatively independent of other drive circuits, which is beneficial to reduce the development difficulty and design a comparison.
  • the liquid crystal panel has vertical and horizontal scanning lines and data lines, and two gate driving chips (GDI ⁇ GD4) are arranged on both sides of the liquid crystal panel, which are responsible for driving 1080 scanning lines of the liquid crystal panel. (Gl ⁇ G1080), there is also a compensation line G1081 driven by the level conversion module.
  • the upper part of the liquid crystal panel is provided with a plurality of source driving chips, the source driving chip is controlled by the source driving circuit board, the driving of the entire liquid crystal panel is realized by the control circuit board, the timing control circuit is included in the control circuit board, and the timing is A level shifting module coupled to the control circuit.
  • the level conversion module includes a first controllable switch Q1 that is turned on at a high level, a second controllable switch Q2 that is turned on at a low level, and a first controllable switch Q1 and a second controllable a channel control unit of the switch Q2; an input end of the first controllable switch Q1 is coupled to a reference high level signal VGH, and an input end of the second controllable switch Q2 is coupled to a reference low level signal VGL; the first controllable switch The output of Q1 and the second controllable switch Q2 is coupled to a compensation line G1081 whose control terminal is coupled to the channel control unit.
  • the level conversion module is further provided with a third controllable switch Q3, the input end of the third controllable switch Q3 being coupled to the compensation line, The output end is coupled with a discharge resistor, and the control end is coupled to the channel control unit; the third controllable switch Q3 is turned on after the first controllable switch Q1 is turned on, and is turned off after the second controllable switch Q2 is turned on, the first After the three controllable switches Q3 are turned on, the first controllable switch Q1 is turned off.
  • the action logics of the first controllable switch Q1 and the second controllable switch Q2 are opposite, and the malfunction can be effectively avoided.
  • the third controllable switch Q3 can discharge when the compensation line is in a high level state, so that the voltage is gradually reduced, and then pulled down to a low level through the third controllable switch Q3 to form a chamfering waveform.
  • the channel control unit of the level conversion module receives the compensation line clock signal CKVX and the chamfer control signal GVOFF output by the timing control circuit; the first controllable switch Q1 is turned on at the rising edge of the compensation line clock signal CKVX, and is chamfered The falling edge of the control signal GVOFF is turned off; the second controllable switch Q2 is turned on at the falling edge of the compensation line clock signal CKVX, and is turned off at the rising edge of the next compensation line clock signal CKVX; the third controllable switch Q3 is at the chamfering control signal GVOFF The falling edge turns on and turns off at the falling edge of the compensation line clock signal CKVX.
  • the timing control circuit controls the output signals of the scan lines and the data lines of the liquid crystal panel. Therefore, the compensation line clock signal CKVX and the chamfer control signal GVOFF are provided by the timing control circuit, and the driving timing and waveform of the compensation line can be accurately controlled without additional Designing the drive circuit facilitates the tubeization and reduces hardware costs.
  • the embodiment further discloses a driving method of the multi-sub-pixel liquid crystal panel, comprising the step A: using a level conversion module to drive the compensation line of the liquid crystal panel before the start of the next frame scan after the last scanning line scan ends.
  • the level conversion module includes a first controllable switch, a second controllable switch, and a third controllable switch, which are included in step A (see the driving waveform of FIG. 7):
  • A1 controlling the first controllable switch to be turned on at the rising edge of the compensation line clock signal CKVX; coupling a reference high level signal to the compensation line G1081;
  • A2 controlling the first controllable switch to be turned off at the falling edge of the chamfering control signal GVOFF, and simultaneously turning on the third controllable switch; coupling the compensation line to a discharge resistor for discharging;
  • A3 Control the third controllable switch to close at the falling edge of the compensation line clock signal CKVX, and control the second The controllable switch is turned on, coupling a reference low level signal to compensation line G1081.
  • the timing control circuit controls the output signals of the scan lines and the data lines of the liquid crystal panel, the compensation line clock signal CKVX and the chamfer control signal GVOFF can be provided by the timing control circuit, and the driving timing and waveform of the compensation line can be accurately controlled. There is no need to design additional drive circuits, reduce the number of circuits and reduce hardware costs.
  • the embodiment is a specific control waveform, and a chamfer angle can be formed on the waveform of the standard square wave to form a chamfer waveform, thereby improving the reliability of the control.
  • the level conversion module includes a first controllable switch and a second controllable switch, and the step A includes:
  • A1 controlling the first controllable switch to be turned on at the rising edge of the compensation line clock signal; coupling a reference high level signal to the compensation line;
  • A2 The first controllable switch is turned off at the falling edge of the compensation line clock signal, and the second controllable switch is turned on to couple a reference low level signal to the compensation line.
  • This embodiment is a standard square wave control waveform, and the implementation is simple, which helps to reduce the design and the corresponding hardware cost.

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Description

一种驱动电路、 液晶显示装置及驱动方法
【技术领域】
本发明涉及液晶显示领域， 更具体的说， 涉及一种驱动电路、 液晶显示装 置及驱动方法。
【背景技术】
在大尺寸薄膜晶体管液晶面板（TFT-LCD )模组开发过程中， 为了解决大 视角色偏的问题， 通常会采用 LCS(Low Color Shift: 低色偏)的技术。 参看图 1 , 图 1是现有的一种多子像素电荷共享式液晶面板的驱动架构图， 图 2是图 1液 晶面板内部的电路示意图，也就是一种低色偏技术在 TFT-LCD 面板内部电路架 构，这种架构的原理是将一个像素分成主区域（Main Area )和副区域（Sub Area ), 在当第一条扫描线 G1的脉沖（Pulse )打开第一行时， 主区域和副区域都充电到 一样的电压， 在当第二条扫描线 G2的脉沖（Pulse )打开第二行时， 也打开上一 行电荷共享开关 CS , 将副区域的电压和电容 Cxi , Cx2做电荷分享， 此时主区 域（Main Area )和副区域 ( Sub Area )对应的像素电压不同， 对应显示的亮度 也不一样， 通过人眼的混色作用， 像素亮度变成主区域和副区域混色后的中间 亮度，这样大视角的亮度更加趋近于正视角的亮度（如图 3所示；)，但是这种 LCS 架构在原有的扫描线基础上， 需要额外增加一条补偿线。 图 2中 G1 ~ G1080行 都是扫描线， 而 G1081则是补偿线。 现有技术中， 无论扫描线还是数据线都需 要门极驱动芯片来驱动， 这样就要求门极驱动芯片的输出通道数比 LCD显示的 行数还要多一个， 如图 2所示， 门极驱动芯片输出总共 1081通道（Channel )。 目前常用门极驱动芯片输出通道数都是可以被 1080整除，比如 270通道， 360 通 道， 540 通道分别用 4颗， 3颗， 2颗级联可以实现 1080通道输出， 但是没办 法支援图 2的 LCS架构最后一行的驱动.现有的做法是用比 1081通道更多输出 通道的门极驱动芯片来驱动 1081行， 多余的通道数将舍弃， 但是这样造成一些 通道的浪费， 而且级联的各颗门极驱动芯片输出通道不一样， 设定门极驱动芯 片输出通道数的相关引脚为高电平或者低电平的设定也比较复杂。 【发明内容】
本发明所要解决的技术问题是提供一种设计筒单、 无需占用门极驱动芯片 通道就能实现补偿线控制的驱动电路、 液晶显示装置及驱动方法。
本发明的目的是通过以下技术方案来实现的：
、 一种多子像素电荷共享式液晶面板的驱动电路， 包括由门极驱动芯片直 接驱动的多条扫描线， 所述驱动电路还包括一条补偿线， 以及与所述补偿线耦 合的电平转换模块， 所述电平转换模块在最后一条扫描线扫描结束之后， 下一 帧扫描开始之前输出一个控制信号驱动所述补偿线。
进一步的， 所述电平转换模块包括高电平导通的第一可控开关、 低电平导 通的第二可控开关、 以及控制所述第一可控开关和第二可控开关的通道控制单 元； 所述第一可控开关的输入端耦合到一基准高电平信号， 所述第二可控开关 的输入端耦合到一基准低电平信号； 所述第一可控开关和第二可控开关的输出 端耦合到所述补偿线， 其控制端耦合到所述通道控制单元。 此为一种具体的电 平转换模块的电路结构， 第一可控开关和第二可控开关的动作逻辑相反， 可以 有效避免误动作。
进一步的， 所述电平转换模块还包括第三可控开关， 所述第三可控开关的 输入端耦合到所述补偿线， 其输出端耦合有放电电阻， 其控制端耦合到所述通 道控制单元； 所述第三可控开关在第一可控开关导通后导通， 在第二可控开关 导通后关闭， 所述第三可控开关导通后， 所述第一可控开关关闭。 利用可控开 关， 可以在补偿线处于高电平状态的时候进行放电， 使得电压逐步降低， 然后 再通过第三可控开关拉低到低电平， 形成了切角波形。
进一步的， 所述液晶面板的驱动电路包括时序控制电路， 所述电平转换模 块的通道控制单元接收时序控制电路输出的补偿线时钟信号和削角控制信号； 所述第一可控开关在补偿线时钟信号上升沿导通， 并在削角控制信号的下降沿 关闭； 所述第二可控开关在补偿线时钟信号下降沿导通， 并在下一个补偿线时 钟信号上升沿关闭； 所述第三可控开关在削角控制信号的下降沿导通， 在补偿 线时钟信号下降沿关闭。 时序控制电路控制着液晶面板的扫描线和数据线的输 出信号， 因此， 由时序控制电路来提供补偿线时钟信号和削角控制信号， 可以 准确控制补偿线的驱动时机和波形， 无须额外设计驱动电路， 有利于筒化电路 并降低硬件成本。
一种液晶显示装置， 包括上述的一种多子像素电荷共享式液晶面板的驱动 电路。
进一步的， 所述液晶显示装置包括面板和控制电路板， 所述面板内设有多 条扫描线和一条补偿线， 所述控制电路板包括时序控制电路， 以及跟时序控制 电路耦合的所述电平转换模块。 将电平转换模块和时序控制电路集成到同一控 制板中， 两者之间距离短， 方便电路设计， 也可以减少信号衰减。
一种多子像素电荷共享式液晶面板的驱动方法， 包括步骤 A: 在最后一条 扫描线由门极驱动芯片驱动扫描结束之后， 在下一帧扫描开始之前采用电平转 换模块驱动液晶面板的补偿线。
进一步的， 所述电平转换模块包括跟补偿线耦合的第一可控开关和第二可 控开关， 所述步骤 A中包括：
A1 : 在补偿线时钟信号上升沿控制第一可控开关导通； 将一个基准高电平 信号耦合到补偿线；
A2: 在补偿线时钟信号下降沿控制第一可控开关关闭， 并控制第二可控开 关导通， 将一个基准低电平信号耦合到补偿线。 此为一种标准的方波控制波形， 实现方式筒单， 有利于降低设计和相应的硬件成本。
进一步的， 所述电平转换模块包括跟补偿线耦合的第一可控开关、 第二可 控开关和第三可控开关， 所述步骤 A中包括：
A1 : 在补偿线时钟信号上升沿控制第一可控开关导通； 将一个基准高电平 信号耦合到补偿线； A2: 在削角控制信号的下降沿控制第一可控开关关闭， 并同时导通第三可 控开关； 将补偿线耦合到一放电电阻进行放电；
A3: 在补偿线时钟信号下降沿控制第三可控开关关闭， 并控制第二可控开 关导通， 将一个基准低电平信号耦合到补偿线。 此为另一种控制波形， 可以在 标准方波的波形上形成切角， 形成切角波形， 提高控制的可靠性。
进一步的， 所述补偿时钟信号和削角控制信号由液晶面板的时序控制电路 产生。 时序控制电路控制着液晶面板的扫描线和数据线的输出信号， 因此， 由 时序控制电路来提供补偿线时钟信号和削角控制信号， 可以准确控制补偿线的 驱动时机和波形， 且无须额外设计驱动电路， 有利于筒化电路并降低硬件成本。
本发明由于单独采用电平转换模块来驱动补偿线， 在最后一条扫描线扫描 结束之后， 下一帧扫描开始之前输出一个控制信号驱动所述补偿线， 这样补偿 线的驱动就无需占用门极驱动芯片的通道， 门极驱动芯片只需要按实际的扫描 线数量来配置， 可以减少通道的浪费， 降低硬件成本； 另外也不用考虑门极驱 动芯片输出通道数跟扫描线和补偿线的驱动配合问题， 扫描线的驱动按常规设 计即可， 而电平转换模块只需要驱动补偿线， 跟其他驱动电路相对独立， 有利 于降低开发难度， 设计比较筒单。
【附图说明】
图 1是现有的一种多子像素电荷共享式液晶显示装置示意图；
图 2是图 1多子像素电荷共享式液晶面板内部电路示意图；
图 3是多子像素显示合成示意图；
图 4是本发明实施例的液晶显示装置示意图；
图 5是本发明实施例时序控制电路和电平转换模块连接示意图；
图 6是本发明实施例电平转换模块的内部电路示意图；
图 7是本发明实施例驱动波形示意图。 【具体实施方式】
本发明公开一种液晶显示装置， 该液晶显示装置包括多子像素液晶面板及 其驱动电路， 液晶面板内包括多条由门极驱动芯片直接驱动的扫描线， 还包括 一条补偿线， 以及跟补偿线耦合的电平转换模块， 补偿线不与扫描线耦合， 电 平转换模块在最后一条扫描线扫描结束之后， 下一帧扫描开始之前输出一个控 制信号驱动所述补偿线。
本发明由于单独采用电平转换模块来驱动补偿线， 在最后一条扫描线扫描 结束之后， 下一帧扫描开始之前输出一个控制信号驱动所述补偿线， 这样补偿 线的驱动就无需占用门极驱动芯片的通道， 门极驱动芯片只需要按实际的扫描 线数量来配置， 可以减少通道的浪费， 降低硬件成本； 另外也不用考虑门极驱 动芯片输出通道数跟扫描线和补偿线的驱动配合问题， 扫描线的驱动按常规设 计即可， 而电平转换模块只需要驱动补偿线， 跟其他驱动电路相对独立， 有利 于降低开发难度， 设计比较筒单。
下面结合附图和较佳的实施例对本发明作进一步说明。
参见图 4、 5, 液晶面板内部设有纵横交错的扫描线和数据线， 在液晶面板 的两侧各设有两个门极驱动芯片（ GDI ~ GD4 ) , 负责驱动液晶面板的 1080条扫 描线（Gl ~ G1080 ), 还有一条补偿线 G1081就由电平转换模块来驱动。 液晶面 板的上部设有多个源极驱动芯片， 源极驱动芯片通过源极驱动电路板来控制， 整个液晶面板的驱动通过控制电路板来实现， 控制电路板内包括时序控制电路， 以及与时序控制电路耦合的电平转换模块。
如图 6所示， 电平转换模块包括高电平导通的第一可控开关 Ql、 低电平导 通的第二可控开关 Q2、以及控制第一可控开关 Q1和第二可控开关 Q2的通道控 制单元； 第一可控开关 Q1的输入端耦合到一基准高电平信号 VGH, 第二可控 开关 Q2的输入端耦合到一基准低电平信号 VGL;第一可控开关 Q1和第二可控 开关 Q2的输出端耦合到补偿线 G1081 , 其控制端耦合到通道控制单元。 电平转 换模块还设有第三可控开关 Q3, 第三可控开关 Q3的输入端耦合到补偿线， 其 输出端耦合有放电电阻， 其控制端耦合到通道控制单元； 第三可控开关 Q3在第 一可控开关 Q1导通后导通， 在第二可控开关 Q2导通后关闭， 所述第三可控开 关 Q3导通后， 所述第一可控开关 Q1关闭。 第一可控开关 Q1和第二可控开关 Q2的动作逻辑相反， 可以有效避免误动作。 而第三可控开关 Q3可以在补偿线 处于高电平状态的时候进行放电， 使得电压逐步降低， 然后再通过第三可控开 关 Q3拉低到低电平， 形成了切角波形。
进一步的， 电平转换模块的通道控制单元接收时序控制电路输出的补偿线 时钟信号 CKVX和削角控制信号 GVOFF; 第一可控开关 Q1在补偿线时钟信号 CKVX上升沿导通， 并在削角控制信号 GVOFF的下降沿关闭； 第二可控开关 Q2在补偿线时钟信号 CKVX下降沿导通， 并在下一个补偿线时钟信号 CKVX 上升沿关闭； 第三可控开关 Q3在削角控制信号 GVOFF的下降沿导通， 在补偿 线时钟信号 CKVX下降沿关闭。 时序控制电路控制着液晶面板的扫描线和数据 线的输出信号， 因此， 由时序控制电路来提供补偿线时钟信号 CKVX和削角控 制信号 GVOFF, 可以准确控制补偿线的驱动时机和波形， 无须额外设计驱动电 路， 有利于筒化电路并降低硬件成本。
本实施方式还公开一种多子像素液晶面板的驱动方法， 包括步骤 A: 采用 电平转换模块， 在最后一条扫描线扫描结束之后， 下一帧扫描开始之前驱动液 晶面板的补偿线。
实施例一
电平转换模块包括第一可控开关、 第二可控开关和第三可控开关， 步骤 A 中包括（参见图 7的驱动波形）：
A1 : 在补偿线时钟信号 CKVX上升沿控制第一可控开关导通； 将一个基准 高电平信号耦合到补偿线 G1081;
A2: 在削角控制信号 GVOFF的下降沿控制第一可控开关关闭， 并同时导 通第三可控开关； 将补偿线耦合到一放电电阻进行放电；
A3: 在补偿线时钟信号 CKVX下降沿控制第三可控开关关闭， 并控制第二 可控开关导通， 将一个基准低电平信号耦合到补偿线 G1081。
由于时序控制电路控制着液晶面板的扫描线和数据线的输出信号， 因此， 可以由时序控制电路来提供补偿线时钟信号 CKVX和削角控制信号 GVOFF,可 以准确控制补偿线的驱动时机和波形， 且无须额外设计驱动电路， 筒化电路并 降低硬件成本。
本实施方式为一种具体的控制波形， 可以在标准方波的波形上形成切角， 形成切角波形， 提高控制的可靠性。
实施例二
电平转换模块包括第一可控开关和第二可控开关， 步骤 A中包括：
A1 : 在补偿线时钟信号上升沿控制第一可控开关导通； 将一个基准高电平 信号耦合到补偿线；
A2: 在补偿线时钟信号下降沿控制第一可控开关关闭， 并控制第二可控开 关导通， 将一个基准低电平信号耦合到补偿线。
此实施方式为一种标准的方波控制波形， 实现方式筒单， 有利于降低设计 和相应的硬件成本。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干筒单推演或替 换， 都应当视为属于本发明的保护范围。

Claims

权利要求
1、 一种多子像素电荷共享式液晶面板的驱动电路， 包括由门极驱动芯片直 接驱动的多条扫描线， 其中， 所述驱动电路还包括一条补偿线， 以及与所述补 偿线耦合的电平转换模块， 所述电平转换模块在最后一条扫描线扫描结束之后， 下一帧扫描开始之前输出一个控制信号驱动所述补偿线。
2、 如权利要求 1所述的一种多子像素电荷共享式液晶面板的驱动电路， 其 中， 所述电平转换模块包括高电平导通的第一可控开关、 低电平导通的第二可 控开关、 以及控制所述第一可控开关和第二可控开关的通道控制单元； 所述第 一可控开关的输入端耦合到一基准高电平信号， 所述第二可控开关的输入端耦 合到一基准低电平信号； 所述第一可控开关和第二可控开关的输出端耦合到所 述补偿线， 其控制端耦合到所述通道控制单元。
3、 如权利要求 2所述的一种多子像素电荷共享式液晶面板的驱动电路， 其 中， 所述电平转换模块还包括第三可控开关， 所述第三可控开关的输入端耦合 到所述补偿线， 其输出端耦合有放电电阻， 其控制端耦合到所述通道控制单元； 所述第三可控开关在第一可控开关导通后导通， 在第二可控开关导通后关闭， 所述第三可控开关导通后， 所述第一可控开关关闭。
4、 如权利要求 3所述的一种多子像素电荷共享式液晶面板的驱动电路， 其 中， 所述液晶面板的驱动电路包括时序控制电路， 所述电平转换模块的通道控 制单元接收时序控制电路输出的补偿线时钟信号和削角控制信号； 所述第一可 控开关在补偿线时钟信号上升沿导通， 并在削角控制信号的下降沿关闭； 所述 第二可控开关在补偿线时钟信号下降沿导通， 并在下一个补偿线时钟信号上升 沿关闭； 所述第三可控开关在削角控制信号的下降沿导通， 在补偿线时钟信号 下降沿关闭。
5、一种液晶显示装置， 包括一种多子像素电荷共享式液晶面板的驱动电路， 所述驱动电路包括由门极驱动芯片直接驱动的多条扫描线， 还包括一条补偿线， 以及与补偿线耦合的电平转换模块， 所述电平转换模块在最后一条扫描线扫描 结束之后， 下一帧扫描开始之前输出一个控制信号驱动所述补偿线。
6、 如权利要求 5所述的一种液晶显示装置， 其中， 所述电平转换模块包括 高电平导通的第一可控开关、 低电平导通的第二可控开关、 以及控制所述第一 可控开关和第二可控开关的通道控制单元； 所述第一可控开关的输入端耦合到 一基准高电平信号， 所述第二可控开关的输入端耦合到一基准低电平信号； 所 述第一可控开关和第二可控开关的输出端耦合到所述补偿线， 其控制端耦合到 所述通道控制单元。
7、 如权利要求 6所述的一种液晶显示装置， 其中， 所述电平转换模块还包 括第三可控开关， 所述第三可控开关的输入端耦合到所述补偿线， 其输出端耦 合有放电电阻， 其控制端耦合到所述通道控制单元； 所述第三可控开关在第一 可控开关导通后导通， 在第二可控开关导通后关闭， 所述第三可控开关导通后， 所述第一可控开关关闭。
8、 如权利要求 7所述的一种液晶显示装置， 其中， 所述液晶面板的驱动电 路包括时序控制电路， 所述电平转换模块的通道控制单元接收时序控制电路输 出的补偿线时钟信号和削角控制信号； 所述第一可控开关在补偿线时钟信号上 升沿导通， 并在削角控制信号的下降沿关闭； 所述第二可控开关在补偿线时钟 信号下降沿导通， 并在下一个补偿线时钟信号上升沿关闭； 所述第三可控开关 在削角控制信号的下降沿导通， 在补偿线时钟信号下降沿关闭。
9、 如权利要求 5所述的一种液晶显示装置， 其中， 所述液晶显示装置包括 面板和控制电路板， 所述面板内设有多条扫描线和一条补偿线， 所述控制电路 板包括时序控制电路， 以及跟时序控制电路耦合的所述电平转换模块。
10、 一种多子像素电荷共享式液晶面板的驱动方法， 包括步骤 A:在最后一 条扫描线由门极驱动芯片驱动扫描结束之后， 在下一帧扫描开始之前采用电平 转换模块驱动液晶面板的补偿线。
11、 如权利要求 10所述的一种多子像素电荷共享式液晶面板的驱动方法， 其中， 所述电平转换模块包括跟补偿线耦合的第一可控开关和第二可控开关， 所述步骤 A中包括：
A1 : 在补偿线时钟信号上升沿控制第一可控开关导通； 将一个基准高电平 信号耦合到补偿线；
A2: 在补偿线时钟信号下降沿控制第一可控开关关闭， 并控制第二可控开 关导通， 将一个基准低电平信号耦合到补偿线。
12、 如权利要求 10所述的一种多子像素电荷共享式液晶面板的驱动方法， 其中， 所述电平转换模块包括跟补偿线耦合的第一可控开关、 第二可控开关和 第三可控开关， 所述步骤 A中包括：
A1 : 在补偿线时钟信号上升沿控制第一可控开关导通； 将一个基准高电平 信号耦合到补偿线；
A2: 在削角控制信号的下降沿控制第一可控开关关闭， 并同时导通第三可 控开关； 将补偿线耦合到一放电电阻进行放电；
A3: 在补偿线时钟信号下降沿控制第三可控开关关闭， 并控制第二可控开 关导通， 将一个基准低电平信号耦合到补偿线。
13、 如权利要求 12所述的一种多子像素电荷共享式液晶面板的驱动方法， 其中， 所述补偿时钟信号和削角控制信号由液晶面板的时序控制电路产生。
PCT/CN2012/084091 2012-09-29 2012-11-05 一种驱动电路、液晶显示装置及驱动方法 Ceased WO2014048007A1 (zh)

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