WO2014045480A1 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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Publication number
WO2014045480A1
WO2014045480A1 PCT/JP2013/002110 JP2013002110W WO2014045480A1 WO 2014045480 A1 WO2014045480 A1 WO 2014045480A1 JP 2013002110 W JP2013002110 W JP 2013002110W WO 2014045480 A1 WO2014045480 A1 WO 2014045480A1
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region
impurity concentration
implantation
electric field
semiconductor device
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PCT/JP2013/002110
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French (fr)
Japanese (ja)
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洪平 海老原
憲治 濱田
川上　剛史
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三菱電機株式会社
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Priority to JP2014536549A priority Critical patent/JP5800095B2/en
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • a depletion layer is formed in an active region that actively functions as a semiconductor element, and electric field concentration occurs at the boundary of the depletion layer, so that the breakdown voltage of the semiconductor device decreases. Therefore, by providing a termination region having a conductivity type opposite to the conductivity type of the semiconductor layer on the outer peripheral side of the active region, the depletion layer is expanded by the pn junction between the semiconductor layer and the termination region, and the electric field concentration is reduced. The breakdown voltage of the semiconductor device can be increased.
  • a JTE (Junction Termination Extension) structure having a plurality of implantation regions having different impurity concentrations is used, so that the semiconductor device moves toward the outer peripheral side.
  • the impurity concentration decreases stepwise, there has been a semiconductor device that can obtain a higher breakdown voltage than when using a JTE structure having a single injection region.
  • electric field concentration may still occur at the boundary between a plurality of injection regions and at the outer peripheral end of the injection region formed at the outermost periphery.
  • the impurity concentration in the outermost implantation region is relatively low.
  • the depletion layer does not sufficiently spread on the outer peripheral end side of the outer peripheral injection region, and as a result, the electric field concentration at the outer peripheral end portion of the outermost peripheral injection region cannot be sufficiently relaxed, and a sufficient breakdown voltage of the semiconductor device can be obtained. There was no problem.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a termination region that can effectively alleviate electric field concentration.
  • a semiconductor device includes a semiconductor layer of a first conductivity type, a first small region formed on a part of the surface of the semiconductor layer and having a first impurity concentration of the second conductivity type and a second region.
  • a first electric field relaxation region in which a second small region having a conductivity type and a second impurity concentration lower than the first impurity concentration is alternately provided, and toward the outer peripheral side of the first electric field relaxation region.
  • a plurality of third small regions that are formed to surround the first electric field relaxation region and that are of the second conductivity type and have a third impurity concentration equal to or higher than the first impurity concentration and the second conductivity type of the second electric field relaxation region.
  • a second electric field relaxation region in which a plurality of fourth small regions having a fourth impurity concentration lower than the first impurity concentration are alternately provided.
  • the effective impurity concentration of the first electric field relaxation region is greater than the effective impurity concentration of the second electric field relaxation region provided on the outer peripheral side than the first electric field relaxation region. Therefore, the effective impurity concentration gradually decreases toward the outer peripheral side of the semiconductor device, and the electric field concentration at the boundary of each region can be mitigated. Further, since the impurity concentration of the third small region provided in the second electric field relaxation region on the outer peripheral side is higher than the impurity concentration of the first small region provided in the first electric field relaxation region, Since the depletion layer sufficiently spreads on the outer peripheral end side of the electric field relaxation region, electric field concentration on the outer peripheral end side of the electric field relaxation region can be more effectively relaxed.
  • Embodiment 1 the configuration of the Schottky diode 100 that is the semiconductor device according to the first embodiment of the present invention will be described.
  • the first conductivity type semiconductor is assumed to be an n-type semiconductor and the second conductivity type semiconductor is assumed to be a p-type semiconductor.
  • the present invention is not limited to this, and the first conductivity type semiconductor is assumed to be p-type.
  • the second conductivity type semiconductor may be an n-type semiconductor.
  • SiC silicon carbide
  • MOSFET Metal Oxide Field Effect Transistor
  • the inner side refers to the active region side that is the central portion side of the semiconductor device
  • the outer side refers to the termination region side that is the outer peripheral side of the semiconductor device.
  • FIG. 1 is a principal cross-sectional view showing a configuration of a Schottky diode 100 that is a semiconductor device according to the first embodiment of the present invention. Show.
  • an n-type semiconductor layer 1 is provided on a 4H—SiC semiconductor substrate (not shown), and a metal electrode 3 is provided on the surface of the semiconductor layer 1.
  • the semiconductor layer 1 includes an active region 50 that functions as an active element and a termination region 60 that is provided on the outer peripheral side of the active region 50 to maintain the breakdown voltage of the semiconductor device.
  • the termination region 60 surrounds the active region 50. Formed.
  • An insulating surface protection film (not shown) is formed on the termination region 60.
  • the p-type guard ring 2, the first electric field relaxation region 4, the connection region 10, and the second electric field relaxation region 5 are formed from the active region 50 side. Impurities are implanted so that the effective impurity concentration in the step changes stepwise.
  • the effective impurity concentration of the electric field relaxation region is the impurity concentration of the electric field relaxation region obtained by averaging the impurity concentration of each small region provided in the electric field relaxation region according to the area of each small region. .
  • the impurity concentration in each region is obtained by dividing the total amount of impurities in that region by the volume of each region.
  • the first electric field relaxation region 4 a plurality of second small regions 7 into which Al ions are implanted are alternately provided in the same manner as the first small region 6 into which Al ions that are p-type impurities are implanted. Yes.
  • the impurity concentration in the first small region 6 is the first impurity concentration
  • the impurity concentration in the second small region 7 is the second impurity concentration
  • the first impurity concentration is higher than the second impurity concentration. It is formed to become.
  • the first small region 6 and the second small region 7 occupy a certain region in the first electric field relaxation region 4 and are smaller than the first electric field relaxation region 4.
  • the third small region 8 into which Al ions are implanted and the fourth small region 9 into which Al ions are implanted are alternately arranged.
  • the third impurity concentration is equal to the first impurity concentration.
  • the fourth impurity concentration is formed to be lower than the first impurity concentration and the second impurity concentration. Further, the impurity concentration of each region is adjusted so that the first impurity concentration and the third impurity concentration are the sum of the second impurity concentration and the fourth impurity concentration.
  • Al ions are used as p-type impurities, but other p-type impurities such as boron may be used.
  • the p-type guard ring 2 provided inside the first electric field relaxation region 4 is formed from a single p-type region having a first impurity concentration equal to the impurity concentration of the first small region 6 already described.
  • a metal electrode 3 is provided on a part of the surface.
  • the connection region 10 provided between the first electric field relaxation region 4 and the second electric field relaxation region 5 is also a region formed from a single p-type region having the first impurity concentration. Yes.
  • the connection region 10 may be omitted, and the first electric field relaxation region 4 and the second electric field relaxation region 5 may be configured to contact each other.
  • FIG. 4 shows the impurity dose in each region in the termination region 60 of the Schottky diode 100 that is the semiconductor device according to the first embodiment of the present invention, and the first implantation region 12 and the second implantation region 13. It is a figure which shows a relationship.
  • the semiconductor layer 1 is formed on a semiconductor substrate (not shown), and the metal electrode 3 serving as a Schottky junction is disposed on the surface of the semiconductor layer 1.
  • the termination region 60 It is necessary to form the termination region 60 before installing the device.
  • An insulating surface protection film (not shown) is formed on the termination region 60 of the semiconductor layer 1.
  • the dose amount indicates the number of impurities doped per unit area.
  • the termination region 60 is formed by two implantation steps.
  • a region where impurities are implanted in the first implantation step which is the first implantation step
  • impurities are implanted in the second implantation step, which is the second implantation step.
  • the region is called the second implantation region 13
  • the termination region 60 is formed by combining the first implantation region 12 and the second implantation region 13.
  • the first injection region 12 and the second injection region 13 are partially overlapped.
  • a first implantation step is performed in which Al ions that are p-type impurities are implanted in the first implantation region 12.
  • the first implantation step is performed with the first implantation mask 11 a installed on the surface of the semiconductor layer 1.
  • the mask pattern of the first implantation mask 11a is such that the first implantation region 12 corresponding to the p-type guard ring 2, the first electric field relaxation region 4, and the third small region 8 is open, The shape covers the area.
  • the dose amount of the impurity implanted in the first implantation step is a dose amount at which the impurity concentration in the second small region 7 of the first implantation region 12 becomes the second impurity concentration.
  • the concentration distribution in the depth direction may be a box profile, a retrograde profile, or another profile.
  • a second implantation step is performed in which Al ions that are p-type impurities are implanted in the second implantation region 13.
  • the second implantation step is performed in a state where the second implantation mask 11 b is installed on the surface of the semiconductor layer 1.
  • the mask pattern of the second implantation mask 11b is such that the second implantation region 13 corresponding to the region of the p-type guard ring 2, the first small region 6, and the second electric field relaxation region 5 has an opening.
  • the shape covers the area.
  • the dose amount of the impurity implanted in the second implantation step is smaller than the dose amount implanted in the first implantation step.
  • pouring process may perform a 2nd process previously, and may perform a 1st injection
  • the region where the first implantation region 12 and the second implantation region 13 overlap that is, Al ions are produced by both the first implantation step and the second implantation step.
  • the implanted region becomes the p-type guard ring 2 having the first impurity concentration.
  • the region into which Al ions are implanted by both the first implantation step and the second implantation step becomes the first small region 6 having the first impurity concentration.
  • the region into which Al ions are implanted by only one implantation step becomes the second small region 7 having the second impurity concentration, and the first electric field relaxation region 4 is formed.
  • the region into which Al ions are implanted by both the first implantation step and the second implantation step has a third impurity concentration (first impurity concentration).
  • a region where the Al ions are implanted only by the second implantation step becomes the fourth small region 9 having the fourth impurity concentration, and the second electric field relaxation region 5 is formed.
  • the region into which Al ions are implanted by both the first implantation step and the second implantation step is the first impurity concentration.
  • the junction region 10 is formed.
  • the first impurity concentration and the third impurity concentration can be adjusted by changing the sum of the dose amounts of Al ions implanted in the first implantation step and the second implantation step.
  • the impurity concentration can be adjusted by changing the dose amount of Al ions implanted in the first implantation step, and the fourth impurity concentration changes the dose amount of Al ions implanted in the second implantation step. Can be adjusted.
  • connection region 10 is formed at the boundary between the first electric field relaxation region 4 and the second electric field relaxation region 5, but if the mask alignment accuracy is sufficiently ensured, the connection region 10 is reduced.
  • the first electric field relaxation region 4 and the second electric field relaxation region 5 may be directly connected by omitting the connection area 10.
  • the p-type guard ring 2 and the first electric field can be obtained by two implantation steps.
  • a termination region 60 composed of the relaxation region 4, the connection region 10, and the second electric field relaxation region 5 can be formed.
  • FIG. 5 is a diagram showing a simulation result regarding a change in potential distribution when a reverse voltage is applied stepwise to the Schottky diode 100 which is the semiconductor device according to the first embodiment of the present invention.
  • Each line in FIG. 5 represents an equipotential line in the semiconductor layer 1 of the Schottky diode 100, and simulation is performed when a low voltage, a medium voltage, and a high voltage are applied as reverse voltages of the Schottky diode 100 in order from the top.
  • Each result is shown.
  • the first small regions 6 having the first impurity concentration and the second small regions 7 having the second impurity concentration are alternately formed in the first electric field relaxation region 4.
  • the third small region 8 having a third impurity concentration equal to the first impurity concentration is lower than the second impurity concentration.
  • the fourth small regions 9 having the fourth impurity concentration are alternately formed, the effective impurity concentration in the first electric field relaxation region 4 is higher than the effective impurity concentration in the second electric field relaxation region 5.
  • the termination region 60 is formed so that the impurity concentration decreases toward the outside of the termination region 60. Therefore, as shown in FIG. 5, as the applied reverse voltage increases, the depletion layer gradually expands from the second electric field relaxation region 5 to the first electric field relaxation region 4 in the injection region. It can be seen that potential sharing is performed stepwise from the electric field relaxation region 5 to the first electric field relaxation region 4.
  • the effective impurity concentration of the second electric field relaxation region 5 provided outside the termination region 60 is lower than the effective impurity concentration of the first electric field relaxation region 4.
  • the impurity concentration of the third small region 8 provided in the electric field relaxation region 5 is the same as the impurity concentration of the first small region 6 provided in the first electric field relaxation region 4. Therefore, it can be seen that the depletion layer is sufficiently spread even outside the second electric field relaxation region 5. Therefore, according to the present embodiment, it is possible to more effectively alleviate electric field concentration at the outer peripheral edge of the boundary surface of each region and the outermost peripheral region into which impurities are implanted.
  • the p-type guard ring 2, the first electric field relaxation region 4, and the second electric field relaxation region 5 are formed by two implantation steps.
  • the termination region 60 including a plurality of regions having different impurity concentrations can be formed with a small number of manufacturing steps.
  • a third electric field relaxation region 17 and a fourth electric field relaxation region 19, which will be described later, and a single region consisting of the second impurity concentration or the fourth impurity concentration are added without increasing a new implantation step. It is also possible to increase the number of gradations of the impurity concentration in the termination region 60 by combining the regions, thereby increasing the breakdown voltage of the semiconductor device.
  • FIG. 6 shows a simulation result of the breakdown voltage of the Schottky diode 100 when the dose amount of the impurity implanted in each implantation step is changed.
  • the vertical axis represents the breakdown voltage of the semiconductor device
  • each bar graph represents the dose injected into the first implantation region 12 in the first implantation step and the second implantation region 13 in the second implantation step. The withstand voltage when the dose amount injected into the substrate is set to a specific dose amount is shown.
  • the dose amount of either the first implantation region 12 or the second implantation region 13 is 0.0 cm ⁇ 2, that is, only one of the first implantation step and the second implantation step is performed. Even when the termination region 60 is formed, a certain level of breakdown voltage is obtained. However, the doses of the first implantation region 12 and the second implantation region 13 are 1.4E + 13 cm ⁇ 2 or less, respectively. It can be seen that a high breakdown voltage semiconductor device can be obtained when the total dose of 12 and the second implantation region 13 is 1.2E + 13 to 2.4E + 13 cm ⁇ 2.
  • the dose amount of the first implantation region 12 is 1.0E + 13 cm ⁇ 2 or more and the dose amount of the second implantation region 13 is 1.0E + 13 cm ⁇ 2 or less, a semiconductor device having a breakdown voltage exceeding 1700 kV is obtained. It turns out that many are obtained.
  • the activation rate of impurities is not 100%, and it is hardly affected by the fixed charges trapped during the process, and the breakdown voltage as simulated is rarely obtained.
  • the dose amount actually implanted needs to be larger than the design value of the dose amount based on the simulation or the like, and in the case of 4H—SiC, it is about 6E + 12 cm ⁇ 2 larger than the design value.
  • the dose amounts of the first implantation region 12 and the second implantation region 13 are 2.0E + 13 cm ⁇ 2 or less, respectively. It is desirable to implant impurities in a range where the total dose of the implantation region 12 and the second implantation region 13 is in the range of 1.2E + 13 to 3.0E + 13 cm ⁇ 2.
  • the second impurity concentration that is the impurity concentration of the second small region 7 is set to be larger than the fourth impurity concentration that is the impurity concentration of the fourth small region.
  • the effective impurity concentration is reduced as it goes to improve the breakdown voltage.
  • the second impurity concentration may be made lower than the fourth impurity concentration.
  • FIG. 6 when the second impurity concentration is lower than the third impurity concentration, that is, when the impurity implanted in the first implantation step is less than the impurity implanted in the second implantation step.
  • the potential is shared stepwise from the first electric field relaxation region 4 having a low effective impurity concentration to the second electric field relaxation region 5 having a high effective impurity concentration, a relatively high breakdown voltage semiconductor device is manufactured. May be obtained.
  • the first small region 6 and the third small region 8 are configured to have the same impurity concentration.
  • the third impurity concentration that is the impurity concentration of the region 8 may be higher than the first impurity concentration that is the impurity concentration of the first small region 6.
  • a depletion layer spreads stepwise from the second electric field relaxation region 5 to the first electric field relaxation region 4, and potential sharing is performed stepwise from the second electric field relaxation region 5 to the first electric field relaxation region 4.
  • the depletion layer further spreads outside the second electric field relaxation region 5. Therefore, it is possible to more effectively alleviate the electric field concentration at the outer peripheral end of the boundary surface of each region and the outermost peripheral region where impurities are implanted without expanding the implantation region to the outer peripheral side.
  • the resist finishes smaller than a width of 1 ⁇ m, it will fall down, and the design is usually made to be slightly thicker than 1 ⁇ m in consideration of the possibility that the resist width shrinks due to excessive exposure.
  • the side surface has a taper as shown in FIG. 7, the implantation process can be performed without falling the resist even if the width is 1 ⁇ m.
  • FIG. 8 shows the result of simulating the shape of the p-type region when Al ions having a dose of 1E + 13 cm ⁇ 2 are implanted at 500 keV into an n ⁇ drift layer having an impurity concentration of 1E + 16 cm ⁇ 3 using a mask with an interval of 1 ⁇ m. is there. As shown in FIG.
  • the interval between the p-type regions is narrowed by about 0.4 ⁇ m, and an advantageous design for increasing the breakdown voltage is possible. Furthermore, when a resist with a tapered shape is used, impurities implanted through the resist also exist immediately below the tapered shape, and a higher concentration p-type region can be obtained compared to the case without a taper, thereby increasing the breakdown voltage. Become advantageous.
  • first electric field relaxation region 4 and second electric field relaxation region 5 are directly connected across connection region 10.
  • first electric field relaxation region 4 and the second electric field relaxation region 5 are directly connected without sandwiching the connection region 10 .
  • the first electric field relaxation region 4 and the second electric field relaxation region 5 are increased as the applied voltage is increased.
  • the electric potential sharing proceeds stepwise to the electric field relaxation region 5 and an effective electric field relaxation effect is obtained.
  • the width of each small region is constant in the first electric field relaxation region 4 and the second electric field relaxation region 5, but as shown in FIG.
  • the widths of the first small region 6 and the third small region 8 having a high impurity concentration are gradually decreased toward the outside of the termination region 60, so
  • the impurity concentration gradually decreases toward the outer peripheral side. Concentration can be relaxed, and a semiconductor device that achieves higher off-voltage can be obtained.
  • the plurality of spaced first small regions 6 can be formed by performing implantation so that the interval between the first small regions 6 changes toward the outer peripheral side.
  • the plurality of spaced second small regions 7 can be formed by performing implantation so that the distance between the small regions 7 changes toward the outer peripheral side.
  • the third small region 8 and the fourth small region 9 that is, each implantation region into which impurities are implanted in each implantation step changes the interval between a plurality of spaced regions in each implantation region. It can be formed by performing implantation so as to cause
  • the implantation depths of the first implantation region 12 and the second implantation region 13 are constant, but as shown in FIGS. 11 and 12, the first implantation region 12 and the second implantation region 12 are the same.
  • the implantation regions 13 may be formed so that the implantation depths thereof are different.
  • 11 shows a case where the implantation depth of the first implantation region 12 is made deeper
  • FIG. 12 shows a case where the implantation depth of the second implantation region 13 is made deeper.
  • the first implantation region 12 is implanted with an implantation energy of 200 to 500 keV
  • the second implantation region 13 is implanted with an implantation energy of 300 to 700 keV.
  • the implantation depth of the second implantation region 13 can be made deeper. In such a case, the depletion layer more easily spreads into the semiconductor layer 1 in the second implantation region 13 implanted deeper, which is advantageous for increasing the breakdown voltage.
  • the implantation depth of either the first implantation region 12 or the second implantation region 13 is preferably shallow.
  • the position of the surface of either the first implantation region 12 or the second implantation region 13 may be an n-type semiconductor.
  • the vertical Schottky diode 100 is described as an example.
  • the MOSFET 101 may have a vertical structure including the gate electrode 26, the field insulating film 27, the interlayer insulating film 28, and the like.
  • the surface of the entire termination region 60 may be an n-type semiconductor.
  • an n + region 70 that is an n-type impurity region that is deeper than the semiconductor layer 1 is provided by ion implantation or high-concentration epitaxial growth in the active region 50.
  • the n + region 70 may be formed on the entire surface of the semiconductor layer 1 without using an implantation mask or the like. Also in this case, since the impurity concentration of the first small region 6 and the third small region 8 is high, the depletion layer can be sufficiently expanded outside the implantation region, and the boundary surface and impurity of each region can be expanded. It is possible to effectively alleviate electric field concentration at the outer peripheral end of the outermost peripheral region into which is injected.
  • n + region 70 when such an n + region 70 is formed in a Schottky diode, it is possible to reduce the resistance during forward conduction, but the breakdown voltage may be reduced due to electric field concentration near the surface of the semiconductor layer 1.
  • JBS Junction Barrier Schottky
  • the JBS region 29 is preferably formed at the same time.
  • FIG. 17 shows the JBS when the JBS region 29 is formed simultaneously with the formation of the first implantation region 12.
  • the active region 50 has a low resistance due to the effect of the n + region 70 and maintains a breakdown voltage in the JBS region 29, and the impurity concentration of the first small region 6 and the third small region 8 in the termination region 60. Therefore, the depletion layer can be sufficiently expanded outside the implantation region, and the electric field concentration at the outer peripheral edge of the boundary surface of each region and the outermost region where impurities are implanted is effectively reduced. be able to.
  • n + region 80 which is an n-type impurity region deeper than the semiconductor layer 1 is formed to the same depth as the p base region 15.
  • the n + region 80 may be formed on the entire surface of the semiconductor layer 1 without using an implantation mask in the MOSFET 101 or the like as shown in FIG.
  • the impurity concentration of the first small region 6 and the third small region 8 is high, the depletion layer can be sufficiently expanded outside the implantation region, and the boundary surface and impurity of each region can be expanded. It is possible to effectively alleviate electric field concentration at the outer peripheral end of the outermost peripheral region into which is injected.
  • the third electric field relaxation region 17 is formed by providing a plurality of fifth small regions 16 having the second impurity concentration apart from each other outside the second electric field relaxation region 5. It is good as well. In such a case, the electric field concentration is further relaxed, and a higher breakdown voltage semiconductor device can be obtained.
  • the termination region 60 shown in FIG. 19 is formed by expanding the first injection region 12 to the outer peripheral side and performing the first injection step. Therefore, it is not necessary to add a new implantation step in order to form the third electric field relaxation region 17.
  • a connection region 10 in which the first injection region 12 and the second injection region 13 are newly overlapped is formed at the boundary between the second electric field relaxation region 5 and the third electric field relaxation region 17.
  • the connection region 10 is reduced in area, or the connection region 10 is omitted and the second electric field relaxation region 5 and the third electric field relaxation region 17 are directly connected. May be.
  • the impurity concentration in the fifth small region 16 may be the first impurity concentration or the fourth impurity concentration, as shown in FIG. 21 or FIG. Good.
  • the impurity concentration of the fifth small region 16 when the impurity concentration of the fifth small region 16 is set to the fourth impurity concentration, the second injection region 13 is expanded to the outer peripheral side and the second injection step is performed to perform the fifth small region. Region 16 is formed.
  • the impurity concentration of the fifth small region 16 is the first impurity concentration
  • the first injection region 12 and the second injection region 13 are expanded, and the third electric field relaxation region 17.
  • the fifth small region 16 is formed by performing each implantation step so that the first implantation region 12 and the second implantation region 13 overlap.
  • the adjacent second electric field relaxation region 5 and third electric field relaxation region 17 are both formed from the second implantation region, that is, the second implantation mask. Therefore, it is not necessary to consider the accuracy of alignment of the implantation mask. As a result, the connection area 10 can be omitted.
  • the impurity concentration of the fifth small region 16 becomes the first impurity concentration, and the impurity concentration of the fifth small region 16 corresponding to the outermost periphery of the termination region 60.
  • the depletion layer expands on the outer peripheral side of the termination region 60, and the electric field concentration can be effectively reduced.
  • the adjacent second electric field relaxation region 5 and third electric field relaxation region 17 are formed from the first implantation region 12 and the second implantation region 13, respectively, that is, the first implantation mask 11a and the second implantation region 13 are formed. Since each is different from the implantation mask 11b, the alignment accuracy of the implantation mask becomes a problem. Therefore, it is effective to provide the connection region 10. However, when the alignment accuracy of the implantation mask is sufficiently ensured, the connection region 10 may be reduced in area or omitted.
  • the first implantation mask 11a and the second implantation mask 11b are overlaid.
  • either one of the first implantation region 12 and the second implantation region 13 in the portion forming the fifth small region 16 is formed.
  • the width should be wider than the other.
  • FIG. 23 shows a case where the width of the second implantation region 13 is wider than the width of the first implantation region 12.
  • a fifth electric field relaxation region 21 may be formed by forming a plurality of seventh small regions 20 on the outer periphery of the fourth electric field relaxation region 19. Even in such a case, the sixth small region 18 and the seventh small region 20 can be formed by expanding the first injection region 12 and the second injection region 13 to the outer peripheral side, There is no need to add a new injection step.
  • the present invention has been described for the case where the semiconductor substrate is made of SiC, it can also be applied to other semiconductor substrates such as silicon (Si).
  • the impurity concentration of each electric field relaxation region is an effective concentration of the impurity concentration in two small regions, the width of each small region is made finer to form a finer structure.
  • the electric field concentration at the boundary surface of each region can be more effectively mitigated.
  • thermal diffusion of impurities becomes a problem.
  • SiC has less thermal diffusion of impurities than other semiconductors such as Si, so that a finer structure is required in a semiconductor device made of SiC. It is possible to form an electric field relaxation region having, and a remarkable effect is obtained in the relaxation of electric field concentration.
  • Embodiment 2 the semiconductor device including the termination region 60 that can be formed by two implantation steps has been described. However, the present invention is not limited thereto, and the termination region is formed by three implantation steps. It is good also as providing.
  • a semiconductor device according to the second embodiment a Schottky diode 102 including a termination region 60 formed by three injection processes will be described. Note that in the semiconductor device according to the second embodiment, description of the same or corresponding parts as those of the semiconductor device according to the first embodiment will be omitted, and different parts will be described.
  • FIG. 26 is a cross-sectional view of a principal part showing a Schottky diode 102 which is a semiconductor device according to the second embodiment.
  • FIG. 27 is a diagram illustrating a dose amount in a termination region of the semiconductor device according to the second embodiment and each implantation step. It is a figure which shows an injection
  • a metal electrode 3 serving as a Schottky junction is formed on the surface corresponding to the active region 50 of the n ⁇ type semiconductor layer 1 formed on a semiconductor substrate (not shown). ing.
  • the metal electrode 3 it is necessary to form a termination region 60 for electric field relaxation in advance.
  • the p-type electric field relaxation regions having different impurity concentrations are formed by three implantation steps having different dose amounts.
  • the first implantation region 12 into which impurities are implanted in the first implantation process, the second implantation region 13 into which impurities are implanted in the second implantation process, and the third Many electric field relaxation regions having different impurity concentrations can be formed by combining the third implantation regions 22 into which impurities are implanted in the implantation step. Therefore, different types of electric field relaxation regions that can be formed from three implantation steps are shown below.
  • An electric field relaxation region (electric field relaxation region 30A) composed of a small region having an impurity concentration determined by a combined dose amount of 12 and the dose amount of the second implantation region 13 A small region having an impurity concentration determined by a combined dose amount of the dose amount of the first implantation region 12, the dose amount of the second implantation region 13, and the dose amount of the third implantation region 22, and the first implantation region
  • An electric field relaxation region (electric field relaxation region 30B) consisting of a small region having an impurity concentration determined by the total dose amount of 12 and the dose amount of the third implantation region 22 A small region having an impurity concentration determined by the combined dose amount of the first implantation region 12, the second implantation region 13, and the third implantation region 22, and the second implantation region
  • An electric field relaxation region / first region composed of a small region with an impurity concentration determined by the combined dose amount and the dose amount of the third implantation region 22 and a small region with an impurity concentration determined by the dose amount of the first implantation region 12.
  • Impurity concentration determined by dose A small region having an impurity concentration determined by the combined amount of the dose amount of the first implantation region 12, the dose amount of the second implantation region 13, and the dose amount of the third implantation region 22.
  • Electric field relaxation region and the dose amount of the first implantation region 12 and the dose amount of the second implantation region 13 which are composed of a low impurity concentration region determined by the dose amount of the third implantation region 22 are determined.
  • Electric field relaxation region (electric field relaxation region 30C) composed of a small region of impurity concentration and a small region of impurity concentration determined by the dose amount of the first implantation region 12 A small impurity concentration region determined by the combined dose amount of the first implantation region 12 and the second implantation region 13 and a small impurity concentration determined by the dose amount of the second implantation region 13
  • a small region having an impurity concentration determined by a combined dose amount of the third implantation region 22 and the dose amount of the second implantation region 13 and the electric field relaxation region composed of a small region having an impurity concentration determined by Low electric field concentration region determined by the sum of the dose amount of the electric field relaxation region / second injection region 13 and the dose amount of the third injection region 12, which is a region having a small impurity concentration determined by the dose amount of the injection region 13.
  • Area and third Field relaxation region made from a small region of an impurity concentration which is determined by the dose of the implanted region 22 (the electric field relaxation region 30E) Electric field relaxation region having an impurity concentration determined by the dose amount of the first implantation region 12 Electric field relaxation region having an impurity concentration determined by the dose amount of the second implantation region 13 Impurity concentration determined by the dose amount of the third implantation region 22 Electric field relaxation region (electric field relaxation region 30F) An electric field relaxation region having an impurity concentration determined by the combined dose amount of the first implantation region 12 and the dose amount of the second implantation region 13A dose amount of the first implantation region 12 and the third implantation region Electric field relaxation region having an impurity concentration determined by the combined dose amount of 22 and an electric field having an impurity concentration determined by the combined dose amount of 22 and an electric field having an impurity concentration determined by the combined dose amount of the second implanted region 13 and the dose amount of the second implanted region 13 Relaxation region / electric field relaxation region having an impurity concentration determined by the combined
  • the electric field relaxation regions share the potential in order from the region with the lower impurity concentration as the applied voltage increases. To do. Thereby, since the electric field concentration is effectively reduced toward the outer periphery of the termination region, a high breakdown voltage semiconductor device can be obtained.
  • the Schottky diode 102 which is a semiconductor device according to the second embodiment has the above-described 19th combination by combining the first implantation region 12, the second implantation region 13, and the third implantation region 22.
  • the terminal region 60 includes six electric field relaxation regions 30A to 30F selected from the types of electric field relaxation regions. With such a configuration, since the electric field relaxation region is formed so that the impurity concentration decreases toward the outer peripheral side of the termination region 60, the potential sharing is stepwise in order from the outer electric field relaxation region as the applied voltage increases. The electric field concentration can be reduced.
  • a high breakdown voltage semiconductor device can be obtained.
  • six types of electric field relaxation regions can be formed from three implantation steps, and the number of gradations in the electric field relaxation region can be increased while suppressing an increase in manufacturing steps. Thus, it becomes possible to manufacture a semiconductor device with a high breakdown voltage.
  • each electric field relaxation region the width of each implantation region is the same, but as shown in FIG. 28, the width of the small region in each different electric field relaxation region is gradually changed toward the outer peripheral side of the termination region.
  • electric field concentration can be more effectively mitigated, and a high breakdown voltage semiconductor device can be obtained.
  • the implantation depths of the first implantation region 12, the second implantation region 13, and the third implantation region 22 are the same depth. However, as shown in FIG. The injection depth may be different. In this case, in the deeply implanted region, the depletion layer is more likely to spread to the semiconductor layer 1, which is advantageous for increasing the breakdown voltage.
  • impurities are usually distributed so as to have a concentration peak in the depth direction, and the impurity concentration on the surface of the implantation region is slightly reduced. In order to prevent breakage at the end of the metal electrode 3, it is advisable to ensure a certain level of surface impurity concentration immediately below the end of the metal electrode 3, and as shown in FIG. It is better to keep the implantation depth shallow. In FIG. 29, the first implantation region is deepest, the second implantation region 13 is deep, and the third implantation region 22 is shallowest.
  • the surface of any of the first implantation region 12, the second implantation region 13, and the third implantation region 22 may be an n-type semiconductor.
  • the surface of the second implantation region is illustrated as an n-type semiconductor.
  • a vertical structure Schottky diode is taken as an example.
  • the surface may be an n-type semiconductor.
  • the embodiments can be freely combined within the scope of the invention, and the embodiments can be appropriately modified or omitted.

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Abstract

Provided is a semiconductor device that is equipped with a terminal region where electric field concentration can be effectively relaxed. This semiconductor device is provided with: a first conductivity type semiconductor layer; a first electric field relaxing region, which is formed on a part of the surface of the semiconductor layer, and which is alternately provided with second conductivity type first small regions having first impurity concentration, and second conductivity type second small regions having second impurity concentration lower than the first impurity concentration; and a second electric field relaxing region, which is formed to surround the first electric field relaxing region toward the outer circumferential side of the first electric field relaxing region, and which is alternately provided with a plurality of second conductivity type third small regions having third impurity concentration equal to or higher than the first impurity concentration, and a plurality of second conductivity type fourth small regions having fourth impurity concentration lower than the second impurity concentration.

Description

半導体装置及び半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は、半導体装置及び半導体装置の製造方法に関するものである。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
　半導体装置において、電圧が印加された場合、半導体素子として能動的に機能する活性領域に空乏層が形成され、その空乏層の境界で電界集中が発生することから半導体装置の耐圧が低下する。そのため、半導体層の導電型と逆の導電型となる終端領域を活性領域の外周側に設けることで、半導体層と終端領域との間のｐｎ接合によって空乏層が広がり、電界集中が緩和され、半導体装置の耐圧を高めることができる。従来の半導体装置では、半導体装置の耐圧を高める終端領域の構造として、異なる濃度の不純物濃度からなる複数の注入領域を有するＪＴＥ（Ｊｕｎｃｔｉｏｎ　Ｔｅｒｍｉｎａｔｉｏｎ　Ｅｘｔｅｎｔｉｏｎ）構造を用いることで、半導体装置の外周側に向かうにつれて不純物濃度が段階的に低くなるため、単一の注入領域を有するＪＴＥ構造を用いる場合と比較して、高い耐圧が得られる半導体装置が存在した。（例えば、特許文献１参照。） In a semiconductor device, when a voltage is applied, a depletion layer is formed in an active region that actively functions as a semiconductor element, and electric field concentration occurs at the boundary of the depletion layer, so that the breakdown voltage of the semiconductor device decreases. Therefore, by providing a termination region having a conductivity type opposite to the conductivity type of the semiconductor layer on the outer peripheral side of the active region, the depletion layer is expanded by the pn junction between the semiconductor layer and the termination region, and the electric field concentration is reduced. The breakdown voltage of the semiconductor device can be increased. In the conventional semiconductor device, as the structure of the termination region that increases the breakdown voltage of the semiconductor device, a JTE (Junction Termination Extension) structure having a plurality of implantation regions having different impurity concentrations is used, so that the semiconductor device moves toward the outer peripheral side. As the impurity concentration decreases stepwise, there has been a semiconductor device that can obtain a higher breakdown voltage than when using a JTE structure having a single injection region. (For example, refer to Patent Document 1.)
特表２０００－５１６７６７号公報JP 2000-516767
　しかしながら、このような半導体装置にあっては、複数の注入領域同士の境界や最外周に形成された注入領域の外周端部においては依然として電界集中が生じる場合があった。特に、半導体装置の外周側に向かうにつれて不純物濃度が段階的に低くなるように注入領域が形成されていることから、最外周の注入領域の不純物濃度は比較的低い濃度となっているため、最外周の注入領域の外周端側では空乏層が十分に広がらず、その結果、最外周の注入領域の外周端部における電界集中を十分に緩和することができず半導体装置の耐圧が十分に得られないという問題があった。 However, in such a semiconductor device, electric field concentration may still occur at the boundary between a plurality of injection regions and at the outer peripheral end of the injection region formed at the outermost periphery. In particular, since the implantation region is formed so that the impurity concentration gradually decreases toward the outer peripheral side of the semiconductor device, the impurity concentration in the outermost implantation region is relatively low. The depletion layer does not sufficiently spread on the outer peripheral end side of the outer peripheral injection region, and as a result, the electric field concentration at the outer peripheral end portion of the outermost peripheral injection region cannot be sufficiently relaxed, and a sufficient breakdown voltage of the semiconductor device can be obtained. There was no problem.
　本発明は、上述のような問題を解決するためになされたもので、電界集中を効果的に緩和することができる終端領域を備えた半導体装置を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a termination region that can effectively alleviate electric field concentration.
　本発明に係る半導体装置は、第一導電型の半導体層と、半導体層の表面の一部に形成され、かつ、第二導電型で第一の不純物濃度である第一の小領域と第二導電型で第一の不純物濃度よりも低い第二の不純物濃度である第二の小領域とがそれぞれ交互に設けられた第一の電界緩和領域と、第一の電界緩和領域の外周側に向かって第一の電界緩和領域を囲むように形成され、かつ、第二導電型で第一の不純物濃度以上の第三の不純物濃度である複数の第三の小領域と第二導電型で第二の不純物濃度よりも低い第四の不純物濃度である複数の第四の小領域とがそれぞれ交互に設けられた第二の電界緩和領域とを備えたものである。 A semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, a first small region formed on a part of the surface of the semiconductor layer and having a first impurity concentration of the second conductivity type and a second region. A first electric field relaxation region in which a second small region having a conductivity type and a second impurity concentration lower than the first impurity concentration is alternately provided, and toward the outer peripheral side of the first electric field relaxation region. A plurality of third small regions that are formed to surround the first electric field relaxation region and that are of the second conductivity type and have a third impurity concentration equal to or higher than the first impurity concentration and the second conductivity type of the second electric field relaxation region. And a second electric field relaxation region in which a plurality of fourth small regions having a fourth impurity concentration lower than the first impurity concentration are alternately provided.
　本発明に係る半導体装置によれば、第一の電界緩和領域の実効的な不純物濃度は第一の電界緩和領域よりも外周側に設けられた第二の電界緩和領域の実効的な不純物濃度よりも高くなることから、半導体装置の外周側に向かうにつれて実効的な不純物濃度が段階的に低くなり各領域の境界での電界集中を緩和することができる。さらに、外周側の第二の電界緩和領域に設けられた第三の小領域の不純物濃度は第一の電界緩和領域に設けられた第一の小領域以上の不純物濃度であることから、第二の電界緩和領域の外周端側において空乏層が十分に広がるため、電界緩和領域の外周端側の電界集中をより効果的に緩和することができる。 According to the semiconductor device of the present invention, the effective impurity concentration of the first electric field relaxation region is greater than the effective impurity concentration of the second electric field relaxation region provided on the outer peripheral side than the first electric field relaxation region. Therefore, the effective impurity concentration gradually decreases toward the outer peripheral side of the semiconductor device, and the electric field concentration at the boundary of each region can be mitigated. Further, since the impurity concentration of the third small region provided in the second electric field relaxation region on the outer peripheral side is higher than the impurity concentration of the first small region provided in the first electric field relaxation region, Since the depletion layer sufficiently spreads on the outer peripheral end side of the electric field relaxation region, electric field concentration on the outer peripheral end side of the electric field relaxation region can be more effectively relaxed.
本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置のドーズ量分布を示す図である。It is a figure which shows dose amount distribution of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the semiconductor device regarding Embodiment 1 of this invention. 本発明に関する半導体装置のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the semiconductor device regarding this invention. 本発明の実施の形態１に関する半導体装置の製造工程を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing process of the semiconductor device regarding Embodiment 1 of this invention. 本発明に関する半導体装置のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the semiconductor device regarding this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置のドーズ量分布を示す図である。It is a figure which shows dose amount distribution of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態１に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 1 of this invention. 本発明の実施の形態２に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 2 of this invention. 本発明の実施の形態２に関する半導体装置のドーズ量分布を示す図である。It is a figure which shows dose amount distribution of the semiconductor device regarding Embodiment 2 of this invention. 本発明の実施の形態２に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 2 of this invention. 本発明の実施の形態２に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 2 of this invention. 本発明の実施の形態２に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 2 of this invention. 本発明の実施の形態２に関する半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device regarding Embodiment 2 of this invention.
実施の形態１．
　まず、本発明の実施の形態１にかかる半導体装置であるショットキーダイオード１００の構成を説明する。以下において、第１導電型の半導体をｎ型の半導体とし、第２導電型の半導体をｐ型の半導体として説明するが、これに限定されるものではなく、第１導電型の半導体をｐ型の半導体とし第２導電型の半導体をｎ型の半導体としてもよい。また、以下において、半導体装置である炭化珪素（ＳｉＣ）からなる縦型構造のショットキーダイオードに本発明を適用する場合について説明するが、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）等の他の半導体装置に用いることもできる。さらに、以下の説明において、内側とは半導体装置の中央部側である活性領域側を指すものとし、外側とは半導体装置の外周側である終端領域側を指すものとする。 Embodiment 1 FIG.
First, the configuration of the Schottky diode 100 that is the semiconductor device according to the first embodiment of the present invention will be described. In the following description, the first conductivity type semiconductor is assumed to be an n-type semiconductor and the second conductivity type semiconductor is assumed to be a p-type semiconductor. However, the present invention is not limited to this, and the first conductivity type semiconductor is assumed to be p-type. The second conductivity type semiconductor may be an n-type semiconductor. In the following, a case where the present invention is applied to a vertical Schottky diode made of silicon carbide (SiC), which is a semiconductor device, will be described. However, other semiconductor devices such as a MOSFET (Metal Oxide Field Effect Transistor) are used. It can also be used. Further, in the following description, the inner side refers to the active region side that is the central portion side of the semiconductor device, and the outer side refers to the termination region side that is the outer peripheral side of the semiconductor device.
　図１は、本発明の実施の形態１に関する半導体装置であるショットキーダイオード１００の構成を示す要部断面図であり、ショットキーダイオード１００の外周側に設けられた終端領域６０の周辺における断面を示している。 FIG. 1 is a principal cross-sectional view showing a configuration of a Schottky diode 100 that is a semiconductor device according to the first embodiment of the present invention. Show.
　図１において、図示しない４Ｈ－ＳｉＣの半導体基板上にｎ型の半導体層１が設けられており、半導体層１の表面上には金属電極３が設置されている。また、半導体層１は能動素子として機能する活性領域５０と活性領域５０の外周側に設けられ半導体装置の耐圧を保持するための終端領域６０から構成され、終端領域６０は活性領域５０を取り囲むように形成される。また、終端領域６０の領域上には図示しない絶縁性の表面保護膜が形成される。さらに、終端領域６０においては、活性領域５０側から、ｐ型ガードリング２、第一の電界緩和領域４、接続領域１０、及び第二の電界緩和領域５が形成されており、各電界緩和領域における実効的な不純物濃度が段階的に変化するように不純物が注入されている。なお、電界緩和領域の実効的な不純物濃度とは、電界緩和領域内に設けられた各小領域の不純物濃度を各小領域の面積に応じて平均化して求めた電界緩和領域の不純物濃度とする。また、各領域における不純物濃度とは、その領域内における不純物の総量を各領域の体積で除算したものとする。 In FIG. 1, an n-type semiconductor layer 1 is provided on a 4H—SiC semiconductor substrate (not shown), and a metal electrode 3 is provided on the surface of the semiconductor layer 1. The semiconductor layer 1 includes an active region 50 that functions as an active element and a termination region 60 that is provided on the outer peripheral side of the active region 50 to maintain the breakdown voltage of the semiconductor device. The termination region 60 surrounds the active region 50. Formed. An insulating surface protection film (not shown) is formed on the termination region 60. Further, in the termination region 60, the p-type guard ring 2, the first electric field relaxation region 4, the connection region 10, and the second electric field relaxation region 5 are formed from the active region 50 side. Impurities are implanted so that the effective impurity concentration in the step changes stepwise. The effective impurity concentration of the electric field relaxation region is the impurity concentration of the electric field relaxation region obtained by averaging the impurity concentration of each small region provided in the electric field relaxation region according to the area of each small region. . The impurity concentration in each region is obtained by dividing the total amount of impurities in that region by the volume of each region.
　第一の電界緩和領域４においては、ｐ型の不純物であるＡｌイオンが注入された第一の小領域６と同じくＡｌイオンが注入された第二の小領域７がそれぞれ交互に複数設けられている。そして、第一の小領域６における不純物濃度を第一の不純物濃度とし第二の小領域７における不純物濃度を第二の不純物濃度とすると、第一の不純物濃度が第二の不純物濃度よりも高くなるように形成されている。ここで、第一の小領域６と第二の小領域７は、第一の電界緩和領域４において一定の領域を占めており、第一の電界緩和領域４よりも小さい領域となっている。以下、他の小領域についても同様である。 In the first electric field relaxation region 4, a plurality of second small regions 7 into which Al ions are implanted are alternately provided in the same manner as the first small region 6 into which Al ions that are p-type impurities are implanted. Yes. When the impurity concentration in the first small region 6 is the first impurity concentration and the impurity concentration in the second small region 7 is the second impurity concentration, the first impurity concentration is higher than the second impurity concentration. It is formed to become. Here, the first small region 6 and the second small region 7 occupy a certain region in the first electric field relaxation region 4 and are smaller than the first electric field relaxation region 4. Hereinafter, the same applies to other small regions.
　一方、第二の電界緩和領域５においては、第一の電界緩和領域４と同様にＡｌイオンが注入された第三の小領域８とＡｌイオンが注入された第四の小領域９がそれぞれ交互に複数設けられている。そして、第三の小領域８における不純物濃度を第三の不純物濃度とし第四の小領域９における不純物濃度を第四の不純物濃度とすると、第三の不純物濃度は第一の不純物濃度と等しく、第四の不純物濃度は第一の不純物濃度及び第二の不純物濃度よりも低くなるように形成されている。さらに、第一の不純物濃度および第三の不純物濃度が、第二の不純物濃度と第四の不純物濃度の和となるように各領域の不純物濃度は調整されている。なお、本実施の形態では、ｐ型の不純物としてＡｌイオンを用いることとしているが、ホウ素等の他のｐ型の不純物を用いることとしてもよい。 On the other hand, in the second electric field relaxation region 5, as in the first electric field relaxation region 4, the third small region 8 into which Al ions are implanted and the fourth small region 9 into which Al ions are implanted are alternately arranged. Are provided in plurality. When the impurity concentration in the third small region 8 is the third impurity concentration and the impurity concentration in the fourth small region 9 is the fourth impurity concentration, the third impurity concentration is equal to the first impurity concentration. The fourth impurity concentration is formed to be lower than the first impurity concentration and the second impurity concentration. Further, the impurity concentration of each region is adjusted so that the first impurity concentration and the third impurity concentration are the sum of the second impurity concentration and the fourth impurity concentration. In the present embodiment, Al ions are used as p-type impurities, but other p-type impurities such as boron may be used.
　また、第一の電界緩和領域４の内側に設けられたｐ型ガードリング２は、既に説明した第一の小領域６の不純物濃度と等しい第一の不純物濃度の単一のｐ型領域から形成され、その表面の一部には金属電極３が設けられている。さらに、第一の電界緩和領域４と第二の電界緩和領域５との間に設けられた接続領域１０も、第一の不純物濃度からなる単一のｐ型領域から形成された領域となっている。なお、接続領域１０については省略し、第一の電界緩和領域４と第二の電界緩和領域５とが接するように構成することとしてもよい。 The p-type guard ring 2 provided inside the first electric field relaxation region 4 is formed from a single p-type region having a first impurity concentration equal to the impurity concentration of the first small region 6 already described. A metal electrode 3 is provided on a part of the surface. Further, the connection region 10 provided between the first electric field relaxation region 4 and the second electric field relaxation region 5 is also a region formed from a single p-type region having the first impurity concentration. Yes. The connection region 10 may be omitted, and the first electric field relaxation region 4 and the second electric field relaxation region 5 may be configured to contact each other.
　次に、本発明の実施の形態１にかかる半導体装置であるショットキーダイオード１００の製造方法について説明する。図２及び図３は、本発明の実施の形態１に関する半導体装置の製造工程を示す断面図である。また、図４は本発明の実施の形態１に関する半導体装置であるショットキーダイオード１００の終端領域６０における各領域の不純物のドーズ量と、第一の注入領域１２及び第二の注入領域１３との関係を示す図である。ショットキーダイオード１００を製造するにあたっては、図示しない半導体基板上に半導体層１を形成し、半導体層１の表面上にはショットキー接合となる金属電極３を設置することとなるが、金属電極３を設置する前に終端領域６０を形成する必要がある。そして、半導体層１の終端領域６０上には、図示しない絶縁性の表面保護膜が形成される。以下においては、特にショットキーダイオード１００の終端領域６０を形成する方法について、図２、図３及び図４を用いて説明する。なお、以下において、ドーズ量とは、単位面積当たりのドーズされた不純物の個数を示すものとする。 Next, a method for manufacturing the Schottky diode 100 that is the semiconductor device according to the first embodiment of the present invention will be described. 2 and 3 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG. 4 shows the impurity dose in each region in the termination region 60 of the Schottky diode 100 that is the semiconductor device according to the first embodiment of the present invention, and the first implantation region 12 and the second implantation region 13. It is a figure which shows a relationship. In manufacturing the Schottky diode 100, the semiconductor layer 1 is formed on a semiconductor substrate (not shown), and the metal electrode 3 serving as a Schottky junction is disposed on the surface of the semiconductor layer 1. It is necessary to form the termination region 60 before installing the device. An insulating surface protection film (not shown) is formed on the termination region 60 of the semiconductor layer 1. Hereinafter, a method for forming the termination region 60 of the Schottky diode 100 will be described with reference to FIGS. 2, 3, and 4. In the following description, the dose amount indicates the number of impurities doped per unit area.
　本実施の形態にかかる半導体装置の製造方法では、２回の注入工程によって終端領域６０を形成する。以下では、一回目の注入工程である第一の注入工程で不純物が注入される領域を第一の注入領域１２と呼び、二回目の注入工程である第二の注入工程で不純物が注入される領域を第二の注入領域１３と呼び、第一の注入領域１２と第二の注入領域１３が組み合わさることによって終端領域６０が形成される。なお、第一の注入領域１２と第二の注入領域１３は一部の領域が重なっている。 In the semiconductor device manufacturing method according to the present embodiment, the termination region 60 is formed by two implantation steps. Hereinafter, a region where impurities are implanted in the first implantation step, which is the first implantation step, is referred to as a first implantation region 12, and impurities are implanted in the second implantation step, which is the second implantation step. The region is called the second implantation region 13, and the termination region 60 is formed by combining the first implantation region 12 and the second implantation region 13. The first injection region 12 and the second injection region 13 are partially overlapped.
　まず、図２において、半導体層１の形成後に第一の注入領域１２においてｐ型の不純物であるＡｌイオンを注入する第一の注入工程を行う。第一の注入工程は、半導体層１の表面上に第一注入マスク１１ａを設置した状態で行われる。第一注入マスク１１ａのマスクパターンは、ｐ型ガードリング２、第一の電界緩和領域４、及び第三の小領域８の領域上に相当する第一の注入領域１２上が開口し、他の領域上を覆う形状となっている。また、第一の注入工程において注入される不純物のドーズ量は、第一の注入領域１２の第二の小領域７における不純物濃度が第二の不純物濃度となるドーズ量とする。なお、第一の注入工程及び後述する他の注入工程において、深さ方向の濃度分布は、ボックスプロファイルでも良いし、レトログレードプロファイルでも良いし、他のプロファイルあっても構わない。 First, in FIG. 2, after the formation of the semiconductor layer 1, a first implantation step is performed in which Al ions that are p-type impurities are implanted in the first implantation region 12. The first implantation step is performed with the first implantation mask 11 a installed on the surface of the semiconductor layer 1. The mask pattern of the first implantation mask 11a is such that the first implantation region 12 corresponding to the p-type guard ring 2, the first electric field relaxation region 4, and the third small region 8 is open, The shape covers the area. Further, the dose amount of the impurity implanted in the first implantation step is a dose amount at which the impurity concentration in the second small region 7 of the first implantation region 12 becomes the second impurity concentration. In the first implantation step and other implantation steps described later, the concentration distribution in the depth direction may be a box profile, a retrograde profile, or another profile.
　続いて、図３において、第二の注入領域１３においてｐ型不純物であるＡｌイオンを注入する第二の注入工程を行う。第二の注入工程は、半導体層１の表面上に第二注入マスク１１ｂを設置した状態で行われる。第二注入マスク１１ｂのマスクパターンは、ｐ型ガードリング２、第１の小領域６、及び第二の電界緩和領域５の領域上に相当する第二の注入領域１３上が開口し、他の領域上を覆う形状となっている。また、第二の注入工程において注入される不純物のドーズ量は、第一の注入工程において注入されるドーズ量よりも少ないものとする。なお、第一の注入工程と第二の注入工程は、先に第二の工程を行い、その後第一の注入工程を行うことしてもよい。 Subsequently, in FIG. 3, a second implantation step is performed in which Al ions that are p-type impurities are implanted in the second implantation region 13. The second implantation step is performed in a state where the second implantation mask 11 b is installed on the surface of the semiconductor layer 1. The mask pattern of the second implantation mask 11b is such that the second implantation region 13 corresponding to the region of the p-type guard ring 2, the first small region 6, and the second electric field relaxation region 5 has an opening. The shape covers the area. In addition, the dose amount of the impurity implanted in the second implantation step is smaller than the dose amount implanted in the first implantation step. In addition, a 1st injection | pouring process and a 2nd injection | pouring process may perform a 2nd process previously, and may perform a 1st injection | pouring process after that.
　以上の工程により、図４に示す内側の領域において、第一の注入領域１２と第二の注入領域１３が重なった領域、すなわち第一の注入工程及び第二の注入工程の双方によってＡｌイオンが注入された領域が第一の不純物濃度のｐ型ガードリング２となる。また、ｐ型ガードリング２の外側の領域において、第一の注入工程及び第二の注入工程の双方によってＡｌイオンが注入された領域が第一の不純物濃度の第一の小領域６となり、第一の注入工程のみによってＡｌイオンが注入された領域が第二の不純物濃度の第二の小領域７となり、第一の電界緩和領域４が形成される。 Through the above steps, in the inner region shown in FIG. 4, the region where the first implantation region 12 and the second implantation region 13 overlap, that is, Al ions are produced by both the first implantation step and the second implantation step. The implanted region becomes the p-type guard ring 2 having the first impurity concentration. Further, in the region outside the p-type guard ring 2, the region into which Al ions are implanted by both the first implantation step and the second implantation step becomes the first small region 6 having the first impurity concentration. The region into which Al ions are implanted by only one implantation step becomes the second small region 7 having the second impurity concentration, and the first electric field relaxation region 4 is formed.
　さらに、第一の電界緩和領域４の外側の領域において、第一の注入工程及び第二の注入工程の双方によってＡｌイオンが注入された領域が第三の不純物濃度（第一の不純物濃度）の第三の小領域８となり、第二の注入工程のみによってＡｌイオンが注入された領域が第四の不純物濃度の第四の小領域９となり、第二の電界緩和領域５が形成される。そして、第一の電界緩和領域４と第二の電界緩和領域５の間の領域において、第一の注入工程及び第二の注入工程の双方によってＡｌイオンが注入された領域が第一の不純物濃度の接合領域１０として形成される。 Furthermore, in the region outside the first electric field relaxation region 4, the region into which Al ions are implanted by both the first implantation step and the second implantation step has a third impurity concentration (first impurity concentration). A region where the Al ions are implanted only by the second implantation step becomes the fourth small region 9 having the fourth impurity concentration, and the second electric field relaxation region 5 is formed. In the region between the first electric field relaxation region 4 and the second electric field relaxation region 5, the region into which Al ions are implanted by both the first implantation step and the second implantation step is the first impurity concentration. The junction region 10 is formed.
　なお、第一の不純物濃度および第三の不純物濃度は第一の注入工程及び第二の注入工程で注入されるＡｌイオンのドーズ量の和を変化させることで調整することができ、第二の不純物濃度は第一の注入工程で注入されるＡｌイオンのドーズ量を変化させることで調整することができ、第四の不純物濃度は第二の注入工程で注入されるＡｌイオンのドーズ量を変化させることで調整することができる。 The first impurity concentration and the third impurity concentration can be adjusted by changing the sum of the dose amounts of Al ions implanted in the first implantation step and the second implantation step. The impurity concentration can be adjusted by changing the dose amount of Al ions implanted in the first implantation step, and the fourth impurity concentration changes the dose amount of Al ions implanted in the second implantation step. Can be adjusted.
　また、第一の電界緩和領域４と第二の電界緩和領域５の境界に、接続領域１０が形成されているが、マスクの位置合わせ精度が十分に保証される場合は、接続領域１０を小面積にするか、接続領域１０を省略して第一の電界緩和領域４と第二の電界緩和領域５を直接接続してもよい。 In addition, the connection region 10 is formed at the boundary between the first electric field relaxation region 4 and the second electric field relaxation region 5, but if the mask alignment accuracy is sufficiently ensured, the connection region 10 is reduced. Alternatively, the first electric field relaxation region 4 and the second electric field relaxation region 5 may be directly connected by omitting the connection area 10.
　このように、第一の不純物濃度および第三の不純物濃度を第二の不純物濃度と第四の不純物濃度の和とすれば、二回の注入工程によって、ｐ型ガードリング２、第一の電界緩和領域４、接続領域１０、及び第二の電界緩和領域５からなる終端領域６０を形成することができる。 Thus, if the first impurity concentration and the third impurity concentration are the sum of the second impurity concentration and the fourth impurity concentration, the p-type guard ring 2 and the first electric field can be obtained by two implantation steps. A termination region 60 composed of the relaxation region 4, the connection region 10, and the second electric field relaxation region 5 can be formed.
　次に、本発明の実施の形態１にかかる半導体装置及びその製造方法の作用、効果について説明する。図５は、本発明の実施の形態１にかかる半導体装置であるショットキーダイオード１００に逆方向電圧を段階的に変化させて印加した場合の電位分布の変化に関するシミュレーション結果を示す図である。図５における各線はショットキーダイオード１００の半導体層１内の等電位線を示しており、上側から順に、低電圧、中電圧、高電圧をショットキーダイオード１００の逆方向電圧として印加した場合のシミュレーション結果をそれぞれ示している。 Next, functions and effects of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described. FIG. 5 is a diagram showing a simulation result regarding a change in potential distribution when a reverse voltage is applied stepwise to the Schottky diode 100 which is the semiconductor device according to the first embodiment of the present invention. Each line in FIG. 5 represents an equipotential line in the semiconductor layer 1 of the Schottky diode 100, and simulation is performed when a low voltage, a medium voltage, and a high voltage are applied as reverse voltages of the Schottky diode 100 in order from the top. Each result is shown.
　本実施の形態にかかる半導体装置では、第一の電界緩和領域４において第一の不純物濃度の第一の小領域６と第二の不純物濃度の第二の小領域７が交互に形成されており、第一の電界緩和領域４の外側に形成される第二の電界緩和領域５において第一の不純物濃度と等しい第三の不純物濃度の第三の小領域８と第二の不純物濃度よりも低い第四の不純物濃度の第四の小領域９が交互に形成されていることから、第一の電界緩和領域４における実効的な不純物濃度は第二の電界緩和領域５における実効的な不純物濃度よりも高くなり、終端領域６０の外側に向かうにつれ不純物濃度が低くなるように終端領域６０が形成されている。そのため、図５に示すように、印加される逆方向電圧が高くなるにつれて、注入領域内部において第二の電界緩和領域５から第一の電界緩和領域４へと空乏層が段階的に広がり第二の電界緩和領域５から第一の電界緩和領域４へと段階的に電位分担が行われていることがわかる。 In the semiconductor device according to the present embodiment, the first small regions 6 having the first impurity concentration and the second small regions 7 having the second impurity concentration are alternately formed in the first electric field relaxation region 4. In the second electric field relaxation region 5 formed outside the first electric field relaxation region 4, the third small region 8 having a third impurity concentration equal to the first impurity concentration is lower than the second impurity concentration. Since the fourth small regions 9 having the fourth impurity concentration are alternately formed, the effective impurity concentration in the first electric field relaxation region 4 is higher than the effective impurity concentration in the second electric field relaxation region 5. The termination region 60 is formed so that the impurity concentration decreases toward the outside of the termination region 60. Therefore, as shown in FIG. 5, as the applied reverse voltage increases, the depletion layer gradually expands from the second electric field relaxation region 5 to the first electric field relaxation region 4 in the injection region. It can be seen that potential sharing is performed stepwise from the electric field relaxation region 5 to the first electric field relaxation region 4.
　また、終端領域６０の外側に設けられた第二の電界緩和領域５の実効的な不純物濃度は第一の電界緩和領域４の実効的な不純物濃度よりも低い濃度となっているが、第二の電界緩和領域５内に設けられた第三の小領域８の不純物濃度は第一の電界緩和領域４内に設けられた第一の小領域６の不純物濃度と同じ第一の不純物濃度となっているため、第二の電界緩和領域５の外側においても空乏層が十分に広がっていることがわかる。よって、本実施の形態によれば、各領域の境界面や不純物が注入された最外周の領域の外周端部における電界集中をより効果的に緩和することができる。 The effective impurity concentration of the second electric field relaxation region 5 provided outside the termination region 60 is lower than the effective impurity concentration of the first electric field relaxation region 4. The impurity concentration of the third small region 8 provided in the electric field relaxation region 5 is the same as the impurity concentration of the first small region 6 provided in the first electric field relaxation region 4. Therefore, it can be seen that the depletion layer is sufficiently spread even outside the second electric field relaxation region 5. Therefore, according to the present embodiment, it is possible to more effectively alleviate electric field concentration at the outer peripheral edge of the boundary surface of each region and the outermost peripheral region into which impurities are implanted.
　さらに、本実施の形態にかかる半導体装置の製造方法では、上述したように、二回の注入工程によってｐ型ガードリング２、第一の電界緩和領域４、及び第二の電界緩和領域５を形成しており、少ない製造工程で不純物濃度が異なる複数の領域を備えた終端領域６０を形成することができる。さらに、新たな注入工程を増やすことなく、後述する第三の電界緩和領域１７や第四の電界緩和領域１９、さらには第二の不純物濃度又は第四の不純物濃度からなる単一の領域を追加することも可能であり、各領域を組み合わせることにより終端領域６０における不純物濃度の階調数を増加させ半導体装置の高耐圧化を図ることができる。 Furthermore, in the method of manufacturing a semiconductor device according to the present embodiment, as described above, the p-type guard ring 2, the first electric field relaxation region 4, and the second electric field relaxation region 5 are formed by two implantation steps. Thus, the termination region 60 including a plurality of regions having different impurity concentrations can be formed with a small number of manufacturing steps. Further, a third electric field relaxation region 17 and a fourth electric field relaxation region 19, which will be described later, and a single region consisting of the second impurity concentration or the fourth impurity concentration are added without increasing a new implantation step. It is also possible to increase the number of gradations of the impurity concentration in the termination region 60 by combining the regions, thereby increasing the breakdown voltage of the semiconductor device.
　また、本実施の形態にかかる半導体装置は、各注入工程で注入される不純物のドーズ量によって耐圧が大きく変化する。図６に、各注入工程で注入される不純物のドーズ量を変化させた場合のショットキーダイオード１００の耐圧についてのシミュレーション結果を示す。図６において、縦軸は半導体装置の耐圧を示しており、各棒グラフは第一の注入工程において第一の注入領域１２に注入されるドーズ量と第二の注入工程において第二の注入領域１３に注入されるドーズ量を特定のドーズ量にした場合の耐圧を示している。これより、第一の注入領域１２又は第二の注入領域１３のいずれか一方のドーズ量が０．０ｃｍ－２、つまり、第一の注入工程又は第二の注入工程のいずれか一方しか行わず終端領域６０を形成した場合においてもある程度の耐圧が得られているが、第一の注入領域１２と第二の注入領域１３のドーズ量がそれぞれ１．４Ｅ＋１３ｃｍ－２以下で、第一の注入領域１２と第二の注入領域１３のドーズ量の合計が１．２Ｅ＋１３～２．４Ｅ＋１３ｃｍ－２の場合に高耐圧の半導体装置が得られることがわかる。さらに、第一の注入領域１２のドーズ量が１．０Ｅ＋１３ｃｍ－２以上であり、第二の注入領域１３のドーズ量が１．０Ｅ＋１３ｃｍ－２以下の場合に、１７００ｋＶを超える耐圧を有する半導体装置が数多く得られることがわかる。 Also, the breakdown voltage of the semiconductor device according to the present embodiment varies greatly depending on the dose of impurities implanted in each implantation process. FIG. 6 shows a simulation result of the breakdown voltage of the Schottky diode 100 when the dose amount of the impurity implanted in each implantation step is changed. In FIG. 6, the vertical axis represents the breakdown voltage of the semiconductor device, and each bar graph represents the dose injected into the first implantation region 12 in the first implantation step and the second implantation region 13 in the second implantation step. The withstand voltage when the dose amount injected into the substrate is set to a specific dose amount is shown. Accordingly, the dose amount of either the first implantation region 12 or the second implantation region 13 is 0.0 cm −2, that is, only one of the first implantation step and the second implantation step is performed. Even when the termination region 60 is formed, a certain level of breakdown voltage is obtained. However, the doses of the first implantation region 12 and the second implantation region 13 are 1.4E + 13 cm −2 or less, respectively. It can be seen that a high breakdown voltage semiconductor device can be obtained when the total dose of 12 and the second implantation region 13 is 1.2E + 13 to 2.4E + 13 cm−2. Further, when the dose amount of the first implantation region 12 is 1.0E + 13 cm −2 or more and the dose amount of the second implantation region 13 is 1.0E + 13 cm −2 or less, a semiconductor device having a breakdown voltage exceeding 1700 kV is obtained. It turns out that many are obtained.
　ただし、現実には、不純物の活性化率が１００％でなはなく、またプロセス中にトラップされる固定電荷による影響を受け、シミュレーションどおりの耐圧が得られることは少ない。以上のような影響を考慮すると、実際に注入するドーズ量は、シミュレーション等に基づくドーズ量の設計値よりも大きくする必要があり、４Ｈ－ＳｉＣの場合には設計値よりも６Ｅ＋１２ｃｍ－２程度大きいドーズ量で注入することが望ましい。そのため、本発明の終端構造では、活性化率や固定電荷の影響を考慮して、第一の注入領域１２と第二の注入領域１３のドーズ量がそれぞれ２．０Ｅ＋１３ｃｍ－２以下で、第一の注入領域１２と第二の注入領域１３のドーズ量の合計が１．２Ｅ＋１３～３．０Ｅ＋１３ｃｍ－２の範囲で不純物の注入を行うことが望ましい。 However, in reality, the activation rate of impurities is not 100%, and it is hardly affected by the fixed charges trapped during the process, and the breakdown voltage as simulated is rarely obtained. Considering the above effects, the dose amount actually implanted needs to be larger than the design value of the dose amount based on the simulation or the like, and in the case of 4H—SiC, it is about 6E + 12 cm−2 larger than the design value. It is desirable to implant at a dose. Therefore, in the termination structure of the present invention, in consideration of the effect of the activation rate and fixed charge, the dose amounts of the first implantation region 12 and the second implantation region 13 are 2.0E + 13 cm −2 or less, respectively. It is desirable to implant impurities in a range where the total dose of the implantation region 12 and the second implantation region 13 is in the range of 1.2E + 13 to 3.0E + 13 cm −2.
　なお、本実施の形態においては、第二の小領域７の不純物濃度である第二の不純物濃度を第四の小領域の不純物濃度である第四の不純物濃度よりも大きくすることで、外周側に向かうにつれて実効的な不純物濃度が小さくなるように構成し、耐圧の向上を図っているが、第二の不純物濃度を第四の不純物濃度よりも小さくすることしてもよい。図６に示すように、第二の不純物濃度が第三の不純物濃度よりも小さくした場合、すなわち第一の注入工程で注入される不純物が第二の注入工程で注入される不純物よりも少ない場合においても、実効的な不純物濃度が低い第一の電界緩和領域４から実効的な不純物濃度が高い第二の電界緩和領域５へと段階的に電位分担するため、比較的高耐圧の半導体装置を得られることがある。 In the present embodiment, the second impurity concentration that is the impurity concentration of the second small region 7 is set to be larger than the fourth impurity concentration that is the impurity concentration of the fourth small region. The effective impurity concentration is reduced as it goes to improve the breakdown voltage. However, the second impurity concentration may be made lower than the fourth impurity concentration. As shown in FIG. 6, when the second impurity concentration is lower than the third impurity concentration, that is, when the impurity implanted in the first implantation step is less than the impurity implanted in the second implantation step. In this case, since the potential is shared stepwise from the first electric field relaxation region 4 having a low effective impurity concentration to the second electric field relaxation region 5 having a high effective impurity concentration, a relatively high breakdown voltage semiconductor device is manufactured. May be obtained.
　また、本実施の形態においては、第一の小領域６と第三の小領域８の不純物濃度が同じになるように構成しているが、新たな注入工程を行うなどして第三の小領域８の不純物濃度である第三の不純物濃度を第一の小領域６の不純物濃度である第一の不純物濃度よりも高くすることとしてもよい。このような場合、第二の小領域７と第四の小領域９の不純物濃度に変化はないため、図５に示すように、印加される逆方向電圧が高くなるにつれて、注入領域内部において第二の電界緩和領域５から第一の電界緩和領域４へと空乏層が段階的に広がり第二の電界緩和領域５から第一の電界緩和領域４へと段階的に電位分担が行われる。また、第二の電界緩和領域５内に設けられた第三の小領域８の不純物濃度がさらに高くなるため、第二の電界緩和領域５の外側において空乏層がより大きく広がる。よって、注入領域を外周側に広げることなく、各領域の境界面や不純物が注入された最外周の領域の外周端部における電界集中をより効果的に緩和することができる。 Further, in the present embodiment, the first small region 6 and the third small region 8 are configured to have the same impurity concentration. The third impurity concentration that is the impurity concentration of the region 8 may be higher than the first impurity concentration that is the impurity concentration of the first small region 6. In such a case, since there is no change in the impurity concentration of the second small region 7 and the fourth small region 9, as shown in FIG. 5, as the applied reverse voltage increases, A depletion layer spreads stepwise from the second electric field relaxation region 5 to the first electric field relaxation region 4, and potential sharing is performed stepwise from the second electric field relaxation region 5 to the first electric field relaxation region 4. In addition, since the impurity concentration of the third small region 8 provided in the second electric field relaxation region 5 is further increased, the depletion layer further spreads outside the second electric field relaxation region 5. Therefore, it is possible to more effectively alleviate the electric field concentration at the outer peripheral end of the boundary surface of each region and the outermost peripheral region where impurities are implanted without expanding the implantation region to the outer peripheral side.
　また、高耐圧化のためには離間した第一の注入領域１２および第二の注入領域１３の最内周の間隔をどれだけ狭められるかが重要になる。ここで、各注入工程によって不純物が注入されたｐ型領域の間隔の最小寸法が余りに小さいときには、注入マスク１１ａとなるレジストが過度に露光された際等に、レジストが倒れて狙いどおりのパターンが得られない可能性がある。レジストが倒れるのを抑制しつつｐ型領域の間隔を狭めるには、図７のように注入マスク１１として側面にテーパー形状の付いたレジストを用いて注入することが有効である。例えばレジストが１μｍの幅よりも小さく仕上がると倒れてしまうとして、通常は過度の露光によりレジスト幅がシュリンクする可能性も踏まえて１μｍよりもやや太く仕上がるように設計を行なう。ただし、図７のように側面にテーパーがある場合は１μｍの幅の仕上がりでもレジストが倒れることなく注入工程を行なうことができる。 Also, in order to increase the withstand voltage, it is important how much the distance between the innermost circumferences of the first implantation region 12 and the second implantation region 13 that are separated can be reduced. Here, when the minimum dimension of the interval between the p-type regions into which impurities are implanted by each implantation step is too small, the resist collapses when the resist serving as the implantation mask 11a is excessively exposed, and a pattern as intended is formed. It may not be obtained. In order to reduce the interval between the p-type regions while suppressing the resist from falling down, it is effective to implant using a resist having a tapered side surface as the implantation mask 11 as shown in FIG. For example, if the resist finishes smaller than a width of 1 μm, it will fall down, and the design is usually made to be slightly thicker than 1 μm in consideration of the possibility that the resist width shrinks due to excessive exposure. However, when the side surface has a taper as shown in FIG. 7, the implantation process can be performed without falling the resist even if the width is 1 μm.
　また、半導体基板が４Ｈ－ＳｉＣからなる場合には、レジスト直下のｎ型領域においては隣り合うｐ型領域の双方からの不純物拡散が起こり、耐圧が得られる現実的な不純物注入量では０．２～０．８μｍ程度の間隔の縮小が可能である。図８は、１μｍ間隔のマスクを用いて、不純物濃度が１Ｅ＋１６ｃｍ－３のｎ－ドリフト層にドーズ量１Ｅ＋１３ｃｍ－２のＡｌイオンを５００ｋｅＶで注入した場合の、ｐ型領域の形状をシミュレーションした結果である。図８に示すように、かかる場合では、ｐ型領域の間隔が約０．４μｍ狭くなり、高耐圧化に向けて有利な設計が可能になる。さらに、テーパー形状の付いたレジストを用いる場合、テーパー形状の直下ではレジスト越しに注入される不純物も存在し、テーパーがない場合と比べてより高濃度なｐ型領域が得られ、高耐圧化に有利になる。 In addition, when the semiconductor substrate is made of 4H—SiC, impurity diffusion from both adjacent p-type regions occurs in the n-type region immediately below the resist, and a practical impurity implantation amount that can achieve a breakdown voltage is 0.2. The interval can be reduced by about 0.8 μm. FIG. 8 shows the result of simulating the shape of the p-type region when Al ions having a dose of 1E + 13 cm−2 are implanted at 500 keV into an n− drift layer having an impurity concentration of 1E + 16 cm−3 using a mask with an interval of 1 μm. is there. As shown in FIG. 8, in such a case, the interval between the p-type regions is narrowed by about 0.4 μm, and an advantageous design for increasing the breakdown voltage is possible. Furthermore, when a resist with a tapered shape is used, impurities implanted through the resist also exist immediately below the tapered shape, and a higher concentration p-type region can be obtained compared to the case without a taper, thereby increasing the breakdown voltage. Become advantageous.
　また、本実施の形態では、ｐ型ガードリング２と第一の電界緩和領域４が直接接続し、接続領域１０を挟んで第一の電界緩和領域４と第二の電界緩和領域５が直接接続するか、接続領域１０を挟まずに第一の電界緩和領域４と第二の電界緩和領域５が直接接続する場合について述べたが、図９に示すように、ガードリング２と第一の電界緩和領域４が離間し、第一の電界緩和領域４と第二の電界緩和領域５が離間して形成されている場合においても、印加電圧の増加とともに、第一の電界緩和領域４と第二の電界緩和領域５に段階的に電位分担が進み、効果的な電界緩和効果が得られる。 In the present embodiment, p-type guard ring 2 and first electric field relaxation region 4 are directly connected, and first electric field relaxation region 4 and second electric field relaxation region 5 are directly connected across connection region 10. Alternatively, the case where the first electric field relaxation region 4 and the second electric field relaxation region 5 are directly connected without sandwiching the connection region 10 has been described. However, as shown in FIG. Even when the relaxation region 4 is separated and the first electric field relaxation region 4 and the second electric field relaxation region 5 are formed apart from each other, the first electric field relaxation region 4 and the second electric field relaxation region 4 are increased as the applied voltage is increased. The electric potential sharing proceeds stepwise to the electric field relaxation region 5 and an effective electric field relaxation effect is obtained.
　また、以上の説明では第一の電界緩和領域４および第二の電界緩和領域５において、それぞれの各小領域の幅は一定のものとしているが、図１０に示すように、第一の電界緩和領域４および第二の電界緩和領域５において、不純物濃度の高い第一の小領域６及び第三の小領域８の幅を終端領域６０の外側に向かって徐々に小さくし、不純物濃度の低い第二の小領域７及び第四の小領域９の幅を終端領域６０の外周に向かって徐々に大きくすることで、外周側に向かうにつれて不純物濃度がよりなだらかに小さくなるため、より効果的に電界集中を緩和することができ、より高いオフ耐圧を実現する半導体装置が得られる。 In the above description, the width of each small region is constant in the first electric field relaxation region 4 and the second electric field relaxation region 5, but as shown in FIG. In the region 4 and the second electric field relaxation region 5, the widths of the first small region 6 and the third small region 8 having a high impurity concentration are gradually decreased toward the outside of the termination region 60, so By gradually increasing the widths of the second small region 7 and the fourth small region 9 toward the outer periphery of the termination region 60, the impurity concentration gradually decreases toward the outer peripheral side. Concentration can be relaxed, and a semiconductor device that achieves higher off-voltage can be obtained.
　かかる場合、第一の注入工程で不純物を注入する際に、複数の離間した第一の小領域６は、互いの間隔を外周側に向かうにつれて変化させるように注入を行うことで形成できる。また、第二の注入工程で不純物を注入する際に、複数の離間した第二の小領域７は、互いの間隔を外周側に向かうにつれて変化させるように注入を行うことで形成できる。この点は、第三の小領域８及び第四の小領域９についても同様で、すなわち、各注入工程で不純物を注入する各注入領域は、各注入領域における複数の離間した領域の間隔を変化させるように注入を行うことで形成することができる。 In such a case, when the impurities are implanted in the first implantation step, the plurality of spaced first small regions 6 can be formed by performing implantation so that the interval between the first small regions 6 changes toward the outer peripheral side. In addition, when the impurities are implanted in the second implantation step, the plurality of spaced second small regions 7 can be formed by performing implantation so that the distance between the small regions 7 changes toward the outer peripheral side. The same applies to the third small region 8 and the fourth small region 9, that is, each implantation region into which impurities are implanted in each implantation step changes the interval between a plurality of spaced regions in each implantation region. It can be formed by performing implantation so as to cause
　また、本実施の形態では、第一の注入領域１２と第二の注入領域１３の注入深さは一定としているが、図１１および図１２で示すように、第一の注入領域１２と第二の注入領域１３の注入深さが異なるように形成してもよい。図１１では第一の注入領域１２の注入深さをより深くした場合、図１２では第二の注入領域１３の注入深さをより深くした場合を示している。例えば、４Ｈ－ＳｉＣからなる半導体基板にＡｌイオンを注入する場合、第一の注入領域１２を２００～５００ｋｅＶ、第二の注入領域１３を３００～７００ｋｅＶなどの注入エネルギーで注入することで、図１２に示すように第二の注入領域１３の注入深さをより深くすることができる。このような場合、より深く注入された第二の注入領域１３では半導体層１へ空乏層がより広がりやすくなり、高耐圧化に有利となる。 In this embodiment, the implantation depths of the first implantation region 12 and the second implantation region 13 are constant, but as shown in FIGS. 11 and 12, the first implantation region 12 and the second implantation region 12 are the same. The implantation regions 13 may be formed so that the implantation depths thereof are different. 11 shows a case where the implantation depth of the first implantation region 12 is made deeper, and FIG. 12 shows a case where the implantation depth of the second implantation region 13 is made deeper. For example, when Al ions are implanted into a semiconductor substrate made of 4H—SiC, the first implantation region 12 is implanted with an implantation energy of 200 to 500 keV, and the second implantation region 13 is implanted with an implantation energy of 300 to 700 keV. As shown in FIG. 5, the implantation depth of the second implantation region 13 can be made deeper. In such a case, the depletion layer more easily spreads into the semiconductor layer 1 in the second implantation region 13 implanted deeper, which is advantageous for increasing the breakdown voltage.
　ただし、イオン注入を行う場合、通常は深さ方向に濃度ピークを持つように不純物が分布し、不純物が注入された各領域の表面における不純物濃度はやや小さくなる。しかし、金属電極３の端部での破壊を防ぐためには、金属電極３の端部直下においてある程度の不純物濃度を確保しておくことが必要であり、図１１および図１２で示すように、第一の注入領域１２と第二の注入領域１３のどちらかの注入深さは浅くしておくと良い。 However, when ion implantation is performed, impurities are normally distributed so as to have a concentration peak in the depth direction, and the impurity concentration on the surface of each region into which the impurities are implanted is slightly reduced. However, in order to prevent the breakage at the end of the metal electrode 3, it is necessary to ensure a certain impurity concentration just below the end of the metal electrode 3. As shown in FIGS. The implantation depth of either the first implantation region 12 or the second implantation region 13 is preferably shallow.
　また、図１３および図１４で示すように、第一の注入領域１２と第二の注入領域１３のどちらかの表面の位置がｎ型半導体となっても良い。 Further, as shown in FIGS. 13 and 14, the position of the surface of either the first implantation region 12 or the second implantation region 13 may be an n-type semiconductor.
　また、本実施の形態では、縦型構造のショットキーダイオード１００を例として挙げて説明したが、他の例として、図１５に示すようなｐ＋コンタクト領域２３、ｎソース領域２４、ゲート絶縁膜２５、ゲート電極２６、フィールド絶縁膜２７、層間絶縁膜２８などを備えた縦型構造のＭＯＳＦＥＴ１０１としてもよい。このようなｐベース領域１５を活性領域５０に持つ半導体装置の場合には、終端領域６０の全領域において表面がｎ型半導体となっても良い。 In this embodiment, the vertical Schottky diode 100 is described as an example. As another example, a p + contact region 23, an n source region 24, and a gate insulating film 25 as shown in FIG. Alternatively, the MOSFET 101 may have a vertical structure including the gate electrode 26, the field insulating film 27, the interlayer insulating film 28, and the like. In the case of such a semiconductor device having the p base region 15 in the active region 50, the surface of the entire termination region 60 may be an n-type semiconductor.
　また、ショットキーダイオードの順方向導通時の抵抗を下げるため、活性領域５０にイオン注入や高濃度エピタキシャル成長を行うなどして、半導体層１よりも濃いｎ型の不純物領域であるｎ＋領域７０を設けることがあるが、図１６で示すように、ショットキーダイオード１００においては注入マスク等を用いずに、半導体層１の表面の全面にｎ＋領域７０を形成してもよい。この場合においても、第一の小領域６および第三の小領域８の不純物濃度が高くなっているため、注入領域の外側において空乏層を十分に広げることができ、各領域の境界面や不純物が注入された最外周の領域の外周端部における電界集中を効果的に緩和することができる。 Further, in order to lower the resistance when the Schottky diode is forward-conducting, an n + region 70 that is an n-type impurity region that is deeper than the semiconductor layer 1 is provided by ion implantation or high-concentration epitaxial growth in the active region 50. However, as shown in FIG. 16, in the Schottky diode 100, the n + region 70 may be formed on the entire surface of the semiconductor layer 1 without using an implantation mask or the like. Also in this case, since the impurity concentration of the first small region 6 and the third small region 8 is high, the depletion layer can be sufficiently expanded outside the implantation region, and the boundary surface and impurity of each region can be expanded. It is possible to effectively alleviate electric field concentration at the outer peripheral end of the outermost peripheral region into which is injected.
　また、このようなｎ＋領域７０をショットキーダイオードに形成した場合、順方向導通時の抵抗の低減が可能であるが、半導体層１の表面付近での電界集中により耐圧が低下する場合がある。低抵抗と高耐圧を両立するには活性領域をＪＢＳ（Ｊｕｎｃｔｉｏｎ　Ｂａｒｒｉｅｒ　Ｓｃｈｏｔｔｋｙ）とすることが効果的で、図１７に示すように第一の注入工程および第二の注入工程のいずれかまたは両方において、ＪＢＳ領域２９を同時に形成しておくとよい。図１７においては、第一の注入領域１２を形成する際に同時にＪＢＳ領域２９を形成した場合のＪＢＳを示している。この場合においては、活性領域５０ではｎ＋領域７０の効果により低抵抗となり、かつＪＢＳ領域２９で耐圧を保持し、また終端領域６０では第一の小領域６および第三の小領域８の不純物濃度が高くなっているため、注入領域の外側において空乏層を十分に広げることができ、各領域の境界面や不純物が注入された最外周の領域の外周端部における電界集中を効果的に緩和することができる。 Further, when such an n + region 70 is formed in a Schottky diode, it is possible to reduce the resistance during forward conduction, but the breakdown voltage may be reduced due to electric field concentration near the surface of the semiconductor layer 1. In order to achieve both low resistance and high breakdown voltage, it is effective to use JBS (Junction Barrier Schottky) as the active region. In either or both of the first injection step and the second injection step, as shown in FIG. The JBS region 29 is preferably formed at the same time. FIG. 17 shows the JBS when the JBS region 29 is formed simultaneously with the formation of the first implantation region 12. In this case, the active region 50 has a low resistance due to the effect of the n + region 70 and maintains a breakdown voltage in the JBS region 29, and the impurity concentration of the first small region 6 and the third small region 8 in the termination region 60. Therefore, the depletion layer can be sufficiently expanded outside the implantation region, and the electric field concentration at the outer peripheral edge of the boundary surface of each region and the outermost region where impurities are implanted is effectively reduced. be able to.
　また、ＭＯＳＦＥＴのオン動作時の抵抗を下げるため、活性領域５０にイオン注入を行い、ｐベース領域１５と同じ程度の深さに半導体層１よりも濃いｎ型の不純物領域であるｎ＋領域８０を設けることがあるが、図１８で示すように、ＭＯＳＦＥＴ１０１などにおいては注入マスクを用いずに、半導体層１の表面の全面にｎ＋領域８０を形成してもよい。この場合においても、第一の小領域６および第三の小領域８の不純物濃度が高くなっているため、注入領域の外側において空乏層を十分に広げることができ、各領域の境界面や不純物が注入された最外周の領域の外周端部における電界集中を効果的に緩和することができる。 Further, in order to reduce the resistance when the MOSFET is turned on, ions are implanted into the active region 50, and an n + region 80, which is an n-type impurity region deeper than the semiconductor layer 1, is formed to the same depth as the p base region 15. As shown in FIG. 18, the n + region 80 may be formed on the entire surface of the semiconductor layer 1 without using an implantation mask in the MOSFET 101 or the like as shown in FIG. Also in this case, since the impurity concentration of the first small region 6 and the third small region 8 is high, the depletion layer can be sufficiently expanded outside the implantation region, and the boundary surface and impurity of each region can be expanded. It is possible to effectively alleviate electric field concentration at the outer peripheral end of the outermost peripheral region into which is injected.
　また、図１９に示すように、第二の電界緩和領域５の外側に第二の不純物濃度の第五の小領域１６を複数離間して備えることにより、第三の電界緩和領域１７を形成することとしてもよい。かかる場合、電界集中がさらに緩和されることとなり、より高耐圧の半導体装置を得ることができる。図１９に示した終端領域６０は、図２０に示すように、第一の注入領域１２を外周側に広げて第一の注入工程を行うことで形成する。そのため、第三の電界緩和領域１７を形成するために新たな注入工程を追加する必要はない。このとき、第二の電界緩和領域５と第三の電界緩和領域１７の境界に、新たに第一の注入領域１２と第二の注入領域１３が重なった接続領域１０が形成されているが、マスクの位置合わせ精度が十分に保証される場合は、接続領域１０を小面積にするか、接続領域１０を省略して第二の電界緩和領域５と第三の電界緩和領域１７を直接接続してもよい。 Further, as shown in FIG. 19, the third electric field relaxation region 17 is formed by providing a plurality of fifth small regions 16 having the second impurity concentration apart from each other outside the second electric field relaxation region 5. It is good as well. In such a case, the electric field concentration is further relaxed, and a higher breakdown voltage semiconductor device can be obtained. As shown in FIG. 20, the termination region 60 shown in FIG. 19 is formed by expanding the first injection region 12 to the outer peripheral side and performing the first injection step. Therefore, it is not necessary to add a new implantation step in order to form the third electric field relaxation region 17. At this time, a connection region 10 in which the first injection region 12 and the second injection region 13 are newly overlapped is formed at the boundary between the second electric field relaxation region 5 and the third electric field relaxation region 17. When the mask alignment accuracy is sufficiently ensured, the connection region 10 is reduced in area, or the connection region 10 is omitted and the second electric field relaxation region 5 and the third electric field relaxation region 17 are directly connected. May be.
　なお、第三の電界緩和領域１７を備える場合において、図２１又は図２２に示すように、第五の小領域１６における不純物濃度は第一の不純物濃度や第四の不純物濃度とすることとしてもよい。図２１において、第五の小領域１６の不純物濃度を第四の不純物濃度とする場合には、第二の注入領域１３を外周側に広げて第二の注入工程を行うことで第五の小領域１６を形成する。一方、図２２において、第五の小領域１６の不純物濃度を第一の不純物濃度とする場合には、第一の注入領域１２と第二の注入領域１３を広げ、第三の電界緩和領域１７において第一の注入領域１２と第二の注入領域１３を重ねるように各注入工程を行うことで第五の小領域１６を形成する。 When the third electric field relaxation region 17 is provided, the impurity concentration in the fifth small region 16 may be the first impurity concentration or the fourth impurity concentration, as shown in FIG. 21 or FIG. Good. In FIG. 21, when the impurity concentration of the fifth small region 16 is set to the fourth impurity concentration, the second injection region 13 is expanded to the outer peripheral side and the second injection step is performed to perform the fifth small region. Region 16 is formed. On the other hand, in FIG. 22, when the impurity concentration of the fifth small region 16 is the first impurity concentration, the first injection region 12 and the second injection region 13 are expanded, and the third electric field relaxation region 17. The fifth small region 16 is formed by performing each implantation step so that the first implantation region 12 and the second implantation region 13 overlap.
　特に、図２１に示すような終端領域６０の場合には、隣接する第二の電界緩和領域５と第三の電界緩和領域１７とがともに第二の注入領域から形成され、すなわち第二注入マスク１１ｂによって形成されるため、注入マスクの位置合わせの精度を考慮する必要がなくなる。その結果、接続領域１０を省略することができる。 In particular, in the case of the termination region 60 as shown in FIG. 21, the adjacent second electric field relaxation region 5 and third electric field relaxation region 17 are both formed from the second implantation region, that is, the second implantation mask. Therefore, it is not necessary to consider the accuracy of alignment of the implantation mask. As a result, the connection area 10 can be omitted.
　また、図２２に示すような終端領域６０とした場合には、第五の小領域１６の不純物濃度は第一の不純物濃度となり、終端領域６０の最外周にあたる第五の小領域１６の不純物濃度が他の場合と比較して大きいため、空乏層が終端領域６０の外周側により広がっていくこととなり電界集中の緩和を効果的に行うことができる。このような場合、隣接する第二の電界緩和領域５と第三の電界緩和領域１７はそれぞれ第一の注入領域１２と第二の注入領域１３から形成され、すなわち第一注入マスク１１ａと第二注入マスク１１ｂからそれぞれ形成される異なるため、注入マスクの位置合わせの精度が問題となるため、接続領域１０を設けることが効果的とである。ただし、注入マスクの位置合わせの精度が十分に確保されるときは、接続領域１０を小面積にするか、省略することとしてもよい。 In the case of the termination region 60 as shown in FIG. 22, the impurity concentration of the fifth small region 16 becomes the first impurity concentration, and the impurity concentration of the fifth small region 16 corresponding to the outermost periphery of the termination region 60. Is larger than the other cases, the depletion layer expands on the outer peripheral side of the termination region 60, and the electric field concentration can be effectively reduced. In such a case, the adjacent second electric field relaxation region 5 and third electric field relaxation region 17 are formed from the first implantation region 12 and the second implantation region 13, respectively, that is, the first implantation mask 11a and the second implantation region 13 are formed. Since each is different from the implantation mask 11b, the alignment accuracy of the implantation mask becomes a problem. Therefore, it is effective to provide the connection region 10. However, when the alignment accuracy of the implantation mask is sufficiently ensured, the connection region 10 may be reduced in area or omitted.
　さらに、第一の注入領域１２と第二の注入領域１３とを重ねることで形成される第一の不純物濃度の各領域の形成において、第一注入マスク１１ａと第二注入マスク１１ｂとの重ね合わせの精度の問題が存在する。マスクの重ね合わせ精度の問題を克服するため、例えば、図２３に示すように、第五の小領域１６を形成する部分の第一の注入領域１２と第二の注入領域１３のどちらか一方の幅を、もう一方よりも広くとると良い。図２３では、第二の注入領域１３の幅が第一の注入領域１２の幅よりも広い場合を示している。 Further, in the formation of the first impurity concentration regions formed by overlapping the first implantation region 12 and the second implantation region 13, the first implantation mask 11a and the second implantation mask 11b are overlaid. There are accuracy issues. In order to overcome the problem of mask overlay accuracy, for example, as shown in FIG. 23, either one of the first implantation region 12 and the second implantation region 13 in the portion forming the fifth small region 16 is formed. The width should be wider than the other. FIG. 23 shows a case where the width of the second implantation region 13 is wider than the width of the first implantation region 12.
　また、図２４に示すように、第五の小領域１６の不純物濃度が第二の不純物濃度の場合には（第一の不純物濃度の場合においても同様）、第三の電界緩和領域１７の外周に第四の不純物濃度の第六の小領域１８を形成することで、第四の電界緩和領域１９が形成され、電界集中がより一層緩和されることとなり、高耐圧な半導体装置を得ることができる。さらに、図２５に示すように、第四の電界緩和領域１９の外周に、第七の小領域２０を複数離間して形成し、第五の電界緩和領域２１を形成することとしてもよい。このような場合であっても、第六の小領域１８や第七の小領域２０は第一の注入領域１２や第二の注入領域１３を外周側に広げることで形成することができるため、新たな注入工程を追加する必要はない。 In addition, as shown in FIG. 24, when the impurity concentration of the fifth small region 16 is the second impurity concentration (the same applies to the case of the first impurity concentration), the outer periphery of the third electric field relaxation region 17 In addition, by forming the sixth small region 18 having the fourth impurity concentration, the fourth electric field relaxation region 19 is formed, the electric field concentration is further relaxed, and a high breakdown voltage semiconductor device can be obtained. it can. Furthermore, as shown in FIG. 25, a fifth electric field relaxation region 21 may be formed by forming a plurality of seventh small regions 20 on the outer periphery of the fourth electric field relaxation region 19. Even in such a case, the sixth small region 18 and the seventh small region 20 can be formed by expanding the first injection region 12 and the second injection region 13 to the outer peripheral side, There is no need to add a new injection step.
　また、本発明は半導体基板がＳｉＣからなる場合について説明を行ったが、珪素（Ｓｉ）等の他の半導体基板においても適用することができる。ここで、本発明においては、各電界緩和領域の不純物濃度は二つの小領域における不純物濃度の実効的な濃度となることから、各小領域の幅を細かくしてより微細な構造とすることで、各領域の境界面における電界集中をより効果的に緩和することができる。微細な構造を形成するに際しては、不純物の熱拡散が問題となるが、ＳｉＣはＳｉ等の他の半導体と比較して不純物の熱拡散が少ないため、ＳｉＣからなる半導体装置においてはより微細な構造を有する電界緩和領域を形成することが可能となり、電界集中の緩和において顕著な効果が得られる。 Further, although the present invention has been described for the case where the semiconductor substrate is made of SiC, it can also be applied to other semiconductor substrates such as silicon (Si). Here, in the present invention, since the impurity concentration of each electric field relaxation region is an effective concentration of the impurity concentration in two small regions, the width of each small region is made finer to form a finer structure. The electric field concentration at the boundary surface of each region can be more effectively mitigated. In forming a fine structure, thermal diffusion of impurities becomes a problem. However, SiC has less thermal diffusion of impurities than other semiconductors such as Si, so that a finer structure is required in a semiconductor device made of SiC. It is possible to form an electric field relaxation region having, and a remarkable effect is obtained in the relaxation of electric field concentration.
実施の形態２．
　実施の形態１においては、２回の注入工程によって形成することができる終端領域６０を備えた半導体装置について説明したが、これに限定されることなく、３回の注入工程によって形成された終端領域を備えることとしてもよい。以下、実施の形態２にかかる半導体装置として、３回の注入工程で形成される終端領域６０を備えたショットキーダイオード１０２について説明する。なお、実施の形態２にかかる半導体装置において、実施の形態１にかかる半導体装置と同一または対応する部分についての説明は省略し、相違する部分について説明を行う。 Embodiment 2. FIG.
In the first embodiment, the semiconductor device including the termination region 60 that can be formed by two implantation steps has been described. However, the present invention is not limited thereto, and the termination region is formed by three implantation steps. It is good also as providing. Hereinafter, as a semiconductor device according to the second embodiment, a Schottky diode 102 including a termination region 60 formed by three injection processes will be described. Note that in the semiconductor device according to the second embodiment, description of the same or corresponding parts as those of the semiconductor device according to the first embodiment will be omitted, and different parts will be described.
　図２６は、実施の形態２にかかる半導体装置であるショットキーダイオード１０２を示す要部断面図であり、図２７は、実施の形態２にかかる半導体装置の終端領域のドーズ量と各注入工程における注入領域を示す図である。図２６に示されたショットキーダイオード１０２は、図示しない半導体基板上に形成されたｎ－型の半導体層１の活性領域５０に対応する表面上に、ショットキー接合となる金属電極３が形成されている。また、金属電極３を形成する前には、あらかじめ電界緩和のための終端領域６０を形成しておく必要がある。 FIG. 26 is a cross-sectional view of a principal part showing a Schottky diode 102 which is a semiconductor device according to the second embodiment. FIG. 27 is a diagram illustrating a dose amount in a termination region of the semiconductor device according to the second embodiment and each implantation step. It is a figure which shows an injection | pouring area | region. In the Schottky diode 102 shown in FIG. 26, a metal electrode 3 serving as a Schottky junction is formed on the surface corresponding to the active region 50 of the n− type semiconductor layer 1 formed on a semiconductor substrate (not shown). ing. In addition, before the metal electrode 3 is formed, it is necessary to form a termination region 60 for electric field relaxation in advance.
　図２６に示されたショットキーダイオード１０２の終端領域６０において、不純物濃度の異なるｐ型の電界緩和領域は、ドーズ量の異なる三回の注入工程によって形成されている。３回の注入工程を行う場合には、第一の注入工程で不純物が注入される第一の注入領域１２、第二の注入工程で不純物が注入される第二の注入領域１３、及び第三の注入工程で不純物が注入される第三の注入領域２２の組み合わせによって、異なる不純物濃度の電界緩和領域は数多く形成することができる。そこで、３回の注入工程から形成することができる異なる種類の電界緩和領域を以下に示す。 In the termination region 60 of the Schottky diode 102 shown in FIG. 26, the p-type electric field relaxation regions having different impurity concentrations are formed by three implantation steps having different dose amounts. When performing the implantation process three times, the first implantation region 12 into which impurities are implanted in the first implantation process, the second implantation region 13 into which impurities are implanted in the second implantation process, and the third Many electric field relaxation regions having different impurity concentrations can be formed by combining the third implantation regions 22 into which impurities are implanted in the implantation step. Therefore, different types of electric field relaxation regions that can be formed from three implantation steps are shown below.
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域からなる電界緩和領域（電界緩和領域３０Ａ）
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第一の注入領域１２のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域からなる電界緩和領域（電界緩和領域３０B）
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第一の注入領域１２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第二の注入領域１３のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第三の注入領域２２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第一の注入領域１２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域（電界緩和領域３０C）
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第二の注入領域１３のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域（電界緩和領域３０D）
・第一の注入領域１２のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第一の注入領域１２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第一の注入領域１２のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第三の注入領域２２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第二の注入領域１３のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域
・第二の注入領域１３のドーズ量と第三の注入領域１２のドーズ量とを合わせたドーズ量で定まる不純物濃度の小領域と、第三の注入領域２２のドーズ量で定まる不純物濃度の小領域からなる電界緩和領域（電界緩和領域３０E）
・第一の注入領域１２のドーズ量で定まる不純物濃度の電界緩和領域
・第二の注入領域１３のドーズ量で定まる不純物濃度の電界緩和領域
・第三の注入領域２２のドーズ量で定まる不純物濃度の電界緩和領域（電界緩和領域３０F）
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量とを合わせたドーズ量で定まる不純物濃度の電界緩和領域
・第一の注入領域１２のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の電界緩和領域
・第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の電界緩和領域
・第一の注入領域１２のドーズ量と第二の注入領域１３のドーズ量と第三の注入領域２２のドーズ量とを合わせたドーズ量で定まる不純物濃度の電界緩和領域 A small region having an impurity concentration determined by a combined dose amount of the dose amount of the first implantation region 12, the dose amount of the second implantation region 13, and the dose amount of the third implantation region 22, and the first implantation region An electric field relaxation region (electric field relaxation region 30A) composed of a small region having an impurity concentration determined by a combined dose amount of 12 and the dose amount of the second implantation region 13
A small region having an impurity concentration determined by a combined dose amount of the dose amount of the first implantation region 12, the dose amount of the second implantation region 13, and the dose amount of the third implantation region 22, and the first implantation region An electric field relaxation region (electric field relaxation region 30B) consisting of a small region having an impurity concentration determined by the total dose amount of 12 and the dose amount of the third implantation region 22
A small region having an impurity concentration determined by the combined dose amount of the first implantation region 12, the second implantation region 13, and the third implantation region 22, and the second implantation region The dose amount of the electric field relaxation region / first implantation region 12 and the second implantation region 13, each of which has a small impurity concentration determined by the combined dose amount of 13 and the dose amount of the third implantation region 22. An electric field relaxation region / first region composed of a small region with an impurity concentration determined by the combined dose amount and the dose amount of the third implantation region 22 and a small region with an impurity concentration determined by the dose amount of the first implantation region 12. A small region having an impurity concentration determined by the combined dose of the dose of one implantation region 12, the dose of the second implantation region 13, and the dose of the third implantation region 22; Impurity concentration determined by dose A small region having an impurity concentration determined by the combined amount of the dose amount of the first implantation region 12, the dose amount of the second implantation region 13, and the dose amount of the third implantation region 22. The electric field relaxation region and the dose amount of the first implantation region 12 and the dose amount of the second implantation region 13 which are composed of a low impurity concentration region determined by the dose amount of the third implantation region 22 are determined. Electric field relaxation region (electric field relaxation region 30C) composed of a small region of impurity concentration and a small region of impurity concentration determined by the dose amount of the first implantation region 12
A small impurity concentration region determined by the combined dose amount of the first implantation region 12 and the second implantation region 13 and a small impurity concentration determined by the dose amount of the second implantation region 13 Electric field relaxation region composed of regions (electric field relaxation region 30D)
A small impurity concentration region determined by the combined dose amount of the first implantation region 12 and the third implantation region 22 and a small impurity concentration determined by the dose amount of the first implantation region 12 A small region having an impurity concentration determined by a combined dose amount of the electric field relaxation region / first implantation region 12 and the dose amount of the third implantation region 22, and a dose amount of the third implantation region 22. A small region having an impurity concentration determined by a combined dose amount of the third implantation region 22 and the dose amount of the second implantation region 13 and the electric field relaxation region composed of a small region having an impurity concentration determined by Low electric field concentration region determined by the sum of the dose amount of the electric field relaxation region / second injection region 13 and the dose amount of the third injection region 12, which is a region having a small impurity concentration determined by the dose amount of the injection region 13. Area and third Field relaxation region made from a small region of an impurity concentration which is determined by the dose of the implanted region 22 (the electric field relaxation region 30E)
Electric field relaxation region having an impurity concentration determined by the dose amount of the first implantation region 12 Electric field relaxation region having an impurity concentration determined by the dose amount of the second implantation region 13 Impurity concentration determined by the dose amount of the third implantation region 22 Electric field relaxation region (electric field relaxation region 30F)
An electric field relaxation region having an impurity concentration determined by the combined dose amount of the first implantation region 12 and the dose amount of the second implantation region 13A dose amount of the first implantation region 12 and the third implantation region Electric field relaxation region having an impurity concentration determined by the combined dose amount of 22 and an electric field having an impurity concentration determined by the combined dose amount of the second implanted region 13 and the dose amount of the second implanted region 13 Relaxation region / electric field relaxation region having an impurity concentration determined by the combined dose of the first implantation region 12, the second implantation region 13, and the third implantation region 22.
　以上の異なる１９種類の電界緩和領域のうちから適宜２種類以上の電界緩和領域を選択し終端領域を形成することで、印加電圧の増加につれて不純物濃度の小さな領域から順に電界緩和領域が電位を分担する。これにより、終端領域の外周に向かって効果的に電界集中を緩和されるため、高耐圧の半導体装置を得ることができる。 By appropriately selecting two or more types of electric field relaxation regions from the above 19 different types of electric field relaxation regions and forming termination regions, the electric field relaxation regions share the potential in order from the region with the lower impurity concentration as the applied voltage increases. To do. Thereby, since the electric field concentration is effectively reduced toward the outer periphery of the termination region, a high breakdown voltage semiconductor device can be obtained.
　図２７において、第一の注入領域１２、第二の注入領域１３、及び第三の注入領域２２と各電界緩和領域におけるドーズ量との関係を示す。実施の形態２にかかる半導体装置であるショットキーダイオード１０２は、図２７に示すように、第一の注入領域１２、第二の注入領域１３、及び第三の注入領域２２の組み合わせによって、上記１９種類の電界緩和領域から選択された６つの電界緩和領域３０Ａ～Ｆを備える終端領域６０から形成されている。このような構成によって、終端領域６０の外周側に向かうにつれて不純物濃度が小さくなるように電界緩和領域が形成されているため、印加電圧が増加するにつれて外側の電界緩和領域から順に電位分担が段階的に進み、電界集中を緩和することができる。その結果、高耐圧の半導体装置が得られる。また、実施の形態２では、３回の注入工程から６種類の電界緩和領域を形成することができ、製造工程の増加を抑制しつつ電界緩和領域の階調数を増加させることが可能であり、高耐圧の半導体装置を製造することが可能となる。 27 shows the relationship between the first injection region 12, the second injection region 13, the third injection region 22, and the dose amount in each electric field relaxation region. As shown in FIG. 27, the Schottky diode 102 which is a semiconductor device according to the second embodiment has the above-described 19th combination by combining the first implantation region 12, the second implantation region 13, and the third implantation region 22. The terminal region 60 includes six electric field relaxation regions 30A to 30F selected from the types of electric field relaxation regions. With such a configuration, since the electric field relaxation region is formed so that the impurity concentration decreases toward the outer peripheral side of the termination region 60, the potential sharing is stepwise in order from the outer electric field relaxation region as the applied voltage increases. The electric field concentration can be reduced. As a result, a high breakdown voltage semiconductor device can be obtained. In the second embodiment, six types of electric field relaxation regions can be formed from three implantation steps, and the number of gradations in the electric field relaxation region can be increased while suppressing an increase in manufacturing steps. Thus, it becomes possible to manufacture a semiconductor device with a high breakdown voltage.
　また、各電界緩和領域において、それぞれの注入領域の幅は同一としているが、図２８に示すように、異なる各電界緩和領域における小領域の幅を終端領域の外周側に向かって徐々に変化させることで、より効果的に電界集中を緩和することができ、高耐圧の半導体装置が得られる。 Further, in each electric field relaxation region, the width of each implantation region is the same, but as shown in FIG. 28, the width of the small region in each different electric field relaxation region is gradually changed toward the outer peripheral side of the termination region. Thus, electric field concentration can be more effectively mitigated, and a high breakdown voltage semiconductor device can be obtained.
　また、上述の説明では第一の注入領域１２、第二の注入領域１３、及び第三の注入領域２２の注入深さは同一の深さとしているが、図２９に示すように、各注入領域の注入深さが異なるように形成してもよい。この場合、深く注入された領域では半導体層１へ空乏層がより広がりやすくなり、高耐圧化に有利となる。ただし、イオン注入を行う場合、通常は深さ方向に濃度ピークを持つように不純物が分布し、注入領域表面の不純物濃度はやや薄くなる。金属電極３の端部での破壊を防ぐためには、金属電極３の端部直下においてある程度の表面不純物濃度を確保しておくことが得策であり、図２９に示すように、各注入領域のいずれかの注入深さは浅くしておくと良い。なお、図２９においては、第一の注入領域が最も深く、続いて第二の注入領域１３が深く、第三の注入領域２２が最も浅く図示している。 In the above description, the implantation depths of the first implantation region 12, the second implantation region 13, and the third implantation region 22 are the same depth. However, as shown in FIG. The injection depth may be different. In this case, in the deeply implanted region, the depletion layer is more likely to spread to the semiconductor layer 1, which is advantageous for increasing the breakdown voltage. However, when ion implantation is performed, impurities are usually distributed so as to have a concentration peak in the depth direction, and the impurity concentration on the surface of the implantation region is slightly reduced. In order to prevent breakage at the end of the metal electrode 3, it is advisable to ensure a certain level of surface impurity concentration immediately below the end of the metal electrode 3, and as shown in FIG. It is better to keep the implantation depth shallow. In FIG. 29, the first implantation region is deepest, the second implantation region 13 is deep, and the third implantation region 22 is shallowest.
　また、図３０に示すように、第一の注入領域１２、第二の注入領域１３、及び第三の注入領域２２のいずれかの表面はｎ型半導体となっても良い。図３０においては、第二の注入領域の表面がｎ型半導体となるように図示している。 Further, as shown in FIG. 30, the surface of any of the first implantation region 12, the second implantation region 13, and the third implantation region 22 may be an n-type semiconductor. In FIG. 30, the surface of the second implantation region is illustrated as an n-type semiconductor.
　また、以上の説明では縦型構造のショットキーダイオードを例として挙げていたが、図３１のように、縦型構造のＭＯＳＦＥＴなどのｐベース領域１５を活性領域に持つ半導体装置においては、終端領域の全てにおいて表面がｎ型半導体となっても良い。 In the above description, a vertical structure Schottky diode is taken as an example. However, in a semiconductor device having a p base region 15 such as a vertical structure MOSFET as an active region as shown in FIG. In all of these, the surface may be an n-type semiconductor.
　また、以上では３種類の注入領域、すなわち３回の注入工程から形成される異なる不純物濃度の電界緩和領域について説明したが、４回の注入工程から形成する場合には異なる不純物濃度の電界緩和領域は６５種類存在し、注入工程の数が多くなるほど異なる不純物濃度の電界緩和領域の種類は急激に増やすことができる。 In the above description, three types of implantation regions, that is, electric field relaxation regions having different impurity concentrations formed from three implantation steps have been described. However, when formed from four implantation steps, electric field relaxation regions having different impurity concentrations. There are 65 types, and as the number of implantation steps increases, the types of electric field relaxation regions having different impurity concentrations can be rapidly increased.
　なお、本発明は、発明の範囲内において、各実施の形態を自由に組み合わせることや、各実施の形態を適宜、変形、省略することが可能である。 In the present invention, the embodiments can be freely combined within the scope of the invention, and the embodiments can be appropriately modified or omitted.
　１　半導体層、２　ｐ型ガードリング、３　金属電極、４　第一の電界緩和領域、５　第二の電界緩和領域、６　第一の小領域、７　第二の小領域、８　第三の小領域、９　第四の小領域、１０　接続領域、１１、１１ａ、１１ｂ　注入マスク、１２　第一の注入領域、１３　第二の注入領域、１４　表面保護膜、１５　ｐベース領域、１６　第五の小領域、１７　第三の電界緩和領域、１８　第六の小領域、１９　第四の電界緩和領域、２０　第七の小領域、２１　第五の電界緩和領域、２２　第三の注入領域、２３　ｐ＋コンタクト領域、２４　ｎソース領域、２５　ゲート絶縁膜、２６　ゲート電極、２７　フィールド絶縁膜、２８　層間絶縁膜、２９　ＪＢＳ領域、３０Ａ、３０Ｂ、３０Ｃ、３０Ｄ、３０Ｅ、３０Ｆ　電界緩和領域、５０　活性領域、６０　終端領域、７０、８０　ｎ＋領域、１００、１０２　ショットキーダイオード、１０１　ＭＯＳＦＥＴ。 1 semiconductor layer, 2 p-type guard ring, 3 metal electrode, 4 first electric field relaxation region, 5 second electric field relaxation region, 6 first small region, 7 second small region, 8 third small region , 9 4th small region, 10 connection region, 11, 11a, 11b implantation mask, 12 first implantation region, 13 second implantation region, 14 surface protective film, 15 p base region, 16 fifth small region 17 Third electric field relaxation region 18 Sixth small region 19 Fourth electric field relaxation region 20 Seventh small region 21 Fifth electric field relaxation region 22 Third injection region 23 p + contact region 24 n source region, 25 gate insulating film, 26 gate electrode, 27 field insulating film, 28 interlayer insulating film, 29 JBS region, 30A, 30B, 30C, 30D, 30E, 30F electric field relaxation region , 50 active regions, 60 termination region, 70, 80 n + region, 100,102 Schottky diode, 101 MOSFET.

Claims (12)

  1. 　第一導電型の半導体層と、
    　前記半導体層の表面の一部に形成され、かつ、第二導電型で第一の不純物濃度である第一の小領域と第二導電型で前記第一の不純物濃度よりも低い第二の不純物濃度である第二の小領域とがそれぞれ交互に設けられた第一の電界緩和領域と、
    　前記第一の電界緩和領域の外周側に向かって前記第一の電界緩和領域を囲むように形成され、かつ、第二導電型で前記第一の不純物濃度以上の第三の不純物濃度である複数の第三の小領域と第二導電型で前記第二の不純物濃度よりも低い第四の不純物濃度である複数の第四の小領域とがそれぞれ交互に設けられた第二の電界緩和領域と、
    　を備えたことを特徴とする半導体装置。     A first conductivity type semiconductor layer;
    A first small region formed on a part of the surface of the semiconductor layer and having a second conductivity type and a first impurity concentration; and a second impurity having a second conductivity type and lower than the first impurity concentration. First electric field relaxation regions alternately provided with second small regions of concentration, and
    A plurality of second conductivity types and a third impurity concentration equal to or higher than the first impurity concentration are formed to surround the first electric field relaxation region toward the outer peripheral side of the first electric field relaxation region. A second electric field relaxation region in which a plurality of fourth subregions having a second conductivity type and a fourth impurity concentration lower than the second impurity concentration are alternately provided. ,
    A semiconductor device comprising:
  2. 　前記第三の不純物濃度は、前記第一の不純物濃度であり、
    　前記第一の不純物濃度は、前記第二の不純物濃度と前記第四の不純物濃度の和である、
    　ことを特徴とする請求項１に記載の半導体装置。     The third impurity concentration is the first impurity concentration;
    The first impurity concentration is a sum of the second impurity concentration and the fourth impurity concentration.
    The semiconductor device according to claim 1.
  3. 　前記複数の第一の小領域の幅は外周側に向かうにつれて小さくなる、
    　ことを特徴とする請求項１又は２に記載の半導体装置。     The width of the plurality of first small regions becomes smaller toward the outer peripheral side,
    The semiconductor device according to claim 1, wherein:
  4. 　前記複数の第二の小領域の幅は外周側に向かうにつれて大きくなる、
    　ことを特徴とする請求項１ないし３のいずれか１項に記載の半導体装置。     The width of the plurality of second small regions increases toward the outer peripheral side,
    The semiconductor device according to claim 1, wherein:
  5. 　前記複数の第三の小領域の幅は外周側に向かうにつれて小さくなる、
    　ことを特徴とする請求項１ないし４のいずれか１項に記載の半導体装置。     The width of the plurality of third small regions becomes smaller toward the outer peripheral side,
    The semiconductor device according to claim 1, wherein:
  6. 　前記複数の第四の小領域の幅は外周側に向かうにつれて大きくなる、
    　ことを特徴とする請求項１ないし５のいずれか１項に記載の半導体装置。     The width of the plurality of fourth small regions becomes larger toward the outer peripheral side,
    The semiconductor device according to claim 1, wherein:
  7. 　前記半導体層は炭化珪素半導体である、
    　ことを特徴とする請求項１ないし６のいずれか１項に記載の半導体装置。     The semiconductor layer is a silicon carbide semiconductor;
    The semiconductor device according to claim 1, wherein:
  8. 　半導体基板上に第一導電型の半導体層を形成する工程と、
    　前記半導体層の表面上に第一注入マスクを形成した後に、前記半導体層の複数の離間した第一の小領域を含む領域に、第一のドーズ量となるように第二導電型の不純物を注入する第一の注入工程と、
    　前記半導体層の表面上に第二注入マスクを形成した後に、前記半導体層の前記第一の小領域と少なくとも一部の領域が重なる複数の離間した第二の小領域を含む領域に、第二のドーズ量となるように第二導電型の不純物を注入する第二の注入工程と、
    　を備えたことを特徴とする半導体装置の製造方法。     Forming a first conductivity type semiconductor layer on a semiconductor substrate;
    After forming the first implantation mask on the surface of the semiconductor layer, impurities of the second conductivity type are introduced into the region including the plurality of spaced apart first small regions of the semiconductor layer so that the first dose amount is obtained. A first injection step of injecting;
    After forming a second implantation mask on the surface of the semiconductor layer, a second region is formed in a region including a plurality of spaced apart second subregions where at least a part of the first subregion of the semiconductor layer overlaps. A second implantation step of implanting a second conductivity type impurity so as to have a dose amount of
    A method for manufacturing a semiconductor device, comprising:
  9. 　前記第一の注入工程において、前記第一の小領域の複数の離間した領域の間隔を外周側に向かうにつれて変化させる、
    　ことを特徴とする請求項８に記載の半導体装置の製造方法。     In the first injection step, the interval between the plurality of spaced apart regions of the first small region is changed toward the outer peripheral side,
    The method for manufacturing a semiconductor device according to claim 8.
  10. 　前記第二の注入工程において、前記第二の小領域の複数の離間した領域の間隔を外周側に向かうにつれて変化させる、
    　ことを特徴とする請求項８又は９に記載の半導体装置の製造方法。     In the second injection step, the interval between the plurality of spaced apart regions of the second small region is changed toward the outer peripheral side,
    10. A method for manufacturing a semiconductor device according to claim 8, wherein
  11. 　前記第一の注入工程における前記不純物の注入する注入深さと前記第二の注入工程における前記不純物を注入する注入深さとは異なる、
    ことを特徴とする請求項８ないし１０のいずれか１項に記載の半導体装置の製造方法。     The implantation depth at which the impurity is implanted in the first implantation step is different from the implantation depth at which the impurity is implanted in the second implantation step.
    The method for manufacturing a semiconductor device according to claim 8, wherein the method is a semiconductor device manufacturing method.
  12. 　前記半導体基板及び前記半導体層は炭化珪素半導体から形成する、
    ことを特徴とする請求項９ないし１１のいずれか１項に記載の半導体装置の製造方法。     The semiconductor substrate and the semiconductor layer are formed of a silicon carbide semiconductor;
    The method for manufacturing a semiconductor device according to claim 9, wherein the method is a semiconductor device manufacturing method.
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