JP2018198295A - Semiconductor device manufacturing method - Google Patents

Abstract

To provide a semiconductor device manufacturing method that can prevent a resist pattern from falling.SOLUTION: A semiconductor device manufacturing method comprises: a step of applying resist to a substrate made from silicon carbide; a step of exposing the resist through a mask having a pattern drawn thereon; a step of applying developing solution to the resist and melting a part of the resist; a step of removing the developing solution by rotating the substrate so as to form a resist pattern; and a step of implanting ions into the substrate, using the resist pattern as a mask. The resist pattern has a line pattern and a plurality of falling prevention patterns arranged in an island shape. The falling prevention patterns are arranged at positions where force applied by the developing solution to the line pattern is mitigated when rotating the substrate, and the falling prevention patterns are formed annularly in a plan view.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Patent Document 1 discloses that when the wiring length of the wiring to be measured is 100 μm or more and the exposure amount is excessive, the frequency with which the resist pattern corresponding to the remaining portion of the positive resist collapses or peels off increases. Has been. Patent Document 1 describes that by setting the wiring length of the dummy wiring to 50 μm or less, a large margin can be obtained for resist collapse even if the wiring length of the main wiring is increased to 100 μm or more. The resist collapse can be prevented because, when a positive resist is used, the resist remaining in the corresponding portion between the dummy wirings in the wiring length direction becomes a support in the wiring width direction.

JP 2005-303089 A

  After the resist is exposed to light, a developing solution is applied to the resist to dissolve a part of the resist. Thereafter, the substrate is rotated to remove the developer. At this time, there is a problem that the resist pattern falls when the developer is in contact with the resist pattern. If the resist pattern falls down, for example, processing using the resist pattern as a mask, such as ion implantation, cannot be performed.

  A thin, thick, and long line resist pattern is particularly prone to falling because it receives a large force from the developer. Thin, thick, and long line resist patterns are required in various semiconductor device manufacturing processes. For example, when JTE (Junction Termination Extension) and FLR (Field Limiting Ring) are formed as a terminal structure of a power device made of silicon carbide, a thin, thick, long line resist pattern is required.

  JTE and FLR are manufactured by implanting impurities into necessary regions by ion implantation using a resist as a mask. In the FLR, it is necessary to provide an impurity implantation region with a narrow interval. Since impurities implanted into silicon carbide hardly thermally diffuse, a narrow resist pattern is required to obtain a narrow unimplanted region. Furthermore, in order to deeply implant impurities into silicon carbide, a thick resist pattern that can withstand high energy implantation is required. Furthermore, when the chip size of the power device is increased in order to pass a large current, a long resist pattern is required to form the FLR. In this case, a thin, thick and long line resist pattern is required. However, in order to prevent the resist pattern from falling, there is a problem that a thin, thick and long line-shaped resist pattern cannot be formed in design.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent a resist pattern from falling down.

  A method of manufacturing a semiconductor device according to the present invention includes a step of applying a resist to a substrate made of silicon carbide, a step of exposing the resist through a mask on which a pattern is drawn, and applying a developer to the resist. A step of dissolving a part of the resist, a step of rotating the substrate and removing the developer to form a resist pattern, a step of ion-implanting the substrate using the resist pattern as a mask, The resist pattern has a line pattern and a plurality of fall prevention patterns provided in an island shape, and the fall prevention pattern has a force exerted on the line pattern by the developer when the substrate is rotated. The fall prevention pattern is formed in an annular shape in plan view.

  Another method of manufacturing a semiconductor device according to the present invention includes a step of applying a resist to a substrate made of silicon carbide, a step of exposing the resist through a mask on which a pattern is drawn, and a developer on the resist. The step of applying and dissolving a part of the resist, and rotating the substrate to remove the developer, have a line pattern and a plurality of fall prevention patterns provided in an island shape. The prevention pattern includes a step of forming a resist pattern provided at a position that relaxes the force exerted on the line pattern by the developer when the substrate is rotated, and a step of ion-implanting the substrate using the resist pattern as a mask. Removing the resist pattern, and exposing the part of the unimplanted region where the ion implantation is not performed due to the falling prevention pattern of the substrate. Wherein the step but to form additional injection resist pattern formed, a step of ion implantation into the substrate of the additional injection resist pattern as a mask, further comprising a.

  Other features of the present invention will become apparent below.

  According to the present invention, it is possible to prevent the line-shaped resist pattern from falling by providing the falling prevention pattern.

It is a top view of a semiconductor device. It is sectional drawing of the semiconductor device in a manufacture process. It is sectional drawing, such as a mask used at an exposure process. It is a top view of a mask. It is sectional drawing of a resist pattern. It is a figure which shows rotation of the board | substrate for removing a developing solution. It is a figure which shows the advancing direction of a developing solution. It is sectional drawing of the resist pattern after removing a developing solution. It is sectional drawing of the semiconductor device in which the impurity was inject | poured by the ion implantation process. It is sectional drawing of the semiconductor device after removing a resist pattern. It is a figure explaining the process until SBD is formed. It is sectional drawing of the board | substrate etc. after the ion implantation which concerns on Embodiment 2. FIG. It is sectional drawing of the board | substrate after ion implantation. FIG. 6 is a cross-sectional view of a termination structure manufactured by a method for manufacturing a semiconductor device according to a second embodiment. 7 is a plan view of a resist pattern according to Embodiment 3. FIG. 6 is a plan view of a resist pattern according to Embodiment 4. FIG. FIG. 10 is a diagram illustrating a developer discharging method according to a fifth embodiment. It is sectional drawing of the fall prevention pattern which concerns on a modification. It is a figure which shows the fall prevention pattern etc. which concern on Embodiment 6. FIG. It is a figure which shows the JTE dose amount dependence of the proof pressure of a semiconductor device. It is a figure which shows distribution of the electric field strength in a termination | terminus area | region. It is a figure which shows the resist pattern which concerns on Embodiment 7. FIG. It is sectional drawing of the semiconductor device after removing a resist pattern. It is a figure which shows the resist pattern for additional injection | pouring. It is a figure which shows that an unimplanted area | region shrinks. It is a figure which shows the fall prevention pattern without a hole. It is a figure which shows the fall prevention pattern without a hole. It is a figure which shows the fall prevention pattern without a hole. FIG. 10 is a diagram illustrating an impurity distribution in an eighth embodiment.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view of the semiconductor device. This semiconductor device includes a cell region 12 formed in the center and a termination region 14 surrounding the cell region 12. For example, an IGBT (Insulated Gate Bipolar Transistor) is formed in the cell region 12 in order to pass a large current. Termination region 14 is provided to alleviate the electric field inside and on the surface of the semiconductor device. A plurality of such semiconductor devices are formed on a substrate such as a semiconductor wafer. A broken line 16 surrounds a region including the boundary between the cell region 12 and the termination region 14. The manufacturing method of the semiconductor device according to the first embodiment mainly relates to the formation of the termination region 14.

  FIG. 2 is a cross-sectional view of the portion surrounded by the broken line 16 in FIG. 1 in the manufacturing process. As shown in FIG. 2, a resist 22 is applied to the substrate 20. The material of the substrate 20 is silicon carbide. For example, the substrate is rotated by a known coater, and a uniform resist 22 is formed on the substrate 20 by centrifugal force.

  Next, the process proceeds to the exposure process. FIG. 3 is a cross-sectional view of a mask or the like used in the exposure process. A mask 24 on which a pattern is drawn is provided above the resist 22. In this state, the resist 22 is exposed through the mask 24. Specifically, for example, irradiation with short ultraviolet rays having a short wavelength is performed, and the pattern of the mask 24 is transferred by changing only the portion of the resist 22 that has been exposed to light. Although the positive resist 22 is employed in the first embodiment, a negative resist may be used.

  FIG. 4 is a plan view of the mask 24. The mask 24 is provided with a line portion 24A, a fall prevention portion 24B, and a cover portion 24C. The line portion 24A is an elongated portion having a width w1. The line portion 24A can be the narrowest portion of the entire mask 24. A plurality of line portions 24A are arranged in parallel. The intervals s2, s3, s4 of the plurality of line portions 24A have the same value.

  A plurality of fall prevention parts 24B are provided along the line part 24A. The fall prevention part 24B has an annular shape. There is a hole in the center of the fall prevention portion 24B. The cover portion 24C is a portion immediately above the cell region. The shortest distance s1 from the line part 24A to the cover part 24C is larger than the intervals s2, s3, s4 of the plurality of line parts 24A.

  Next, the process proceeds to the development process. In this step, a developing solution is applied to the resist 22 to dissolve a part of the resist 22. Specifically, the portion of the resist 22 that has been exposed to light is dissolved with a developer. The resist 22 that remains without melting constitutes a resist pattern. Then, the resist pattern is left on the substrate 20 by rotating the substrate 20 and removing the developer.

  FIG. 5 is a cross-sectional view of a resist pattern. The resist pattern includes a line pattern 22A that was not exposed to light by the line portion 24A, a fall prevention pattern 22B that was not exposed to light by the fall prevention portion 24B, and a cover pattern 22C that was not exposed to light by the cover portion 24C. . The shape of the line pattern 22A matches the shape of the line portion 24A. Therefore, a plurality of line patterns 22A are formed. The line pattern 22A is provided in an annular shape so as to surround the fall prevention pattern 22B and the cover pattern 22C. The shape of the fall prevention pattern 22B matches the shape of the fall prevention portion 24B. Therefore, the fall prevention pattern 22B has an annular shape in plan view. The shape of the cover pattern 22C matches the shape of the cover portion 24C.

  In order to withstand high energy injection, the thickness of the line pattern 22A is preferably 2.0 μm or more, for example. The width of the line pattern 22A is preferably as small as 0.7 μm or less, for example. Such a line pattern 22A having a small width is the smallest pattern among the resist patterns. The aspect ratio of the line pattern 22A is 2.86 or more. In order to enlarge the area of the cell region 12 to some extent, the length of the linear portion of the line pattern 22A is preferably set to 2.0 mm or more.

  FIG. 6 is a diagram showing the rotation of the substrate 20 for removing the developer 30. When the substrate 20 is rotated in the direction of the dashed arrow, the developer receives a force in a direction away from the center of the substrate 20. The arrows in FIG. 5 indicate the direction in which the developer 30 advances as the substrate 20 rotates. Since the line pattern 22A and the cover pattern 22C are widely open, the amount of the developer in this region is large. The developer 30 in this region moves away from the cover pattern 22C and proceeds in the direction of the fall prevention pattern 22B and the line pattern 22A. At this time, the developing solution 30 strikes the line pattern 22A after the momentum is weakened directly or indirectly by the fall prevention pattern 22B.

  FIG. 7 is a diagram illustrating the traveling direction of the developer 30. The arrow indicates the flow direction of the developer 30. The traveling direction of the developer 30 toward the line pattern 22A varies depending on the fall prevention pattern 22B. The developer 30 collides between the fall prevention patterns 22B, and the momentum is weakened. The fall prevention pattern 22B weakens the flow of the developer 30 like a tetrapot on a breakwater. Therefore, the force exerted from the developer 30 to the line pattern 22A is weakened. Therefore, it is possible to prevent the line pattern 22A from falling down due to the developer 30.

  Thereafter, the developer 30 is completely removed by drying the substrate as necessary. FIG. 8 is a cross-sectional view of the resist pattern after the developer 30 is removed. Since the fall prevention pattern 22B has the same shape as the fall prevention part 24B in FIG. 4, it is circular in plan view. The overall width w2 of the fall prevention pattern 22B is preferably larger than the width w1 of the line pattern. By doing so, the falling prevention pattern 22B can be prevented from falling before the line pattern 22A by the developer 30.

  There is a cover pattern 22C that covers the cell region on the side opposite to the line pattern 22A of the fall prevention pattern 22B. As described above, the shortest distance s1 from the line pattern 22A to the cover pattern 22C is larger than the intervals s2, s3, and s4 of the plurality of line patterns 22A. Therefore, the line pattern 22A is concentrated in a portion away from the cover pattern 22C.

  The fall prevention pattern 22B is preferably provided closer to the line pattern 22A than the cover pattern 22C. By doing so, it can be prevented to some extent that the developer 30 accelerated by the rotation of the substrate 20 directly hits the line pattern 22A.

  Next, the process proceeds to the ion implantation process. FIG. 9 is a cross-sectional view of a semiconductor device into which impurities are implanted in the ion implantation process. In this step, ions are implanted into the substrate 20 using the resist pattern as a mask. FRL 32 (Field Limiting Ring) is formed by ion-implanting into substrate 20 using a plurality of line patterns 22A as a mask, and JTE 34 (Junction Termination Extension) is formed by ion-implanting between cover pattern 22C and line pattern 22A. The If the substrate 20 is n-type, the implanted impurity is p-type, and if the substrate 20 is p-type, the implanted impurity is n-type.

  By the way, the electric field strength increases to some extent at the boundary between FLR 32 and JTE 34. If the uninjected region due to the fall prevention pattern 22B is large, the electric field strength of the uninjected region may be larger than the boundary between the FLR 32 and the JTE 34. Therefore, the non-implanted region by the fall prevention pattern 22B should be small. In order to reduce the non-implanted region due to the fall prevention pattern 22B, the width w3 of the fall prevention pattern 22B is preferably set to be equal to or less than the width w1 of the line pattern 22A. By doing so, the uninjected region can be made smaller and the electric field strength applied to the unimplanted region can be reduced. Specifically, the electric field strength in the unimplanted region can be made smaller than the electric field strength at the boundary between FLR 32 and JTE 34. In particular, it is preferable to reduce the length in the direction perpendicular to the longitudinal direction of the line pattern 22A in the unimplanted region.

  By making the fall prevention pattern 22B into an annular shape with holes, the uninjected region can be made smaller than when there is no hole. In particular, in silicon carbide, the implanted impurities hardly thermally diffuse, so the approximate range of the implanted region is determined by the shape of the resist pattern. Therefore, by providing a hole in the center of the fall prevention pattern 22B, the width of the uninjected region can be reduced, and the electric field strength applied to the uninjected region can be reduced.

  Next, the resist pattern is removed. FIG. 10 is a cross-sectional view of the semiconductor device after the resist pattern is removed. After the termination structure is formed in this way, a Schottky barrier diode (SBD) is finally completed. FIG. 11 is a diagram illustrating a process until an SBD is formed. The upper part shows a cross-sectional view of the semiconductor device at the stage of forming a resist pattern. The middle section shows a cross-sectional view of a semiconductor device in which ions are implanted using a resist pattern as a mask. The lower part shows a cross-sectional view of the semiconductor device in which the SBD is formed.

A high concentration region 40 having a higher impurity concentration than JTE 34 is formed in JTE 34. If JTE34 is a p layer, the high concentration region 40 is a p ⁺ layer. An insulating film 42 is formed on the FLR 32 and the JTE 34. The insulating film 42 exposes part of the JTE 34. As a result, the JTE 34 can be connected to the surface electrode 46 via the Schottky electrode 44. A protective film 48 is formed on the uppermost layer of the region where the FLLR 42 is present and the region where the JTE 34 is present.

  By the way, unless the lateral spread of the impurity during ion implantation is taken into consideration, the impurity is not implanted immediately below the fall prevention pattern 22B. If a fall prevention pattern that completely surrounds the cover pattern 22C is formed, the JTE 34 is divided. In other words, the impurity between the fall prevention pattern and the line pattern functions as a part of the FLR. In this case, since the depletion layer extends from directly under the fall prevention pattern to the JTE and reaches the high concentration region 40 formed in a part of the JTE 34, the voltage applied to the JTE side increases, and the JTE electric field relaxation region and the JTE contact region The electric field strength increases at the boundary. In this case, the withstand voltage decreases.

  In the first embodiment, a plurality of fall prevention patterns 22B are formed in an island shape so that such a problem does not occur. Therefore, the JTE 34 is not divided by the fall prevention pattern 22B, and the potential in the JTE 34 can be stabilized.

  In the method of manufacturing the semiconductor device according to the first embodiment, since the fall prevention pattern 22B is provided, the thin, thick and long line pattern 22A required for the manufacture of the FLR structure can be prevented from being collapsed by the developer 30. Moreover, since a plurality of fall prevention patterns 22B are provided in an island shape, the JTE is not divided. Moreover, since the fall prevention pattern 22B is formed in an annular shape, it has a through hole in the center. Since ions can be implanted into the substrate 20 through the through hole, the unimplanted region due to the provision of the fall prevention pattern 22B can be reduced.

  Therefore, the manufacturing method of the semiconductor device according to the first embodiment requires a resist pattern that is thin and has a long width to withstand high energy ion implantation, such as FLR that relaxes the electric field of the power device. It is particularly suitable for a method for manufacturing a silicon carbide semiconductor device.

  However, the method for manufacturing a semiconductor device according to the first embodiment of the present invention can be modified in various ways within a range not losing its characteristics. For example, although the first embodiment has described the configuration having the FLR 32 and the JTE 34 in the termination structure, the above technique can be applied to a process for forming another structure. That is, the above-described technique can be applied to any process in which there is a demand to reduce the influence on the electrical characteristics by the suppressing means while suppressing the pattern collapse due to the developer 30. Further, the fall prevention pattern 22B may be provided anywhere as long as it is provided at a position that alleviates the force exerted by the developer 3030 on the line pattern 22A when the substrate 20 is rotated. The modifications mentioned in the first embodiment can be applied to a method for manufacturing a semiconductor device according to the following embodiments. It should be noted that the semiconductor device manufacturing method according to the embodiment has much in common with the first embodiment, and will be described with a focus on differences from the first embodiment.

Embodiment 2. FIG.
FIG. 12 is a cross-sectional view of the substrate and the like after ion implantation according to the second embodiment. FIG. 12 shows one fall prevention pattern 22B. Impurities 34a are implanted into the substrate 20 through the openings 22b of the fall prevention pattern 22B. Impurities 34b are implanted into the substrate 20 through the outer side 23 of the fall prevention pattern 22B. The impurities 34a and 34b are connected under the falling prevention pattern 22B. In other words, the impurities 34a and 34b implanted to the left and right of the fall prevention pattern 22B by ion implantation are connected directly under the fall prevention pattern 22B.

  The lateral spreading distance of the impurity during ion implantation is x4. The width w3 of the fall prevention pattern 22B according to the second embodiment is 2 × x4 or less. That is, the width w3 is less than or equal to a value obtained by doubling the distance x4. Therefore, the impurities 34a and 34b are connected directly below the fall prevention pattern 22B due to the lateral spread during ion implantation. Thereby, it is possible to suppress an increase in electric field strength due to the non-implanted region immediately below the fall prevention pattern 22B. For example, when ion implantation is performed at least once at 700 keV, the amount of lateral spread of impurities is about 250 nm. In this case, the width w3 of the fall prevention pattern 22B may be 500 nm or less.

  FIG. 13 is a cross-sectional view of the substrate 20 after ion implantation using a resist pattern. Impurities are connected directly under the fall prevention pattern 22B, thereby preventing an uninjected region from occurring in the JTE 34. FIG. 14 is a cross-sectional view of a termination structure manufactured by the method for manufacturing a semiconductor device according to the second embodiment. By realizing the JTE 34 having no uninjected region, it is possible to suppress the influence on the characteristics of the Schottky barrier diode due to the provision of the fall prevention pattern 22AB.

Embodiment 3 FIG.
FIG. 15 is a plan view of a resist pattern according to the third embodiment. The fall prevention pattern 22B has a parallel portion 22c parallel to the line pattern 22A on the opposite side to the line pattern 22A. The fall prevention pattern 22B has an annular shape having an opening in the center. The fall prevention pattern 22B is a quadrangle having an opening in the center in plan view. The overall width w2 of the fall prevention pattern 22B is preferably larger than the width w1 of the line pattern 22A.

  When the developing solution 30 is removed by rotating the substrate 20, the developing solution 30 collides with the parallel portion 22c, and the momentum of the developing solution 30 is weakened. Therefore, the force exerted by the developer 30 on the line pattern 22A can be weakened.

Embodiment 4 FIG.
FIG. 16 is a plan view of a resist pattern according to the fourth embodiment. The plurality of fall prevention patterns 22B are provided in a staggered pattern. As a result, there is a fall prevention pattern 22B in the vertical direction of the line pattern 22A at any position of the line pattern 22A. In other words, if the line pattern 22A is traced in a direction perpendicular to the inside of the chip from an arbitrary position, the line pattern 22A always falls on the fall prevention pattern 22B.

  When the developing solution 30 is removed by rotating the substrate, the developing solution 30 collides with the fall prevention pattern 22B, and the momentum of the developing solution 30 is weakened. By providing the plurality of fall prevention patterns 22B in a staggered manner, the developer 30 hits the fall prevention pattern 22B, so that the developer 30 does not hit the line pattern 22A directly. Therefore, the force exerted by the developer 30 on the line pattern 22A can be weakened.

Embodiment 5. FIG.
FIG. 17 is a diagram illustrating a method for discharging the developing solution 30 according to the fifth embodiment. In the fifth embodiment, the fall prevention pattern 22B is tapered in a direction away from the substrate 20. The fall prevention pattern 22 </ b> B preferably has a tapered shape having side surfaces inclined by 30 ° to 60 ° with respect to the upper surface of the substrate 20. The developer 30 that has advanced in the direction of the line pattern 22A hits the fall prevention pattern 22B and is guided upward, so that the developer 30 can be more easily discharged.

  FIG. 18 is a cross-sectional view of a fall prevention pattern 22B according to a modification. There is no opening in the center of the fall prevention pattern 22B. By making the fall prevention pattern 22B tapered, the force from the developer 30 to the fall prevention pattern can be reduced as compared with the fall prevention pattern having a side surface perpendicular to the upper surface of the substrate 20. Therefore, the width of the fall prevention pattern 22B can be reduced to some extent. If the width of the fall prevention pattern 22B can be reduced, the non-implanted region is also reduced, so that it is not necessary to provide a hole in the fall prevention pattern 22B.

Embodiment 6 FIG.
FIG. 19 is a diagram illustrating a fall prevention pattern 22B and the like according to the sixth embodiment. In the sixth embodiment, the area that the fall prevention pattern 22B occupies in the JTE electric field relaxation region that is the region from the end of the JTE 34 to the end of the high concentration region 40 is 25% or less. FIG. 19 shows that the width of the JTE electric field relaxation region is 20 μm, the diameter of the fall prevention pattern 22B is 3 μm, and the diameter of the opening of the fall prevention pattern 22B is 1 μm. Further, the fall prevention pattern 22B was arranged at a period of 6 μm in a direction parallel to the line pattern 22A. In this case, the area ratio occupied by the fall prevention pattern 22B in the JTE electric field relaxation region is 5.2%.

  FIG. 20 is a diagram illustrating the JTE dose dependency of the breakdown voltage of a 1200 V semiconductor device. It can be seen that the breakdown voltage decreases if the dose amount Nd of JTE34 is too high or too low. FIG. 21 shows the electric field intensity distribution in the termination region. The solid line in the upper graph of FIG. 21 shows the electric field strength distribution when the dose amount of JTE34 is high. If the dose amount becomes too high, the depletion layer is difficult to extend to the JTE electric field relaxation region, and the voltage applied to the FLR region becomes high. As a result, the electric field strength increases at the boundary between the JTE electric field relaxation region and the FLR region, and the breakdown voltage decreases.

  On the other hand, the broken line in the upper graph of FIG. 21 shows the electric field strength distribution when the dose of JTE is low. If the dose amount of JTE34 becomes too low, the depletion layer extends and reaches the high concentration region 40, so that the voltage applied to JTE34 increases. As a result, the electric field strength increases at the boundary between the JTE electric field relaxation region and the JTE contact region, and the breakdown voltage decreases.

As shown in FIG. 20, there is an optimum dose amount of JTE 34 for maintaining the withstand voltage. In this case, the impurity dose of JTE34 is preferably 2.1E13 cm ⁻³ to 2.8E13 cm ⁻³ . Although a 1200 V semiconductor device has been described here, a range in which a withstand voltage of about 1400 V can be provided in order to ensure a margin is shown.

Here, when the 2.8E13cm ^-3 a dose of JTE34, substantial dose if the area fraction of an area of preventing pattern 22B collapse in JTE electric field relaxation region is 25% or less 2.1E13cm ^-3 The above is equivalent. Then, it can be seen from FIG. 20 that if the dose amount is 2.1E13 cm ⁻³ , a good breakdown voltage can be realized. In this case, it is possible to prevent the breakdown voltage from being lowered due to an increase in electric field strength at the boundary between the JTE electric field relaxation region and the JTE contact region due to a decrease in the dose amount in the JTE electric field relaxation region by providing the fall prevention pattern 22B.

Embodiment 7 FIG.
FIG. 22 shows a resist pattern according to the seventh embodiment. A plan view is shown in the upper stage, and a cross-sectional view is shown in the lower stage. The fall prevention pattern 22B has a circular shape in a plan view that does not have an opening. Ions are implanted into the substrate 20 using this resist pattern as a mask. As a result, a relatively large non-implanted region 35 is formed under the fall prevention pattern 22B.

  Next, the resist pattern shown in FIG. 22 is removed. FIG. 23 is a cross-sectional view of the semiconductor device after the resist pattern is removed. A relatively large uninjected region 35 remains in the JTE electric field relaxation region.

  Next, a resist pattern for additional implantation is formed. FIG. 24 is a diagram showing a resist pattern 50 for additional implantation. A plan view is shown in the upper stage, and a cross-sectional view is shown in the lower stage. An opening 50 </ b> A is formed in the additional implantation resist pattern 50. The opening 50 </ b> A exposes a part of the unimplanted region 35 that is not ion-implanted due to the falling prevention pattern of the substrate 20. Ions are implanted into the substrate 20 using the additional implantation resist pattern 50 as a mask. The impurity implanted here is preferably matched with the impurity implanted using the resist pattern as a mask.

  When ions are implanted into the substrate 20 using the additional implantation resist pattern 50 as a mask, an impurity region 56 is formed in the substrate 20. Impurity region 56 is formed in part of unimplanted region 35. The impurity region 56 is smaller than the unimplanted region 35. By reducing the size of the non-implanted region by implanting impurities into part of the non-implanted region 35, the electric field strength applied to the non-implanted region can be reduced.

  FIG. 25 is a diagram showing that the unimplanted region is reduced. It is shown that an unimplanted region 35 is generated by the fall prevention pattern 22B in the upper stage. The lower part shows an impurity region 56 formed by ion implantation into the substrate 20 using the resist pattern 50 for additional implantation as a mask. It is preferable to match the implantation conditions for forming the FLR 32 and the JTE 34 with the implantation conditions for forming the impurity region 56.

  Here, if additional ion implantation is performed on the portion where the JTE 34 is formed due to the misalignment in the photolithography process, a region that is doubly implanted into a part of the substrate 20 is generated. Since the double-implanted portion has a high impurity concentration, the electric field strength increases. In particular, it should be noted that the implanted impurities hardly thermally diffuse in silicon carbide. That is, when impurities are implanted twice in a region of silicon carbide, the impurity concentration in that region does not decrease by diffusion, and the electric field strength in that region becomes very high.

  In order to prevent such double implantation, it is preferable to form the resist pattern 50 for additional implantation so that a distance x5 from the end of the fall prevention pattern 22B to the end of the opening 50A is generated. Ensuring a certain amount of x5 means forming an impurity region 56 smaller than the unimplanted region 35. Thereby, the area | region injected twice can be suppressed. In order to prevent double injection, it is preferable to increase x5 to some extent, but if it is too large, a large uninjected region remains. Therefore, the distance x5 is preferably smaller than the width w1 of the line pattern 22A. As a result, the width of the uninjected region can be made smaller than w1, so that the electric field strength in the uninjected region can be made smaller than the electric field strength at the boundary between FLR 32 and JTE 34.

  As described above, in the method of manufacturing a semiconductor device according to the seventh embodiment, after performing the ion implantation using the resist pattern described in the first embodiment, the portion that has not been implanted by the fall prevention pattern 22B is additionally provided. Ion implantation is performed. Since this additional injection can prevent a large uninjected region from occurring in the JTE 34, the fall prevention pattern 22B may be enlarged to enhance the effect of protecting the line pattern 22A from the collision of the developer 30. For example, by making the width of the fall prevention pattern 22B larger than the width of the line pattern 22A, the effect of preventing the fall of the line pattern by the developer 30 can be enhanced.

  Since additional injection is performed, it is not necessary to provide a hole in the fall prevention pattern 22B. Therefore, for example, as shown in FIGS. 26, 27, and 28, a fall prevention pattern 22B having no holes can be provided. Since the fall prevention pattern without holes is not easily fallen by the developer 30, the line pattern 22A can be reliably protected.

Embodiment 8 FIG.
The semiconductor device manufacturing method according to the eighth embodiment is similar to the semiconductor device manufacturing method according to the seventh embodiment. FIG. 29 is a diagram showing an impurity distribution in the eighth embodiment. The impurity ion-implanted into the substrate 20 using the resist pattern including the fall prevention pattern 22B as a mask and the impurity implanted into the substrate 20 using the additional implantation resist pattern 50 as a mask are connected by lateral expansion by ion implantation. That is, the JTE 34 and the impurity region 56 are connected.

  The lateral spreading distance of the impurity during ion implantation using the resist pattern is set to x6. The lateral spreading distance of the impurity during ion implantation using the additional implantation resist pattern 50 is x7. The distance x8 between the end of the fall prevention pattern 22B according to the eighth embodiment and the end of the additional implantation resist pattern 50 is made smaller than x6 + x7. For this reason, the JTE 34 and the impurity region 56 are connected by lateral expansion during ion implantation. Accordingly, it is possible to suppress an increase in electric field strength in an unimplanted region that is not ion-implanted by the fall prevention pattern 22B and that is not ion-implanted by the additional implantation resist pattern 50. Further, the impurity concentration of the impurity region formed by the lateral expansion is about one digit smaller than the impurity concentration of the ion-implanted portion. Therefore, even if the horizontally expanded regions overlap, the electric field strength does not become as high as when double injection is performed.

  The features of the manufacturing method may be used in combination with the semiconductor device according to each embodiment described so far.

  22 resist, 22A line pattern, 22B fall prevention pattern, 22C cover pattern, 32 FLR, 34 JTE

Claims (16)

Applying a resist to a substrate made of silicon carbide;
Exposing the resist through a mask having a pattern drawn thereon;
Applying a developer to the resist to dissolve a part of the resist;
Forming a resist pattern by rotating the substrate and removing the developer; and
Ion implantation into the substrate using the resist pattern as a mask,
The resist pattern has a line pattern and a plurality of fall prevention patterns provided in an island shape,
The fall prevention pattern is provided at a position for relaxing the force exerted on the line pattern by the developer when the substrate is rotated,
The method of manufacturing a semiconductor device, wherein the fall prevention pattern is formed in an annular shape in plan view.   The method of manufacturing a semiconductor device according to claim 1, wherein a width of the fall prevention pattern is equal to or less than a width of the line pattern.   3. The method of manufacturing a semiconductor device according to claim 1, wherein impurities implanted to the left and right of the fall prevention pattern by the ion implantation are connected immediately below the fall prevention pattern. Applying a resist to a substrate made of silicon carbide;
Exposing the resist through a mask having a pattern drawn thereon;
Applying a developer to the resist to dissolve a part of the resist;
By rotating the substrate to remove the developer, the developer has a line pattern and a plurality of fall prevention patterns provided in an island shape, and the fall prevention pattern is rotated when the substrate is rotated. Forming a resist pattern provided at a position to relieve the force exerted on the line pattern;
Ion implantation into the substrate using the resist pattern as a mask;
Removing the resist pattern;
Forming a resist pattern for additional implantation in which an opening exposing a portion of the unimplanted region where the ion implantation is not performed because the collapse prevention pattern is present in the substrate;
And a step of ion-implanting the substrate using the additional implantation resist pattern as a mask.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a distance from an end of the fall prevention pattern to an end of the opening is smaller than a width of the line pattern.   6. The impurity ion-implanted into the substrate using the resist pattern as a mask and the impurity implanted into the substrate using the additional implantation resist pattern as a mask are connected by lateral expansion by ion implantation. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The method of manufacturing a semiconductor device according to claim 1, wherein the fall prevention pattern is circular in a plan view, and a diameter of the fall prevention pattern is larger than a width of the line pattern.   The method for manufacturing a semiconductor device according to claim 1, wherein the fall prevention pattern has a parallel portion parallel to the line pattern on the opposite side to the line pattern.   The plurality of fall prevention patterns are provided in a zigzag pattern, and the fall prevention pattern is provided in any direction of the line pattern in a direction perpendicular to the line pattern. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The method for manufacturing a semiconductor device according to claim 1, wherein the fall prevention pattern is tapered in a direction away from the substrate. The resist pattern includes a cover pattern that covers a cell region on the side opposite to the line pattern of the fall prevention pattern,
A plurality of the line patterns are formed,
The method for manufacturing a semiconductor device according to claim 1, wherein a shortest distance from the line pattern to the cover pattern is larger than an interval between the plurality of line patterns.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the fall prevention pattern is provided closer to the line pattern than the cover pattern. The line pattern is provided in an annular shape so as to surround the fall prevention pattern and the cover pattern,
The method of manufacturing a semiconductor device according to claim 11, wherein an overall width of the fall prevention pattern is larger than a width of the line pattern.   The method for manufacturing a semiconductor device according to claim 1, wherein the line pattern is a pattern having the smallest width among the resist patterns.   FRL (Field Limiting Ring) is formed by ion-implanting the substrate using the plurality of line patterns as a mask, and JTE (Junction Termination Extension) is formed by ion-implanting between the cover pattern and the line pattern. The method for manufacturing a semiconductor device according to claim 11, wherein:   A part of the region where the JTE is formed has a high concentration region having an impurity concentration higher than that of the JTE, and the area occupied by the fall prevention pattern in the region from the end of the JTE to the end of the high concentration region is 16. The method of manufacturing a semiconductor device according to claim 15, wherein the manufacturing method is 25% or less.

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