WO2014042198A1 - Light-emitting diode and method for producing same - Google Patents

Light-emitting diode and method for producing same Download PDF

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Publication number
WO2014042198A1
WO2014042198A1 PCT/JP2013/074567 JP2013074567W WO2014042198A1 WO 2014042198 A1 WO2014042198 A1 WO 2014042198A1 JP 2013074567 W JP2013074567 W JP 2013074567W WO 2014042198 A1 WO2014042198 A1 WO 2014042198A1
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layer
light emitting
substrate
emitting diode
light
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PCT/JP2013/074567
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French (fr)
Japanese (ja)
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範行 粟飯原
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昭和電工株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) is used as the material of the well layer 47
  • the Al composition is higher than the material of the barrier layer 48 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y1 ⁇ 1, X1 ⁇ X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ AlGaAs whose band gap energy is larger than X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) can be used.
  • the lower clad layer 41 and the upper clad layer 45 are provided on the lower surface of the lower guide layer 42 and the upper surface of the upper guide layer 44, respectively, as shown in FIG.
  • the material of the lower cladding layer 41 and the upper cladding layer 45 is preferably AlGaAs or AlGaInP.
  • AlGaInP is used as the material of the lower clad layer 41 and the upper clad layer 45, it does not contain As that easily causes defects, so that it has high crystallinity and contributes to high output.
  • the lower cladding layer 41 and the upper cladding layer 45 are configured to have different polarities.
  • the carrier concentration and thickness of the lower clad layer 41 and the upper clad layer 45 can be in a known suitable range, and the conditions are preferably optimized so that the luminous efficiency of the active layer 4 is increased.
  • a Ge substrate, a metal substrate, a Si substrate, a GaAs substrate, a GaP substrate, or the like can be used.
  • a Si substrate, a GaAs substrate, a GaP substrate, or the like can be used.
  • substrate is used is demonstrated.
  • Metal substrate When a metal substrate is used as the support substrate 1, a structure in which a plurality of metal layers (metal plates) are stacked can be employed. In the case of a structure in which a plurality of metal layers (metal plates) are laminated, it is preferable that two types of metal layers are alternately laminated, and in particular, these two types of metal layers (for example, the first metal layer).
  • the number of layers of the second metal layer is preferably an odd number in total. For example, when the two types of metal layers are the first metal layer 61b and the second metal layer 61a and the number of layers is three, the structure is as shown in FIG.
  • any one of a Si substrate, a GaAs substrate, and a GaP substrate can be used as the support substrate 1 in the present embodiment.
  • a Si substrate for example, a layer made of Ti / Au / In is arranged on the surface of the silicon substrate on the metal reflective layer side, and a layer made of Ti / Au is further arranged on the back surface of the silicon substrate. Can be applied.
  • the diffusion prevention layer 11 can suppress the metal contained in the bonding layer 10 and the support substrate 1 from diffusing and reacting with the metal reflection layer 2.
  • a material of the diffusion preventing layer 11 nickel, titanium, platinum, chromium, tantalum, tungsten, molybdenum, or the like can be used.
  • the diffusion prevention layer 11 can improve the performance of the barrier by a combination of two or more kinds of metals, for example, a combination of platinum and titanium. Even if the diffusion preventing layer 11 is not provided, the bonding layer 10 can have the same function as the diffusion preventing layer 11 by adding these materials to the bonding layer 10 described later.
  • a Ge substrate is used as the support substrate 1
  • a layer 52 made of, for example, Au / Pt is formed on the front surface 51A of the Ge substrate 51, and on the back surface of the Ge substrate 51, for example, Then, a layer 53 made of Pt / Au is formed to produce the support substrate 1.
  • the materials of the layer 52 and the layer 53 are not limited to these, and may be selected within a range that does not impair the effects of the present invention.
  • a metal substrate is used as the support substrate 1
  • a structure in which three layers of metals having different thermal expansion coefficients are laminated will be described.
  • a metal substrate is used as the support substrate 1
  • a first metal layer (first metal plate) 61b having a thermal expansion coefficient larger than that of the active layer and a material having a thermal expansion coefficient of the active layer.
  • a smaller second metal layer (second metal plate) 61a is employed and hot pressed to form a metal substrate.
  • first metal layers 61b and one substantially flat plate-like second metal layer 61a are prepared.
  • Cu having a thickness of 10 ⁇ m is used as the first metal layer 61b
  • Mo having a thickness of 75 ⁇ m is used as the second metal layer 61a.
  • the second metal layer 61a is inserted between the two first metal layers 61b, and these are overlapped.
  • the first metal layer 61b is Cu
  • the second metal layer 61a is Mo
  • the three layers of Cu (10 ⁇ m) / Mo (75 ⁇ m) / Cu (10 ⁇ m) are used.
  • Forming a metal substrate for example, the metal substrate has a thermal expansion coefficient of 5.7 ppm / K and a thermal conductivity of 220 W / m ⁇ K.
  • a metal protective film 61c that covers the entire surface of the metal substrate, that is, the upper surface, the lower surface, and the side surfaces is formed.
  • the side surface covered by the metal protective film 61c is the outer peripheral side surface of the metal substrate. Therefore, when the side surface of the metal substrate of each light-emitting diode after singulation is covered with the metal protective film 61c, a step of covering the side surface with the metal protective film 61c is performed separately.
  • FIG. 6 shows a part of the metal substrate that is not on the outer peripheral end side, and the metal protective film on the outer peripheral side surface is not shown in the figure.
  • a known film forming method can be used for the metal protective film 61c, but a plating method capable of forming a film on the entire surface including the side surfaces is most preferable.
  • nickel is then plated with gold, and a metal substrate in which the upper surface, side surfaces, and lower surface of the metal substrate are covered with a nickel film and a gold film (metal protective film) can be produced.
  • the plating material is not particularly limited, and known materials such as copper, silver, nickel, chromium, platinum, and gold can be applied. However, a layer that combines nickel having good adhesion and gold having excellent chemical resistance is optimal.
  • known techniques and chemicals can be used.
  • An electroless plating method that does not require an electrode is simple and desirable.
  • an epitaxial stacked body 30 including the compound semiconductor layer 5 is formed by growing a plurality of epitaxial layers on one surface 21 a of a semiconductor substrate (growth substrate) 21.
  • the semiconductor substrate 21 is a substrate for forming the epitaxial stacked body 30.
  • the semiconductor substrate 21 is a Si-doped n-type GaAs single crystal substrate in which one surface 21a is inclined by 15 ° from the (100) plane.
  • GaAs gallium arsenide
  • a metal organic chemical vapor deposition (MOCVD) method As a method for forming the epitaxial layered structure 30, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or a liquid phase epitaxial (Liquid Phase EpiLex) method is used. Etc. can be used.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • Etc. liquid phase epitaxial
  • an etching stop layer 22b made of Si-doped n-type (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P is formed on the buffer layer 22a.
  • the etching stop layer 22b is a layer for preventing the cladding layer and the light emitting layer from being etched when the semiconductor substrate is removed by etching.
  • the light emitting layer 43 having a 20-pair quantum well structure of P is formed.
  • the light emitting layer 43 can have a multilayer structure (laminated structure) of a well layer 47 and a barrier layer 48 having a barrier layer (also referred to as a barrier layer) 48 at both ends.
  • the material of the well layer 47 includes ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1), (Al X2 Ga 1-X2 ) As (0 ⁇ X2 ⁇ 1) or (In X3 Ga 1-X3 ) As (0 ⁇ X3 ⁇ 1)) can be used.
  • a material of the barrier layer 48 a material suitable for the material of the well layer 47 is preferably selected. In order to prevent the absorption in the barrier layer 48 and increase the light emission efficiency, it is preferable that the composition has a band gap larger than that of the well layer 47.
  • the Mg-doped p-type current diffusion layer 7 is formed on the lower cladding layer 41.
  • An upper guide layer 44 and a lower guide layer 42 may be provided between the upper clad layer 45 and the lower clad layer 41 and the light emitting layer 43, respectively.
  • the metal reflection layer 2 is formed on the Mg-doped p-type current diffusion layer 7.
  • the metal reflective layer 2 composed of one or more of gold, copper, silver, aluminum, Pt, or an alloy thereof is Mg-doped.
  • the semiconductor substrate on which the epitaxial multilayer body 30, the metal reflective layer 2, and the like are formed and the support substrate 1 formed in the support substrate manufacturing process are bonded.
  • a Ge substrate is used as the support substrate 1
  • a layer 52 made of Au / Pt formed on the front surface 51A of the Ge substrate 51 as shown in FIG.
  • the metal reflecting layer 2 having the structure shown in FIG.
  • heating is performed at 320 ° C. and pressurization is performed at 500 g / cm 2
  • the support substrate 1 is bonded to the structure including the epitaxial multilayer as shown in FIG.
  • the metal substrate as shown in FIG.
  • the semiconductor device according to the present embodiment is not limited to the arrangement form of the back electrode 13 as described above.
  • steps for forming the electrode structure as shown in FIGS. 1B and 1D will be described.
  • a p-type electrode (ohmic electrode) 15 is formed on the current diffusion layer (p-type semiconductor layer) 7.
  • a translucent film (SiO 2 film) 14 is formed on the entire surface of the current diffusion layer 7 by using, for example, a CVD method.
  • the material constituting the translucent film 14 may be SiO 2, SiN, SiON, Al 2 O 3, MgF 2, TiO 2, TiN, ZnO, ITO, IZO or the like is used.
  • a plurality of through holes for embedding a conductive member constituting the ohmic electrode 15 are formed in the light-transmitting film 14 by using a photolithography technique and an etching technique. Specifically, a photoresist pattern having holes corresponding to the through holes is formed on the light transmitting film 14, and the light transmitting film 14 corresponding to the through holes is removed using a hydrofluoric acid-based etchant. As a result, a plurality of through holes are formed in the translucent film 14.
  • the metal reflective layer 2 is formed on the ohmic electrode 15 and the light-transmitting film 14, but the semiconductor device as shown in FIGS. 1B and 1D can be manufactured by adopting the steps described above in the subsequent steps. .
  • the light emitting diodes on the wafer are separated.
  • the structure including the support substrate 1 formed in the above steps is cut with a laser, for example, at intervals of 350 ⁇ m to manufacture the light emitting diode 100.
  • the metal protective film is not formed on the side surface of the substrate 1, but the side surface of the cut substrate 1 is formed under the same conditions as the formation conditions of the upper and lower metal protective films.
  • a metal protective film may be formed on the substrate.
  • a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 350 ⁇ m by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer.
  • MOCVD apparatus metal organic chemical vapor deposition apparatus method
  • trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw material for the group III constituent element did.
  • biscyclopentadienyl magnesium bis- (C 5 H 5 ) 2 Mg
  • disilane Si 2 H 6
  • phosphine PH 3
  • arsine AsH 3
  • the buffer layer made of GaAs has a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the etching stop layer had a carrier concentration of 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the contact layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.05 ⁇ m.
  • DBR layer Al0 is that the carrier concentration of about 1 ⁇ 10 18 cm -3, and Al0.9Ga0.1As with a thickness of about 57 nm, the carrier concentration of about 1 ⁇ 10 18 cm -3, a thickness of about 52 nm. 8 pairs of 3Ga0.7As were alternately laminated.
  • the upper cladding layer had a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the well layer is undoped (Al 0.1 Ga 0.9 ) 0.5 In 0.5 P with a thickness of about 5 nm
  • the barrier layer is undoped and has a thickness of about 5 nm (Al 0.5 Ga 0 .5 ) 0.5 In 0.5 P.
  • 20 pairs of well layers and barrier layers were alternately laminated.
  • the lower cladding layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the current spreading layer was formed by laminating Al0.3Ga0.7As with a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 3 ⁇ m.
  • a structure in which a compound semiconductor layer, a reflective layer, and the like are formed on a GaAs substrate and a metal substrate are disposed so as to face each other and are carried into a decompression device.
  • a decompression device In the state heated at 0 degreeC, they were joined by the load of 500 kg weight, and the joining structure was formed.
  • the GaAs substrate which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
  • a vacuum deposition method is used so that the thickness of AuGe and Ni alloy is 0.5 ⁇ m, Pt is 0.2 ⁇ m, and Au is 1 ⁇ m. A film was formed to form a surface electrode.
  • 1.2 ⁇ m of Au and 0.15 ⁇ m of AuBe were sequentially formed by a vacuum deposition method to form a back electrode.
  • a light emitting diode lamp was assembled by mounting the light emitting diode chip of Example 1 manufactured as described above on a mounting substrate.
  • the characteristics of the light emitting diode were evaluated.
  • a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode (light-emitting diode lamp)
  • infrared light having a peak wavelength of 730 nm was emitted.
  • the forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.9 volts.
  • the light emission output when the forward current was 20 mA was 12 mW.
  • Example 2 Next, a light emitting diode of Example 2 will be described.
  • the light-emitting diode of Example 2 is a combination in which the compound semiconductor layer and the metal reflective layer are electrically connected through a through electrode (ohmic electrode). Note that Example 2 is an example of the embodiment shown in FIG. 1D, and the formation of the compound semiconductor layer is the same as Example 1.
  • a p-type electrode (ohmic electrode) was formed on the current diffusion layer. Specifically, a light-transmitting film (SiO 2 film) having a thickness of 0.3 ⁇ m was formed on the entire surface of the current diffusion layer by using, for example, a CVD method.
  • a plurality of through-holes having a diameter of 9 ⁇ m for embedding a conductive member constituting the ohmic electrode was formed in the light-transmitting film by using a photolithography technique and an etching technique.
  • a plurality of cylindrical ohmic electrodes having a height of 0.3 ⁇ m and a diameter of 9 ⁇ m were formed on the current diffusion layer by filling the plurality of through-holes of the light-transmitting film with AuBe alloy by vapor deposition.
  • a metal reflection layer made of an Au film having a thickness of 0.7 ⁇ m was formed by vapor deposition.
  • a diffusion preventing layer made of a Ti film having a thickness of 0.5 ⁇ m was formed on the metal reflective layer by vapor deposition.
  • a bonding layer made of AuGe having a thickness of 1.0 ⁇ m was formed on the diffusion prevention layer by vapor deposition.
  • the support substrate 1 was produced using a Ge substrate.
  • a layer made of Au / Pt was formed to a thickness of 0.5 ⁇ m / 0.1 ⁇ m on the surface of the Ge substrate.
  • a layer 43 made of Pt / Au was formed to a thickness of 0.1 ⁇ m / 0.5 ⁇ m.
  • the structure in which the compound semiconductor layer, the metal reflection layer, and the like are formed on the GaAs substrate and the surface of the support substrate 1 are arranged so as to face each other and are carried into the decompression device. In the state heated at 400 degreeC, they were joined by the load of 500 kg weight, and the joining structure was formed.
  • a film is formed on the surface of the contact layer opposite to the support substrate by vacuum deposition so that the thickness of AuGe and Ni alloy is 0.5 ⁇ m, Pt is 0.2 ⁇ m, and Au is 1.0 ⁇ m.
  • a surface electrode (n-type electrode) was formed.
  • a light emitting diode lamp was assembled by mounting the light emitting diode chip of Example 1 manufactured as described above on a mounting substrate.
  • the characteristics of the light emitting diode were evaluated.
  • a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode (light-emitting diode lamp)
  • infrared light having a peak wavelength of 730 nm was emitted.
  • the forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.9 volts.
  • the light emission output when the forward current was 20 mA was 12 mW.
  • an n-type contact layer made of Si (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P doped with Si is used instead of the DBR layer in the light emitting diode of Example 1 described above.
  • the output was 20% higher than that of the comparative example, and the light output directly above the lamp was 70% higher. This is because in Examples 1 and 2, the light from the light-emitting portion can be efficiently extracted by interference due to resonance between the metal reflection film and the DBR layer, and interference is maximized particularly in the directly upward direction. it is conceivable that.
  • SYMBOLS 1 Support substrate 2 Metal reflecting layer 3 DBR layer 4 Active layer 5 Compound semiconductor layer 6 Light emission part 7 Current diffusion layer 8 Contact layer 10 Bonding layer 11 Diffusion prevention layer 12 Front electrode 13 Back electrode 14 Translucent film 15 Ohmic electrode (through electrode) 21 Semiconductor substrate (Growth substrate) DESCRIPTION OF SYMBOLS 30 Epitaxial laminated body 41 Lower clad layer 42 Lower guide layer 43 Light emitting layer 44 Upper guide layer 45 Upper clad layer 47 Well layer 48 Barrier layer (barrier layer) 100 light emitting diode

Abstract

This light-emitting diode is one obtained by providing the top of a support substrate with a light-emitting section containing, in order, a metal reflective layer and a compound-semiconductor layer which contains, in order, an active layer and a DBR layer, wherein the support substrate and the light-emitting section are joined to one another.

Description

発光ダイオードおよびその製造方法Light emitting diode and manufacturing method thereof
　本発明は、発光ダイオードおよびその製造方法に関する。
　本願は、２０１２年９月１４日に日本に出願された特願２０１２－２０３３９７号と、２０１３年２月２８日に日本に出願された特願２０１３－０３８８５７号とに基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a light emitting diode and a method for manufacturing the same.
This application claims priority based on Japanese Patent Application No. 2012-20397 filed in Japan on September 14, 2012 and Japanese Patent Application No. 2013-0388857 filed in Japan on February 28, 2013. The contents are incorporated here.
　発光層で発生した光を素子上面の一部から取り出す点光源型の発光ダイオードが知られている。この点光源型の発光ダイオードにおいて、発光層における通電領域をその面内の一部に制限するための電流狭窄構造を有するものが知られている（例えば、特許文献１）。電流狭窄構造を有する発光ダイオードでは、発光領域が限定され、その領域の真上に設けられた光射出孔から光を射出させるため、高い光出力が得られると共に射出させた光を光学部品等に効率良く取り込むことが可能である。 A point light source type light emitting diode that extracts light generated in the light emitting layer from a part of the upper surface of the element is known. As this point light source type light emitting diode, one having a current confinement structure for limiting a current-carrying region in a light emitting layer to a part of the surface is known (for example, Patent Document 1). In a light emitting diode having a current confinement structure, a light emitting region is limited, and light is emitted from a light emitting hole provided immediately above the region, so that high light output is obtained and the emitted light is applied to an optical component or the like. It is possible to capture efficiently.
　点光源型の発光ダイオードのうち特に、共振器型発光ダイオード（ＲＣＬＥＤ：Resonant-Cavity Light Emitting Diode）は、２つのミラーからなる共振器内で発生する定在波の腹が共振器内に配置した発光層に位置するように構成される。このような構成を有する共振器型発光ダイオードは、光出射側のミラーの反射率を基板側のミラーの反射率よりも低く設定することによりレーザ発振させないでＬＥＤモードで動作する、高効率の発光素子である（特許文献２，３）。共振器型発光ダイオードは上述したような共振器構造を備えるため、通常の発光ダイオードと比較して、発光スペクトル線幅が狭い、出射光の指向性が高い、自然放出によるキャリア寿命が短いため高速応答が可能である、等の効果を享受できる。そのため、共振器型発光ダイオードは特にセンサなどに適している。 Among the point light source type light emitting diodes, in particular, the resonator type light emitting diode (RCLED: Resonant-Cavity Light Emitting Diode) has antinodes of standing waves generated in the resonator composed of two mirrors arranged in the resonator. It is comprised so that it may be located in a light emitting layer. The resonator type light emitting diode having such a configuration operates in the LED mode without causing laser oscillation by setting the reflectance of the mirror on the light emitting side to be lower than the reflectance of the mirror on the substrate side. Element (Patent Documents 2 and 3). Since the resonator type light emitting diode has the resonator structure as described above, the emission spectral line width is narrower, the directivity of the emitted light is higher, and the carrier lifetime due to spontaneous emission is shorter than that of a normal light emitting diode. It is possible to enjoy effects such as being able to respond. Therefore, the resonator type light emitting diode is particularly suitable for a sensor or the like.
　共振器型発光ダイオードにおいて、基板に平行な方向において発光領域を狭くするために、上部ミラー層及び活性層等をピラー構造とし、そのピラー構造の頂面の光取り出し面に光出射用の開口を有する層を備えた構成が知られている（例えば、特許文献４）。
　図１１は、基板１３１上に、下部ＤＢＲ層１３２と、活性層１３３と、上部ＤＢＲ層１３４と、コンタクト層１３５とを順に備えた従来の共振器型発光ダイオードであって、活性層１３３と、上部ＤＢＲ層１３４と、コンタクト層１３５とをピラー構造１３７とし、ピラー構造１３７及びその周囲を保護膜１３８で被覆し、その保護膜１３８上に電極膜１３９を形成し、ピラー構造１３７の頂面１３７ａ（光取り出し面）において電極膜１３９に光出射用の開口１３９ａを形成した共振器型発光ダイオードを示す。符号１４０は裏面電極である。 In the resonator type light emitting diode, in order to narrow the light emitting region in the direction parallel to the substrate, the upper mirror layer and the active layer have a pillar structure, and an opening for light emission is provided on the light extraction surface on the top surface of the pillar structure. The structure provided with the layer which has is known (for example, patent document 4).
FIG. 11 shows a conventional resonator type light emitting diode having a lower DBR layer 132, an active layer 133, an upper DBR layer 134, and a contact layer 135 in this order on a substrate 131. The upper DBR layer 134 and the contact layer 135 have a pillar structure 137, the pillar structure 137 and its periphery are covered with a protective film 138, an electrode film 139 is formed on the protective film 138, and the top surface 137a of the pillar structure 137 is formed. A resonator type light emitting diode in which an opening 139a for light emission is formed in the electrode film 139 on the (light extraction surface) is shown. Reference numeral 140 denotes a back electrode.
日本国特開２００３－３１８４２号公報Japanese Laid-Open Patent Publication No. 2003-31842 日本国特開２００２－７６４３３号公報Japanese Unexamined Patent Publication No. 2002-76433 日本国特開２００７－２９９９４９号公報Japanese Unexamined Patent Publication No. 2007-299949 日本国特開平９－２８３８６２号公報Japanese Unexamined Patent Publication No. 9-283862
　上記のような共振器型発光ダイオードは上述の通り、指向性は高いが、点光源型であることから点光源部分からしか発光されないため、用途によっては出力が十分ではない場合がある。高指向性を維持しつつ、より高出力を有する発光ダイオードのニーズがある。
　また、共振器型発光ダイオードは、上述したように２つのミラー（図１１においては下部ＤＢＲ層１３２と上部ＤＢＲ層１３４）からなる共振器内で発生する定在波の腹が発光層に位置するように構成されているが、下部ＤＢＲ層１３２での反射が十分でない場合がある。 As described above, the resonator type light emitting diode as described above has high directivity, but since it is a point light source type, it emits light only from the point light source part, and therefore the output may not be sufficient depending on the application. There is a need for light emitting diodes with higher output while maintaining high directivity.
Further, in the resonator type light emitting diode, as described above, the antinodes of standing waves generated in the resonator composed of the two mirrors (the lower DBR layer 132 and the upper DBR layer 134 in FIG. 11) are located in the light emitting layer. However, the reflection at the lower DBR layer 132 may not be sufficient.
　本発明は、上記事情を鑑みてなされたものであり、高指向性及び高出力を有する発光ダイオード、及び、その製造方法を提供することを目的とする。 This invention is made | formed in view of the said situation, and aims at providing the light emitting diode which has high directivity and high output, and its manufacturing method.
　本発明者らは、上記目的を達成するために鋭意研究を重ねた結果、以下に示す本発明を完成させるに至った。 As a result of intensive studies to achieve the above object, the present inventors have completed the present invention shown below.
[１]本発明の一態様に係る発光ダイオードは、支持基板上に、金属反射層と、活性層及びＤＢＲ層を順に含む化合物半導体層とを順に含む発光部を備え、前記支持基板と前記発光部とが接合されてなる。
[２]上記［１］に記載の発光ダイオードでは、前記支持基板は、Ｇｅ基板、金属基板、Ｓｉ基板、ＧａＡｓ基板、ＧａＰ基板、のいずれかを含んでよい。
[３]上記［１］に記載の発光ダイオードでは、前記金属反射層は、金、銅、銀、アルミニウム、Ｐｔ、又はこれらの合金のいずれか一層又は二層以上から構成されてもよい。
[４]上記［１］に記載の発光ダイオードでは、前記金属反射層の前記支持基板側に形成された拡散防止層及び／又は接合層を介して、前記発光部が前記前記支持基板に接合されていてもよい。
[５]上記［１］に記載の発光ダイオードでは、前記金属反射層と前記活性層との間に貫通孔を備えた透光膜が成膜され、前記貫通孔内にオーミック電極が形成されていてもよい。
[６]上記［１］に記載の発光ダイオードでは、前記ＤＢＲ層は、屈折率の異なる２種類の層が交互に３～１０対積層されて構成されてもよい。
[７]上記［１］に記載の発光ダイオードでは、前記屈折率の異なる２種類の層は、組成の異なる２種類の（ＡｌＸｈＧａ１－Ｘｈ）Ｙ３Ｉｎ１－Ｙ３Ｐ（０＜Ｘｈ≦１、Ｙ３＝０．５）、（ＡｌＸｌＧａ１－Ｘｌ）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘｌ＜１、Ｙ３＝０．５）の対であり、両者のＡｌの組成差ΔＸ＝ｘｈ－ｘｌが０．５より大きいか又は等しくなる組み合わせか、又は、ＧａＩｎＰとＡｌＩｎＰの組み合わせか、又は、組成の異なる２種類のＡｌｘｌＧａ１－ｘｌＡｓ（０．１≦ｘｌ≦１）、ＡｌｘｈＧａ１－ｘｈＡｓ（０．１≦ｘｈ≦１）の対であり、両者の組成差ΔＸ＝ｘｈ－ｘｌが０．５より大きいか等しくなる組み合わせかのいずれかから選択されてもよい。
[８]上記［１］に記載の発光ダイオードでは、前記活性層に含まれる発光層は、（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））、のいずれかから構成されてもよい。 [1] A light-emitting diode according to an aspect of the present invention includes a light-emitting portion including a metal reflective layer and a compound semiconductor layer including an active layer and a DBR layer in order on a support substrate, and the support substrate and the light-emitting element The part is joined.
[2] In the light emitting diode according to [1], the support substrate may include any one of a Ge substrate, a metal substrate, a Si substrate, a GaAs substrate, and a GaP substrate.
[3] In the light emitting diode according to [1], the metal reflective layer may be composed of one or more layers of gold, copper, silver, aluminum, Pt, or an alloy thereof.
[4] In the light emitting diode according to [1], the light emitting unit is bonded to the support substrate via a diffusion prevention layer and / or a bonding layer formed on the support substrate side of the metal reflective layer. It may be.
[5] In the light emitting diode according to [1], a light-transmitting film having a through hole is formed between the metal reflective layer and the active layer, and an ohmic electrode is formed in the through hole. May be.
[6] In the light emitting diode according to [1], the DBR layer may be configured by alternately stacking 3 to 10 pairs of two types of layers having different refractive indexes.
[7] In the light-emitting diode according to [1], the two types of layers having different refractive indexes may be two types of (Al Xh Ga 1-Xh ) Y3 In 1-Y3 P (0 <Xh ≦ 1, Y3 = 0.5), (Al Xl Ga 1-Xl ) Y3 In 1-Y3 P; 0 ≦ Xl <1, Y3 = 0.5), and the difference in Al composition between the two ΔX = xh -Xl is greater than or equal to 0.5, or a combination of GaInP and AlInP, or two types of different Al xl Ga 1-xl As (0.1 ≦ xl ≦ 1), Al xh Ga 1-xh As (0.1 ≦ xh ≦ 1) may be selected from any combination in which the composition difference ΔX = xh−xl of both is greater than or equal to 0.5.
[8] In the light-emitting diode according to [1], the light-emitting layer included in the active layer has ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 ≦ X2 ≦ 1), (In X3 Ga 1-X3 ) As (0 ≦ X3 ≦ 1)).

[９]本発明の一態様に係る発光ダイオードの製造方法は、支持基板上に、金属反射層と、活性層及びＤＢＲ層を順に含む化合物半導体層とを順に含む発光部を備えた発光ダイオードの製造方法であって、成長用基板上に、ＤＢＲ層及び活性層を順に含む化合物半導体層を形成する工程と、前記化合物半導体層上に金属反射層を形成して発光部を形成する工程と、前記発光部と支持基板とを接合する工程と、前記成長用基板を除去する工程と、を有する。
[9] A method for manufacturing a light-emitting diode according to an aspect of the present invention includes a light-emitting diode including a light-emitting portion including a metal reflective layer and a compound semiconductor layer including an active layer and a DBR layer in order on a support substrate. A manufacturing method, comprising: forming a compound semiconductor layer including a DBR layer and an active layer in order on a growth substrate; forming a light emitting portion by forming a metal reflective layer on the compound semiconductor layer; A step of bonding the light emitting portion and the support substrate, and a step of removing the growth substrate.
　本発明の発光ダイオードによれば、ＤＢＲ層と金属反射層とによって共振器型構造を構成する。共振器型構造を備えることにより高指向性を有する。また、ＤＢＲ層とＤＢＲ層とからなる従来の共振器型構造では、反射側のＤＢＲ層の直上の反射率はほぼ１００％とすることもできるが、斜めから入射する光に対する反射率は例えば、３０度を超えると６０％以下の反射率となる。これに対して、金属反射層では、入射角度によらず、９０％以上の反射率を有するものとすることができ、これにより、本発明の発光ダイオードは、ＤＢＲ層とＤＢＲ層とからなる共振器型構造を有する従来の共振器型発光ダイオードよりも高出力となる。なお、本発明の発光ダイオードは、支持基板と化合物半導体層との間に金属反射層が挟まれた構造となっているが、この構造は、化合物半導体層の成長に用いた成長用基板を除去して、支持基板に改めて、その化合物半導体層を含む発光部を貼り付けた構成を採用することにより可能となったものである。
　また、本発明の発光ダイオードによれば、面発光型なので、点発光型の共振器型発光ダイオードよりも高出力である。
　また、本発明の発光ダイオードによれば、面発光型なので、製造の際、点発光型の共振器型発光ダイオードの製造で必要となる穴あけエッチング工程が必要ない。 According to the light emitting diode of the present invention, the resonator structure is constituted by the DBR layer and the metal reflection layer. By having a resonator type structure, it has high directivity. Further, in the conventional resonator structure composed of the DBR layer and the DBR layer, the reflectance directly above the DBR layer on the reflection side can be almost 100%, but the reflectance with respect to light incident from an oblique direction is, for example, When it exceeds 30 degrees, the reflectance is 60% or less. On the other hand, the metal reflective layer can have a reflectance of 90% or more regardless of the incident angle, whereby the light emitting diode of the present invention has a resonance composed of a DBR layer and a DBR layer. The output is higher than that of a conventional resonator type light emitting diode having a ceramic structure. The light emitting diode of the present invention has a structure in which a metal reflective layer is sandwiched between a support substrate and a compound semiconductor layer. This structure removes the growth substrate used for the growth of the compound semiconductor layer. Thus, it is possible to adopt a configuration in which a light emitting portion including the compound semiconductor layer is attached to the support substrate.
Further, according to the light emitting diode of the present invention, since it is a surface light emitting type, it has a higher output than a point light emitting type resonator type light emitting diode.
Further, according to the light emitting diode of the present invention, since it is a surface light emitting type, a hole etching process required for manufacturing a point light emitting type resonator type light emitting diode is not required at the time of manufacturing.
本発明の一実施形態である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態の変形例である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is a modification of one Embodiment of this invention. 本発明の一実施形態の変形例である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is a modification of one Embodiment of this invention. 本発明の一実施形態の変形例である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is a modification of one Embodiment of this invention. 図１Ａ～Ｄ中に示す活性層４を詳細に説明するための拡大断面模式図である。FIG. 2 is an enlarged schematic cross-sectional view for explaining in detail an active layer 4 shown in FIGS. 1A to 1D. 本発明の一実施形態である発光ダイオードにおける支持基板１に、Ｇｅ基板を用いた例を説明するための断面摸式図である。It is a cross-sectional schematic diagram for demonstrating the example which used Ge substrate for the support substrate 1 in the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードにおける支持基板１に、金属基板を用いた例を説明するための断面摸式図である。It is a cross-sectional schematic diagram for demonstrating the example which used the metal substrate for the support substrate 1 in the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である支持基板を、Ｇｅ基板を用いて製造する方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the method to manufacture the support substrate which is one Embodiment of this invention using Ge substrate. 本発明の一実施形態である支持基板を、金属基板を用いて製造する方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the method to manufacture the support substrate which is one Embodiment of this invention using a metal substrate. 本発明の一実施形態である発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode which is one Embodiment of this invention. 従来の発光ダイオードを説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the conventional light emitting diode.
　以下、本発明を適用した実施形態の発光ダイオードおよびその製造方法について、図を用いてその構成を説明する。なお、以下の説明で用いる図面は、特徴をわかりやすくするために便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などは実際と同じであるとは限らない。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。また、本発明に係る発明は、本発明の損なわない範囲で、以下の説明において記載しない層を備えてもよい。
Hereinafter, the structure of a light emitting diode according to an embodiment to which the present invention is applied and a method for manufacturing the same will be described with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. . In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be appropriately changed and implemented without changing the gist thereof. In addition, the invention according to the present invention may include a layer not described in the following description as long as the present invention is not impaired.
［発光ダイオード］
　図１Ａは、本発明を適用した一実施形態の発光ダイオードの一例を示す断面模式図である。
　本実施形態の発光ダイオード１００は、支持基板１上に、金属反射層２と、活性層４及びＤＢＲ層３を順に含む化合物半導体層５とを順に含む発光部６を備え、支持基板１と発光部６とが接合されてなる、ことを特徴とする。
　図１Ａで示す例では、金属反射層２と活性層４とは電流拡散層７を介して接合されている。また、本実施形態においては、化合物半導体層５の支持基板１の反対側には、コンタクト層８を介して表面電極１２が設けられており、支持基板１の金属反射層２の反対側には裏面電極１３設けられている。
　なお、電極の形態は特に限定せず、例えば、金属反射層２と電流拡散層７との間に貫通孔を備えた透光膜が成膜され、当該貫通孔内にオーミック電極が形成された形態でもよい（図１Ｂ、Ｄ参照）。
[Light emitting diode]
FIG. 1A is a schematic cross-sectional view showing an example of a light emitting diode according to an embodiment to which the present invention is applied.
The light emitting diode 100 of this embodiment includes a light emitting unit 6 including a metal reflective layer 2 and a compound semiconductor layer 5 including an active layer 4 and a DBR layer 3 in this order on a support substrate 1, and emits light from the support substrate 1. It is characterized in that the portion 6 is joined.
In the example shown in FIG. 1A, the metal reflection layer 2 and the active layer 4 are joined via a current diffusion layer 7. In the present embodiment, the surface electrode 12 is provided on the opposite side of the compound semiconductor layer 5 to the support substrate 1 via the contact layer 8, and on the opposite side of the metal reflective layer 2 of the support substrate 1. A back electrode 13 is provided.
The form of the electrode is not particularly limited. For example, a translucent film having a through hole is formed between the metal reflection layer 2 and the current diffusion layer 7, and an ohmic electrode is formed in the through hole. A form may be sufficient (refer FIG. 1B and D).
＜金属反射層＞
　金属反射層２は、後述する発光層４３からの光を金属反射層２で正面方向ｆへ反射させて、正面方向ｆでの光取り出し効率を向上させることができ、これにより、発光ダイオードをより高輝度化できる。
　金属反射層２の材料としては、ＡｇＰｄＣｕ合金（ＡＰＣ）、金、銅、銀、アルミニウム、Ｐｔなどの金属、又はこれらの合金等の一層又は二層以上を用いることができる。
<Metal reflective layer>
The metal reflection layer 2 can reflect light from the light emitting layer 43 (described later) in the front direction f by the metal reflection layer 2 and improve the light extraction efficiency in the front direction f. High brightness can be achieved.
As a material of the metal reflective layer 2, one or more layers of metals such as AgPdCu alloy (APC), gold, copper, silver, aluminum, Pt, or alloys thereof can be used.
＜電流拡散層＞
　電流拡散層７は、電流拡散とともに、接合ダメージの活性層への伝播の抑制を目的として配置するものであり、ＧａＰの代わりに発光波長に対し透明なＡｌＧａＩｎＰ、ＡｌＧａＡｓ等を用いることができる。材料としてはＴＭＧａ、ＴＭＡｌ、ＴＭＩｎ、ＰＨ３、ＡｓＨ３を用いることができる。 <Current diffusion layer>
The current diffusion layer 7 is disposed for the purpose of suppressing propagation of junction damage to the active layer along with current diffusion, and AlGaInP, AlGaAs, or the like that is transparent to the emission wavelength can be used instead of GaP. As the material, TMGa, TMAl, TMIn, PH 3 , AsH 3 can be used.
＜活性層４＞
　本実施形態において、化合物半導体層５は、金属反射層２上に、電流拡散層７、活性層４及びＤＢＲ層３を順に含むことを特徴とする。
　活性層４は、図２に示すように、下部クラッド層４１、下部ガイド層４２、発光層４３、上部ガイド層４４、上部クラッド層４５が順次積層されて構成されている。すなわち、活性層４は、放射再結合をもたらすキャリア（担体；ｃａｒｒｉｅｒ）及び発光を発光層４３に「閉じ込める」ために、発光層４３の下側及び上側に対峙して配置した下部クラッド層４１、下部ガイド層４２、及び上部ガイド層４４、上部クラッド層４５を含む、所謂、ダブルヘテロ（英略称：ＤＨ）構造とすることが高強度の発光を得る上で好ましい。 <Active layer 4>
In the present embodiment, the compound semiconductor layer 5 includes a current diffusion layer 7, an active layer 4, and a DBR layer 3 in this order on the metal reflective layer 2.
As shown in FIG. 2, the active layer 4 includes a lower clad layer 41, a lower guide layer 42, a light emitting layer 43, an upper guide layer 44, and an upper clad layer 45 that are sequentially laminated. That is, the active layer 4 includes a lower clad layer 41 disposed facing the lower side and the upper side of the light emitting layer 43 in order to “confine” the light emitting layer 43 with carriers (carriers) and light emission that cause radiative recombination. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 42, the upper guide layer 44, and the upper clad layer 45 is preferable for obtaining high-intensity light emission.
　図２に示すように、発光層４３は、発光ダイオード（ＬＥＤ）の発光波長を制御するため、量子井戸構造を構成することができる。すなわち、発光層４３は、バリア層（障壁層ともいう）４８を両端に有する、井戸層４７とバリア層４８との多層構造（積層構造）とすることができる。 As shown in FIG. 2, the light emitting layer 43 can form a quantum well structure in order to control the light emission wavelength of the light emitting diode (LED). That is, the light emitting layer 43 can have a multilayer structure (laminated structure) of the well layer 47 and the barrier layer 48 having a barrier layer (also referred to as a barrier layer) 48 at both ends.
　発光層４３の層厚は、０．０２～２μｍの範囲であることが好ましい。発光層４３の伝導型は特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The thickness of the light emitting layer 43 is preferably in the range of 0.02 to 2 μm. The conductivity type of the light emitting layer 43 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable to have an undoped crystallinity with a good crystallinity or a carrier concentration of less than 3 × 10 17 cm −3 .
　井戸層４７の材料としては、（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））等を用いることができる。 The material of the well layer 47 includes ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 ≦ X2 ≦ 1), (In X3 Ga 1-X3 ) As (0 ≦ X3 ≦ 1)) and the like can be used.
　井戸層４７の層厚は、３～３０ｎｍの範囲が好適である。より好ましくは、３～１０ｎｍの範囲である。 The layer thickness of the well layer 47 is preferably in the range of 3 to 30 nm. More preferably, it is in the range of 3 to 10 nm.
　バリア層（障壁層）４８の材料としては、井戸層４７の材料に対して適した材料を選択するのが好ましい。バリア層４８での吸収を防止して発光効率を高めるため、井戸層４７よりもバンドギャップが大きくなる組成とするのが好ましい。 As the material of the barrier layer (barrier layer) 48, it is preferable to select a material suitable for the material of the well layer 47. In order to prevent absorption in the barrier layer 48 and increase the light emission efficiency, it is preferable that the composition has a band gap larger than that of the well layer 47.
　例えば、井戸層４７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用いた場合にはバリア層４８の材料としてＡｌＧａＡｓやＡｌＧａＩｎＰが好ましい。バリア層４８の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層４７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、バリア層４８の材料としてよりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）または井戸層（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 47, AlGaAs or AlGaInP is preferable as the material of the barrier layer 48. When AlGaInP is used as the material of the barrier layer 48, since it does not contain As which tends to create defects, it has high crystallinity and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 47, the Al composition is higher than the material of the barrier layer 48 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ AlGaAs whose band gap energy is larger than X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　バリア層４８の層厚は、井戸層４７の層厚と等しいか又は井戸層４７の層厚より厚いのが好ましい。トンネル効果が生じる層厚範囲で十分に厚くすることにより、トンネル効果による井戸層間への広がりが抑制されてキャリアの閉じ込め効果が増大し、電子と正孔の発光再結合確率が大きくなり、発光出力の向上を図ることができる。 The layer thickness of the barrier layer 48 is preferably equal to the layer thickness of the well layer 47 or thicker than the layer thickness of the well layer 47. By sufficiently thickening the layer thickness range in which the tunnel effect occurs, spreading between the well layers due to the tunnel effect is suppressed, the carrier confinement effect is increased, the probability of recombination of electrons and holes is increased, and the light emission output Can be improved.
　井戸層４７とバリア層４８との多層構造において、井戸層４７とバリア層４８とを交互に積層する対の数は特に限定されるものではないが、２対以上４０対以下であることが好ましい。すなわち、活性層４には、井戸層４７が２～４０層含まれていることが好ましい。ここで、活性層４の発光効率が好適となる条件としては、井戸層４７が５層以上であることが好ましい。一方、井戸層４７及びバリア層４８は、キャリア濃度が低いため、多くの対にすると順方向電圧（ＶＦ）が増大してしまう。このため、井戸層４７は４０対以下であることが好ましく、２０対以下であることがより好ましい。 In the multilayer structure of the well layers 47 and the barrier layers 48, the number of pairs in which the well layers 47 and the barrier layers 48 are alternately stacked is not particularly limited, but is preferably 2 or more and 40 or less. . That is, the active layer 4 preferably includes 2 to 40 well layers 47. Here, as a condition that the luminous efficiency of the active layer 4 is suitable, the well layer 47 is preferably five or more layers. On the other hand, since the well layer 47 and the barrier layer 48 have a low carrier concentration, the forward voltage (V F ) increases when the number of pairs is increased. For this reason, the number of well layers 47 is preferably 40 pairs or less, and more preferably 20 pairs or less.
　下部ガイド層４２及び上部ガイド層４４は、図２に示すように、発光層４３の下面及び上面にそれぞれ設けられている。具体的には、発光層４３の下面に下部ガイド層４２が設けられ、発光層４３の上面に上部ガイド層４４が設けられている。 The lower guide layer 42 and the upper guide layer 44 are provided on the lower surface and the upper surface of the light emitting layer 43, respectively, as shown in FIG. Specifically, the lower guide layer 42 is provided on the lower surface of the light emitting layer 43, and the upper guide layer 44 is provided on the upper surface of the light emitting layer 43.
　下部ガイド層４２および上部ガイド層４４の材料としては、公知の化合物半導体材料を用いることができ、発光層４３の材料に対して適した材料を選択するのが好ましい。例えば、ＡｌＧａＡｓ、ＡｌＧａＩｎＰを用いることができる。 As the material of the lower guide layer 42 and the upper guide layer 44, a known compound semiconductor material can be used, and it is preferable to select a material suitable for the material of the light emitting layer 43. For example, AlGaAs or AlGaInP can be used.
　例えば、井戸層４７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用い、バリア層４８の材料としてＡｌＧａＡｓ又はＡｌＧａＩｎＰを用いた場合、下部ガイド層４２および上部ガイド層４４の材料としてはＡｌＧａＡｓ又はＡｌＧａＩｎＰが好ましい。下部ガイド層４２および上部ガイド層４４の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層４７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、下部ガイド層４２及び上部ガイド層４４の材料としては、よりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）、または井戸層４７の材料である（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 47 and AlGaAs or AlGaInP is used as the material of the barrier layer 48, the material of the lower guide layer 42 and the upper guide layer 44 is preferably AlGaAs or AlGaInP. When AlGaInP is used as the material of the lower guide layer 42 and the upper guide layer 44, it does not contain As that easily causes defects, so that the crystallinity is high and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 47, as the material of the lower guide layer 42 and the upper guide layer 44 (Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or the material of the well layer 47 (Al X1 AlGaAs having a larger band gap energy than Ga 1 -X1 ) Y1 In 1 -Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　下部ガイド層４２及び上部ガイド層４４は、夫々、下部クラッド層４１及び上部クラッド層４５と発光層４３との欠陥の伝搬を低減するために設けられている。このため、下部ガイド層４２および上部ガイド層４４の層厚は１０ｎｍ以上が好ましく、２０ｎｍ～１００ｎｍがより好ましい。 The lower guide layer 42 and the upper guide layer 44 are provided to reduce the propagation of defects between the lower cladding layer 41 and the upper cladding layer 45 and the light emitting layer 43, respectively. For this reason, the layer thickness of the lower guide layer 42 and the upper guide layer 44 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
　下部ガイド層４２及び上部ガイド層４４の伝導型は特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The conductivity types of the lower guide layer 42 and the upper guide layer 44 are not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable to have an undoped crystallinity with a good crystallinity or a carrier concentration of less than 3 × 10 17 cm −3 .
　下部クラッド層４１及び上部クラッド層４５は、図２に示すように、下部ガイド層４２の下面及び上部ガイド層４４上面にそれぞれ設けられている。 The lower clad layer 41 and the upper clad layer 45 are provided on the lower surface of the lower guide layer 42 and the upper surface of the upper guide layer 44, respectively, as shown in FIG.
　下部クラッド層４１及び上部クラッド層４５の材料としては、公知の化合物半導体材料を用いることができ、発光層４３の材料に対して適した材料を選択するのが好ましい。例えば、ＡｌＧａＡｓ、ＡｌＧａＩｎＰを用いることができる。 As the material of the lower cladding layer 41 and the upper cladding layer 45, a known compound semiconductor material can be used, and it is preferable to select a material suitable for the material of the light emitting layer 43. For example, AlGaAs or AlGaInP can be used.
　例えば、井戸層４７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用い、バリア層４８の材料としてＡｌＧａＡｓ又はＡｌＧａＩｎＰを用いた場合、下部クラッド層４１及び上部クラッド層４５の材料としてはＡｌＧａＡｓ又はＡｌＧａＩｎＰが好ましい。下部クラッド層４１及び上部クラッド層４５の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層４７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、下部クラッド層４１及び上部クラッド層４５の材料としては、よりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）、または井戸層４７の材料である（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 47 and AlGaAs or AlGaInP is used as the material of the barrier layer 48, the material of the lower cladding layer 41 and the upper cladding layer 45 is preferably AlGaAs or AlGaInP. When AlGaInP is used as the material of the lower clad layer 41 and the upper clad layer 45, it does not contain As that easily causes defects, so that it has high crystallinity and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 47, the material of the lower cladding layer 41 and the upper cladding layer 45 is used. (Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or the material of the well layer 47 (Al X1 AlGaAs having a larger band gap energy than Ga 1 -X1 ) Y1 In 1 -Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　下部クラッド層４１と上部クラッド層４５とは、極性が異なるように構成されている。また、下部クラッド層４１及び上部クラッド層４５のキャリア濃度及び厚さは、公知の好適な範囲を用いることができ、活性層４の発光効率が高まるように条件を最適化することが好ましい。 The lower cladding layer 41 and the upper cladding layer 45 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 41 and the upper clad layer 45 can be in a known suitable range, and the conditions are preferably optimized so that the luminous efficiency of the active layer 4 is increased.
＜ＤＢＲ層＞
　ＤＢＲ（Distributed Bragg Reflector）層３は、λ／（４ｎ）の膜厚で（λ：反射すべき光の真空中での波長、ｎ：層材料の屈折率）、屈折率が異なる２種類の層を交互に積層した多層膜からなるものである。反射率は２種類の屈折率の差が大きいと、比較的少ない層数の多層膜で高反射率が得られる。通常の反射膜のようにある面で反射されるのでなく、多層膜の全体として光の干渉現象に基づき反射が起きることが特徴である。
　ＤＢＲ層３の材料は発光波長に対して透明であることが好ましく、又、ＤＢＲ層３を構成する２種類の材料の屈折率の差が大きくなる組み合わせとなるよう選択されるのが好ましい。 <DBR layer>
DBR (Distributed Bragg Reflector) layer 3 has two types of layers having a film thickness of λ / (4n) (λ: wavelength of light to be reflected in vacuum, n: refractive index of layer material) and different refractive indexes. It consists of a multilayer film in which are stacked alternately. When the difference between the two types of refractive indexes is large, a high reflectance can be obtained with a multilayer film having a relatively small number of layers. Instead of being reflected on a certain surface as in a normal reflective film, the multilayer film as a whole is characterized in that reflection occurs based on the light interference phenomenon.
The material of the DBR layer 3 is preferably transparent to the emission wavelength, and is preferably selected so as to be a combination that increases the difference in refractive index between the two types of materials constituting the DBR layer 3.
　ＤＢＲ層３は、屈折率の異なる２種類の層３ａ、３ｂが交互に３～１０対積層されてなるのが好ましい。積層数が３対以下である場合は反射率が低すぎるために出力の増大に寄与しないため、ＤＢＲ層３は、屈折率の異なる２種類の層３ａ、３ｂが交互に３対以上積層されてなるのが好ましい。また、ＤＢＲ層３は反射方向とは相対する面側より共振した光を取り出す。しかし、積層数を１０対以上にした場合、反射率が増大し過ぎ光の取り出しが低下するため、屈折率の異なる２種類の層３ａ、３ｂを交互に積層する際は、１０対未満とすることが好ましい。
　ＤＢＲ層３を構成する屈折率の異なる２種類の層３ａ、３ｂは、組成の異なる２種類の（ＡｌＸｈＧａ１－Ｘｈ）Ｙ３Ｉｎ１－Ｙ３Ｐ（０＜Ｘｈ≦１、Ｙ３＝０．５）、（ＡｌＸｌＧａ１－Ｘｌ）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘｌ＜１、Ｙ３＝０．５）の対である。また、ＤＢＲ層３を構成する屈折率の異なる２種類の層３ａ、３ｂは、両者のＡｌの組成差ΔＸ＝ｘh－ｘｌが０．５より大きいか又は等しくなる組み合わせか、又は、ＧａＩｎＰとＡｌＩｎＰの組み合わせか、又は、組成の異なる２種類のＡｌｘｌＧａ１－ｘｌＡｓ（０．１≦ｘｌ≦１）、ＡｌｘｈＧａ１－ｘｈＡｓ（０．１≦ｘｈ≦１）の組み合わせであり、これら組み合わせのいずれかから選択されるのが効率よく高い反射率が得られることから望ましい。
　ＤＢＲ層３を構成する屈折率の異なる２種類の層３ａ、３ｂはとしては特に、組成の異なるＡｌＧａＩｎＰの組み合わせは、結晶欠陥を生じやすいＡｓを含まないので好ましく、ＧａＩｎＰとＡｌＩｎＰはその中で屈折率差を最も大きくとれるので、反射層の数を少なくすることができ、組成の切り替えも単純であるので好ましい。また、ＡｌＧａＡｓは、大きな屈折率差をとりやすいという利点がある。 The DBR layer 3 is preferably formed by alternately stacking 3 to 10 pairs of two types of layers 3a and 3b having different refractive indexes. When the number of stacked layers is 3 pairs or less, the reflectivity is too low to contribute to an increase in output. Therefore, the DBR layer 3 is formed by alternately stacking 3 or more pairs of two types of layers 3a and 3b having different refractive indexes. Preferably it is. In addition, the DBR layer 3 takes out the resonated light from the surface side opposite to the reflection direction. However, when the number of stacked layers is 10 pairs or more, the reflectivity increases too much and the light extraction decreases. Therefore, when the two types of layers 3a and 3b having different refractive indexes are alternately stacked, the number is less than 10 pairs. It is preferable.
The two types of layers 3a and 3b having different refractive indexes constituting the DBR layer 3 are composed of two types of (Al Xh Ga 1-Xh ) Y3 In 1-Y3 P (0 <Xh ≦ 1, Y3 = 0. 5), (Al Xl Ga 1-Xl ) Y3 In 1-Y3 P; 0 ≦ Xl <1, Y3 = 0.5). Further, the two types of layers 3a and 3b having different refractive indexes constituting the DBR layer 3 are a combination in which the Al composition difference ΔX = xh−xl is greater than or equal to 0.5, or GaInP and AlInP. Or a combination of two types of Al xl Ga 1-xl As (0.1 ≦ xl ≦ 1) and Al xh Ga 1-xh As (0.1 ≦ xh ≦ 1) having different compositions, It is desirable to select one of these combinations because a high reflectance can be obtained efficiently.
As the two types of layers 3a and 3b having different refractive indexes constituting the DBR layer 3, a combination of AlGaInP having different compositions is preferable because it does not contain As which easily causes crystal defects, and GaInP and AlInP are refracted therein. Since the rate difference can be maximized, the number of reflection layers can be reduced, and the composition switching is also simple, which is preferable. Moreover, AlGaAs has an advantage that a large difference in refractive index is easily obtained.
　本実施形態の発光ダイオード１００は、活性層４を金属反射層２とＤＢＲ層３で挟む構造である。すなわち、活性層４で発光した光が金属反射層２とＤＢＲ層３と間で共振して定在波の腹が発光層に位置させる構成をとることにより、レーザ発振させないで、従来の発光ダイオードよりも指向性が高く、高効率の発光ダイオードとなっている。 The light emitting diode 100 of this embodiment has a structure in which the active layer 4 is sandwiched between the metal reflection layer 2 and the DBR layer 3. That is, the light emitted from the active layer 4 resonates between the metal reflection layer 2 and the DBR layer 3 so that the antinodes of the standing waves are positioned in the light emitting layer. It has higher directivity and is a highly efficient light emitting diode.
＜コンタクト層＞
　コンタクト層８は、表面電極１２との接触抵抗を低下させるために設けられている。コンタクト層８の材料は、発光層４３よりバンドギャップの大きい材料であることが好ましい。また、コンタクト層８のキャリア濃度の下限値は、電極との接触抵抗を低下させるために５×１０１７ｃｍ－３以上であることが好ましく、１×１０１８ｃｍ－３以上がより好ましい。キャリア濃度の上限値は、結晶性の低下が起こりやすくなる２×１０１９ｃｍ－３以下が望ましい。コンタクト層８の厚さは、０．０５μｍ以上が好ましい。コンタクト層８の厚さの上限値は特に限定されないが、エピタキシャル成長に係るコストを適正範囲にするため、１０μｍ以下とすることが望ましい。 <Contact layer>
The contact layer 8 is provided to reduce the contact resistance with the surface electrode 12. The material of the contact layer 8 is preferably a material having a band gap larger than that of the light emitting layer 43. Further, the lower limit value of the carrier concentration of the contact layer 8 is preferably 5 × 10 17 cm −3 or more, more preferably 1 × 10 18 cm −3 or more, in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 19 cm −3 or less at which the crystallinity is likely to decrease. The thickness of the contact layer 8 is preferably 0.05 μm or more. The upper limit value of the thickness of the contact layer 8 is not particularly limited, but is desirably 10 μm or less in order to make the cost for epitaxial growth within an appropriate range.
　ここで、上述してきた金属反射層２及び化合物半導体層５（活性層４、ＤＢＲ層３、コンタクト層８）の構造には、公知の機能層を適時加えることができる。例えば、素子駆動電流の通流する領域を制限するための電流阻止層や電流狭窄層など公知の層構造を設けることができる。 Here, well-known functional layers can be added to the structures of the metal reflection layer 2 and the compound semiconductor layer 5 (the active layer 4, the DBR layer 3, and the contact layer 8) as described above. For example, a known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.
　また、表面電極１２及び裏面電極１３については、それぞれ公知の電極材料を用いることができるが、表面電極１２としては、ＡｕＧｅＮｉを用いることができ、裏面電極１３としてはＡｕＢｅを用いることができる。 Also, for the front electrode 12 and the back electrode 13, known electrode materials can be used, respectively. As the front electrode 12, AuGeNi can be used, and as the back electrode 13, AuBe can be used.
　ここで、上述してきたような図１Ａで示す半導体装置では、支持基板１の金属反射層２の反対側に裏面電極１３を設ける例を示したが、本実施形態における表面電極１２及び裏面電極１３の形態は特に限定しない。電極構造としては例えば、図１Ｂに示すように、金属反射層２と電流拡散層７との間に透光膜１４が成膜され、当該透光膜１４に例えばｐ型のオーミック電極１５が形成された形態でもよい。
　なお、図１Ｂにおいては、図１Ａに示す半導体装置における部材と同一の部材については同一の符号を付して示している。 Here, in the semiconductor device shown in FIG. 1A as described above, an example in which the back electrode 13 is provided on the opposite side of the metal reflective layer 2 of the support substrate 1 has been described. However, the front electrode 12 and the back electrode 13 in the present embodiment. The form of is not particularly limited. As an electrode structure, for example, as shown in FIG. 1B, a light-transmitting film 14 is formed between the metal reflecting layer 2 and the current diffusion layer 7, and a p-type ohmic electrode 15 is formed on the light-transmitting film 14, for example. It may be in the form.
In FIG. 1B, the same members as those in the semiconductor device shown in FIG. 1A are denoted by the same reference numerals.
＜支持基板＞
　本実施形態における支持基板１としては、Ｇｅ基板、金属基板、Ｓｉ基板、ＧａＡｓ基板、ＧａＰ基板等を用いることができる。
　以下、それぞれの基板を用いた場合について説明する。 <Support substrate>
As the support substrate 1 in this embodiment, a Ge substrate, a metal substrate, a Si substrate, a GaAs substrate, a GaP substrate, or the like can be used.
Hereinafter, the case where each board | substrate is used is demonstrated.
「Ｇｅ基板」
　図３は、本実施形態の発光ダイオードにおいて、支持基板１としてＧｅ基板５１とした例の断面模式図である。
　支持基板１としてＧｅ基板５１を用いた場合、金属反射層２側のおもて面にＴｉ／Ａｕ／Ｉｎでなる層５２を配置し、裏面にＴｉ／Ａｕでなる層５３を配置することで、本実施形態に係る支持基板１に適用することができる。
　なお、上記層５２及び層５３の材料としては、他にもＧｅと密着性がよい金属層、例えばＰｔやＡｕを用いることができる。 "Ge substrate"
FIG. 3 is a schematic cross-sectional view of an example in which the Ge substrate 51 is used as the support substrate 1 in the light emitting diode of the present embodiment.
When the Ge substrate 51 is used as the support substrate 1, a layer 52 made of Ti / Au / In is arranged on the front surface of the metal reflective layer 2 side, and a layer 53 made of Ti / Au is arranged on the back surface. The present invention can be applied to the support substrate 1 according to this embodiment.
In addition, as a material of the layer 52 and the layer 53, a metal layer having good adhesion to Ge, for example, Pt or Au can be used.
「金属基板」
　支持基板１として金属基板を用いる場合、複数の金属層（金属板）を積層した構造とすることができる。
　複数の金属層（金属板）を積層した構造とする場合、２種類の金属層が交互に積層されてなるのが好ましく、特に、この２種類の金属層（例えば、これらを第1の金属層、第２の金属層という）の層数は合わせて奇数とするのが好ましい。
　例えば、前記２種類の金属層を第1の金属層６１ｂ、第２の金属層６１ａとし、層数を３層とした場合は、図４に示すような構造となる。 "Metal substrate"
When a metal substrate is used as the support substrate 1, a structure in which a plurality of metal layers (metal plates) are stacked can be employed.
In the case of a structure in which a plurality of metal layers (metal plates) are laminated, it is preferable that two types of metal layers are alternately laminated, and in particular, these two types of metal layers (for example, the first metal layer). The number of layers of the second metal layer is preferably an odd number in total.
For example, when the two types of metal layers are the first metal layer 61b and the second metal layer 61a and the number of layers is three, the structure is as shown in FIG.
　図４に示すように、金属基板を、第２の金属層６１ａを第1の金属層６１ｂで挟んだ構造とした場合、金属基板の反りや割れの観点から、第２の金属層６１ａとして化合物半導体層５（図４には図示せず）より熱膨張係数が小さい材料を用いるときは、第１の金属層６１ｂを化合物半導体層より熱膨張係数が大きい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層５の熱膨張係数に近いものとなるため、化合物半導体層５と金属基板とを接合する際の金属基板の反りや割れを抑制することができ、発光ダイオードの製造歩留まりを向上させることができるからである。同様に、第２の金属層６１ａとして化合物半導体層５より熱膨張係数が大きい材料を用いるときは、第１の金属層６１ｂを化合物半導体層５より熱膨張係数が小さい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層５の熱膨張係数に近いものとなるため、化合物半導体層５と金属基板とを接合する際の金属基板の反りや割れを抑制でき、発光ダイオードの製造歩留まりを向上できるからである。 As shown in FIG. 4, when the metal substrate has a structure in which the second metal layer 61a is sandwiched between the first metal layers 61b, the compound as the second metal layer 61a is used from the viewpoint of warping and cracking of the metal substrate. When a material having a smaller thermal expansion coefficient than that of the semiconductor layer 5 (not shown in FIG. 4) is used, it is preferable to use the first metal layer 61b made of a material having a larger thermal expansion coefficient than the compound semiconductor layer. Since the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer 5, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer 5 and the metal substrate are joined, This is because the manufacturing yield of the light emitting diode can be improved. Similarly, when a material having a larger thermal expansion coefficient than that of the compound semiconductor layer 5 is used as the second metal layer 61 a, the first metal layer 61 b made of a material having a smaller thermal expansion coefficient than that of the compound semiconductor layer 5 is used. Is preferred. Since the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer 5, warpage and cracking of the metal substrate when the compound semiconductor layer 5 and the metal substrate are joined can be suppressed, and the light emitting diode This is because the manufacturing yield can be improved.
　２種類の金属層としては、例えば、銀（熱膨張係数＝１８．９ｐｐｍ／Ｋ）、銅（熱膨張係数＝１６．５ｐｐｍ／Ｋ）、金（熱膨張係数＝１４．２ｐｐｍ／Ｋ）、アルミニウム（熱膨張係数＝２３．１ｐｐｍ／Ｋ）、ニッケル（熱膨張係数＝１３．４ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層と、モリブデン（熱膨張係数＝５．１ｐｐｍ／Ｋ）、タングステン（熱膨張係数＝４．３ｐｐｍ／Ｋ）、クロム（熱膨張係数＝４．９ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層との組み合わせを用いることができる。
　好適な例としては、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板があげられる。上記の観点ではＭｏ／Ｃｕ／Ｍｏの３層からなる金属基板でも同様な効果が得られるが、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板は、機械的強度が高いＭｏを加工しやすいＣｕで挟んだ構成なので、Ｍｏ／Ｃｕ／Ｍｏの３層からなる金属基板よりも切断等の加工が容易であるという利点がある。 Examples of the two metal layers include silver (thermal expansion coefficient = 18.9 ppm / K), copper (thermal expansion coefficient = 16.5 ppm / K), gold (thermal expansion coefficient = 14.2 ppm / K), and aluminum. (Thermal expansion coefficient = 23.1 ppm / K), nickel (thermal expansion coefficient = 13.4 ppm / K) and a metal layer made of any of these alloys, molybdenum (thermal expansion coefficient = 5.1 ppm / K), Combinations of tungsten (thermal expansion coefficient = 4.3 ppm / K), chromium (thermal expansion coefficient = 4.9 ppm / K), and a metal layer made of any of these alloys can be used.
A preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.
　金属基板全体としての熱膨張係数は例えば、Ｃｕ（３０μｍ）／Ｍｏ（２５μｍ）／Ｃｕ（３０μｍ）の３層からなる金属基板では６．１ｐｐｍ／Ｋであり、Ｍｏ（２５μｍ）／Ｃｕ（７０μｍ）／Ｍｏ（２５μｍ）の３層からなる金属基板では５．７ｐｐｍ／Ｋとなる。 The thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm). In the case of a metal substrate composed of three layers of / Mo (25 μm), it is 5.7 ppm / K.
　また、後述する成長用基板に化合物半導体層等を成長させた後に、金属基板を接合してその成長用基板をエッチング液を用いて除去する際に、そのエッチング液による劣化を回避するために、金属基板の上面及び下面を金属保護膜６１ｃで覆うことが好ましい。
　金属保護膜６１ｃの材料としては、密着性に優れるクロム、ニッケル、化学的に安定な白金、又は金の少なくともいずれか一つを含む金属からなるものであることが好ましい。
　金属保護膜６１ｃは密着性がよいニッケルと耐薬品に優れる金を組み合わせた層からなるのが最適である。 In addition, after growing a compound semiconductor layer or the like on a growth substrate described later, when joining the metal substrate and removing the growth substrate using an etching solution, in order to avoid deterioration due to the etching solution, It is preferable to cover the upper and lower surfaces of the metal substrate with a metal protective film 61c.
The material of the metal protective film 61c is preferably made of a metal containing at least one of chromium, nickel, chemically stable platinum, and gold having excellent adhesion.
The metal protective film 61c is optimally composed of a layer combining nickel having good adhesion and gold having excellent chemical resistance.
　また、本実施形態における支持基板１としては、上述したようなＧｅ基板または金属基板のほかにも、Ｓｉ基板、ＧａＡｓ基板、ＧａＰ基板のいずれかを用いることができる。
　Ｓｉ基板を用いる場合には、例えば、シリコン基板の金属反射層側の表面に、Ｔｉ／Ａｕ／Ｉｎでなる層を配置し、さらにシリコン基板の裏面に、Ｔｉ／Ａｕでなる層を配置することにより適用できる。 In addition to the Ge substrate or metal substrate as described above, any one of a Si substrate, a GaAs substrate, and a GaP substrate can be used as the support substrate 1 in the present embodiment.
In the case of using a Si substrate, for example, a layer made of Ti / Au / In is arranged on the surface of the silicon substrate on the metal reflective layer side, and a layer made of Ti / Au is further arranged on the back surface of the silicon substrate. Can be applied.
　図１Ｃは、本発明の一実施形態の変形例である発光ダイオードの断面摸式図である。
　本実施形態においては、図１Ｃに示すように、金属反射層２の支持基板１側に拡散防止層１１及び／又は接合層１０を配置して、発光部６が支持基板１に接合されていてもよい。なお、図１Ｃにおいては、図１Ａに示す半導体装置における部材と同一の部材については同一の符号を付して示している。 FIG. 1C is a schematic cross-sectional view of a light-emitting diode that is a modification of the embodiment of the present invention.
In the present embodiment, as shown in FIG. 1C, the diffusion preventing layer 11 and / or the bonding layer 10 is disposed on the support substrate 1 side of the metal reflection layer 2, and the light emitting unit 6 is bonded to the support substrate 1. Also good. In FIG. 1C, the same members as those in the semiconductor device shown in FIG. 1A are denoted by the same reference numerals.
＜拡散防止層＞
　拡散防止層１１は、接合層１０及び支持基板１に含まれる金属が拡散して、金属反射層２と反応するのを抑制することができる。
　拡散防止層１１の材料としては、ニッケル、チタン、白金、クロム、タンタル、タングステン、モリブデン等を用いることができる。
　拡散防止層１１は、２種類以上の金属の組み合わせ、たとえば白金とチタンの組み合わせなどにより、バリアの性能を向上させることができる。
　なお、拡散防止層１１を設けなくても、後述する接合層１０にそれらの材料を添加することにより接合層１０に拡散防止層１１と同様な機能を持たせることもできる。 <Diffusion prevention layer>
The diffusion prevention layer 11 can suppress the metal contained in the bonding layer 10 and the support substrate 1 from diffusing and reacting with the metal reflection layer 2.
As a material of the diffusion preventing layer 11, nickel, titanium, platinum, chromium, tantalum, tungsten, molybdenum, or the like can be used.
The diffusion prevention layer 11 can improve the performance of the barrier by a combination of two or more kinds of metals, for example, a combination of platinum and titanium.
Even if the diffusion preventing layer 11 is not provided, the bonding layer 10 can have the same function as the diffusion preventing layer 11 by adding these materials to the bonding layer 10 described later.
＜接合層＞
　接合層１０は、活性層４を含む化合物半導体層５等を支持基板１に接合するための層である。
　接合層１０の材料としては、化学的に安定で、融点の低いＡｕ系の共晶金属などが用いられる。Ａｕ系の共晶金属としては、例えば、ＡｕＧｅ、ＡｕＳｎ、ＡｕＳｉ、ＡｕＩｎなどの合金の共晶組成を挙げることができる。 <Junction layer>
The bonding layer 10 is a layer for bonding the compound semiconductor layer 5 including the active layer 4 to the support substrate 1.
As a material for the bonding layer 10, an Au-based eutectic metal that is chemically stable and has a low melting point is used. Examples of the Au-based eutectic metal include eutectic compositions of alloys such as AuGe, AuSn, AuSi, and AuIn.
　図１Ｄに、前述したような図１Ｃに示す発光ダイオードにおける電極構造において、図１Ｂで示したようなオーミック電極の構造を採用した発光ダイオードを示す。
　本実施形態においては、図１Ｄに示すように、金属反射層２の支持基板１側に拡散防止層１１及び接合層１０を配置するとともに、金属反射層２と電流拡散層７との間に貫通孔を備えた透光膜１４が成膜され、当該貫通孔内にオーミック電極１５が形成された構造としてもよい。
　このように、拡散防止層１１及び接合層１０を備え、さらに電極構造を透光膜に形成するオーミック電極１５とすることによって、接合層１０や支持基板１に含まれる金属が拡散することによる金属反射層２との反応を抑制できるとともに、電極をオーミック電極１５とすることによって、順方向の電流をより安定して確保することができ、順方向電圧の過度の上昇を抑制することができる。
　なお、図１Ｄにおいては、図１Ａ～Ｃのそれぞれに示す半導体装置における部材と同一の部材については同一の符号を付して示している。
　また、本実施形態においては、拡散防止層１１または接合層１０のいずれか一方のみを備える構造としてもよい。 FIG. 1D shows a light emitting diode employing the ohmic electrode structure shown in FIG. 1B in the electrode structure of the light emitting diode shown in FIG. 1C as described above.
In this embodiment, as shown in FIG. 1D, the diffusion prevention layer 11 and the bonding layer 10 are disposed on the support substrate 1 side of the metal reflection layer 2 and penetrated between the metal reflection layer 2 and the current diffusion layer 7. A translucent film 14 having a hole may be formed, and an ohmic electrode 15 may be formed in the through hole.
As described above, the ohmic electrode 15 having the diffusion preventing layer 11 and the bonding layer 10 and further forming the electrode structure on the translucent film allows the metal contained in the bonding layer 10 and the support substrate 1 to diffuse. While the reaction with the reflective layer 2 can be suppressed and the electrode is the ohmic electrode 15, a forward current can be more stably secured, and an excessive increase in the forward voltage can be suppressed.
In FIG. 1D, the same members as those in the semiconductor device shown in FIGS. 1A to 1C are denoted by the same reference numerals.
Moreover, in this embodiment, it is good also as a structure provided only with either the diffusion prevention layer 11 or the joining layer 10. FIG.
［発光ダイオードの製造方法］
　次に、本発明の一実施形態である発光ダイオードの製造方法について説明する。
　本実施形態の発光ダイオードの製造方法は、成長用基板上に、ＤＢＲ層及び活性層を順に含む化合物半導体層を形成する工程と、化合物半導体層上に金属反射層を形成して発光部を形成する工程と、発光部と支持基板とを接合する工程と、成長用基板を除去する工程と、を有することを特徴とする。 [Method for manufacturing light-emitting diode]
Next, the manufacturing method of the light emitting diode which is one Embodiment of this invention is demonstrated.
In the method of manufacturing a light emitting diode according to the present embodiment, a step of forming a compound semiconductor layer including a DBR layer and an active layer in order on a growth substrate, and forming a light emitting portion by forming a metal reflective layer on the compound semiconductor layer And a step of bonding the light emitting portion and the support substrate, and a step of removing the growth substrate.
＜支持基板の製造工程＞
〔１〕支持基板１としてＧｅ基板を用いた場合
　図５に示すように、Ｇｅ基板５１のおもて面５１Ａに例えば、Ａｕ／Ｐｔでなる層５２を形成し、Ｇｅ基板５１の裏面に例えば、Ｐｔ／Ａｕでなる層５３を形成して、支持基板１を作製する。
　なお、層５２及び層５３の材料はこれらに限らず、本発明の効果を損なわない範囲において選択してよい。 <Manufacturing process of support substrate>
[1] When a Ge substrate is used as the support substrate 1 As shown in FIG. 5, a layer 52 made of, for example, Au / Pt is formed on the front surface 51A of the Ge substrate 51, and on the back surface of the Ge substrate 51, for example, Then, a layer 53 made of Pt / Au is formed to produce the support substrate 1.
The materials of the layer 52 and the layer 53 are not limited to these, and may be selected within a range that does not impair the effects of the present invention.
〔２〕支持基板１として金属基板を用いた場合
　本実施形態では、熱膨張係数がそれぞれ異なる３層の金属を積層した構造について説明する。
　図６に示すように、支持基板１として金属基板を用いる場合、熱膨張係数が活性層の材料より大きい第１の金属層（第１の金属板）６１ｂと、熱膨張係数が活性層の材料より小さい第２の金属層（第２の金属板）６１ａとを採用して、ホットプレスして金属基板を形成する。 [2] When a metal substrate is used as the support substrate 1 In this embodiment, a structure in which three layers of metals having different thermal expansion coefficients are laminated will be described.
As shown in FIG. 6, when a metal substrate is used as the support substrate 1, a first metal layer (first metal plate) 61b having a thermal expansion coefficient larger than that of the active layer and a material having a thermal expansion coefficient of the active layer. A smaller second metal layer (second metal plate) 61a is employed and hot pressed to form a metal substrate.
　具体的にはまず、２枚の略平板状の第１の金属層６１ｂと、１枚の略平板状の第２の金属層６１ａを用意する。例えば、第１の金属層６１ｂとしては厚さ１０μｍのＣｕ、第２の金属層６１ａとしては厚さ７５μｍのＭｏを用いる。
　次に、２枚の第１の金属層６１ｂの間に第２の金属層６１ａを挿入してこれらを重ねて配置する。 Specifically, first, two substantially flat plate-like first metal layers 61b and one substantially flat plate-like second metal layer 61a are prepared. For example, Cu having a thickness of 10 μm is used as the first metal layer 61b, and Mo having a thickness of 75 μm is used as the second metal layer 61a.
Next, the second metal layer 61a is inserted between the two first metal layers 61b, and these are overlapped.
　次に、重ね合わせたそれらの金属層を所定の加圧装置に配置して、高温下で第１の金属層６１ｂと第２の金属層６１ａに荷重をかける。これにより、図６に示すように、第１の金属層６１ｂがＣｕであり、第２の金属層６１ａがＭｏであり、Ｃｕ（１０μｍ）／Ｍｏ（７５μｍ）／Ｃｕ（１０μｍ）の３層からなる金属基板を形成する。
　金属基板は、例えば、熱膨張係数が５．７ｐｐｍ／Ｋとなり、熱伝導率は２２０Ｗ／ｍ・Ｋとなる。 Next, these superimposed metal layers are placed in a predetermined pressure device, and a load is applied to the first metal layer 61b and the second metal layer 61a at a high temperature. Thus, as shown in FIG. 6, the first metal layer 61b is Cu, the second metal layer 61a is Mo, and the three layers of Cu (10 μm) / Mo (75 μm) / Cu (10 μm) are used. Forming a metal substrate.
For example, the metal substrate has a thermal expansion coefficient of 5.7 ppm / K and a thermal conductivity of 220 W / m · K.
　次に、図６に示すように、金属基板の全面すなわち、上面、下面及び側面を覆う金属保護膜６１ｃを形成する。このとき、金属基板は各発光ダイオードに個片化のために切断される前なので、金属保護膜６１ｃが覆う側面とは金属基板の外周側面である。
　従って、個片化後の各発光ダイオードの金属基板の側面を金属保護膜６１ｃで覆う場合には別途、金属保護膜６１ｃで側面を覆う工程を実施する。
　なお、図６は、金属基板の外周端側でない箇所の一部を示しているものであり、外周側面の金属保護膜は図に表れていない。 Next, as shown in FIG. 6, a metal protective film 61c that covers the entire surface of the metal substrate, that is, the upper surface, the lower surface, and the side surfaces is formed. At this time, since the metal substrate is before being cut into individual light emitting diodes, the side surface covered by the metal protective film 61c is the outer peripheral side surface of the metal substrate.
Therefore, when the side surface of the metal substrate of each light-emitting diode after singulation is covered with the metal protective film 61c, a step of covering the side surface with the metal protective film 61c is performed separately.
FIG. 6 shows a part of the metal substrate that is not on the outer peripheral end side, and the metal protective film on the outer peripheral side surface is not shown in the figure.
　金属保護膜６１ｃは公知の膜形成方法を用いることができるが、側面を含めた全面に膜形成ができるめっき法が最も好ましい。例えば、無電解めっき法では、ニッケルその後、金をめっきし、金属基板の上面、側面、下面をニッケル膜及び金膜（金属保護膜）で覆われた金属基板を作製できる。
　めっき材質は、特に制限はなく、銅、銀、ニッケル、クロム、白金、金など公知の材質が適用できるが、密着性がよいニッケルと耐薬品に優れる金を組み合わせた層が最適である。
　めっき法は、公知の技術、薬品が使用できる。電極が不要な無電解めっき法が、簡便で望ましい。 A known film forming method can be used for the metal protective film 61c, but a plating method capable of forming a film on the entire surface including the side surfaces is most preferable. For example, in the electroless plating method, nickel is then plated with gold, and a metal substrate in which the upper surface, side surfaces, and lower surface of the metal substrate are covered with a nickel film and a gold film (metal protective film) can be produced.
The plating material is not particularly limited, and known materials such as copper, silver, nickel, chromium, platinum, and gold can be applied. However, a layer that combines nickel having good adhesion and gold having excellent chemical resistance is optimal.
As the plating method, known techniques and chemicals can be used. An electroless plating method that does not require an electrode is simple and desirable.
〔３〕支持基板１としてＳｉ基板を用いた場合
　Ｓｉ基板のおもて面に例えば、Ａｕ／Ｐｔでなる層を形成し、Ｓｉ基板の裏面に例えば、Ｐｔ／Ａｕでなる層を形成して、支持基板１を作製する。
　なお、Ｓｉ基板のおもて面または裏面に形成する各層の材料はこれらに限らず、本発明の効果を損なわない範囲において選択してよい。 [3] When Si substrate is used as support substrate 1 For example, a layer made of Au / Pt is formed on the front surface of the Si substrate, and a layer made of Pt / Au is formed on the back surface of the Si substrate, for example. The support substrate 1 is produced.
The material of each layer formed on the front surface or the back surface of the Si substrate is not limited to these, and may be selected within a range not impairing the effects of the present invention.
〔４〕支持基板１としてＧａＰ基板を用いた場合
　例えば、ｐ型ＧａＰからなる機能性基板を用意し、そのおもて面に例えば、Ａｕ／Ｐｔでなる層を形成し、裏面に例えば、Ｐｔ／Ａｕでなる層を形成して、支持基板１を作製する。
　なお、本実施形態においては、上述してきたような基板のほかに、ＧａＡｓ基板も支持基板１として用いることができる。 [4] When a GaP substrate is used as the support substrate 1 For example, a functional substrate made of p-type GaP is prepared, a layer made of, for example, Au / Pt is formed on the front surface, and, for example, Pt is made on the back surface. A layer made of / Au is formed to produce the support substrate 1.
In this embodiment, a GaAs substrate can be used as the support substrate 1 in addition to the substrate as described above.
＜化合物半導体層の形成工程＞
　次に、成長用基板上に、ＤＢＲ層及び活性層を順に含む化合物半導体層を形成する工程について説明する。
　まず、図７に示すように、半導体基板（成長用基板）２１の一面２１ａ上に、複数のエピタキシャル層を成長させて化合物半導体層５を含むエピタキシャル積層体３０を形成する。
　半導体基板２１は、エピタキシャル積層体３０形成用基板であり、例えば、一面２１ａが（１００）面から１５°傾けた面とされた、Ｓｉドープしたｎ型のＧａＡｓ単結晶基板である。エピタキシャル積層体３０としてＡｌＧａＩｎＰ層またはＡｌＧａＡｓ層を用いる場合、エピタキシャル積層体３０を形成する基板として砒化ガリウム（ＧａＡｓ）単結晶基板を用いることができる。 <Step of forming compound semiconductor layer>
Next, a process of forming a compound semiconductor layer including a DBR layer and an active layer in this order on the growth substrate will be described.
First, as shown in FIG. 7, an epitaxial stacked body 30 including the compound semiconductor layer 5 is formed by growing a plurality of epitaxial layers on one surface 21 a of a semiconductor substrate (growth substrate) 21.
The semiconductor substrate 21 is a substrate for forming the epitaxial stacked body 30. For example, the semiconductor substrate 21 is a Si-doped n-type GaAs single crystal substrate in which one surface 21a is inclined by 15 ° from the (100) plane. When an AlGaInP layer or an AlGaAs layer is used as the epitaxial stacked body 30, a gallium arsenide (GaAs) single crystal substrate can be used as a substrate on which the epitaxial stacked body 30 is formed.
　エピタキシャル積層体３０の形成方法としては、有機金属化学気相成長（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ：ＭＯＣＶＤ）法、分子線エピタキシャル（Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｉｃｙ：ＭＢＥ）法や液相エピタキシャル（Ｌｉｑｕｉｄ　Ｐｈａｓｅ　Ｅｐｉｔａｘｉｃｙ：ＬＰＥ）法などを用いることができる。 As a method for forming the epitaxial layered structure 30, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or a liquid phase epitaxial (Liquid Phase EpiLex) method is used. Etc. can be used.
　本実施形態では、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）をＩＩＩ族構成元素の原料に用いた減圧ＭＯＣＶＤ法を用いて、各層をエピタキシャル成長させる。
　なお、Ｍｇのドーピング原料にはビスシクロペンタジエニルマグネシウム（（Ｃ５Ｈ５）２Ｍｇ）を用いる。また、Ｓｉのドーピング原料にはジシラン（Ｓｉ２Ｈ６）を用いる。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）又はアルシン（ＡｓＨ３）を用いる。 In the present embodiment, the low pressure MOCVD method using trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) as group III constituent elements. Each layer is epitaxially grown using
Note that biscyclopentadienyl magnesium ((C 5 H 5 ) 2 Mg) is used as a Mg doping material. Further, disilane (Si 2 H 6 ) is used as a Si doping raw material. Further, phosphine (PH 3 ) or arsine (AsH 3 ) is used as a raw material for the group V constituent element.
　具体的には、まず、半導体基板２１の一面２１ａ上に、Ｓｉをドープしたｎ型のＧａＡｓからなる緩衝層２２ａを成膜する。緩衝層２２ａとしては、例えば、Ｓｉをドープしたｎ型のＧａＡｓを用い、キャリア濃度を２×１０１８ｃｍ－３とし、層厚を０．２μｍとする。 Specifically, first, a buffer layer 22 a made of n-type GaAs doped with Si is formed on one surface 21 a of the semiconductor substrate 21. As the buffer layer 22a, for example, n-type GaAs doped with Si is used, the carrier concentration is 2 × 10 18 cm −3 , and the layer thickness is 0.2 μm.
　次に、本実施形態では、緩衝層２２ａ上に、Ｓｉドープしたｎ型の（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなるエッチングストップ層２２ｂを成膜する。
　エッチングストップ層２２ｂは、半導体基板をエッチング除去する際、クラッド層および発光層までがエッチングされてしまうことを防ぐための層であり、例えば、Ｓｉドープの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなり、層厚を０．５μｍとする。 Next, in this embodiment, an etching stop layer 22b made of Si-doped n-type (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P is formed on the buffer layer 22a.
The etching stop layer 22b is a layer for preventing the cladding layer and the light emitting layer from being etched when the semiconductor substrate is removed by etching. For example, Si-doped (Al 0.5 Ga 0.5 ) 0 It consists .5 In 0.5 P, the thickness and 0.5 [mu] m.
　次に、エッチングストップ層２２ｂ上に、Ｓｉドープしたｎ型のＧａＡｓからなるコンタクト層８を成膜する。 Next, a contact layer 8 made of Si-doped n-type GaAs is formed on the etching stop layer 22b.
　次に、コンタクト層８上に、ＤＢＲ層３を形成する。
　具体的には、屈折率の異なる２種類の層３ａ、３ｂを交互に積層する。本実施形態では、屈折率の異なる２種類の層３ａ、３ｂは、組成の異なる２種類の（ＡｌＸｈＧａ１－Ｘｈ）Ｙ３Ｉｎ１－Ｙ３Ｐ（０＜Ｘｈ≦１、Ｙ３＝０．５）、（ＡｌＸｌＧａ１－Ｘｌ）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘｌ＜１、Ｙ３＝０．５）の対とすることができる。また、屈折率の異なる２種類の層３ａ、３ｂは、両者のＡｌの組成差ΔＸ＝ｘh－ｘｌが０．５より大きいか又は等しくなる組み合わせか、又は、ＧａＩｎＰとＡｌＩｎＰの組み合わせか、又は、組成の異なる２種類のＡｌｘｌＧａ１－ｘｌＡｓ（０．１≦ｘｌ≦１）、ＡｌｘｈＧａ１－ｘｈＡｓ（０．１≦ｘｈ≦１）の組み合わせであり、これら組み合わせかのいずれかから選択されるのが好ましい。 Next, the DBR layer 3 is formed on the contact layer 8.
Specifically, two types of layers 3a and 3b having different refractive indexes are alternately stacked. In the present embodiment, the two types of layers 3a and 3b having different refractive indexes are composed of two types of (Al Xh Ga 1-Xh ) Y3 In 1-Y3 P (0 <Xh ≦ 1, Y3 = 0.5) having different compositions. ), (Al Xl Ga 1-Xl ) Y3 In 1-Y3 P; 0 ≦ Xl <1, Y3 = 0.5). Also, the two types of layers 3a and 3b having different refractive indexes may be a combination in which the Al composition difference ΔX = xh−xl is greater than or equal to 0.5, a combination of GaInP and AlInP, or A combination of two types of Al xl Ga 1-xl As (0.1 ≦ xl ≦ 1) and Al xh Ga 1-xh As (0.1 ≦ xh ≦ 1) having different compositions, and any one of these combinations Is preferably selected.
　次に、ＤＢＲ層３上に、活性層４を形成する。
　具体的には、まず、図８に示すように、Ｓｉをドープしたｎ型のＡｌ０．５Ｉｎ０．５Ｐからなる上部クラッド層４５を成膜する。 Next, the active layer 4 is formed on the DBR layer 3.
Specifically, first, as shown in FIG. 8, an upper cladding layer 45 made of n-type Al 0.5 In 0.5 P doped with Si is formed.
　次に、上部クラッド層４５上に、例えば、アンドープの（Ａｌ０．１Ｇａ０．９）０．５Ｉｎ０．５Ｐ／（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐの２０対の量子井戸構造からなる発光層４３を成膜する。
　具体的には、発光層４３は、バリア層（障壁層ともいう）４８を両端に有する、井戸層４７とバリア層４８との多層構造（積層構造）とすることができる。 Next, on the upper cladding layer 45, for example, of an undoped (Al 0.1 Ga 0.9) 0.5 In 0.5 P / (Al 0.7 Ga 0.3) 0.5 In 0.5 A light emitting layer 43 having a 20-pair quantum well structure of P is formed.
Specifically, the light emitting layer 43 can have a multilayer structure (laminated structure) of a well layer 47 and a barrier layer 48 having a barrier layer (also referred to as a barrier layer) 48 at both ends.
　井戸層４７の材料としては、（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））のいずれかを用いることができる。
　バリア層４８の材料としては、井戸層４７の材料に対して適した材料を選択するのが好ましい。バリア層４８での吸収を防止して発光効率を高めるため、井戸層４７よりもバンドギャップが大きくなる組成とするのが好ましい。 The material of the well layer 47 includes ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 ≦ X2 ≦ 1) or (In X3 Ga 1-X3 ) As (0 ≦ X3 ≦ 1)) can be used.
As a material of the barrier layer 48, a material suitable for the material of the well layer 47 is preferably selected. In order to prevent the absorption in the barrier layer 48 and increase the light emission efficiency, it is preferable that the composition has a band gap larger than that of the well layer 47.
　次に、発光層４３上に、Ｍｇをドープしたｐ型のＡｌ０．５Ｉｎ０．５Ｐからなる下部クラッド層４１を成膜する。 Next, a lower cladding layer 41 made of p-type Al 0.5 In 0.5 P doped with Mg is formed on the light emitting layer 43.
　次に、下部クラッド層４１上に、Ｍｇドープしたｐ型の電流拡散層７を成膜する。 Next, the Mg-doped p-type current diffusion layer 7 is formed on the lower cladding layer 41.
　なお、上部クラッド層４５、下部クラッド層４１それぞれと発光層４３との間に、上部ガイド層４４、下部ガイド層４２を設けてもよい。 An upper guide layer 44 and a lower guide layer 42 may be provided between the upper clad layer 45 and the lower clad layer 41 and the light emitting layer 43, respectively.
＜金属反射層の形成工程＞
　次に、図７に示すように、Ｍｇドープしたｐ型の電流拡散層７上に金属反射層２を形成する。
　具体的には、例えば、蒸着法を用いて、金、銅、銀、アルミニウム、Ｐｔ、又はこれらの合金のいずれか一層又は二層以上からなる金属反射層２をＭｇドープしたｐ型の電流拡散層７上に形成する。 <Metal reflective layer formation process>
Next, as shown in FIG. 7, the metal reflection layer 2 is formed on the Mg-doped p-type current diffusion layer 7.
Specifically, for example, using a vapor deposition method, p-type current diffusion in which the metal reflective layer 2 composed of one or more of gold, copper, silver, aluminum, Pt, or an alloy thereof is Mg-doped. Form on layer 7.
　＜拡散防止層の形成工程＞
　本実施形態においては、金属反射層２上に、適宜、拡散防止層又は／及び接合層を形成してもよい（図１Ｃ、Ｄ参照）。
　具体的には、まず金属反射層２上に拡散防止層（不図示）を形成する。例えば、蒸着法を用いて、ニッケルからなる拡散防止層を金属反射層２上に形成できる。
＜接合層の形成工程＞
　次に、拡散防止層上に接合層（不図示）を形成する。例えば、蒸着法を用いて、Ａｕ系の共晶金属であるＡｕＧｅからなる接合層を上記拡散防止層上に形成する。 <Diffusion prevention layer formation process>
In the present embodiment, a diffusion preventing layer and / or a bonding layer may be appropriately formed on the metal reflective layer 2 (see FIGS. 1C and D).
Specifically, a diffusion preventing layer (not shown) is first formed on the metal reflective layer 2. For example, a diffusion prevention layer made of nickel can be formed on the metal reflection layer 2 by vapor deposition.
<Junction layer formation process>
Next, a bonding layer (not shown) is formed on the diffusion preventing layer. For example, a bonding layer made of AuGe, which is an Au-based eutectic metal, is formed on the diffusion prevention layer by vapor deposition.
＜支持基板の接合工程＞
　次に、図９に示すように、エピタキシャル積層体３０や金属反射層２等を形成した半導体基板と、上記支持基板の製造工程で形成した支持基板１とを接合する。
　具体的には、例えば、支持基板１としてＧｅ基板を用いた場合は、まず図５に示したようなＧｅ基板５１のおもて面５１Ａに形成したＡｕ／Ｐｔでなる層５２と、図７に示した構造体の金属反射層２とを重ね合わせる。その後、例えば、３２０℃で加熱・５００ｇ／ｃｍ２で加圧し、図９に示すように、支持基板１をエピタキシャル積層体を含む構造体に接合する。
　また、支持基板１として金属基板を用いた場合は、図６に示したような金属基板と、図７に示した構造体の金属反射層２とが対向して重ね合わされるように配置する。次に、減圧装置内を３×１０－５Ｐａまで排気した後、４００℃に加熱した状態で、５００ｋｇの荷重を印加して図７に示した構造体の金属反射層２と金属基板とを接合する。 <Support substrate bonding process>
Next, as shown in FIG. 9, the semiconductor substrate on which the epitaxial multilayer body 30, the metal reflective layer 2, and the like are formed and the support substrate 1 formed in the support substrate manufacturing process are bonded.
Specifically, for example, when a Ge substrate is used as the support substrate 1, first, a layer 52 made of Au / Pt formed on the front surface 51A of the Ge substrate 51 as shown in FIG. The metal reflecting layer 2 having the structure shown in FIG. Thereafter, for example, heating is performed at 320 ° C. and pressurization is performed at 500 g / cm 2 , and the support substrate 1 is bonded to the structure including the epitaxial multilayer as shown in FIG.
When a metal substrate is used as the support substrate 1, the metal substrate as shown in FIG. 6 and the metal reflective layer 2 of the structure shown in FIG. 7 are arranged so as to face each other. Next, after evacuating the inside of the decompression device to 3 × 10 −5 Pa, with heating to 400 ° C., a load of 500 kg is applied to connect the metal reflective layer 2 and the metal substrate of the structure shown in FIG. Join.
＜半導体基板および緩衝層除去工程＞
　次に、図１０に示すように、図９に示す接合構造体から、成長用基板（半導体基板）２１及び緩衝層２２ａをアンモニア系エッチャントにより選択的に除去する。
＜エッチングストップ層除去工程＞
　次に、エッチングストップ層２２ｂを塩酸系エッチャントにより選択的に除去する。 <Semiconductor substrate and buffer layer removal step>
Next, as shown in FIG. 10, the growth substrate (semiconductor substrate) 21 and the buffer layer 22a are selectively removed from the bonding structure shown in FIG. 9 with an ammonia-based etchant.
<Etching stop layer removal process>
Next, the etching stop layer 22b is selectively removed with a hydrochloric acid-based etchant.
＜表面電極及び裏面電極の形成工程＞
　次に、コンタクト層８上に、例えば、ＡｎＧｅ／Ｎｉを含有する材料からなる表面電極１２を形成すると共に、支持基板１の金属反射層２が形成されている方と反対側の面に、ＡｕＢｅを含有する材料からなる裏面電極１３を形成する。
　具体的には例えば、蒸着法を用いて、ＡｎＧｅ／Ｎｉを含有する材料をコンタクト層８上に、そしてＡｕＢｅを含有する材料を支持基板１上に成膜する。 <Formation process of front surface electrode and back surface electrode>
Next, on the contact layer 8, for example, a surface electrode 12 made of a material containing AnGe / Ni is formed, and on the surface opposite to the side on which the metal reflective layer 2 of the support substrate 1 is formed, AuBe A back electrode 13 made of a material containing is formed.
Specifically, for example, a material containing AnGe / Ni is formed on the contact layer 8 and a material containing AuBe is formed on the support substrate 1 by vapor deposition.
　なお、上述したように、本実施形態における半導体装置では、上述したような裏面電極１３の配置形態に限らない。
　以下に、図１Ｂ及びＤに示したような電極構造を形成するための工程について説明する。
　まず、上述した方法により電流拡散層７を成膜した後、電流拡散層（ｐ型半導体層）７上にｐ型電極（オーミック電極）１５を形成する。
　具体的には、電流拡散層７全面に、例えば、ＣＶＤ法を用いて透光膜（ＳｉＯ２膜）１４を形成する。なお、透光膜１４を構成する材料としては、ＳｉＯ２、ＳｉＮ、ＳｉＯＮ、Ａｌ２Ｏ３、ＭｇＦ２、ＴｉＯ２、ＴｉＮ、ＺｎＯ、ＩＴＯ、ＩＺＯなどを用いることができる。 As described above, the semiconductor device according to the present embodiment is not limited to the arrangement form of the back electrode 13 as described above.
Hereinafter, steps for forming the electrode structure as shown in FIGS. 1B and 1D will be described.
First, after forming the current diffusion layer 7 by the above-described method, a p-type electrode (ohmic electrode) 15 is formed on the current diffusion layer (p-type semiconductor layer) 7.
Specifically, a translucent film (SiO 2 film) 14 is formed on the entire surface of the current diffusion layer 7 by using, for example, a CVD method. As the material constituting the translucent film 14, may be SiO 2, SiN, SiON, Al 2 O 3, MgF 2, TiO 2, TiN, ZnO, ITO, IZO or the like is used.
　次に、フォトリソグラフィー技術及びエッチング技術を用いて、透光膜１４に、オーミック電極１５を構成する導電性部材を埋め込むための複数の貫通孔を形成する。
　具体的には、それらの貫通孔に対応する孔を有するフォトレジストパターンを透光膜１４上に形成し、フッ酸系のエッチャントを用いて貫通孔に対応する箇所の透光膜１４を除去することにより、透光膜１４に複数の貫通孔を形成する。 Next, a plurality of through holes for embedding a conductive member constituting the ohmic electrode 15 are formed in the light-transmitting film 14 by using a photolithography technique and an etching technique.
Specifically, a photoresist pattern having holes corresponding to the through holes is formed on the light transmitting film 14, and the light transmitting film 14 corresponding to the through holes is removed using a hydrofluoric acid-based etchant. As a result, a plurality of through holes are formed in the translucent film 14.
　次に、例えば、蒸着法を用いて、電流拡散層７上であって、透光膜１４の複数の貫通孔に、例えばＡｕとＢｅを含有する材料からなるオーミック電極１５を形成する。なお、オーミック電極１５に用いる材料は特に限定しないが、ＡｕＢｅの合金からなることが好ましい。 Next, an ohmic electrode 15 made of a material containing, for example, Au and Be, is formed on the plurality of through holes of the light transmitting film 14 on the current diffusion layer 7 by using, for example, a vapor deposition method. The material used for the ohmic electrode 15 is not particularly limited, but is preferably made of an AuBe alloy.
　次に、オーミック電極１５及び透光膜１４上に金属反射層２を形成するが、これ以降の工程は上述した工程を採用することで、図１Ｂ及びＤに示したような半導体装置を製造できる。 Next, the metal reflective layer 2 is formed on the ohmic electrode 15 and the light-transmitting film 14, but the semiconductor device as shown in FIGS. 1B and 1D can be manufactured by adopting the steps described above in the subsequent steps. .
＜個片化工程＞
　次に、ウェハ上の発光ダイオードを個片化する。
　切断する領域の半導体層を除去した後に、以上の工程で形成された支持基板１を含む構造体をレーザで例えば、３５０μｍ間隔で切断し、発光ダイオード１００を作製する。 <Individualization process>
Next, the light emitting diodes on the wafer are separated.
After removing the semiconductor layer in the region to be cut, the structure including the support substrate 1 formed in the above steps is cut with a laser, for example, at intervals of 350 μm to manufacture the light emitting diode 100.
＜支持基板側面の金属保護膜形成工程＞
　個片化された各発光ダイオード１００では、基板１の側面には金属保護膜は形成されていないが、上面及び下面の金属保護膜の形成条件と同様な条件で、切断された基板１の側面に金属保護膜を形成してもよい。 <Metal protective film forming process on side surface of supporting substrate>
In each of the separated light emitting diodes 100, the metal protective film is not formed on the side surface of the substrate 1, but the side surface of the cut substrate 1 is formed under the same conditions as the formation conditions of the upper and lower metal protective films. A metal protective film may be formed on the substrate.
　以下、本発明を実施例に基づいて具体的に説明する。しかし、本発明はこれらの実施例のみに限定されるものではない。 Hereinafter, the present invention will be specifically described based on examples. However, the present invention is not limited only to these examples.
（実施例１）
　実施例１は、図１Ｃおよび図２に示した実施形態の実施例である。本実施例では、特性評価のために発光ダイオードチップを基板上に実装した発光ダイオードランプを作製した。また、支持基板１としてＧｅ基板を用い作製した。 (Example 1)
Example 1 is an example of the embodiment shown in FIGS. 1C and 2. In this example, a light-emitting diode lamp in which a light-emitting diode chip was mounted on a substrate was prepared for characteristic evaluation. Further, a Ge substrate was used as the support substrate 1.
　まず、Ｇｅ基板の表面にＡｕ／Ｐｔでなる層を０．５μｍ／０．１μｍの厚さで形成した。ゲルマニウム基板の裏面に、Ｐｔ／Ａｕでなる層を０．１μｍ／０．５μｍの厚さで形成した。 First, a layer made of Au / Pt with a thickness of 0.5 μm / 0.1 μm was formed on the surface of the Ge substrate. A layer made of Pt / Au was formed on the back surface of the germanium substrate with a thickness of 0.1 μm / 0.5 μm.
　次に、Ｓｉをドープしたｎ型のＧａＡｓ単結晶からなるＧａＡｓ基板上に、化合物半導体層を順次積層して発光波長７３０ｎｍのエピタキシャルウェハを作製した。
　ＧａＡｓ基板は、（１００）面から（０－１－１）方向に１５°傾けた面を成長面とし、キャリア濃度を２×１０１８ｃｍ－３とした。
　化合物半導体層としては、ＳｉをドープしたＧａＡｓからなるｎ型の緩衝層、Ｓｉドープの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなるエッチングストップ層、Ｓｉドープしたｎ型のＡｌ０．３ＧａＡｓからなるコンタクト層、ＤＢＲ層、ＳｉドープのＡｌ０．５Ｉｎ０．５Ｐからなるｎ型の上部クラッド層、（Ａｌ０．１Ｇａ０．９）０．５Ｉｎ０．５Ｐ／（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐの２０対からなる井戸層／バリア層の発光層、Ａｌ０．５Ｉｎ０．５Ｐからなるｐ型の下部クラッド層、Ａｌ０．３Ｇａ０．７Ａｓからなる電流拡散層である。 Next, an epitaxial wafer having an emission wavelength of 730 nm was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si.
In the GaAs substrate, the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 × 10 18 cm −3 .
As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an etching stop layer made of Si-doped (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P, Si-doped n a contact layer made of Al0.3GaAs type, DBR layer, n-type upper cladding layer made of Al 0.5 in 0.5 P doped with Si, (Al 0.1 Ga 0.9) 0.5 in 0. 5 P / (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P 20 well layer / barrier layer light emitting layer, Al 0.5 In 0.5 P p-type lower part The clad layer is a current diffusion layer made of Al0.3Ga0.7As.
　本実施例では、減圧有機金属化学気相堆積装置法（ＭＯＣＶＤ装置）を用い、直径５０ｍｍ、厚さ３５０μｍのＧａＡｓ基板に化合物半導体層をエピタキシャル成長させて、エピタキシャルウェハを形成した。エピタキシャル成長層を成長させる際、ＩＩＩ族構成元素の原料としては、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を使用した。また、Ｍｇのドーピング原料としては、ビスシクロペンタジエニルマグネシウム（ｂｉｓ－（Ｃ５Ｈ５）２Ｍｇ）を使用した。また、Ｓｉのドーピング原料としては、ジシラン（Ｓｉ２Ｈ６）を使用した。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）を使用した。また、各層の成長温度としては、７００℃で成長させた。 In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 350 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw material for the group III constituent element did. Further, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) was used as a Mg doping material. Further, disilane (Si 2 H 6 ) was used as a Si doping material. Further, phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements. The growth temperature of each layer was 700 ° C.
　ＧａＡｓからなる緩衝層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約０．５μｍとした。エッチングストップ層は、キャリア濃度を１×１０１８ｃｍ－３、層厚を約０．５μｍとした。コンタクト層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約０．０５μｍとした。ＤＢＲ層はキャリア濃度を約１×１０１８ｃｍ－３、層厚を約５７ｎｍとしたＡｌ０．９Ｇａ０．１Ａｓと、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約５２ｎｍとしたＡｌ０．３Ｇａ０．７Ａｓを交互に８対積層した。上部クラッド層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を約０．５μｍとした。井戸層は、アンドープで層厚が約５ｎｍの（Ａｌ０．１Ｇａ０．９）０．５Ｉｎ０．５Ｐとし、バリア層はアンドープで層厚が約５ｎｍの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐとした。また、井戸層とバリア層とを交互に２０対積層した。下部クラッド層は、キャリア濃度を約８×１０１７ｃｍ－３、層厚を約０．５μｍとした。又、電流拡散層はキャリア濃度を約１×１０１８ｃｍ－３、層厚を約３μｍとしたＡｌ０．３Ｇａ０．７Ａｓを積層した。 The buffer layer made of GaAs has a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The etching stop layer had a carrier concentration of 1 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 0.05 μm. DBR layer Al0 is that the carrier concentration of about 1 × 10 18 cm -3, and Al0.9Ga0.1As with a thickness of about 57 nm, the carrier concentration of about 1 × 10 18 cm -3, a thickness of about 52 nm. 8 pairs of 3Ga0.7As were alternately laminated. The upper cladding layer had a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The well layer is undoped (Al 0.1 Ga 0.9 ) 0.5 In 0.5 P with a thickness of about 5 nm, and the barrier layer is undoped and has a thickness of about 5 nm (Al 0.5 Ga 0 .5 ) 0.5 In 0.5 P. Further, 20 pairs of well layers and barrier layers were alternately laminated. The lower cladding layer had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 0.5 μm. The current spreading layer was formed by laminating Al0.3Ga0.7As with a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 3 μm.
　次に、電流拡散層上に、蒸着法を用いて、厚さ０．７μｍのＡｕ膜からなる金属反射層を形成した。
　次に、金属反射層上に、蒸着法を用いて、厚さ０．５μｍのＴｉ膜からなる拡散防止層を形成した。
　次に、拡散防止層上に、蒸着法を用いて、厚さ１．０μｍのＡｕＧｅからなる接合層を形成した。 Next, a metal reflective layer made of an Au film having a thickness of 0.7 μm was formed on the current diffusion layer by vapor deposition.
Next, a diffusion preventing layer made of a Ti film having a thickness of 0.5 μm was formed on the metal reflective layer by vapor deposition.
Next, a bonding layer made of AuGe having a thickness of 1.0 μm was formed on the diffusion prevention layer by vapor deposition.
　次に、ＧａＡｓ基板上に化合物半導体層及び反射層等を形成した構造体（図７参照）と、金属基板とを対向して重ね合わせるように配置して減圧装置内に搬入し、その後、４００℃で加熱した状態で、５００ｋｇ重の荷重でそれらを接合して接合構造体を形成した。 Next, a structure (see FIG. 7) in which a compound semiconductor layer, a reflective layer, and the like are formed on a GaAs substrate and a metal substrate are disposed so as to face each other and are carried into a decompression device. In the state heated at 0 degreeC, they were joined by the load of 500 kg weight, and the joining structure was formed.
　次に、接合構造体から、化合物半導体層の成長基板であるＧａＡｓ基板と緩衝層とをアンモニア系エッチャントにより選択的に除去し、さらに、エッチングストップ層を塩酸系エッチャントにより選択的に除去した。 Next, the GaAs substrate, which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
　次に、コンタクト層のＧｅ基板と反対側の面にレジストパターンを形成後、ＡｕＧｅ、Ｎｉ合金を厚さが０．５μｍ、Ｐｔを０．２μｍ、Ａｕを１μｍとなるように真空蒸着法を用いて成膜し表面電極を形成した。
　次に、Ｇｅ基板の裏面に、Ａｕを１．２μｍ、ＡｕＢｅを０．１５μｍを順に真空蒸着法によって成膜し、裏面電極を形成した。 Next, after forming a resist pattern on the surface of the contact layer opposite to the Ge substrate, a vacuum deposition method is used so that the thickness of AuGe and Ni alloy is 0.5 μm, Pt is 0.2 μm, and Au is 1 μm. A film was formed to form a surface electrode.
Next, on the back surface of the Ge substrate, 1.2 μm of Au and 0.15 μm of AuBe were sequentially formed by a vacuum deposition method to form a back electrode.
　次に、ウェットエッチングとレーザ切断を順に行って個片化して、実施例の発光ダイオードを作製した。

　次に、上述のように作製した実施例１の発光ダイオードチップをマウント基板上に実装して発光ダイオードランプを組み立てた。　 Next, wet etching and laser cutting were sequentially performed to obtain individual pieces, thereby manufacturing the light emitting diode of the example.

Next, a light emitting diode lamp was assembled by mounting the light emitting diode chip of Example 1 manufactured as described above on a mounting substrate.
　次に、この発光ダイオード（発光ダイオードランプ）の特性を評価した。
　この発光ダイオード（発光ダイオードランプ）のｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長７３０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は、約１．９ボルトとなった。順方向電流を２０ｍＡとした際の発光出力は、１２ｍＷであった。 Next, the characteristics of the light emitting diode (light emitting diode lamp) were evaluated.
When a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode (light-emitting diode lamp), infrared light having a peak wavelength of 730 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.9 volts. The light emission output when the forward current was 20 mA was 12 mW.
　（実施例２）
　次に実施例２の発光ダイオードを示す。実施例２の発光ダイオードは、貫通電極（オーミック電極）を介して化合物半導体層と金属反射層を電気的に導通させた組み合わせである。なお、実施例２は、図１Ｄに示した実施形態の実施例であって、化合物半導体層の形成は、実施例１と同じである。 (Example 2)
Next, a light emitting diode of Example 2 will be described. The light-emitting diode of Example 2 is a combination in which the compound semiconductor layer and the metal reflective layer are electrically connected through a through electrode (ohmic electrode). Note that Example 2 is an example of the embodiment shown in FIG. 1D, and the formation of the compound semiconductor layer is the same as Example 1.
　電流拡散層上に、ｐ型の電極（オーミック電極）を形成した。
　具体的には、電流拡散層全面に、例えば、ＣＶＤ法を用いて厚さ０．３μｍの透光膜（ＳｉＯ２膜）を形成した。 A p-type electrode (ohmic electrode) was formed on the current diffusion layer.
Specifically, a light-transmitting film (SiO 2 film) having a thickness of 0.3 μm was formed on the entire surface of the current diffusion layer by using, for example, a CVD method.
　次に、フォトリソグラフィー技術及びエッチング技術を用いて、透光膜に、オーミック電極を構成する導電性部材を埋め込むための直径９μｍの複数の貫通孔を形成した。
　次いで、蒸着法を用いて、透光膜の複数の貫通孔にＡｕＢｅ合金を充填することにより、電流拡散層上に高さ０．３μｍ、直径９μｍの複数の円柱状のオーミック電極を形成した。
　次に、蒸着法を用いて、厚さ０．７μｍのＡｕ膜からなる金属反射層を形成した。
　次に、金属反射層上に、蒸着法を用いて、厚さ０．５μｍのＴｉ膜からなる拡散防止層を形成した。
　次に、拡散防止層上に、蒸着法を用いて、厚さ１．０μｍのＡｕＧｅからなる接合層を形成した。 Next, a plurality of through-holes having a diameter of 9 μm for embedding a conductive member constituting the ohmic electrode was formed in the light-transmitting film by using a photolithography technique and an etching technique.
Next, a plurality of cylindrical ohmic electrodes having a height of 0.3 μm and a diameter of 9 μm were formed on the current diffusion layer by filling the plurality of through-holes of the light-transmitting film with AuBe alloy by vapor deposition.
Next, a metal reflection layer made of an Au film having a thickness of 0.7 μm was formed by vapor deposition.
Next, a diffusion preventing layer made of a Ti film having a thickness of 0.5 μm was formed on the metal reflective layer by vapor deposition.
Next, a bonding layer made of AuGe having a thickness of 1.0 μm was formed on the diffusion prevention layer by vapor deposition.
　次に支持基板１をＧｅ基板を用い作製した。Ｇｅ基板の表面にＡｕ／Ｐｔでなる層を０．５μｍ／０．１μｍの厚さで形成した。Ｇｅ基板の裏面に、Ｐｔ／Ａｕでなる層４３を０．１μｍ／０．５μｍの厚さで形成した。 Next, the support substrate 1 was produced using a Ge substrate. A layer made of Au / Pt was formed to a thickness of 0.5 μm / 0.1 μm on the surface of the Ge substrate. On the back surface of the Ge substrate, a layer 43 made of Pt / Au was formed to a thickness of 0.1 μm / 0.5 μm.
　次に、ＧａＡｓ基板上に化合物半導体層及び金属反射層等を形成した構造体（図７参照）と、支持基板１表面とを対向して重ね合わせるように配置して減圧装置内に搬入し、４００℃で加熱した状態で、５００ｋｇ重の荷重でそれらを接合して接合構造体を形成した。 Next, the structure (see FIG. 7) in which the compound semiconductor layer, the metal reflection layer, and the like are formed on the GaAs substrate and the surface of the support substrate 1 are arranged so as to face each other and are carried into the decompression device. In the state heated at 400 degreeC, they were joined by the load of 500 kg weight, and the joining structure was formed.
　次に、接合構造体から、化合物半導体層の成長基板であるＧａＡｓ基板と緩衝層とをアンモニア系エッチャントにより選択的に除去し、さらに、エッチングストップ層を塩酸系エッチャントにより選択的に除去した。 Next, the GaAs substrate, which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
　次に、コンタクト層の支持基板と反対側の面に、ＡｕＧｅ、Ｎｉ合金を厚さが０．５μｍ、Ｐｔを０．２μｍ、Ａｕを１．０μｍとなるように真空蒸着法を用いて成膜し表面電極（ｎ型電極）を形成した。 Next, a film is formed on the surface of the contact layer opposite to the support substrate by vacuum deposition so that the thickness of AuGe and Ni alloy is 0.5 μm, Pt is 0.2 μm, and Au is 1.0 μm. A surface electrode (n-type electrode) was formed.
　次に、ウェットエッチングとレーザ切断を順に行って個片化して、実施例の発光ダイオードを作製した。
　次に、上述のように作製した実施例１の発光ダイオードチップをマウント基板上に実装して発光ダイオードランプを組み立てた。 Next, wet etching and laser cutting were sequentially performed to obtain individual pieces, thereby manufacturing the light emitting diode of the example.
Next, a light emitting diode lamp was assembled by mounting the light emitting diode chip of Example 1 manufactured as described above on a mounting substrate.
　次に、この発光ダイオード（発光ダイオードランプ）の特性を評価した。
　この発光ダイオード（発光ダイオードランプ）のｎ型及びｐ型のオーミック電極間に電流を流したところ、ピーク波長７３０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は、約１．９ボルトとなった。順方向電流を２０ｍＡとした際の発光出力は、１２ｍＷであった。 Next, the characteristics of the light emitting diode (light emitting diode lamp) were evaluated.
When a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode (light-emitting diode lamp), infrared light having a peak wavelength of 730 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.9 volts. The light emission output when the forward current was 20 mA was 12 mW.
（比較例）
　比較例の発光ダイオードは上記実施例１の発光ダイオードにおけるＤＢＲ層の代わりにＳｉをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｎ型のコンタクト層を３μｍ積層したこと以外は実施例１と同様である。
　この発光ダイオードのｎ型及びｐ型のオーミック電極間に電流を流したところ、ピーク波長７３０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は、約１．９ボルトであり、発光出力は、１０ｍＷであった。 (Comparative example)
In the light emitting diode of the comparative example, an n-type contact layer made of Si (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P doped with Si is used instead of the DBR layer in the light emitting diode of Example 1 described above. The same as Example 1 except for the lamination.
When a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode, infrared light having a peak wavelength of 730 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.9 volts, and the light emission output was 10 mW.
　実施例１及び２のランプは、比較例に比べて出力が２０％高く、またランプ直上の発光出力に関しては７０％高い出力が得られた。これは、実施例１及び２においては金属反射膜とＤＢＲ層の間での共振により発光部からの光が干渉により効率よく取り出し可能となったためであり、特に直上方向において干渉が最大となるためと考えられる。
In the lamps of Examples 1 and 2, the output was 20% higher than that of the comparative example, and the light output directly above the lamp was 70% higher. This is because in Examples 1 and 2, the light from the light-emitting portion can be efficiently extracted by interference due to resonance between the metal reflection film and the DBR layer, and interference is maximized particularly in the directly upward direction. it is conceivable that.
　１　支持基板
　２　金属反射層
　３　ＤＢＲ層
　４　活性層
　５　化合物半導体層
　６　発光部

　７　電流拡散層
　８　コンタクト層
　１０　　接合層
　１１　　拡散防止層
　１２　表面電極
　１３　裏面電極
　１４　透光膜
　１５　オーミック電極（貫通電極）
　２１　半導体基板（成長用基板）
　３０　エピタキシャル積層体
　４１　下部クラッド層
　４２　下部ガイド層
　４３　発光層
　４４　上部ガイド層
　４５　上部クラッド層
　４７　井戸層
　４８　バリア層（障壁層）
　１００　発光ダイオード DESCRIPTION OF SYMBOLS 1 Support substrate 2 Metal reflecting layer 3 DBR layer 4 Active layer 5 Compound semiconductor layer 6 Light emission part

7 Current diffusion layer 8 Contact layer 10 Bonding layer 11 Diffusion prevention layer 12 Front electrode 13 Back electrode 14 Translucent film 15 Ohmic electrode (through electrode)
21 Semiconductor substrate (Growth substrate)
DESCRIPTION OF SYMBOLS 30 Epitaxial laminated body 41 Lower clad layer 42 Lower guide layer 43 Light emitting layer 44 Upper guide layer 45 Upper clad layer 47 Well layer 48 Barrier layer (barrier layer)
100 light emitting diode

Claims (9)

  1. 　支持基板上に、金属反射層と、活性層及びＤＢＲ層を順に含む化合物半導体層とを順に含む発光部を備え、
    　前記支持基板と前記発光部とが接合されてなることを特徴とする発光ダイオード。     On the support substrate, provided with a light emitting part including a metal reflective layer and a compound semiconductor layer including an active layer and a DBR layer in order,
    A light-emitting diode, wherein the support substrate and the light-emitting portion are joined.
  2. 　前記支持基板は、Ｇｅ基板、金属基板、Ｓｉ基板、ＧａＡｓ基板、ＧａＰ基板、のいずれかを含んでなることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein the support substrate includes any one of a Ge substrate, a metal substrate, a Si substrate, a GaAs substrate, and a GaP substrate.
  3. 　前記金属反射層は、金、銅、銀、アルミニウム、Ｐｔ、又はこれらの合金のいずれか一層又は二層以上からなることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein the metal reflective layer is composed of one or more layers of gold, copper, silver, aluminum, Pt, or an alloy thereof.
  4. 　前記金属反射層の前記支持基板側に形成された拡散防止層及び／又は接合層を介して、前記発光部が前記前記支持基板に接合されていることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting device according to claim 1, wherein the light emitting unit is bonded to the support substrate via a diffusion prevention layer and / or a bonding layer formed on the support substrate side of the metal reflective layer. diode.
  5. 　前記金属反射層と前記活性層との間に貫通孔を備えた透光膜が成膜され、前記貫通孔内にオーミック電極が形成されていることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein a translucent film having a through hole is formed between the metal reflective layer and the active layer, and an ohmic electrode is formed in the through hole. .
  6. 　前記ＤＢＲ層は、屈折率の異なる２種類の層が交互に３～１０対積層されてなることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein the DBR layer is formed by alternately stacking 3 to 10 pairs of two kinds of layers having different refractive indexes.
  7. 　前記屈折率の異なる２種類の層は、組成の異なる２種類の（ＡｌＸｈＧａ１－Ｘｈ）Ｙ３Ｉｎ１－Ｙ３Ｐ（０＜Ｘｈ≦１、Ｙ３＝０．５）、（ＡｌＸｌＧａ１－Ｘｌ）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘｌ＜１、Ｙ３＝０．５）の対であり、両者のＡｌの組成差ΔＸ＝ｘh－ｘｌが０．５より大きいか又は等しくなる組み合わせか、又は、ＧａＩｎＰとＡｌＩｎＰの組み合わせか、又は、組成の異なる２種類のＡｌｘｌＧａ１－ｘｌＡｓ（０．１≦ｘｌ≦１）、ＡｌｘｈＧａ１－ｘｈＡｓ（０．１≦ｘｈ≦１）の対であり、両者の組成差ΔＸ＝ｘｈ－ｘｌが０．５より大きいか等しくなる組み合わせかのいずれかから選択されることを特徴とする請求項１に記載の発光ダイオード。 The two types of layers having different refractive indexes are composed of two types of (Al Xh Ga 1-Xh ) Y3 In 1-Y3 P (0 <Xh ≦ 1, Y3 = 0.5), (Al Xl Ga 1 ) having different compositions. -Xl) Y3 in 1-Y3 P ; 0 ≦ xl <1, Y3 = 0.5) is a pair of, or combination composition difference ΔX = xh-xl of both Al is 0.5 greater than or equal Or a combination of GaInP and AlInP, or two types of different Al xl Ga 1-xl As (0.1 ≦ xl ≦ 1), Al xh Ga 1-xh As (0.1 ≦ xh ≦ 1) The light emitting diode according to claim 1, wherein the light emitting diode is selected from any combination in which the difference in composition ΔX = xh−xl of both is greater than or equal to 0.5.
  8. 　前記活性層に含まれる発光層は、（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））、のいずれかからなることを特徴とする請求項１に記載の発光ダイオード。 The light emitting layer included in the active layer includes ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 The light-emitting diode according to claim 1, wherein the light-emitting diode is any one of ≦ X2 ≦ 1) and (In X3 Ga 1-X3 ) As (0 ≦ X3 ≦ 1)).
  9. 　支持基板上に、金属反射層と、活性層及びＤＢＲ層を順に含む化合物半導体層とを順に含む発光部を備えた発光ダイオードの製造方法であって、
    　成長用基板上に、ＤＢＲ層及び活性層を順に含む化合物半導体層を形成する工程と、
    　前記化合物半導体層上に金属反射層を形成して発光部を形成する工程と、
    　前記発光部と支持基板とを接合する工程と、
    　前記成長用基板を除去する工程と、
    を有することを特徴とする発光ダイオードの製造方法。     A method of manufacturing a light-emitting diode comprising a light-emitting unit including a metal reflective layer and a compound semiconductor layer including an active layer and a DBR layer in order on a support substrate,
    Forming a compound semiconductor layer including a DBR layer and an active layer in this order on a growth substrate;
    Forming a light emitting portion by forming a metal reflective layer on the compound semiconductor layer;
    Bonding the light emitting unit and the support substrate;
    Removing the growth substrate;
    A method for producing a light emitting diode, comprising:
PCT/JP2013/074567 2012-09-14 2013-09-11 Light-emitting diode and method for producing same WO2014042198A1 (en)

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JP2007067198A (en) * 2005-08-31 2007-03-15 Harison Toshiba Lighting Corp Light emitting element
JP2009076490A (en) * 2007-09-18 2009-04-09 Hitachi Cable Ltd Light-emitting device
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JP2006157024A (en) * 2004-11-30 2006-06-15 Osram Opto Semiconductors Gmbh Light emission semiconductor element
JP2007067198A (en) * 2005-08-31 2007-03-15 Harison Toshiba Lighting Corp Light emitting element
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