JP2012186194A - Light-emitting diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting diode, a light-emitting diode lamp, and a lighting apparatus that emit red light and/or infrared light having high-speed response and high output.SOLUTION: A light-emitting diode according to the present invention comprises, in this order, a DBR reflective layer and a light-emitting part on a substrate. The light-emitting part has an active layer of a quantum well structure in which well layers and barrier layers that are composed of a compound semiconductor having a composition formula of (AlGa)As (0≤X1≤1) are alternately stacked, and a first cladding layer and a second cladding layer that sandwich the active layer and are composed of a compound semiconductor having a composition formula of (AlGa)InP (0≤X2≤1 and 0<Y1≤1). The number of pairs of the well layers and the barrier layers is 5 or less.

Description

  The present invention relates to a light-emitting diode, a light-emitting diode lamp, and an illumination device, and more particularly, to a light-emitting diode, a light-emitting diode lamp, and an illumination device that emit red light or infrared light having high-speed response and high output.

Light emitting diodes that emit red light or infrared light have widespread applications such as communication, various sensors, night lighting, and light sources for plant factories.
Accordingly, demands for light emitting diodes that emit red or infrared light are mainly focused on high power output, or mainly focused on high-speed response, to those focused on both. It has changed. In particular, in a light emitting diode for communication, high-speed response and high output are indispensable for performing large-capacity optical space transmission.

 As a light emitting diode that emits red light and infrared light, a light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate by a liquid phase epitaxial method is known (for example, Patent Documents 1 to 4).

 Patent Document 4 discloses a so-called substrate removal type light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate using a liquid phase epitaxial method, and then the GaAs substrate used as the growth substrate is removed. ing. In the light emitting diode disclosed in Patent Document 4, the output is 4 mW or less when the response speed (rise time) is about 40 to 55 nsec. In addition, when the response speed is about 20 nsec, the output is slightly higher than 5 mW, and it is considered that the light-emitting diode manufactured by using the liquid phase epitaxial method has the highest response speed and high output.

JP-A-6-21507 JP 2001-274454 A Japanese Patent Laid-Open No. 7-38148 JP 2006-190792 A

However, the above output is not sufficient as a light emitting diode for communication.
Unlike a semiconductor laser, a light-emitting diode uses spontaneous emission light, so that high-speed response and high output are in a trade-off relationship. Therefore, for example, even if the layer thickness of the light emitting layer is simply reduced to increase the carrier confinement effect to increase the light emission recombination probability of electrons and holes, the light emission output will decrease even if high speed response is achieved. There's a problem.

  The present invention has been made in view of the above circumstances, and provides a light-emitting diode, a light-emitting diode lamp, and an illumination device that emits red light and / or infrared light having both high-speed response and high output. With the goal.

As a result of intensive studies to solve the above problems, the present inventor has obtained an active layer having a quantum well structure in which five pairs or less of AlGaAs well layers and barrier layers made of AlGaAs or quaternary mixed crystal AlGaInP are alternately stacked. The clad layer sandwiching the active layer is made of quaternary mixed crystal AlGaInP, so that high-output red light and / or infrared light is emitted while maintaining high-speed response. The diode was completed.
At this time, the present inventor first adopts a quantum well structure having a high carrier confinement effect and suitable for a high-speed response as an active layer, and also in order to secure a high injected carrier density, the well layer and the barrier layer. The number of pairs was 5 or less. With this configuration, a response speed equal to or higher than the above-mentioned fastest response speed of a light-emitting diode manufactured using a liquid phase epitaxial method was realized.
In addition, a cladding layer sandwiching a quantum well structure composed of a ternary mixed crystal quantum well structure or a ternary mixed crystal well layer and a quaternary mixed crystal barrier layer has a large band gap and is transparent to the emission wavelength. Since it does not contain As, which is easy to make defects, quaternary mixed crystal AlGaInP having good crystallinity was adopted.

  As described above, the present inventor employs a configuration in which a quantum well structure of 5 pairs or less is used as an active layer to ensure high-speed response, and in this configuration, a ternary mixed crystal quantum well structure or a ternary mixed crystal. Growth substrate used for the growth of compound semiconductor layers while adopting a revolutionary combination of quaternary mixed crystal in the clad layer sandwiching the quantum well structure composed of a well layer and a quaternary mixed crystal barrier layer By adopting a structure in which a compound semiconductor layer is pasted again on a substrate that does not absorb light and a substrate that does not absorb light, high output was successfully achieved.

The present invention provides the following means.
(1) A light emitting diode comprising a DBR reflective layer and a light emitting part on a substrate in order, wherein the light emitting part is a compound semiconductor of the composition formula (Al _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1). An active layer having a quantum well structure in which well layers and barrier layers made of AlN are alternately stacked, and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1,0) sandwiching the active layer A light emitting diode comprising a first clad layer and a second clad layer made of a compound semiconductor of <Y1 ≦ 1), wherein the number of pairs of the well layer and the barrier layer is 5 or less.
(2) A light emitting diode comprising a DBR reflection layer and a light emitting part on a substrate in order, wherein the light emitting part is a compound semiconductor of the composition formula (Al _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1). And a quantum well structure in which barrier layers made of compound semiconductors of the composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1) are alternately stacked Active layer and a first cladding layer made of a compound semiconductor of the composition formula (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) sandwiching the active layer And a second cladding layer,
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned.
(3) The light-emitting diode according to any one of (1) and (2) above, wherein a bonding area between the active layer and the cladding layer is 20000 to 90000 μm ² .
Note that the “joining area between the active layer and the clad layer” means that when the active layer and the clad layer are joined via a layer such as a guide layer, these layers and the active layer or the clad layer Means the junction area between
(4) The Al composition X1 of the well layer is 0.20 ≦ X1 ≦ 0.36, the thickness of the well layer is 3 to 30 nm, and the emission wavelength is set to 660 to 720 nm. The light-emitting diode according to any one of (1) to (3) above.
(5) An Al composition X1 of the well layer is set to 0 ≦ X1 ≦ 0.2, a thickness of the well layer is set to 3 to 30 nm, and an emission wavelength is set to 720 to 850 nm. The light-emitting diode according to any one of 1) to (3).
(6) The light-emitting diode according to any one of (1) to (5) above, wherein the DBR reflective layer is formed by alternately stacking 10 to 50 pairs of two types of layers having different refractive indexes.
(7) The two types of layers having different refractive indexes are two types of (Al _Xh Ga _1-Xh ) _{Y 3} In _{1 -Y 3} P (0 <Xh ≦ 1, Y3 = 0.5), (Al _{Xl Ga 1-xl) Y3 in 1} -Y3 P; 0 ≦ xl <1, Y3 = 0.5) is a combination of, the composition difference ΔX = xh-xl both of Al or greater than or equal to 0.5 The light-emitting diode according to item (6), wherein
(8) The light-emitting diode according to (6), wherein the two types of layers having different refractive indexes are a combination of GaInP and AlInP.
(9) The two types of layers having different refractive indexes are composed of two types of Al _xl Ga _1-xl As (0.1 ≦ xl ≦ 1) and Al _xh Ga _1-xh As (0.1 ≦ xh ≦) having different compositions. The light-emitting diode according to the item (6), which is a combination of 1) and has a composition difference ΔX = xh−xl between the two Al larger than or equal to 0.5.
(10) The light-emitting diode according to any one of (1) to (9), wherein a current diffusion layer is provided on a surface of the light-emitting portion opposite to the DBR reflection layer.

According to the light emitting diode of the present invention, an active layer having a quantum well structure in which AlGaAs well layers and barrier layers are alternately stacked, or a quantum well in which AlGaAs well layers and AlGaInP barrier layers are alternately stacked. As the structure using an active layer with a structure and using a quantum well with a large confinement effect of injected carriers, the carrier density in the well layer is increased by confining sufficient injected carriers in the well layer. The luminescence recombination probability is increased and the response speed is improved.
Also, the carriers injected into the quantum well structure spread to the whole well layer in the quantum well structure due to the tunneling effect due to its wave nature, but the number of pairs of well layers and barrier layers in the quantum well structure is 5 Since the following configuration is adopted, a decrease in the confinement effect of injected carriers due to the spread is avoided as much as possible, and high-speed response is ensured.
Furthermore, since the structure emits light from the active layer having the quantum well structure, the monochromaticity is high.
In addition, the first clad layer and the second clad layer sandwiching the active layer employ a configuration made of AlGaInP that is transparent to the emission wavelength and has high crystallinity because it does not contain As that easily creates defects. As a result, the probability of non-radiative recombination of electrons and holes through the defect is reduced, and the light emission output is improved.
Further, since the first clad layer and the second clad layer sandwiching the active layer are composed of quaternary mixed crystal AlGaInP, the Al concentration is higher than that of the light emitting diode in which the clad layer is composed of ternary mixed crystal. Low and improved moisture resistance.
Since the DBR reflection film is provided between the light emitting layer and the substrate, it is possible to avoid a decrease in light emission output due to light absorption by the GaAs substrate.

According to the light emitting diode of the present invention, by adopting a configuration in which the junction area between the active layer and the clad layer is 20000-90000 μm ² , the current density is increased by making the junction area 90000 μm ² or less. While ensuring the output, the light emission recombination probability is increased and the response speed is improved. On the other hand, by setting it to 20000 μm ² or more, by suppressing the saturation of the light emission output with respect to the energization current, there is no significant decrease in the light emission output and a high output is secured.

  According to the light emitting diode of the present invention, the Al composition X1 of the well layer is 0.20 ≦ X1 ≦ 0.36, the thickness of the well layer is 3 to 30 nm, and the emission wavelength is set to 660 to 720 nm. By adopting, the response speed is high and a high output is realized as compared with the conventional red light emitting diode of 660 to 720 nm.

  According to the light-emitting diode of the present invention, the Al composition X1 of the well layer is set to 0 ≦ X1 ≦ 0.2, the thickness of the well layer is set to 3 to 30 nm, and the emission wavelength is set to 720 to 850 nm. By doing so, the response speed is high and a high output is realized as compared with the conventional infrared light emitting diode of 720 to 850 nm.

It is a top view of the light emitting diode which is one Embodiment of this invention. It is a figure for demonstrating the active layer which comprises the light emitting diode which is one Embodiment of this invention. It is a graph which shows the relationship between the number of pairs of the light emitting diode which is one Embodiment of this invention, an output, and a response speed (when the junction area of an active layer and a clad layer is 123000 micrometers ² ). It is a graph which shows the relationship between the number of pairs of the light emitting diode which is one Embodiment of this invention, an output, and a response speed (when the junction area of an active layer and a clad layer is 53000 micrometers ² ).

  Hereinafter, a light emitting diode according to an embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the drawings used in the following description, the same members are denoted by the same reference numerals or the reference numerals are omitted. Also, the drawings used in the following description are schematic, and length, width, thickness ratio, and the like may be different from actual ones.

<Light Emitting Diode (First Embodiment)>
FIG. 1 is a schematic cross-sectional view of a light-emitting diode according to the first embodiment. FIG. 2 is a schematic sectional view of a laminated structure of a well layer and a barrier layer.
The light emitting diode 100 according to the first embodiment is a light emitting diode including a DBR reflection layer 3 and a light emitting unit 20 in this order on a substrate 1, and the light emitting unit 20 has a composition formula (Al _X1 Ga _1-X1). ) An active layer 7 having a quantum well structure in which well layers 15 and barrier layers 16 made of a compound semiconductor of As (0 ≦ X1 ≦ 1) are alternately stacked, and a composition formula (Al _X2 Ga _{1 − X2} ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1), the first cladding layer 5 and the second cladding layer 6 made of a compound semiconductor, and a well layer and a barrier layer The number of pairs is 5 or less.

As shown in FIG. 1, the compound semiconductor layer (also referred to as an epitaxial growth layer) 30 has a structure in which a pn junction light emitting unit 20 and a current diffusion layer 10 are sequentially stacked. A known functional layer can be added to the structure of the compound semiconductor layer 30 as appropriate. For example, a contact layer for reducing the contact resistance of an ohmic electrode, a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, and conversely, limiting a region through which the element driving current flows. Therefore, a known layer structure such as a current blocking layer or a current confinement layer can be provided.
The compound semiconductor layer 30 is preferably formed by epitaxial growth on a GaAs substrate.

  For example, as shown in FIG. 1, the light emitting unit 20 provided on the n-type substrate has an n-type lower cladding layer (first cladding layer) 5, a lower guide layer 6, an active layer 7 on the DBR reflection layer 3. An upper guide layer 8 and a p-type upper clad layer (second clad layer) 9 are sequentially laminated. That is, the light emitting unit 20 includes a lower clad layer 5 disposed opposite to the upper side and the upper side of the active layer 7 in order to “confine” the carrier (carrier) that causes radiative recombination and light emission in the active layer 7. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 6, the upper guide layer 8, and the upper cladding layer 9 is preferable in order to obtain high-intensity light emission.

  As shown in FIG. 2, the active layer 7 forms a quantum well structure in order to control the emission wavelength of the light emitting diode (LED). That is, the active layer 7 has a multilayer structure (laminated structure) of the well layer 15 and the barrier layer 16 having a barrier layer (also referred to as a barrier layer) 16 at both ends.

The layer thickness of the active layer 7 is preferably in the range of 0.02 to 2 μm. Further, the conductivity type of the active layer 7 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  The DBR (Distributed Bragg Reflector) reflective layer 3 has two types of refractive indexes having a thickness of λ / (4n) (λ: wavelength of light to be reflected in vacuum, n: refractive index of layer material). It consists of a multilayer film in which layers are alternately stacked. When the difference between the two types of refractive indexes is large, a high reflectance can be obtained with a multilayer film having a relatively small number of layers. Instead of being reflected on a certain surface as in a normal reflecting film, the entire multilayer film is characterized by reflection based on the light interference phenomenon.

The DBR (Distributed Bragg Reflector) reflecting layer 3 is preferably formed by alternately laminating 10 to 50 pairs of two types of layers having different refractive indexes. This is because when the number is 10 pairs or less, the reflectance is too low, so that it does not contribute to an increase in output, and even when the number is 50 pairs or more, the increase in reflectance is small.
Two types of layers having different refractive indexes constituting the DBR (Distributed Bragg Reflector) reflecting layer 3 are two types of (Al _Xh Ga _1-Xh ) _{Y 3} In _{1 -Y 3} P (0 <Xh ≦ 1, Y ₃ ) having different compositions. = 0.5), (Al _Xl Ga _1-Xl ) _Y3 In _1-Y3 P; 0 ≦ Xl <1, Y3 = 0.5), and the Al composition difference ΔX = xh−xl A combination of greater than or equal to 0.5, a combination of GaInP and AlInP, or two types of Al _xl Ga _1-xl As (0.1 ≦ xl ≦ 1) and Al _xh Ga _{1 having} different compositions _-Xh As (0.1 ≦ xh ≦ 1) pair, and the high and efficient reflection is selected from any combination in which the composition difference ΔX = xh−xl of both is greater than or equal to 0.5 This is desirable because the rate is obtained.
A combination of AlGaInP having different compositions is preferable because it does not contain As that easily causes crystal defects, and GaInP and AlInP have the largest refractive index difference among them, so that the number of reflective layers can be reduced and the composition can be switched. Is also preferable because it is simple. Moreover, AlGaAs has an advantage that a large difference in refractive index is easily obtained.

The well layer 15 is made of a compound semiconductor having a composition formula (Al _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1).
The Al composition X1 is preferably 0 ≦ X1 ≦ 0.36. By making Al composition X1 into this range, it can have a desired light emission wavelength in the range of 660 nm to 850 nm.
Table 1 shows the relationship between the Al composition X1 and the emission wavelength when the thickness of the well layer 15 is 7 nm. It can be seen that the lower the Al composition X1, the longer the emission wavelength. Moreover, from the tendency of the change, the Al composition corresponding to the emission wavelength not listed in the table can be estimated.

The thickness of the well layer 15 is preferably in the range of 3 to 30 nm. More preferably, it is the range of 3-10 nm.
Table 2 shows the relationship between the thickness of the well layer 15 and the emission wavelength when the Al composition of the well layer 15 is X1 = 0.23. Table 3 shows the relationship between the thickness of the well layer 15 and the emission wavelength when the Al composition of the well layer 15 is X1 = 0.17. Table 4 shows the relationship between the thickness of the well layer 15 and the emission wavelength when the Al composition X1 of the well layer 15 is 0.02. As the layer thickness decreases, the wavelength decreases due to the quantum effect. When it is thick, the emission wavelength is determined by the composition. Further, from the tendency of the change, the layer thickness corresponding to the emission wavelength not listed in the table can be estimated.

Based on the relationship between the above emission wavelength and the Al composition X1 and the layer thickness of the well layer 15, the Al composition X1 and the layer thickness of the well layer 15 are obtained so that a desired emission wavelength within a range of 660 nm to 850 nm is obtained. Can be decided.
For example, when the Al composition X1 of the well layer 15 is 0.20 ≦ X1 ≦ 0.36 and the thickness of the well layer 15 is 3 to 30 nm, a light emitting diode having an emission wavelength of 660 to 720 nm can be manufactured. it can.
Further, by setting the Al composition X1 of the well layer 15 to 0 ≦ X1 ≦ 0.2 and the thickness of the well layer 15 to 3 to 30 nm, a light emitting diode having an emission wavelength of 720 to 850 nm can be manufactured.

The barrier layer 16 is made of a compound semiconductor having a composition formula (Al _X Ga _1-X ) As (0 <X ≦ 1). X preferably has a composition with a larger band gap than the well layer 15 in order to prevent absorption in the barrier layer 16 and increase luminous efficiency. Moreover, it is preferable that Al concentration is low from a crystalline viewpoint. Therefore, X is more preferably in the range of 0.1 to 0.4. The optimum X composition is determined by the relationship with the well layer composition. When the crystallinity is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

  The layer thickness of the barrier layer 16 is preferably equal to the layer thickness of the well layer 15 or thicker than that of the well layer 15. By sufficiently thickening the layer thickness range in which the tunnel effect occurs, spreading between the well layers due to the tunnel effect is suppressed, the carrier confinement effect is increased, the probability of recombination of electrons and holes is increased, and the light emission output Can be improved.

In the light emitting diode of the present invention, the number of pairs in which the well layers 15 and barrier layers 16 having the quantum well structure forming the active layer 7 are alternately stacked is 5 or less, and one pair may be used.
With this configuration, the carrier confinement effect is increased, the luminescence recombination probability of electrons and holes is increased, and a high response speed (rise time) of 25 nsec or less is secured.
As shown in the examples described later, the response speed increased as the number of pairs of the well layer 15 and the barrier layer 16 was decreased from 5 to 1. Under the conditions shown in the example, the highest speed of 17 nsec was realized when the number of pairs was one.
The smaller the number of quantum well layers, the narrower the region where electrons and holes are confined, so that the probability of light emission recombination increases, and as a result, the response speed increases.

If the number of the well layers 15 and the barrier layers 16 is reduced, the junction capacitance (capacitance) of the PN junction increases. This is because the well layer 15 and the barrier layer 16 are undoped or have a low carrier concentration, so that the well layer 15 and the barrier layer 16 function as a depletion layer in the pn junction, and the thinner the depletion layer, the larger the capacitance.
In general, it is desirable that the capacitance is small in order to increase the response speed. However, in the structure of the present invention, by reducing the number of the well layers 15 and the barrier layers 16, the response speed is increased even though the capacitance is increased. The effect is found.
This is presumably because the effect of increasing the recombination rate of injected carriers by reducing the number of well layers 15 and barrier layers 16 is greater.

The junction area between the active layer 7 and the lower cladding layer 5 or the upper cladding layer 9 is preferably 20000 to 90000 μm ² .

By setting the junction area between the active layer 7 and the lower cladding layer 5 or the upper cladding layer 9 to 90000 μm ² or less, the current density is increased, the light emission recombination probability is increased, and the response speed is improved.
For example, as shown in the examples described later, the bonding area between the active layer 7 and the lower cladding layer 5 or the upper cladding layer 9 is 123000 μm ² (350 μm × 350 μm) and narrower than that 53000 μm ² (230 μm × 230 μm). When the number of pairs of the well layer 15 and the barrier layer 16 is 5, the response speed is improved by about 10%, and when the number of pairs is 1, the response is 20%. Increased speed.

On the other hand, by setting the bonding area between the active layer 7 and the lower cladding layer 5 or the upper cladding layer 9 to 20000 μm ² or more, the light output is not greatly reduced, and high output is secured.
For example, as shown in the examples described later, when the junction area between the active layer 7 and the lower cladding layer 5 or the upper cladding layer 9 is 53000 μm ² , the number of pairs of the well layers 15 and the barrier layers 16 is 5 pairs. Sometimes the light emission output was 6.4 mW (response speed 20 nsec), and even with one pair, a high light emission output of 5.8 mW (response speed 13 nsec) could be maintained.

  As shown in FIG. 1, the lower guide layer 6 and the upper guide layer 8 are provided on the lower surface and the upper surface of the active layer 7, respectively. Specifically, the lower guide layer 6 is provided on the lower surface of the active layer 7, and the upper guide layer 8 is provided on the upper surface of the active layer 7.

The lower guide layer 6 and the upper guide layer 8 have a composition of (Al _X Ga _1-X ) As (0 <X ≦ 1). The Al composition X is preferably a composition having a band gap equal to or larger than that of the barrier layer 15, and more preferably in the range of 0.2 to 0.6. The optimum X composition from the viewpoint of crystallinity is determined by the relationship with the composition of the well layer. When the crystallinity is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

Table 5 shows the Al composition X of the barrier layer 16 and the guide layer that maximizes the light emission output at the light emission wavelength when the well layer 15 has a layer thickness of 7 nm. The barrier layer and the guide layer preferably have a composition with a larger band gap than that of the well layer. However, the optimum composition is determined in relation to the composition of the well layer in order to improve the crystallinity and improve the light emission output. When the crystallinity is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

  The lower guide layer 6 and the upper guide layer 8 are provided to reduce the propagation of defects in the lower cladding layer 5, the upper cladding layer 9, and the active layer 7, respectively. That is, the V group constituent element of the lower guide layer 6, the upper guide layer 8 and the active layer 7 is arsenic (As), whereas in the present invention, the V group constituent element of the lower cladding layer 5 and the upper cladding layer 9 is phosphorus ( Therefore, defects are likely to occur at the interface. Propagation of defects to the active layer 7 causes a reduction in the performance of the light emitting diode. For this reason, the thickness of the lower guide layer 6 and the upper guide layer 8 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.

The conductivity types of the lower guide layer 6 and the upper guide layer 8 are not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  As shown in FIG. 1, the lower cladding layer 5 and the upper cladding layer 9 are provided on the lower surface of the lower guide layer 6 and the upper surface of the upper guide layer 8, respectively.

The lower cladding layer 5 and the upper cladding layer 9 are made of a compound semiconductor of (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1), and have a band higher than that of the barrier layer 16. A material having a large gap is preferable, and a material having a larger band gap than the lower guide layer 6 and the upper guide layer 8 is more preferable. As the _{material, (Al X2 Ga 1-X2} ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0 <Y1 ≦ 1) Al composition X2 has a composition which is 0.3 to 0.7 It is preferable. Y1 is preferably 0.4 to 0.6.

  The lower clad layer 5 and the upper clad layer 9 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 5 and the upper clad layer 9 can be in a known suitable range, and it is preferable to optimize the conditions so that the luminous efficiency of the active layer 7 is increased. Further, the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the lower cladding layer 5 and the upper cladding layer 9.

Specifically, as the lower clad layer 5, for example, p-type (Al _X2 Ga ₁ -X 2) _{Y 1} In ₁ -Y ₁ P doped with Mg (0.3 ≦ X 2 ≦ 0.7, 0.4 ≦ It is desirable to use a semiconductor material composed of Y1 ≦ 0.6). The carrier concentration is preferably in the range of 2 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm.

On the other hand, as the upper clad layer 9, for example, Si-doped n-type (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0.3 ≦ X2 ≦ 0.7, 0.4 ≦ Y1 ≦ 0) .6) is preferably used. The carrier concentration is preferably in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm. The polarities of the lower clad layer 5 and the upper clad layer 9 can be selected in consideration of the element structure of the compound semiconductor layer 2.

  Further, above the constituent layers of the light emitting unit 7, a contact layer for lowering the contact resistance of the ohmic electrode, a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely A known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.

As shown in FIG. 4, the current spreading layer 10 is provided below the light emitting unit 7. The current diffusion layer 10 relaxes strain generated by the active layer 12 when the compound semiconductor layer 2 is epitaxially grown on the GaAs substrate.
The current spreading layer 10 may be made of a material that is transparent with respect to the emission wavelength from the light emitting unit 7 (active layer 7), for example, GaP. When GaP is applied to the current diffusion layer 10, bonding can be facilitated and high bonding strength can be obtained by using the functional substrate 3 as a GaP substrate.
The thickness of the current spreading layer 10 is preferably in the range of 0.5 to 20 μm. If the thickness is 0.5 μm or less, current diffusion is insufficient, and if it is 20 μm or more, the cost for crystal growth to the thickness increases.

  The p-type ohmic electrode (first electrode) 12 is a low-resistance ohmic contact electrode provided on the main light extraction surface of the light-emitting diode 100, and the n-type ohmic electrode (second electrode) 13 is a substrate of the light-emitting diode 100. It is a low-resistance ohmic contact electrode provided on the side back surface. Here, the p-type ohmic electrode 12 is provided on the surface of the current diffusion layer 10, and for example, an alloy made of AuBe / Au or AuZn / Au can be used. On the other hand, the n-type ohmic electrode 13 can be made of, for example, an alloy made of AuGe or Ni alloy / Au.

<Method for manufacturing light-emitting diode>
Next, the manufacturing method of the light emitting diode 100 of this embodiment is demonstrated using FIG.

(Formation process of compound semiconductor layer)
First, the compound semiconductor layer 30 shown in FIG. 1 is produced. The compound semiconductor layer 30 includes an n-type GaAs substrate 1 on which a buffer layer 2 made of GaAs, a layer 3a made of GaInP (a layer having a high refractive index) 3a and a layer 3b made of AlInP (a layer having a low refractive index) 3b are alternately arranged. 40 pairs of DBR reflection layers 3, Si-doped n-type lower cladding layer 5, lower guide layer 6, active layer 7, upper guide layer 8, Mg-doped p-type upper cladding layer 9, Mg-doped p A current diffusion layer 10 made of type GaP is sequentially stacked.

As the GaAs substrate 1, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface on which the GaAs substrate 1 is epitaxially grown is preferably smooth. The plane orientation of the surface of the GaAs substrate 1 is easy to epitaxially grow, and a substrate that is turned off within ± 20 ° from the (100) plane and (100) that are mass-produced is desirable from the standpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate 1 is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction.
In this specification, in the notation of Miller index, “-” means a bar attached to the index immediately after that.

The dislocation density of the GaAs substrate 1 is desirably low in order to improve the crystallinity of the compound semiconductor layer 30. Specifically, for example, 10,000 pieces cm ⁻² or less, preferably 1,000 pieces cm ⁻² or less are suitable.

The GaAs substrate 1 may be n-type or p-type. The carrier concentration of the GaAs substrate 1 can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate 1 is Si-doped n-type, the carrier concentration is preferably in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . On the other hand, when the GaAs substrate 1 is a Zn-doped p-type, the carrier concentration is preferably in the range of 2 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ .

  The thickness of the GaAs substrate 1 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 1 is thinner than an appropriate range, the compound semiconductor layer 30 may be broken during the manufacturing process. On the other hand, if the thickness of the GaAs substrate 1 is thicker than an appropriate range, the material cost increases. For this reason, when the substrate size of the GaAs substrate 1 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 μm is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 μm is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 μm is desirable.

  Thus, by increasing the thickness of the substrate according to the substrate size of the GaAs substrate 1, it is possible to reduce the warpage of the compound semiconductor layer 30 caused by the light emitting unit 20. As a result, the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 7 can be reduced. The shape of the GaAs substrate 1 is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.

  The buffer layer 2 is provided to reduce the propagation of defects between the GaAs substrate 1 and the constituent layers of the light emitting unit 20. For this reason, the buffer layer 2 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The material of the buffer layer 2 is preferably the same as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 2 in the same manner as the GaAs substrate 1. The buffer layer 2 may be a multilayer film made of a material different from that of the GaAs substrate 1 in order to reduce the propagation of defects. The thickness of the buffer layer 2 is preferably 0.1 μm or more, and more preferably 0.2 μm or more.

The DBR reflection layer 3 is provided to reflect light traveling in the substrate direction. The material of the DBR reflective layer 3 is preferably transparent with respect to the emission wavelength, and is preferably selected so as to be a combination that increases the difference in refractive index between the two types of materials constituting the DBR reflective layer 3. . In this embodiment, the material of the DBR reflective layer 3 is a combination of AlInP and GaInP, but two types of (Al _Xl Ga _1-Xl ) _0.5 In _0.5 P (0 ≦ xl <1) having different compositions are used. , (Al _Xh Ga _1-Xh ) _0.5 In _0.5 P (0 <xh ≦ 1), and two types of Al _xl Ga _1-xl As (0. It is also possible to select from 1 ≦ xl ≦ 1) and Al _xh Ga _1-xh As (0.1 ≦ xh ≦ 1).

  In the present embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is most desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, the GaAs substrate 1 used for the epitaxial growth of the compound semiconductor layer 30 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film. The layers constituting the compound semiconductor layer 30 can be stacked by setting a GaAs substrate 1 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing the layers. As the MOCVD apparatus, a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.

When the layers of the compound semiconductor layer 30 are epitaxially grown, examples of the group III constituent material include trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) can be used. Further, as a Mg doping raw material, for example, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si ₂ H ₆ ) or the like can be used.
In addition, phosphine (PH ₃ ), arsine (AsH ₃ ), or the like can be used as a raw material for the group V constituent element.
As the growth temperature of each layer, when p-type GaP is used as the current diffusion layer 10, 720 to 770 ° C. can be applied, and for the other layers, 600 to 700 ° C. can be applied.
Further, when p-type GaInP is used as the current diffusion layer 10, 600 to 700 ° C. can be applied.
Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.

  The compound semiconductor layer 30 produced in this way has a good surface state with few crystal defects despite having the light emitting portion 20. The compound semiconductor layer 30 may be subjected to surface processing such as polishing corresponding to the element structure.

(First and second electrode forming steps)
Next, a p-type ohmic electrode 12 that is a first electrode and an n-type ohmic electrode 13 that is a second electrode are formed.

<Light Emitting Diode (Second Embodiment)>
In the light emitting diode according to the second embodiment to which the present invention is applied, the AlGaAs barrier layer 16 in the light emitting diode according to the first embodiment is composed of the composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P (0 The difference is that the barrier layer is made of a compound semiconductor of ≦ X3 ≦ 1, 0 <Y2 ≦ 1).

The barrier layer is made of a compound semiconductor having a composition formula ( _{AlX3Ga1 -X3} ) _{Y2In1 -Y2P} (0≤X3≤1, 0 <Y2≤1).
The Al composition X3 is preferably a composition having a larger band gap than the well layer, and specifically, a range of 0 to 0.2 is preferable.
Y2 is preferably 0.4 to 0.6 and more preferably 0.45 to 0.55 in order to prevent generation of distortion due to lattice mismatch with the substrate.
The layer thickness of the barrier layer is preferably equal to or greater than the layer thickness of the well layer. By sufficiently thickening the layer thickness range in which the tunnel effect occurs, spreading between the well layers due to the tunnel effect is suppressed, the carrier confinement effect is increased, the probability of recombination of electrons and holes is increased, and the light emission output Can be improved.

  Hereinafter, the effect of the present invention will be specifically described with reference to examples. The present invention is not limited to these examples.

  In this example, an example in which a light-emitting diode according to the present invention is manufactured will be specifically described. In addition, the light emitting diode manufactured in this example includes a light emitting diode having an active layer having a quantum well structure of a well layer made of AlGaAs and a barrier layer made of AlGaAs, and a barrier layer made of AlGaAs and a barrier layer made of AlGainP. And an infrared light emitting diode having an active layer having a quantum well structure. In this example, a light-emitting diode lamp in which a light-emitting diode chip was mounted on a substrate was prepared for characteristic evaluation.

Example 1
The light-emitting diode of Example 1 was an example of the first embodiment, and the junction area between the active layer and the cladding layer was 123000 μm ² (350 μm × 350 μm).
First, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si. In the GaAs substrate, a plane inclined by 15 ° in the (0-1-1) direction from the (100) plane was used as a growth plane, and the carrier concentration was set to 2 × 10 ¹⁸ cm ⁻³ . The layer thickness of the GaAs substrate was about 0.5 μm. As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type DBR reflective layer having a 40-pair repeating structure of Si-doped AlInP and GaInP, and Si-doped (Al _0.7 N-type lower cladding layer made of Ga _0.3 ) _0.5 In _0.5 P, lower guide layer made of Al _0.4 Ga _0.6 As, Al _0.17 Ga _0.83 As / Al _0. Well layer / barrier layer composed of ₃ Ga _0.7 As pairs, upper guide layer composed of Al _0.4 Ga _0.6 As, Mg-doped (Al _0.7 Ga _0.3 ) _0.5 In _{0 .5} P p-type upper clad layer, (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P thin film intermediate layer, Mg-doped p-type GaP current diffusion layer It was.

In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In) are used as the raw material for the group III constituent element did. Further, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) was used as a Mg doping material. Further, disilane (Si ₂ H ₆ ) was used as a Si doping material. Further, phosphine (PH ₃ ) and arsine (AsH ₃ ) were used as raw materials for the group V constituent elements. As the growth temperature of each layer, the current diffusion layer made of p-type GaP was grown at 750 ° C. The other layers were grown at 700 ° C.

The buffer layer made of GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The lower cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The lower guide layer was undoped and had a thickness of about 50 nm. The well layer was undoped Al _0.17 Ga _0.83 As with a thickness of about 7 nm, and the barrier layer was undoped Al _0.3 Ga _0.7 As with a thickness of about 19 nm. Three pairs of well layers and barrier layers were alternately laminated. The upper guide layer was undoped and had a thickness of about 50 nm. The upper cladding layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 50 nm. The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 10 μm.
Alternating addition, DBR reflection layer and the carrier concentration of about 1 × ¹⁰ 18 ^{cm -3,} and AlInP that were about 71nm thickness, carrier concentration of about 1 × ¹⁰ 18 ^{cm -3,} a thickness of about 67nm was GaInP the 40 pairs were stacked.

  Next, a film was formed on the surface of the current diffusion layer by vacuum deposition so that AuBe was 0.2 μm and Au was 1 μm. Thereafter, patterning was performed using a general photolithography means, and a p-type ohmic electrode was formed as the first electrode. Next, a roughening treatment was performed on the light extraction surface which is a surface other than the electrode portion.

  Next, a second electrode is formed on the back surface of the substrate by vacuum deposition so that AuGe and Ni alloy have a thickness of 0.5 μm, Pt of 0.2 μm, and Au of 1 μm, and an n-type ohmic electrode is formed. Formed. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.

  Next, a dicing saw was used to cut from the compound semiconductor layer side at 350 μm intervals to form chips. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.

  100 light emitting diode lamps each having the light emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled. This light-emitting diode lamp was manufactured by supporting (mounting) a mount with a die bonder, wire-bonding a p-type ohmic electrode and a p-electrode terminal with a gold wire, and sealing with a general epoxy resin.

The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are shown in Table 6, FIG. 3 and FIG. FIG. 3 is a graph showing the relationship between the number of pairs of light emitting diodes and the output and response speed when the junction area between the active layer and the clad layer is 123000 μm ² , and FIG. 4 shows the junction between the active layer and the clad layer. It is a graph which shows the relationship between the number of pairs of a light emitting diode in case an area is 53000 micrometers ² , output, and a response speed.
As shown in Table 6, in the first example, when a current was passed between the n-type and p-type ohmic electrodes, red light having a peak emission wavelength of 730 nm was emitted. The forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was 1.6 volts. When the forward current was 20 mA, the response speed (rise time) tr and the light emission output (P ₀ ) were 15 nsec and 5.5 mW, respectively.

(Example 2)
The light-emitting diode of Example 2 is an example of the first embodiment, and was manufactured under the same conditions as in Example 1 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. .
The response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 18 nsec, 5.8 mW, and 1.6 V, respectively.

(Example 3)
The light-emitting diode of Example 3 is an example of the first embodiment, and was manufactured under the same conditions as in Example 1 except that the number of pairs of well layers and barrier layers was five, and the same evaluation was performed. .
The response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 21 nsec, 6.0 mW, and 1.6 V, respectively.

Example 4
The light emitting diode of Example 4 was produced under the same conditions as in Example 3 except that the configuration of the DBR reflective layer was changed, and the same evaluation was performed.
Specifically, the DBR reflective layer has (Al _0.9 Ga _0.1 ) _0.5 In _0.5 P with a carrier concentration of about 1 × 10 ¹⁸ cm ^{−3 and a} layer thickness of about 71 nm, and a carrier concentration. (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P with a thickness of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 68 nm were stacked alternately.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 21 nsec, 5.7 mW, and 1.6 V, respectively.

(Example 5)
The light emitting diode of Example 5 was produced under the same conditions as in Example 3 except that the configuration of the DBR reflective layer was changed, and the same evaluation was performed.
Specifically, DBR reflective layer was about 1 × ¹⁰ 18 carrier concentration ^{cm -3,} and _Al 0.9 _{Ga 0.1} As that were about 71nm thickness, a carrier concentration of about 1 × ¹⁰ 18 ^{cm -3} 40 pairs of Al _0.1 Ga _0.9 As having a layer thickness of about 64 nm were alternately laminated.
The response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 20 nsec, 6.1 mW, and 1.6 V, respectively.

The light emitting diodes of Examples 6 to 8 are also examples of the first embodiment, but are examples in which the junction area between the active layer and the cladding layer is 53000 μm ² (230 μm × 230 μm).

(Example 6)
The light-emitting diode of Example 6 was fabricated under the same conditions as in Example 1 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 13 nsec, 5.8 mW, and 1.7 V, respectively.

(Example 7)
The light emitting diode of Example 7 was fabricated under the same conditions as in Example 6 except that the number of pairs of the well layer and the barrier layer was 3, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 17 nsec, 6.2 mW, and 1.7 V, respectively.

(Example 8)
The light emitting diode of Example 8 was produced under the same conditions as in Example 6 except that the number of pairs of well layers and barrier layers was 5, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 20 nsec, 6.4 mW, and 1.7 V, respectively.

Example 9
Although the light emitting diode of Example 9 is also an example of the first embodiment, the junction area between the active layer and the cladding layer is 20000 μm ² (200 μm × 100 μm).

The light emitting diode of Example 9 was fabricated under the same conditions as in Example 3 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 17 nsec, 6.5 mW, and 1.8 V, respectively.

(Example 10)
The light-emitting diode of Example 10 is also an example of the first embodiment, but is an example in which the junction area between the active layer and the cladding layer is 90000 μm ² (300 μm × 300 μm).

The light emitting diode of Example 10 was fabricated under the same conditions as in Example 3 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 21 nsec, 6.2 mW, and 1.6 V, respectively.

  The light emitting diodes of Examples 11 and 12 are examples of the second embodiment.

(Example 11)
The light-emitting diode of Example 11 is an example in which the junction area between the active layer and the cladding layer is 123000 μm ² (350 μm × 350 μm).
The layer structure of the light-emitting diode of Example 11 is as follows.
First, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si. In the GaAs substrate, a plane inclined by 15 ° in the (0-1-1) direction from the (100) plane was used as a growth plane, and the carrier concentration was set to 2 × 10 ¹⁸ cm ⁻³ . The layer thickness of the GaAs substrate was about 0.5 μm. As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type DBR reflective layer having a 40-pair repeating structure of Si-doped AlInP and GaInP, and Si-doped (Al _0.7 N-type lower cladding layer made of Ga _0.3 ) _0.5 In _0.5 P, lower guide layer made of Al _0.4 Ga _0.6 As, Al _0.17 Ga _0.83 As / (Al _{0 .1} Ga _0.9 ) _0.5 In _0.5 P well layer / barrier layer, Al _0.4 Ga _0.6 As upper guide layer, Mg doped (Al _0.7 Ga _0.3) p-type upper cladding layer composed of _0.5 in _{0.5 P,} an intermediate layer of a thin film made of _{(Al 0.5 Ga 0.5) 0.5 in} 0.5 P, p which is Mg-doped A current spreading layer made of type GaP It was.
The buffer layer made of GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 3.5 μm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The upper guide layer was undoped and had a thickness of about 50 nm. The well layer is undoped Al _0.17 Ga _0.83 As with a layer thickness of about 7 nm, and the barrier layer is undoped (Al _0.1 Ga _0.9 ) _0.5 In _{0. 5} P. The number of pairs of well layers and barrier layers was set to 5. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.05 μm. The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 9 μm.
The response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 21 nsec, 5.8 mW, and 1.6 V, respectively.

(Example 12)
The light-emitting diode of Example 12 was produced under the same conditions as Example 11 except that the junction area between the active layer and the cladding layer was 53000 μm ² (230 μm × 230 μm), and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 20 nsec, 6.3 mW, and 1.7 V, respectively.

  Reference Examples 1 to 4 are examples in which the number of pairs of the well layer and the barrier layer is 10 pairs and 20 pairs, and the ternary mixed crystal quantum well structure or the ternary mixed crystal well layer and the quaternary mixed layer of the present invention are used. This is to show that a structure in which a quantum well structure composed of a crystal barrier layer is sandwiched between quaternary cladding layers is suitable for high light emission output.

(Reference Example 1)
The light emitting diode of Reference Example 1 was produced under the same conditions as the light emitting diode of Example 1 except that the number of pairs of well layers and barrier layers was 10, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 26 nsec, 6.3 mW, and 1.6 V, respectively.

(Reference Example 2)
The light emitting diode of Reference Example 2 was produced under the same conditions as those of the light emitting diode of Example 1 except that the number of pairs of well layers and barrier layers was 20, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 35 nsec, 6.7 mW, and 1.6 V, respectively.

(Reference Example 3)
The light emitting diode of Reference Example 3 was produced under the same conditions as the light emitting diode of Example 6 except that the number of pairs of well layers and barrier layers was 10, and the same evaluation was performed.
The response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 25 nsec, 6.8 mW, and 1.7 V, respectively.

(Reference Example 4)
The light emitting diode of Reference Example 4 was produced under the same conditions as those of the light emitting diode of Example 6 except that the number of pairs of well layers and barrier layers was 20, and the same evaluation was performed.
The response speed (tr), light emission output (P ₀ ), and forward voltage (V _F ) were 32 nsec, 7.0 mW, and 1.7 V, respectively.

(Comparative Example 1)
An example of a light emitting diode having a light emission wavelength of 730 nm having a structure in which a thick film is grown and a substrate is removed by a liquid phase epitaxial method is shown.
An AlGaAs layer was grown on a GaAs substrate using a slide boat type growth apparatus.
A p-type GaAs substrate was set in a substrate storage groove of a slide boat type growth apparatus, and Ga metal, GaAs polycrystal, metal Al, and a dopant were put in a crucible prepared for growth of each layer. The growing layer has a four-layer structure of a transparent thick film layer (first p-type layer), a lower clad layer (p-type clad layer), an active layer, and an upper clad layer (n-type clad layer). did.
A slide boat type growth apparatus in which these raw materials are set is set in a quartz reaction tube, heated to 950 ° C. in a hydrogen stream, dissolved, and then the ambient temperature is lowered to 910 ° C. After pressing and bringing into contact with the raw material solution (melt), the temperature is lowered at a rate of 0.5 ° C./min. After reaching the predetermined temperature, the operation of repeatedly touching each raw material solution after pressing the slider is repeated repeatedly. Specifically, after contact with the melt, the atmospheric temperature was lowered to 703 ° C. to grow the n-clad layer, and then the slider was pushed to separate the raw material solution from the wafer to complete the epitaxial growth.

The structure of the obtained epitaxial layer is as follows: the first p-type layer has an Al composition X1 = 0.3 to 0.4, the layer thickness is 64 μm, the carrier concentration is 3 × 10 ¹⁷ cm ⁻³ , and the p-type cladding layer is Al Composition X2 = 0.4 to 0.5, layer thickness 79 μm, carrier concentration 5 × 10 ¹⁷ cm ⁻³ , p-type active layer has a composition with an emission wavelength of 760 nm, layer thickness 1 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³ , the n-type cladding layer had an Al composition X4 = 0.4 to 0.5, a layer thickness of 25 μm, and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ .

  After the epitaxial growth was completed, the epitaxial substrate was taken out, the n-type GaAlAs cladding layer surface was protected, and the p-type GaAs substrate was selectively removed with an ammonia-hydrogen peroxide etchant. Thereafter, gold electrodes were formed on both sides of the epitaxial wafer, and a surface electrode in which a wire bonding pad having a diameter of 100 μm was arranged at the center was formed using an electrode mask having a long side of 350 μm. On the back electrode, ohmic electrodes having a diameter of 20 μm were formed at intervals of 80 μm. Thereafter, separation and etching were performed by dicing, so that a 350 μm square light-emitting diode in which the n-type GaAlAs layer was on the surface side was produced.

Table 4 shows the results of mounting the light emitting diode of Comparative Example 1 and evaluating the characteristics of the light emitting diode lamp.
As shown in Table 4, when a current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 760 nm was emitted. The forward voltage (V _F ) when a current of 20 mA (mA) was passed in the forward direction was 1.9 volts (V).
The response speed (tr) and the light emission output (P ₀ ) when the forward current was 20 mA were 25 nsec and 3.0 mW, respectively.
For any sample of Comparative Example 1, the response speed was equal or slower than that of Examples 1 to 16 of the present invention, and the light emission output was low.

  The light emitting diode, the light emitting diode lamp, and the lighting device of the present invention can be used as a light emitting diode, a light emitting diode lamp, and a lighting device that emits red light and / or infrared light having both high-speed response and high output.

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate 2 ... Buffer layer 3 ... DBR reflection layer 3a ... 1st component layer of DBR reflection layer 3b ... 2nd component layer of DBR reflection layer 5 ... Lower part Cladding layer (first cladding layer)
6 ... Lower guide layer (first guide layer)
7 ... Active layer 8 ... Upper guide layer (second guide layer)
9: Upper clad layer (second clad layer)
10 ... current diffusion layer 12 ... p-type ohmic electrode (first electrode)
13 ... n-type ohmic electrode (second electrode)
DESCRIPTION OF SYMBOLS 20 ... Light emission part 30 ... Compound semiconductor layer 100 ... Light emitting diode

Claims (10)

A light-emitting diode comprising a DBR reflective layer and a light-emitting unit on a substrate in order,
The light emitting portion includes an active layer having a quantum well structure in which well layers and barrier layers made of a compound semiconductor having a composition formula (Al _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) are alternately stacked, and the active layer A first clad layer and a second clad layer made of a compound semiconductor having a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) are provided. And
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. A light-emitting diode comprising a DBR reflective layer and a light-emitting unit on a substrate in order,
The light emitting portion includes a well layer made of a compound semiconductor having a composition formula (Al _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), a composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1) An active layer having a quantum well structure in which barrier layers made of compound semiconductors are alternately stacked, and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In ₁ sandwiching the active layer _A first cladding layer and a second cladding layer made of a compound semiconductor of _-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1),
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. 3. The light emitting diode according to claim 1, wherein a junction area between the active layer and the clad layer is 20000 to 90000 μm ² .   2. The Al composition X1 of the well layer is set to 0.20 ≦ X1 ≦ 0.36, the thickness of the well layer is set to 3 to 30 nm, and an emission wavelength is set to 660 to 720 nm. 4. The light emitting diode according to any one of items 1 to 3.   The Al composition X1 of the well layer is 0 ≦ X1 ≦ 0.2, the thickness of the well layer is 3 to 30 nm, and the emission wavelength is set to 720 to 850 nm. The light-emitting diode according to any one of the above.   6. The light emitting diode according to claim 1, wherein the DBR reflective layer is formed by alternately laminating 10 to 50 pairs of two kinds of layers having different refractive indexes. The two types of layers having different refractive indices are composed of two types of (Al _Xh Ga _1-Xh ) _{Y 3} In _{1 -Y 3} P (0 <Xh ≦ 1, Y 3 = 0.5), (Al _Xl Ga _{1− Xl} ) _{Y3In1 -Y3P} ; 0 ≦ Xl <1, Y3 = 0.5), and the difference between the two Al compositions ΔX = xh−xl is greater than or equal to 0.5, The light emitting diode according to claim 6.   The light emitting diode according to claim 6, wherein the two types of layers having different refractive indexes are a combination of GaInP and AlInP. The two types of layers having different refractive indexes are composed of two types of Al _xl Ga _1-xl As (0.1 ≦ xl ≦ 1) and Al _xh Ga _1-xh As (0.1 ≦ xh ≦ 1) having different compositions. The light-emitting diode according to claim 6, wherein the light-emitting diode is a combination, and the difference in composition ΔX = xh−xl between the two Al is greater than or equal to 0.5. 10. The light-emitting diode according to claim 1, further comprising a current diffusion layer on a surface of the light-emitting portion opposite to the DBR reflection layer.

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