JP3587699B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

Info

Publication number
JP3587699B2
JP3587699B2 JP27323898A JP27323898A JP3587699B2 JP 3587699 B2 JP3587699 B2 JP 3587699B2 JP 27323898 A JP27323898 A JP 27323898A JP 27323898 A JP27323898 A JP 27323898A JP 3587699 B2 JP3587699 B2 JP 3587699B2
Authority
JP
Japan
Prior art keywords
layer
window layer
light emitting
semiconductor light
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27323898A
Other languages
Japanese (ja)
Other versions
JP2000101132A (en
Inventor
弘之 細羽
孝尚 倉橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP27323898A priority Critical patent/JP3587699B2/en
Publication of JP2000101132A publication Critical patent/JP2000101132A/en
Application granted granted Critical
Publication of JP3587699B2 publication Critical patent/JP3587699B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Led Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、基板の上に化合物半導体結晶を積層して構成される半導体発光素子に関し、特に、積層表面における結晶欠陥を低減し、平坦化する技術に関する。
【0002】
【従来の技術】
基板の上に化合物半導体結晶を積層して構成される半導体発光素子は、結晶格子の長さが0.5%以上異なる格子不整合結晶を利用できるようになって以来、青色から赤外までの広い波長領域で高輝度の発光が可能となってきた。
【0003】
例えば、米国特許5,008,718号公報に記載されている緑色発光する半導体発光素子は、図11の如き構造を有する(以下、「従来例1」という)。該半導体発光素子1100は以下のような手順で作製される。
【0004】
図11において、n型GaAs仮基板(図示せず)の上に該仮基板に格子整合したn型InAlGaP第1クラッド層102、ノンドープInAlGaP発光層103、p型InAlGaP第2クラッド層104、並びにp型GaP窓層105を成長する。GaAs仮基板(図示せず)を除去した後、前記n型第1クラッド層102上に透明基板層109を成長し、半導体発光素子用ウェハーとする。
【0005】
次に、透明基板層109上に、n側電極107を設ける。窓層105の電極形成面105aの中央部に円形のp側電極106を設ける。前記ウェハーを300μm角程度の大きさに分割して、図11の半導体発光素子1100が作製される。両電極106、107は外部導体と電気的に接続される。例えばp側電極106には外部導体(図示せず)と接続された直径30μm程度の金属ワイヤ(図示せず)がボンディングされる。
【0006】
半導体発光素子の輝度を高くするため、窓層105にはGaPを用いている。GaPは結晶格子の値が前記仮基板のGaAs結晶に比べて約3.4%も小さく、格子不整合結晶であるが、バンドギャップが発光層103のInAlGaP結晶のバンドギャップより十分大きいため、発光層103で発生する発光層103のバンドギャップに近いエネルギーの波長の光に対し窓層105の透過率を十分高く保つことができる。その結果、発光層103から出た光の窓層105による吸収を低減し、半導体発光素子の輝度を高くすることができる。
【0007】
半導体発光素子の輝度を高くするには窓層105の抵抗値を低くすることも重要である。両電極106、107から電流を注入すると発光層103で波長560nmの緑色発光が生じる。窓層105の抵抗値が高い場合、p側電極106から注入された電流は横方向への広がりが少ないため、発光層103のp側電極106に対向する部分で集中して発光が生じる。発光層3で発生した光のうち、半導体発光素子と外部との境界面に略垂直に入射する光は効率よく半導体発光素子外部に出力されるが、その他の光は前記境界面で反射され、半導体発光素子の輝度に寄与しない。したがって、発光層103のp側電極106に対向する部分で発光が生じた場合、前記境界面に垂直に入射する光も該p側電極106で反射され、半導体発光素子の輝度が低下する。
【0008】
抵抗値を下げる方法として窓層105のp型不純物濃度を高くする方法が良く知られている。ところが、典型的なp型不純物であるZn(亜鉛)、Mg(マグネシウム)、Be(ベリリウム)等は結晶中を拡散しやすい物質であり、窓層105のp型不純物濃度を高くすると発光層3までp型不純物が拡散し、該発光層3における電流の光への変換効率そのものが低下し、半導体発光素子の輝度が低下する。
【0009】
このような問題を解決するため、特開平5−335619号公報では、窓層を2層構造とし、活性層に近い窓層のp型不純物濃度を低く、活性層から遠い窓層のp型不純物濃度を高くして、電流が発光層全体に広がるようにするとともに、p型不純物が発光層にまで拡散することを防止して半導体発光素子の輝度が低下することを防ぐ技術が開示されている(以下、「従来例2」という)。
【0010】
図12に、従来例2の半導体発光素子1200の略断面図を示す。半導体基板101に、窓層105を2層構造とし、活性層に近い第1窓層111と活性層から遠い第2窓層112とにより、窓層105を構成している。
【0011】
従来例2の半導体発光素子では、窓層105にGaAlAsを用いているが、GaAlAsはバンドギャップが狭く、緑色光に対しては透過率が低い。本発明者らは窓層をバンドギャップの大きいGaPとしても同様の効果が得られることを確認した(以下「従来例の半導体発光素子」という)。
【0012】
【発明が解決しようとする課題】
しかしながら、窓層に用いるGaPのp型不純物濃度を高くすると、多数の結晶欠陥がp側電極形成面に発生し、該結晶欠陥によりp側電極形成面に凹凸が発生する。p側電極106は面積が直径約100μm程度と狭いため、p側電極形成面105aに凹凸があるとウェハーを分割し、p側電極106にワイヤーをボンディングして半導体発光素子を作成するプロセスにおいて、p側電極106が窓層105から剥がれ易いという問題がある。
【0013】
上記結晶欠陥のうち、ヒロック(hill−rock)と呼ばれる結晶欠陥が最も重要である。このヒロック欠陥は、基板と異なる面方位の結晶面が生じるために発生する突起状の欠陥である。いったんヒロック欠陥が発生するとその上に成長される結晶によって平坦化されず、突起状の形状が保たれたまま結晶成長する。本発明者らはヒロック欠陥は、下地よりp型不純物濃度が高い層を成長する初期の段階で発生すること、成長層のp型不純物濃度が高いほど大量に発生することを見出した。
【0014】
ヒロック欠陥が発生する理由としては、不純物濃度を高くするために、不純物材料を急激に増加させた時、GaPの主要構成元素であるGaやPの動きが不純物材料により一時的に妨げられ、成長中の結晶表面全体に均一に分散できないことが原因と考えられる。特にP、As、N、Sb等のV族元素は動きにくく、III族元素と結合して移動するため、同時に使用するIII族元素の種類が結晶欠陥の発生の有無と関係が大きい。例えばIII族元素がGaの場合、V族元素との結合が弱いために、V族元素が外れやすい。その結果、下地より不純物濃度の高い層の成長初期においてV族元素が均一に分散せず、ヒロックが発生するものと考えられる。
【0015】
本発明は、III−V族化合物半導体結晶の主要構成元素であるIII族元素とV族元素が結晶成長過程において結晶表面全体に均一に分散するようにして、ヒロック等の結晶欠陥の発生を抑え、電極形成面の凹凸を減らして平坦化し、上記半導体発光素子作成プロセスにおいて電極の剥がれが生じにくい半導体発光素子用ウェハーを提供することを目的とする。
【0016】
【課題を解決するための手段】
本発明の請求項1記載の半導体発光素子は、基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、該基板には下部電極、および該窓層には上部電極が形成され、該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とから なり、該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、前記第1窓層と第2窓層の界面があり、前記第1窓層の前記界面近傍の部分前記第1窓層における前記部分と隣接する部分よりIn ( インジウム)元素の組成比が高く前記第2窓層の前記界面近傍の部分は、前記第2窓層における前記部分と隣接する部分よりIn元素の組成比が高く前記第1,第2窓層はIn w Ga x4 Al 1-w-x4 P(但し、0≦w≦1、0≦x4≦1)からなることを特徴とするものである。
【0017】
また、請求項2記載の半導体発光素子の半導体の各層は次の構成よりなることを特徴とするものである。
【0018】
半導体基板:GaAs、
第1クラッド層:In0.5(Gax1Al1-x10.5P(但し、0≦x1≦1)、
活性層:In0.5(Gax2Al1-x20.5P(但し、0≦x2<1)、または、GayAl1-yAs(但し、0≦y≦1)、または、InzGa1-zAs(但し、0≦z<1)、
第2クラッド層:In0.5(Gax3Al1-x30.5P(但し、0≦x3≦1)。
【0019】
【0020】
また、請求項記載の半導体発光素子は、前記第2クラッド層と前記第1窓層の界面があり、前記第1窓層の前記界面近傍の部分は、前記第1窓層における前記部分と隣接する部分よりIn元素の組成比こと特徴とするものである。
【0021】
また、請求項記載の半導体発光素子は、基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、該基板および該窓層の片面にはそれぞれ電極が形成され、該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とからなり、該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、前記第1窓層と第2窓層の界面近傍において、前記発光層から離れるにしたがって前記第2窓層内の不純物濃度を漸次増加させ、前記第1窓層と第2窓層の界面近傍おける前記第2窓層内のIn組成比を不純物濃度の増加にほぼ比例して漸次増加させたことを特徴とするものである。
【0022】
また、請求項記載の半導体発光素子は、前記第2クラッド層と前記第1窓層の界面近傍の前記第1窓層内の不純物濃度を漸次増加させたことを特徴とするものである。
【0023】
【0024】
また、請求項記載の半導体発光素子は、前記第2クラッド層と前記第1窓層との界面上に電流阻止層を配設し、且つ、該電流阻止層の形状は上部電極の形状とほぼ相似形であることを特徴とするものである。
【0025】
また、請求項記載の半導体発光素子は、前記電流阻止層が次の構成よりなることを特徴とするものである。
電流阻止層:InvAlx6Ga1-v-x6P(但し、0≦v≦1、0≦x6≦1)。
【0026】
さらに、請求項記載の半導体発光素子は、前記電流阻止層が半導体発光素子の中央部または周辺部に設けられていることを特徴とするものである。
【0027】
【発明の実施の形態】
以下、本発明の実施の形態を各図面に基づき詳細に説明する。
[実施の形態1]
図1は、本発明にかかる実施の形態1の半導体発光素子を説明する面であり、図1(a)は、半導体発光素子の略断面図、図1(b)は、窓層5の厚さ方向におけるIn組成比の分布を示す図である。
【0028】
本発明の実施の形態1の半導体発光素子100の結晶成長は、減圧MOVPE法(減圧MOCVD法)を用いて行い、半導体発光素子100の各層は、次の構成より成る。1はn型GaAs基板、2はn型In0.5Al0.5Pクラッド層であり、不純物はSiで不純物濃度は5×1017cm-3、厚さ約1μm、3はアンドープIn0.5(Ga0.55Al0.450.5P発光層、厚さ約0.5μm、4はp型In0.5Al0.5Pクラッド層、不純物はZnで不純物濃度は5×1017cm-3、厚さ約1μm、11はp型GaP第1窓層、不純物はZnで不純物濃度は1×1018cm-3、厚さ約1μm、12はp型GaP第2窓層、不純物はZnで不純物濃度は1×1019cm-3、厚さ約5μm、であり、第1窓層11と第2窓層12とにより、窓層5を形成している。
【0029】
上記各層を積層した後、n型GaAs基板1の片面にn側電極7、p型窓層12の片面の電極形成面5aにp側電極6を形成し、半導体発光素子用ウェハー(以下、「実施の形態1のウェハー」という)を作成した。n側電極7は基板1全面に形成するが、p側電極6は光を取り出すために、例えば、直径約100μm程度の円形形状とした。このウェハーを約300μm角の大きさに分割し、半導体発光素子100を作成した。
【0030】
p型GaP第1窓層11とp型GaP第2窓層12のZnの不純物濃度は、それぞれ、1×1018cm-3と1×1019cm-3と、その界面において、大きな不純物濃度分布に落差があるため、第2窓層12のヒロック欠陥密度の増加の要因となっていることが分かったため、図1(b)に示すように、p型GaP第1窓層11とp型GaP第2窓層12との界面近傍、III族元素のIn添加され、InGaPからなっている。
【0031】
実施の形態1においては、第1窓層11とp型GaP第2窓層12との界面近傍に、厚さ約0.1μmのIn0.01Ga0.99P層(Znの不純物濃度1×1018cm-3)と厚さ約0.1μmのIn0.01Ga0.99P層(Znの不純物濃度1×1019cm-3を持つ構造となっている。
【0032】
これは、InがGaと同じく結晶表面を動きやすいこと、InとV族元素との結合はGaとV族元素との結合より強固であるため、不純物濃度が急激に増加しても、InとV族元素(例えば、P、As、N、Sb等)との結合が解離し難いことから、V族元素がInと結合して移動することにより、不純物のZnが結晶表面に均一に分散することができるためと考えられる。
【0033】
結晶中のIII族元素全体に対する特定のIII族元素の割合をIII族元素の組成比というが、前記両窓層11、12の界面近傍の第1窓層11および第2窓層12内の厚さ0.1μmの領域のIn組成比を約0.01とすれば、上記V族元素の均一分散を実現することができた。
【0034】
実施の形態1の半導体発光素子において、要約すると、前記半導体の各層は次の構成よりなるものである。
半導体基板:GaAs、
第1クラッド層:In0.5(Gax1Al1-x10.5P(但し、0≦x1≦1)、
活性層:In0.5(Gax2Al1-x20.5P(但し、0≦x2<1)、または、GayAl1-yAs(但し、0≦y≦1)、または、InzGa1-zAs(但し、0≦z<1)、
第2クラッド層:In0.5(Gax3Al1-x30.5P(但し、0≦x3≦1)、
窓層:Inw Ga x4 Al 1-w-x4P(但し、0≦w≦1、0≦x4≦1)。
【0035】
図2に、縦軸にヒロック欠陥密度、横軸にIn組成比を取り、第1窓層と第2窓層と 界面近傍のIn組成比に対するヒロック欠陥密度の測定結果の一例を示す。
【0036】
図2において、In組成比が、およそ、5×10-4、9×10-4、4×10-3、4×10-2、に対して、ヒロック欠陥密度は、それぞれ、約1000、100、10、5(個数/cm2)と、In組成比を0からわずかに大きくするだけでヒロック欠陥密度は大幅に減少することが分かる。図2はGaP単層について測定したものであるが半導体発光素子用ウェハーの場合、In組成比を大きくしたときのヒロック欠陥密度の減少はもう少し緩やかであった。In組成比を更に大きくするとヒロック欠陥密度も減少するが、わずかに加えた場合ほど急激な減少は見られない。
【0037】
一方、窓層5のIn組成比を増加させると、In組成比が0.23迄は間接遷移の半導体であり、GaP半導体のバンドギャップの値とほぼ同じであり、ヒロック低減による結晶性の向上により、電流拡散が増加して、輝度は向上する。しかし、窓層5のIn組成比が更に高くなると、窓層5の緑色光に対する透過率が低くなって、半導体発光素子の輝度が低下する。これは、窓層5のバンドギャップが小さくなるためである。
【0038】
従来例の半導体発光素子を作製するウェハー(以下、「従来例のウェハー」という)では、欠陥密度が約1000個/cm2であったものが、本実施の形態1のウェハーでは約100個/cm2と、1/5に減少した。実施の形態1のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来のウェハーを用いた場合に対して、約30%向上した。発光波長は560nmの緑色であり、輝度は従来の半導体発光素子に比べて、約20%増加することができた。
【0039】
[実施の形態2]
図3は、本発明にかかる実施の形態2の半導体発光素子を説明する面であり、図3(a)は、半導体発光素子の略断面図、図3(b)は、窓層5の厚さ方向におけるIn組成比の分布を示す図である。
【0040】
本発明の実施の形態2の半導体発光素子200の結晶成長は、実施の形態1と同様に、減圧MOVPE法(減圧MOCVD法)を用いて行われる。
【0041】
本実施の形態2の半導体発光素子200は、窓層5全体をIn0.01Ga0.99Pとし、p型In0.01Ga0.99P第1窓層(不純物はZnで不純物濃度は1×1018cm-3、厚さ約1μm)21、p型In0.01Ga0.99P第2窓層(不純物はZnで不純物濃度は1×1019cm-3、厚さ約5μm)22、とにより、窓層5を形成している。
【0042】
そして、第1窓層21とp型GaP第2窓層22との界面近傍に、厚さ約0.1μmのIn0.05Ga0.95P層(Znの不純物濃度1×1018cm-3)と厚さ約0.1μmのIn0.05Ga0.95P層(Znの不純物濃度1×1019cm-3を持つ構造となっており、その他の各層は、実施の形態1の半導体発光素子と同じである。このように窓層5全体をInGaPとしても欠陥密度を減少させることがわかる。
【0043】
本実施の形態2の半導体発光素子構成を有するウェハー(以下、「実施の形態2のウェハー」という)では、欠陥密度を約10個/cm2と従来例のウェハーに比べ、1/100に減少した。実施の形態2のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来例のウェハーを用いて作成した場合に対し約40%向上し、輝度は従来例の半導体発光素子より、約20%増加した。
【0044】
[実施の形態3]
図4は、本発明にかかる実施の形態3の半導体発光素子を説明する面であり、図4(a)は、半導体発光素子の略断面図、図4(b)は、窓層5の厚さ方向におけるIn組成比の分布を示す図である。
【0045】
本実施の形態3の半導体発光素子300は、窓層5全体をIn0.01(Ga0.8Al0.20.99P層とAlを入れた化合物半導体層とした点を除けば、実施の形態2の半導体発光素子と同じである。
【0046】
即ち、p型In0.01Al0.2Ga0.79P第1窓層(不純物はZnで不純物濃度は1×1018cm-3、厚さ約1μm)31、p型In0.01Al0.2Ga0.79P第2窓層(不純物はZnで不純物濃度は1×1019cm-3、厚さ約5μm)32、とにより、窓層5を形成している。
【0047】
そして、第1窓層31とp型GaP第2窓層32との界面近傍に、厚さ約0.1μmのIn0.01Al0.2Ga0.79P層(Znの不純物濃度1×1018cm-3)と厚さ約0.1μmのIn0.01Al0.2Ga0.79P層(Znの不純物濃度1×1019cm-3を持つ構造となっている。このように、窓層5全体をInAlGaPとしても欠陥密度を減少させることがわかる。窓層5を構成するIII族元素にAlを加えることにより、窓層5のバンドギャップが小さくなることを防ぐことができる。
【0048】
III族元素Alは窓層のバンドギャップを広げる効果はあるが、Gaと同様、V族元素(例えば、P、As、N、Sb等)との結合力が弱いため、結晶欠陥を減らす効果は無い。さらに、結晶表面を移動する速度が遅いためInによる結晶欠陥を抑制する効果を失わせる傾向がある。このため、緑色光を発生する半導体発光素子においては、前記第1窓層31と第2窓層32の界面近傍の第1窓層31および第2窓層32内のIn組成比を0.2以上とすることは困難であった。
【0049】
本実施の形態3の半導体発光素子構成を有するウェハー(以下、「実施の形態3のウェハー」という)では欠陥密度は30個/cm2と実施の形態2のウェハーに比較して欠陥密度は約3倍となった。しかし、従来例のウェハーに比べると欠陥密度は約1/30である。本実施の形態3の半導体発光素子の輝度は従来例の半導体発光素子比べて、約30%増加した。
【0050】
実施の形態3の半導体発光素子において、要約すると、前記半導体の各層は次の構成よりなるものである。
半導体基板:GaAs、
第1クラッド層:In0.5(Gax1Al1-x10.5P(但し、0≦x1≦1)、
活性層:In0.5(Gax2Al1-x20.5P(但し、0≦x2<1)、または、GayAl1-yAs(但し、0≦y≦1)、または、InzGa1-zAs(但し、0≦z<1)、
第2クラッド層:In0.5(Gax3Al1-x30.5P(但し、0≦x3≦1)、
窓層:Inw Ga x4 Al 1-x4P(但し、0≦w≦1、0≦x4≦1)。
【0051】
[実施の形態4]
図5は、本発明にかかる実施の形態4の半導体発光素子を説明する面であり、図5(a)は、半導体発光素子の略断面図、図5(b)は、窓層5の厚さ方向におけるIn組成比の分布を示す図である。
【0052】
本発明の実施の形態4の半導体発光素子400の結晶成長は、減圧MOVPE法(減圧MOCVD法)を用いて行い、図5(b)に示すように第2クラッド層4と第1窓層41との界面近傍の第1窓層41内にもInを添加し、In0.01Ga0.99P層とした点を除けば、実施の形態1の半導体発光素子100と同じである。第1窓層41と第2窓層12とにより、窓層5を構成している。
【0053】
本実施の形態4の半導体発光素子構成を有するウェハー(以下、「実施の形態4のウェハー」という)では欠陥密度が約80個/cm2であり、実施の形態4のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来例のウェハーを用いた場合に対し、約40%向上した。
【0054】
[実施の形態5]
図6は、本発明にかかる実施の形態5の半導体発光素子を説明する面であり、図6(a)は、半導体発光素子の略断面図、図6(b)は、窓層5の厚さ方向におけるp型不純物濃度の分布を示す図である。
【0055】
実施の形態5の半導体発光素子500は、第1窓層11と第2窓層52の界面近傍の第2窓層52内の厚さ1μmの領域において、p型(Zn)不純物濃度を1×1018cm-3から1×1019cm-3まで1桁漸次増加させた点を除けば、実施の形態1の半導体発光素子と同じである。
【0056】
本実施の形態5の半導体発光素子構成を有するウェハー(以下、「実施の形態5のウェハー」という)では、欠陥密度が従来のウェハーでは、約1000個/cm2であったものが、約500個/cm2と半減させることができた。実施の形態5のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来例のウェハーを用いた場合に比べて、約7%向上した。
【0057】
[実施の形態6]
図7は、本発明にかかる実施の形態6の半導体発光素子を説明する面であり、図7(a)は、半導体発光素子の略断面図、図7(b)は、窓層5の厚さ方向におけるIn組成比の分布、及び第1窓層61と第2窓層62のp型不純物濃度の分布を示す図である。
【0058】
本実施の形態6の半導体発光素子600は、第1窓層61と第2クラッド層4との界面近傍の第1窓層61内の厚さ0.2μmの領域において、p型不純物濃度を5×1017cm-3から1×1018cm-3まで半桁漸次増加させたことを除けば実施の形態5の半導体発光素子と同じである。
【0059】
実施の形態5のウェハーの欠陥密度は約500個/cm2であったが、本実施の形態6の半導体発光素子構成を有するウェハー(以下、「実施の形態6のウェハー」という)では欠陥密度が約300個/cm2とさらに減少させることができた。実施の形態6のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来例のウェハーを用いた場合の歩留まりに対し、約10%向上した。
【0060】
[実施の形態7]
図8は、本発明にかかる実施の形態7の半導体発光素子を説明する面であり、図8(a)は、半導体発光素子の略断面図、図8(b)は、窓層5の厚さ方向におけるIn組成比の分布を示す図、及び、図8(c)は、第1窓層61と第2窓層62と第2クラッド層のp型不純物濃度の分布を示す図である。
【0061】
本実施の形態7の半導体発光素子700は、第1窓層71の組成はIn0.01Ga0.99P層であり、第1窓層71と第2窓層72との界面近傍の第1窓層71内の厚さ約1μmの領域において、In組成比を0.01から0.05まで漸次増加させて、In0.05Ga0.95P層にするとともに、p型不純物濃度も1×1018cm-3から1×1019cm-3までIn組成比の増加にほぼ比例して漸次増加させた点を除けば、第1の実施の形態の半導体発光素子と同じである。
【0062】
本実施の形態7の半導体発光素子構成を有するウェハー(以下、「実施の形態7のウェハー」という)では、欠陥密度を約0〜5個/cm2と略無欠陥とすることができた。この実施の形態7のウェハーを用いて半導体発光素子を作成した場合の歩留まりは、従来例のウェハーを用いた場合に対し、約50%向上した。
【0063】
[実施の形態8]
図9は、本発明にかかる実施の形態8の半導体発光素子800を説明するための略断面図である。実施の形態1の半導体発光素子100との違いは、第2クラッド層4と第1窓層11との間の第2クラッド層4上で、且つ、p側電極6と対向する位置に、n型電流阻止層8を設けた点である。
【0064】
p側電極6の下に位置する発光層3の部分で発生した光は、p側電極6で反射されて、外部へ放射され難い。即ち、p側電極6の下に位置する発光層3の領域を流れる発光電流は、外部発光出力にあまり寄与しない無効電流である。n型電流阻止層8は、p型第2クラッド層4との界面で、n−p接合を形成している。半導体発光素子に電流を流すため、両電極6、7に順バイアス電圧を印加した時、前記接合は逆バイアスとなって、電流の流れを阻止する。従って、半導体発光素子に注入された電流は、すべて発光層3のp側電極6に対向していない部分に流れることになり、無効電流が殆ど無くなる。この場合、電流阻止層8の形状は、上部p型電極6の形状とほぼ相似形である。
【0065】
n型電流阻止層8の組成は、一般的には、InvAlx6Ga1-v-x6P(但し、0≦v≦1、0≦x6≦1)が用いられ、望ましい組成の一例として、In0.01Al0.01Ga0.98Pがある。
【0066】
本実施の形態8にかかる半導体発光素子では、p側電極6およびn型電流阻止層8は、直径約100μmの円形形状とした。これはp側電極6の面積を電流を流すために施すワイヤをボンディングができる必要最小限の大きさとし、p側電極6による輝度低下を最小限に抑えるためである。p側電極6およびn型電流阻止層8は素子の中央部に設けている。このため発光層3全面に均一に電流を流すことができ、半導体発光素子の輝度を従来例に比べて、約40%増加することができた。この半導体発光素子は屋外用表示板等の用途に用いることができる。
【0067】
[実施の形態9]
図10は、本発明の実施の形態9にかかる半導体発光素子900の略断面図を表している。実施の形態8の半導体発光素子800と同様、第2クラッド層4と第1窓層の間で第2クラッド層4上のp側電極6と対向する位置にn型電流阻止層8を設けた。本実施の形態9にかかる半導体発光素子900では、p側電極6およびn型電流阻止層8は、素子中央部分の直径約100μmの円形形状の部分を残して、素子の周辺部分に設けた。電流が素子中央の直径約100μmの狭い部分に集中するため、電流のON/OFFに対する光のON/OFFの応答速度を高めることができ、このため光通信用の光源として用いることができる。
【0068】
p側電極6およびn型電流阻止層8を形成しない部分の面積Sは必要な輝度と応答速度の値とによって決定される。即ち、応答速度が遅くても良いが高い輝度が要求される場合は、Sを大きくし、逆に輝度は低くても良いが応答速度を早くする必要がある場合にはSを小さくする。
【0069】
面積Sと輝度Bとの関係については、面積Sを大きくしても、輝度Bはあまり変化しない。これは、面積Sを大きくすると、電流密度が低下し、輝度Bは電流量に比例するからである。
【0070】
一方、面積Sと応答速度τとの関係については、面積Sを小さくすると、応答速度τは向上する。しかし、あまり小さくし過ぎると、抵抗の増加という悪影響が生じる。一例として、面積S=100μmφでは、電流I=20mAで、順方向電圧VF=1.95Vであり、S=50μmφでは、I=20mAで、順方向電圧VF=2.2Vとなり、応答速度τは約20%向上する。しかし、順方向電圧VFが0.25V増加するので、本発明では、面積S=100μmφが多く用いられる。応答速度τの具体的な数値の一例として、面積S=100μmφとすることにより、応答速度τ17.1μsを4.4μsに向上することができた。
【0071】
発光層をIn0.1Ga0.9Asとすることにより、発光波長950nmの半導体発光素子が得られ、赤外光を用いた無線通信用の光源として有効である。一方、発光層をGa0.9Al0.1Asとすることにより、発光波長850nmの半導体発光素子が得られる。前記発光波長の異なる2つの半導体発光素子を光源として用いることにより、赤外光を用いた波長多重無線通信が可能となる。また、上り信号と下り信号とで発光波長を変えることにより、赤外光を用いた全二重無線通信を行なうことも可能となる。
【0072】
また発光面積が小さいので、半導体発光素子の出射光を光ファイバーへ入射することが容易である。特に、光ファイバーとしてコアがプラスチックの光ファイバー(APF)を用いる場合、発光層3をIn0.5(GaxAl1-x0.5Pとし、Alの組成比xを0から1の間で調節することにより、APFの伝送損失の小さい波長550nm〜680nmの発光波長を有する半導体発光素子が得られる。この半導体発光素子は、APFを用いた光ファイバ通信用の光源として有効である。
【0073】
以上の説明は第1クラッド層、発光層、第2クラッド層に基板に格子整合した結晶薄膜を用いた場合について説明したが、格子不整合結晶薄膜を用いても効果は変わらないことは明らかである。
【0074】
また、基板としてはGaAsの場合について説明したが、サファイア等の絶縁性結晶、およびSi(シリコン)、SiC(シリコンカーバイド)等のIV族半導体、ZnSe等のII−VI族化合物半導体であっても良い。
【0075】
また、V族元素にPを用いた場合について説明したが、As、N、Sb等その他のV族元素を用いても同様の効果が得られる。
【0076】
要約すると、不純物濃度が異なる複数の窓層を積層する時、その窓層を構成する主要構成元素のうちIII族元素として結晶成長過程において結晶表面での動きが早く、V族元素と結合が強いInを添加することが重要である。しかし、Inは半導体のバンドギャップを小さくするので、添加量は発光層で生じた光に対し透過率を高く保つ範囲とする必要がある。
【0077】
【発明の効果】
本発明の請求項1記載の半導体発光素子によれば、基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、該基板には下部電極、および該窓層には上部電極が形成され、該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とからなり、該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、前記第1窓層と第2窓層の界面があり、前記第1窓層の前記界面近傍の部分前記第1窓層にお ける前記部分と隣接する部分よりIn ( インジウム)元素の組成比が高く前記第2窓層の前記界面近傍の部分は、前記第2窓層における前記部分と隣接する部分よりIn元素の組成比が高く前記第1,第2窓層はIn w Ga x4 Al 1-w-x4 P(但し、0≦w≦1、0≦x4≦1)からなることを特徴とするものである。
【0078】
従って、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥(ヒロック(hill−rock)と呼ばれる結晶欠陥)を大きく減少させることができ、その結果、このウェハーを用いた半導体発光素子作製時の電極剥離による不良品の発生を減少させ、半導体発光素子の生産歩留まりを高くすることができる。
【0079】
また、請求項2記載の半導体発光素子によれば、半導体の各層は次の構成よりなることを特徴とするものである。
半導体基板:GaAs、
第1クラッド層:In0.5(Gax1Al1-x10.5P(但し、0≦x1≦1)、
活性層:In0.5(Gax2Al1-x20.5P(但し、0≦x2<1)、または、GayAl1-yAs(但し、0≦y≦1)、または、InzGa1-zAs(但し、0≦z<1)、
第2クラッド層:In0.5(Gax3Al1-x30.5P(但し、0≦x3≦1)。
【0080】
従って、従来例のGaPに比べ、InやAlを添加することにより、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥を減少させることができるウェハーの構成を提供できる。
【0081】
また、請求項記載の半導体発光素子よれば、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥を減少させることができるウェハー作製手段を提供することができる。窓層にInを添加し過ぎると、従来例のGaPに比べ、抵抗率が増加し、動作電圧(順方向電圧VF)が増加するが、第2窓層にのみIn元素の組成比を高くすることにより、結晶欠陥は減少し、且つ、第1窓層のIn元素の組成比は低いため、動作電圧を低くすることができる。
【0082】
更に、請求項1からに記載の半導体発光素子は、基板と、III−V族化合物半導体結晶よりなる第1クラッド層、発光層、および反対導電型の第2クラッド層並びに窓層がこの順序で結晶成長されており、前記基板および窓層にはそれぞれ電極が形成され、前記窓層は少なくとも発光層に近い第1窓層と発光層より遠い第2窓層を有し、前記第2窓層は前記第1窓層より不純物濃度の高い半導体発光素子であって、前記第1窓層および第2窓層における前記III−V族化合物半導体結晶の主要構成元素の組成比、もしくは前記第2窓層内の不純物濃度を前記第1窓層と第2窓層の界面近傍において変化させ、結晶成長過程における主要構成元素を均一に分散させることにより、窓層の電極形成面における結晶欠陥を低減することができる。特に、前記結晶成長過程における主要構成元素を均一に分散させる手段として、前記第1窓層と第2窓層の界面近傍における第1窓層および第2窓層内のIn組成比を、前記界面近傍から離れた各層内のIn組成比よりも高くしたことを特徴とするものである。
【0083】
また、請求項記載の半導体発光素子によれば、前記第2クラッド層と前記第1窓層の界面があり、前記第1窓層の前記界面近傍の部分は、前記第1窓層における前記部分と隣接する部分よりIn元素の組成比こと特徴とするものである。
【0084】
従って、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥を請求項の手段に対し、より一層減少させることができるウェハー作製手段を提供することができる。また、第2クラッド層と前記第1窓層の界面近傍(約0.1μm厚程度)に結晶欠陥が多く存在するため、この界面近傍のみIn組成比を高くすることにより、動作電圧はあまり上がらず、且つ、結晶欠陥を減少させることができる。
【0085】
また、請求項に記載の発明にかかる半導体発光素子は前記結晶成長過程における主要構成元素を均一に分散させる手段として、前記第1窓層と第2窓層の界面近傍に加えて、前記発光層と前記第1窓層の界面近傍における第1窓層内のIn組成比を、前記界面近傍から離れた第1窓層内のIn組成比よりも高くしたことを特徴とするものである。
【0086】
また、請求項記載の半導体発光素子によれば、基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、該基板および該窓層の片面にはそれぞれ電極が形成され、該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とからなり、該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、前記第1窓層と第2窓層の界面近傍において、前記発光層から離れるにしたがって前記第2窓層内の不純物濃度を漸次増加させ、前記第1窓層と第2窓層の界面近傍おける前記第2窓層内のIn組成比を不純物濃度の増加にほぼ比例して漸次増加させたことを特徴とするものである。
【0087】
従って、半導体発光素子構成を有するウェハーの窓層の発光波長に対する透過率を減少させること無く、窓層の電極形成面上の結晶欠陥を減少させるウェハー作製手段を提供することができる。従来例では、不純物濃度を急激に変化させた界面近傍では、結晶欠陥が発生しやすかったが、不純物濃度を漸次増加させることにより、透過率及び抵抗率とも従来例と変わらないため、動作電圧も変わらず、Inを添加する場合に比べて、効果はやや小さいが、結晶欠陥は約1/2に低減でき、歩留まりを約7%向上することができた。
【0088】
また、請求項記載の半導体発光素子によれば、前記第2クラッド層と前記第1窓層の界面近傍の前記第1窓層内の不純物濃度を漸次増加させたことを特徴とするものである。
【0089】
従って、半導体発光素子構成を有するウェハーの窓層の発光波長に対する透過率を減少させること無く、窓層の電極形成面上の結晶欠陥を請求項の手段に比べ、さらに一層減少させるウェハー作製手段を提供することができる。クラッド層と窓層の界面近傍では、結晶欠陥が発生しやすいが、界面近傍の不純物濃度を漸次増加させることにより、透過率及び動作電圧をInを増加させる場合に比べて、効果はやや小さいものの、結晶欠陥は約3/10に低減することができた。
【0090】
また、請求項4記載の半導体発光素子では、前記第1窓層と第2窓層の界面近傍おける前記第2窓層内のIn組成比を不純物濃度の増加にほぼ比例して漸次増加させている。
【0091】
従って、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥を請求項の手段に対し、更に減少させることができるウェハー作製手段を提供することができる。この結果、歩留まりを約50%向上することができた。
【0092】
また、請求項記載の半導体発光素子によれば、前記第2クラッド層と前記第1窓層との界面上に電流阻止層を配設し、且つ、該電流阻止層の形状は上部電極の形状とほぼ相似形であることを特徴とするものである。
【0093】
従って、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥が少なく、歩留まりの良好で、無効電流の少ない半導体発光素子を提供することができる。この結果、半導体発光素子の輝度を約40%増加することができた。
【0094】
また、請求項記載の半導体発光素子よれば、前記電流阻止層が次の構成よりなることを特徴とするものである。
電流阻止層:InvAlx6Ga1-v-x6P(但し、0≦v≦1、0≦x6≦1)。
【0095】
従って、半導体発光素子構成を有するウェハーの窓層の電極形成面上の結晶欠陥が少なく、歩留まりの良好で、無効電流の少ない半導体発光素子の構成を提供できる。クラッド層と窓層の間に、InとAlを含むInAlGaP電流阻止層を有するため、結晶欠陥をさらに低減することができ、一例として、結晶欠陥を0〜3/cm2程度まで低減することができた。
【0096】
さらに、請求項記載の半導体発光素子よれば、前記電流阻止層が半導体発光素子の中央部または周辺部に設けられていることを特徴とするものである。
【0097】
従って、窓層の電極形成面上の結晶欠陥が少なく、歩留まりが高く、輝度の高い半導体発光素子または電流のON/OFFに対する光のON/OFFの応答が速い(変調速度の早い)半導体発光素子を提供することができる。また、電流阻止層が半導体発光素子の周辺部に設けられている場合、電流が中央部に集中し、発光部の電流密度が増加するため、動作電流を小さく選ぶことも可能であり、そのため、応答速度は、面積S=100μmφとすることにより、本発明の請求項1〜記載の半導体発光素子の発光応答速度τが17.1μsであったものを、本発明の請求項記載の半導体発光素子の発光応答速度τを4.4μsに向上することができた。
【図面の簡単な説明】
【図1】本発明の一実施の形態1に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布を示す図である。
【図2】本発明のGaAs基板上のGaP単層におけるヒロック密度のIn組成比依存性を表す図である。
【図3】本発明の一実施の形態2に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布を示す図である。
【図4】本発明の一実施の形態3に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布を示す図である。
【図5】本発明の一実施の形態4に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布を示す図である。
【図6】本発明の一実施の形態5に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるp型不純物濃度の分布を示す図である。
【図7】本発明の一実施の形態6に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布、及び第1窓層61と第2窓層62のp型不純物濃度の分布を示す図である。
【図8】本発明の一実施の形態7に係る半導体発光素子を説明する面であり、(a)は半導体発光素子の略断面図、(b)は窓層の厚さ方向におけるIn組成比の分布を示す図、(c)は第1窓層と第2窓層と第2クラッド層のp型不純物濃度の分布を示す図である。
【図9】本発明の一実施の形態8に係る半導体発光素子を説明するための略断面図である。
【図10】本発明の一実施の形態9に係る半導体発光素子を説明するための略断面図である。
【図11】従来例1の半導体発光素子の略断面図である。
【図12】従来例2の半導体発光素子の略断面図である。
【符号の説明】
100 本発明の実施の形態1の半導体発光素子
200 本発明の実施の形態2の半導体発光素子
300 本発明の実施の形態3の半導体発光素子
400 本発明の実施の形態4の半導体発光素子
500 本発明の実施の形態5の半導体発光素子
600 本発明の実施の形態6の半導体発光素子
700 本発明の実施の形態7の半導体発光素子
800 本発明の実施の形態8の半導体発光素子
900 本発明の実施の形態9の半導体発光素子
1 n型GaAs基板
2 n型In0.5Al0.5Pクラッド層
3 アンドープIn0.5(Ga0.55Al0.450.5P発光層
4 p型In0.5Al0.5Pクラッド層
5 窓層
5a 電極形成面
6 p側電極(上部電極)
7 n側電極(下部電極)
8 n型電流阻止層
11 p型GaP第1窓層
12 p型GaP第2窓層
21 p型In0.01Ga0.99P第1窓層
22 p型In0.01Ga0.99P第2窓層
31 p型In0.01Al0.2Ga0.79P第1窓層
32 p型In0.01Al0.2Ga0.79P第2窓層
41 第1窓層
61 第1窓層
62 第2窓層
71 p型In0.01Ga0.99P第1窓層
72 第2窓層
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor light emitting device formed by laminating a compound semiconductor crystal on a substrate, and more particularly to a technique for reducing crystal defects on the surface of the lamination and planarizing the same.
[0002]
[Prior art]
A semiconductor light emitting device formed by laminating a compound semiconductor crystal on a substrate has been used in a range from blue to infrared since a lattice mismatched crystal having a crystal lattice length different by 0.5% or more has become available. High-brightness light emission has become possible in a wide wavelength range.
[0003]
For example, a semiconductor light emitting device that emits green light described in US Pat. No. 5,008,718 has a structure as shown in FIG. 11 (hereinafter, referred to as “conventional example 1”). The semiconductor light emitting device 1100 is manufactured by the following procedure.
[0004]
In FIG. 11, on an n-type GaAs temporary substrate (not shown), an n-type InAlGaP first cladding layer 102 lattice-matched to the temporary substrate, a non-doped InAlGaP light emitting layer 103, a p-type InAlGaP second cladding layer 104, and p-type A GaP type window layer 105 is grown. After removing the GaAs temporary substrate (not shown), a transparent substrate layer 109 is grown on the n-type first cladding layer 102 to obtain a semiconductor light emitting device wafer.
[0005]
Next, the n-side electrode 107 is provided on the transparent substrate layer 109. A circular p-side electrode 106 is provided at the center of the electrode forming surface 105a of the window layer 105. The semiconductor wafer 1100 shown in FIG. 11 is manufactured by dividing the wafer into a size of about 300 μm square. Both electrodes 106 and 107 are electrically connected to an external conductor. For example, a metal wire (not shown) having a diameter of about 30 μm connected to an external conductor (not shown) is bonded to the p-side electrode 106.
[0006]
GaP is used for the window layer 105 in order to increase the luminance of the semiconductor light emitting element. GaP has a crystal lattice value about 3.4% smaller than that of the GaAs crystal of the temporary substrate and is a lattice-mismatched crystal. However, since the band gap is sufficiently larger than the band gap of the InAlGaP crystal of the light-emitting layer 103, GaP emits light. The transmittance of the window layer 105 can be kept sufficiently high for light having a wavelength close to the band gap of the light-emitting layer 103 generated in the layer 103. As a result, absorption of light emitted from the light-emitting layer 103 by the window layer 105 can be reduced, and the luminance of the semiconductor light-emitting element can be increased.
[0007]
To increase the luminance of the semiconductor light emitting element, it is also important to reduce the resistance value of the window layer 105. When a current is injected from both electrodes 106 and 107, green light having a wavelength of 560 nm is generated in the light emitting layer 103. When the resistance value of the window layer 105 is high, the current injected from the p-side electrode 106 has a small spread in the horizontal direction, so that light emission is concentrated at a portion of the light-emitting layer 103 facing the p-side electrode 106. Of the light generated in the light-emitting layer 3, light that is substantially perpendicularly incident on the interface between the semiconductor light-emitting element and the outside is efficiently output to the outside of the semiconductor light-emitting element, but other light is reflected at the interface, It does not contribute to the luminance of the semiconductor light emitting device. Therefore, when light emission occurs at a portion of the light emitting layer 103 facing the p-side electrode 106, light that is perpendicularly incident on the boundary surface is also reflected by the p-side electrode 106, and the brightness of the semiconductor light emitting element is reduced.
[0008]
As a method of reducing the resistance value, a method of increasing the p-type impurity concentration of the window layer 105 is well known. However, typical p-type impurities such as Zn (zinc), Mg (magnesium), and Be (beryllium) are substances that easily diffuse in the crystal. The p-type impurity diffuses to this extent, and the conversion efficiency of current into light in the light emitting layer 3 itself decreases, and the luminance of the semiconductor light emitting element decreases.
[0009]
In order to solve such a problem, Japanese Patent Application Laid-Open No. Hei 5-335519 discloses that a window layer has a two-layer structure, a p-type impurity concentration of a window layer close to an active layer is low, and a p-type impurity of a window layer far from the active layer is low. A technique is disclosed in which the concentration is increased so that the current spreads over the entire light emitting layer, and the luminance of the semiconductor light emitting element is prevented from lowering by preventing the p-type impurity from diffusing into the light emitting layer. (Hereinafter, referred to as “Conventional Example 2”).
[0010]
FIG. 12 shows a schematic cross-sectional view of a semiconductor light emitting device 1200 of Conventional Example 2. In the semiconductor substrate 101, the window layer 105 has a two-layer structure, and the first window layer 111 near the active layer and the second window layer 112 far from the active layer constitute the window layer 105.
[0011]
In the semiconductor light emitting device of Conventional Example 2, GaAlAs is used for the window layer 105, but GaAlAs has a narrow band gap and a low transmittance for green light. The present inventors have confirmed that the same effect can be obtained even when the window layer is made of GaP having a large band gap (hereinafter, referred to as a “conventional semiconductor light emitting device”).
[0012]
[Problems to be solved by the invention]
However, when the p-type impurity concentration of GaP used for the window layer is increased, many crystal defects are generated on the p-side electrode formation surface, and the crystal defects cause irregularities on the p-side electrode formation surface. Since the area of the p-side electrode 106 is as small as about 100 μm in diameter, if the p-side electrode formation surface 105a has irregularities, the wafer is divided, and a wire is bonded to the p-side electrode 106 to form a semiconductor light emitting device. There is a problem that the p-side electrode 106 is easily peeled off from the window layer 105.
[0013]
Of the above-mentioned crystal defects, a crystal defect called a hillock is most important. The hillock defect is a protruding defect generated because a crystal plane having a different plane orientation from the substrate is generated. Once a hillock defect occurs, it is not flattened by the crystal grown thereon, and the crystal grows while maintaining the protruding shape. The present inventors have found that hillock defects occur at an early stage of growing a layer having a higher p-type impurity concentration than that of the base, and that the higher the p-type impurity concentration of the grown layer, the more hillock defects occur.
[0014]
Hillock defects occur because when the impurity material is rapidly increased in order to increase the impurity concentration, the movement of Ga and P, which are the main constituent elements of GaP, is temporarily hindered by the impurity material, and It is considered that the cause is that it cannot be uniformly dispersed over the entire crystal surface. In particular, group V elements such as P, As, N, and Sb are difficult to move and move in combination with group III elements. Therefore, the type of group III element used at the same time has a large relationship with the presence or absence of crystal defects. For example, when the group III element is Ga, the bonding with the group V element is weak, so that the group V element is likely to come off. As a result, it is considered that the group V element is not uniformly dispersed in the initial stage of the growth of the layer having a higher impurity concentration than the base, and hillocks are generated.
[0015]
The present invention suppresses generation of crystal defects such as hillocks by uniformly dispersing the group III element and the group V element, which are main constituent elements of the group III-V compound semiconductor crystal, over the entire crystal surface during the crystal growth process. It is another object of the present invention to provide a semiconductor light emitting device wafer in which the surface of an electrode is reduced and flattened to reduce the possibility of peeling of electrodes in the semiconductor light emitting device manufacturing process.
[0016]
[Means for Solving the Problems]
The semiconductor light-emitting device according to claim 1 of the present invention includes a substrate, a first clad layer made of at least a group III-V compound semiconductor crystal, a light-emitting layer, a second clad layer having a conductivity type opposite to that of the first clad layer, and A window electrode, and a lower electrode is formed on the substrate, and an upper electrode is formed on the window layer.DepartsA first window layer closer to the light layer and a second window layer farther from the light emitting layer;From BecomeThe second window layer is a semiconductor layer having a higher impurity concentration than the first window layer, and has an interface between the first window layer and the second window layer, and a portion near the interface of the first window layer.Is,The portion of the first window layer adjacent to the portion is more In ( High composition ratio of indium) element,Portion of the second window layer near the interfaceIs beforeNote2 window layersAdjacent to the part inpartMore InThe composition ratio of the elementshigh,The first and second window layers are made of In. w Ga x4 Al 1-w-x4 P (where 0 ≦ w ≦ 1, 0 ≦ x4 ≦ 1)It is characterized by the following.
[0017]
Further, each layer of the semiconductor of the semiconductor light emitting device according to the second aspect has the following configuration.
[0018]
Semiconductor substrate: GaAs,
First cladding layer: In0.5(Gax1Al1-x1)0.5P (however, 0 ≦ x1 ≦ 1),
Active layer: In0.5(Gax2Al1-x2)0.5P (however, 0 ≦ x2 <1) or GayAl1-yAs (however, 0 ≦ y ≦ 1) or InzGa1-zAs (where 0 ≦ z <1),
Second cladding layer: In0.5(Gax3Al1-x3)0.5P (however, 0 ≦ x3 ≦ 1).
[0019]
[0020]
Claims3The semiconductor light emitting device according to the above,There is an interface between the second cladding layer and the first window layer,Of the first window layerThe portion near the interface is closer to the portion than the portion in the first window layer.Composition ratio of In elementButHighIIt is characterized by the following.
[0021]
Claims4In the semiconductor light-emitting device described in the above, a substrate, a first clad layer made of at least a group III-V compound semiconductor crystal, a light-emitting layer, a second clad layer of the opposite conductivity type to the first clad layer, and a window layer are arranged in this order. Electrodes are formed on one side of the substrate and the window layer, respectively.DepartsA first window layer closer to the light layer and a second window layer farther from the light emitting layer;Consists ofThe second window layer is a semiconductor layer having a higher impurity concentration than the first window layer, and near the interface between the first window layer and the second window layer;As you move away from the light emitting layerGradually increasing the impurity concentration in the second window layerThe In composition ratio in the second window layer near the interface between the first window layer and the second window layer is gradually increased substantially in proportion to the increase in impurity concentration.It is characterized by having.
[0022]
Claims5In the semiconductor light emitting device described above, the impurity concentration in the first window layer near the interface between the second cladding layer and the first window layer is gradually increased.
[0023]
[0024]
Claims6In the semiconductor light emitting device described above, a current blocking layer is provided on an interface between the second cladding layer and the first window layer, and the shape of the current blocking layer is substantially similar to the shape of the upper electrode. It is characterized by the following.
[0025]
Claims7In the semiconductor light emitting device described above, the current blocking layer has the following configuration.
Current blocking layer: InvAlx6Ga1-v-x6P (however, 0 ≦ v ≦ 1, 0 ≦ x6 ≦ 1).
[0026]
Claims8The described semiconductor light emitting device is characterized in that the current blocking layer is provided at a central portion or a peripheral portion of the semiconductor light emitting device.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
1A and 1B are diagrams illustrating a semiconductor light emitting device according to a first embodiment of the present invention. FIG. 1A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 4 is a diagram showing a distribution of an In composition ratio in a vertical direction.
[0028]
The crystal growth of the semiconductor light emitting device 100 according to the first embodiment of the present invention is performed using a reduced pressure MOVPE method (a reduced pressure MOCVD method), and each layer of the semiconductor light emitting device 100 has the following configuration. 1 is an n-type GaAs substrate, 2 is an n-type In0.5Al0.5P cladding layer, the impurity is Si and the impurity concentration is 5 × 1017cm-3, The thickness is about 1 μm, and 3 is undoped In.0.5(Ga0.55Al0.45)0.5P light emitting layer, thickness about 0.5 μm, 4 is p-type In0.5Al0.5P clad layer, impurity is Zn and impurity concentration is 5 × 1017cm-3The thickness is about 1 μm, 11 is a p-type GaP first window layer, the impurity is Zn and the impurity concentration is 1 × 1018cm-3A thickness of about 1 μm, 12 is a p-type GaP second window layer, the impurity is Zn and the impurity concentration is 1 × 1019cm-3The first window layer 11 and the second window layer 12 form the window layer 5.
[0029]
After laminating the above layers, an n-side electrode 7 is formed on one side of the n-type GaAs substrate 1 and a p-side electrode 6 is formed on one side of the electrode forming surface 5a of the p-type window layer 12, and a semiconductor light emitting device wafer (hereinafter, referred to as “ "The wafer of the first embodiment"). The n-side electrode 7 is formed on the entire surface of the substrate 1, while the p-side electrode 6 has, for example, a circular shape with a diameter of about 100 μm in order to extract light. This wafer was divided into a size of about 300 μm square to produce a semiconductor light emitting device 100.
[0030]
The impurity concentration of Zn in the p-type GaP first window layer 11 and the p-type GaP second window layer 12 is 1 × 1018cm-3And 1 × 1019cm-3It has been found that a large drop in the impurity concentration distribution at the interface causes a rise in the hillock defect density of the second window layer 12, and as shown in FIG. Near the interface between the GaP first window layer 11 and the p-type GaP second window layer 12Is, Group III element InButAdditionIs, InGaPFromHas become.
[0031]
In the first embodiment, near the interface between the first window layer 11 and the p-type GaP second window layer 12, the thickness of about 0.1 μm0.01Ga0.99P layer (Zn impurity concentration 1 × 1018cm-3) And about 0.1 μm thick In0.01Ga0.99P layer (Zn impurity concentration 1 × 1019cm-3)WhenIt has a structure with.
[0032]
This is because In moves easily on the crystal surface like Ga, and the bond between In and the group V element is stronger than the bond between Ga and the group V element. Since the bond with the group V element (for example, P, As, N, Sb, etc.) is hard to be dissociated, the impurity Zn is uniformly dispersed on the crystal surface by the movement of the group V element by bonding with In. It is thought that it is possible.
[0033]
The ratio of the specific Group III element to the entire Group III element in the crystal is referred to as the composition ratio of the Group III element, and the thickness in the first window layer 11 and the second window layer 12 near the interface between the window layers 11 and 12 is defined. When the In composition ratio in the region having a thickness of 0.1 μm was set to about 0.01, uniform dispersion of the group V element could be realized.
[0034]
In summary, in the semiconductor light emitting device of the first embodiment, each layer of the semiconductor has the following configuration.
Semiconductor substrate: GaAs,
First cladding layer: In0.5(Gax1Al1-x1)0.5P (however, 0 ≦ x1 ≦ 1),
Active layer: In0.5(Gax2Al1-x2)0.5P (however, 0 ≦ x2 <1) or GayAl1-yAs (however, 0 ≦ y ≦ 1) or InzGa1-zAs (where 0 ≦ z <1),
Second cladding layer: In0.5(Gax3Al1-x3)0.5P (however, 0 ≦ x3 ≦ 1),
Window layer: Inw Ga x4 Al 1-w-x4P (however, 0 ≦ w ≦ 1, 0 ≦ x4 ≦ 1).
[0035]
FIG. 2 shows the hillock defect density on the vertical axis and the In composition ratio on the horizontal axis.of Near the interface1 shows an example of the measurement results of the hillock defect density with respect to the In composition ratio of the sample.
[0036]
In FIG. 2, the In composition ratio is approximately 5 × 10-Four, 9 × 10-Four, 4 × 10-3, 4 × 10-2And the hillock defect densities are about 1000, 100, 10, and 5 (number / cm, respectively).Two) And that the hillock defect density is greatly reduced only by slightly increasing the In composition ratio from 0. FIG. 2 shows a measurement of a GaP single layer. In the case of a semiconductor light emitting device wafer, the decrease in the hillock defect density when the In composition ratio was increased was more moderate. When the In composition ratio is further increased, the hillock defect density also decreases, but does not decrease as sharply as when a small amount is added.
[0037]
On the other hand, when the In composition ratio of the window layer 5 is increased, the semiconductor is an indirect transition semiconductor up to the In composition ratio of 0.23, which is almost the same as the band gap value of the GaP semiconductor. As a result, current diffusion increases, and luminance improves. However, when the In composition ratio of the window layer 5 is further increased, the transmittance of the window layer 5 for green light is reduced, and the luminance of the semiconductor light emitting device is reduced. This is because the band gap of the window layer 5 becomes small.
[0038]
In a wafer for fabricating a semiconductor light emitting device of a conventional example (hereinafter, referred to as a “wafer of a conventional example”), a defect density is about 1000 defects / cm.TwoHowever, in the wafer of the first embodiment, about 100 wafers / cmTwoAnd decreased to 1/5. The yield when semiconductor light emitting devices are manufactured using the wafer of Embodiment 1 is improved by about 30% as compared with the case where a conventional wafer is used. The emission wavelength was green at 560 nm, and the luminance was able to be increased by about 20% as compared with the conventional semiconductor light emitting device.
[0039]
[Embodiment 2]
3A and 3B are diagrams illustrating a semiconductor light emitting device according to a second embodiment of the present invention. FIG. 3A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 4 is a diagram showing a distribution of an In composition ratio in a vertical direction.
[0040]
The crystal growth of the semiconductor light emitting device 200 according to the second embodiment of the present invention is performed by using the low-pressure MOVPE method (low-pressure MOCVD method) as in the first embodiment.
[0041]
In the semiconductor light emitting device 200 according to the second embodiment, the entirety of the window layer 5 is In.0.01Ga0.99P and p-type In0.01Ga0.99P first window layer (impurity is Zn and impurity concentration is 1 × 1018cm-3, Thickness of about 1 μm) 21, p-type In0.01Ga0.99P second window layer (impurity is Zn and impurity concentration is 1 × 1019cm-3, A thickness of about 5 μm) 22 to form the window layer 5.
[0042]
Then, near the interface between the first window layer 21 and the p-type GaP second window layer 22, a thickness of about 0.1 μm0.05Ga0.95P layer (Zn impurity concentration 1 × 1018cm-3) And about 0.1 μm thick In0.05Ga0.95P layer (Zn impurity concentration 1 × 1019cm-3)WhenThe other layers are the same as those of the semiconductor light emitting device of the first embodiment. Thus, it can be seen that the defect density is reduced even when the entire window layer 5 is made of InGaP.
[0043]
In the wafer having the semiconductor light emitting device configuration of the second embodiment (hereinafter, referred to as “wafer of the second embodiment”), the defect density is about 10 / cm.TwoAnd 1/100 of that of the conventional wafer. The yield when a semiconductor light emitting device is manufactured using the wafer of the second embodiment is improved by about 40% as compared with the case where the semiconductor light emitting device is manufactured using the conventional wafer, and the luminance is about 20% higher than that of the conventional semiconductor light emitting device. % Increased.
[0044]
[Embodiment 3]
4A and 4B are diagrams illustrating a semiconductor light emitting device according to a third embodiment of the present invention. FIG. 4A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 4 is a diagram showing a distribution of an In composition ratio in a vertical direction.
[0045]
In the semiconductor light emitting device 300 of the third embodiment, the entirety of the window layer 5 is In.0.01(Ga0.8Al0.2)0.99It is the same as the semiconductor light emitting device of the second embodiment except that a P layer and a compound semiconductor layer containing Al are used.
[0046]
That is, p-type In0.01Al0.2Ga0.79P first window layer (impurity is Zn and impurity concentration is 1 × 1018cm-3, Thickness about 1 μm) 31, p-type In0.01Al0.2Ga0.79P second window layer (impurity is Zn and impurity concentration is 1 × 1019cm-3, A thickness of about 5 μm) 32 to form the window layer 5.
[0047]
Then, near the interface between the first window layer 31 and the p-type GaP second window layer 32, an In layer having a thickness of about 0.1 μm is formed.0.01Al0.2Ga0.79P layer (Zn impurity concentration 1 × 1018cm-3) And about 0.1 μm thick In0.01Al0.2Ga0.79P layer (Zn impurity concentration 1 × 1019cm-3)WhenIt has a structure with. Thus, it can be seen that the defect density is reduced even when the entire window layer 5 is made of InAlGaP. By adding Al to the group III element constituting the window layer 5, the band gap of the window layer 5 can be prevented from being reduced.
[0048]
Although the group III element Al has an effect of widening the band gap of the window layer, it has a weak bonding force with a group V element (for example, P, As, N, Sb, etc.) like Ga, so that the effect of reducing crystal defects is low. There is no. Further, since the speed of moving the crystal surface is low, the effect of suppressing crystal defects due to In tends to be lost. For this reason, in a semiconductor light emitting device that emits green light, the In composition ratio in the first window layer 31 and the second window layer 32 near the interface between the first window layer 31 and the second window layer 32 is set to 0.2. It was difficult to do so.
[0049]
The defect density of the wafer having the semiconductor light emitting element configuration of the third embodiment (hereinafter, referred to as “wafer of the third embodiment”) is 30 defects / cm.TwoAnd the defect density was about three times that of the wafer of the second embodiment. However, the defect density is about 1/30 as compared with the conventional wafer. The brightness of the semiconductor light emitting device of the third embodiment is the same as that of the conventional semiconductor light emitting device.ToIn comparison, it increased by about 30%.
[0050]
In summary, in the semiconductor light emitting device of the third embodiment, each layer of the semiconductor has the following configuration.
Semiconductor substrate: GaAs,
First cladding layer: In0.5(Gax1Al1-x1)0.5P (however, 0 ≦ x1 ≦ 1),
Active layer: In0.5(Gax2Al1-x2)0.5P (however, 0 ≦ x2 <1) or GayAl1-yAs (however, 0 ≦ y ≦ 1) or InzGa1-zAs (where 0 ≦ z <1),
Second cladding layer: In0.5(Gax3Al1-x3)0.5P (however, 0 ≦ x3 ≦ 1),
Window layer: Inw Ga x4 Al 1-x4P (however, 0 ≦ w ≦ 1, 0 ≦ x4 ≦ 1).
[0051]
[Embodiment 4]
5A and 5B are diagrams illustrating a semiconductor light emitting device according to a fourth embodiment of the present invention. FIG. 5A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 4 is a diagram showing a distribution of an In composition ratio in a vertical direction.
[0052]
The crystal growth of the semiconductor light emitting device 400 according to the fourth embodiment of the present invention is performed by using a reduced pressure MOVPE method (a reduced pressure MOCVD method), and the second cladding layer 4 and the first window layer 41 are formed as shown in FIG. Is also added in the first window layer 41 near the interface with0.01Ga0.99P layerPointExcept for this, it is the same as the semiconductor light emitting device 100 of the first embodiment. The first window layer 41 and the second window layer 12 constitute the window layer 5.
[0053]
The wafer having the semiconductor light emitting device configuration of the fourth embodiment (hereinafter referred to as “wafer of the fourth embodiment”) has a defect density of about 80 defects / cm.TwoThus, the yield in the case where a semiconductor light emitting device is manufactured using the wafer of the fourth embodiment is improved by about 40% as compared with the case where a conventional wafer is used.
[0054]
[Embodiment 5]
6A and 6B are diagrams illustrating a semiconductor light emitting device according to a fifth embodiment of the present invention. FIG. 6A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 5 is a diagram showing a distribution of a p-type impurity concentration in a vertical direction.
[0055]
The semiconductor light emitting device 500 according to the fifth embodiment has a p-type (Zn) impurity concentration of 1 × in a 1 μm thick region in the second window layer 52 near the interface between the first window layer 11 and the second window layer 52. 1018cm-3From 1 × 1019cm-3It is the same as the semiconductor light emitting device of the first embodiment except that it is gradually increased by one digit.
[0056]
In the wafer having the semiconductor light emitting element configuration of the fifth embodiment (hereinafter, referred to as “wafer of the fifth embodiment”), the defect density of a conventional wafer is about 1000 / cm.TwoWas about 500 pieces / cmTwoAnd could be halved. The yield in the case where a semiconductor light emitting device is manufactured using the wafer of the fifth embodiment is improved by about 7% as compared with the case where a conventional wafer is used.
[0057]
Embodiment 6
7A and 7B are diagrams illustrating a semiconductor light emitting device according to a sixth embodiment of the present invention. FIG. 7A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 9 is a diagram showing a distribution of an In composition ratio in a vertical direction and a distribution of a p-type impurity concentration of a first window layer 61 and a second window layer 62.
[0058]
The semiconductor light emitting device 600 of the sixth embodiment has a p-type impurity concentration of 5 μm in a 0.2 μm thick region in the first window layer 61 near the interface between the first window layer 61 and the second cladding layer 4. × 1017cm-3From 1 × 1018cm-3It is the same as the semiconductor light emitting device of the fifth embodiment except that it is gradually increased up to half a digit.
[0059]
The defect density of the wafer of the fifth embodiment is about 500 defects / cm.TwoHowever, the defect density of the wafer having the semiconductor light emitting device configuration of the sixth embodiment (hereinafter referred to as “wafer of the sixth embodiment”) is about 300 defects / cm.TwoAnd could be further reduced. The yield in the case where a semiconductor light emitting device was manufactured using the wafer of the sixth embodiment was improved by about 10% as compared with the yield in the case where a conventional wafer was used.
[0060]
Embodiment 7
8A and 8B are diagrams illustrating a semiconductor light emitting device according to a seventh embodiment of the present invention. FIG. 8A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. FIG. 8C is a diagram showing the distribution of the In composition ratio in the vertical direction, and FIG. 8C is a diagram showing the distribution of the p-type impurity concentration of the first window layer 61, the second window layer 62, and the second cladding layer.
[0061]
In the semiconductor light emitting device 700 according to the seventh embodiment, the composition of the first window layer 71 is In.0.01Ga0.99In the P layer, the In composition ratio is gradually increased from 0.01 to 0.05 in a region having a thickness of about 1 μm in the first window layer 71 near the interface between the first window layer 71 and the second window layer 72. Let In0.05Ga0.95A p-type impurity concentration of 1 × 1018cm-3From 1 × 1019cm-3It is the same as the semiconductor light emitting device of the first embodiment except that it is gradually increased almost in proportion to the increase of the In composition ratio up to.
[0062]
In the wafer having the semiconductor light emitting device configuration of the seventh embodiment (hereinafter referred to as “wafer of the seventh embodiment”), the defect density is about 0 to 5 defects / cm.TwoAnd almost no defect. The yield when semiconductor light emitting devices are manufactured using the wafer of the seventh embodiment is improved by about 50% as compared with the case where a conventional wafer is used.
[0063]
Embodiment 8
FIG. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device 800 according to Embodiment 8 of the present invention. The difference from the semiconductor light emitting device 100 of the first embodiment is that n is provided on the second cladding layer 4 between the second cladding layer 4 and the first window layer 11 and at a position facing the p-side electrode 6. This is the point that the mold current blocking layer 8 is provided.
[0064]
Light generated in the portion of the light emitting layer 3 located below the p-side electrode 6 is reflected by the p-side electrode 6 and is hardly radiated to the outside. That is, the light emitting current flowing through the region of the light emitting layer 3 located below the p-side electrode 6 is a reactive current that does not significantly contribute to the external light emitting output. The n-type current blocking layer 8 forms an n-p junction at the interface with the p-type second cladding layer 4. When a forward bias voltage is applied to both electrodes 6 and 7 in order to cause a current to flow through the semiconductor light emitting element, the junction becomes reverse biased and blocks the flow of current. Therefore, all the current injected into the semiconductor light emitting element flows to a portion of the light emitting layer 3 that is not opposed to the p-side electrode 6, and almost no reactive current is generated. In this case, the shape of the current blocking layer 8 is substantially similar to the shape of the upper p-type electrode 6.
[0065]
The composition of the n-type current blocking layer 8 is generally InvAlx6Ga1-v-x6P (however, 0 ≦ v ≦ 1, 0 ≦ x6 ≦ 1) is used, and as an example of a desirable composition, In0.01Al0.01Ga0.98There is P.
[0066]
In the semiconductor light emitting device according to the eighth embodiment, the p-side electrode 6 and the n-type current blocking layer 8 have a circular shape with a diameter of about 100 μm. This is because the area of the p-side electrode 6 is set to the minimum necessary size capable of bonding a wire to be applied for flowing a current, and the reduction in luminance due to the p-side electrode 6 is minimized. The p-side electrode 6 and the n-type current blocking layer 8 are provided at the center of the device. Therefore, a current can be uniformly applied to the entire surface of the light emitting layer 3, and the luminance of the semiconductor light emitting device can be increased by about 40% as compared with the conventional example. This semiconductor light emitting device can be used for applications such as outdoor display panels.
[0067]
Embodiment 9
FIG. 10 is a schematic sectional view of a semiconductor light emitting device 900 according to the ninth embodiment of the present invention. Similarly to the semiconductor light emitting device 800 of the eighth embodiment, an n-type current blocking layer 8 is provided between the second cladding layer 4 and the first window layer at a position facing the p-side electrode 6 on the second cladding layer 4. . In the semiconductor light emitting device 900 according to the ninth embodiment, the p-side electrode 6 and the n-type current blocking layer 8 are provided in the peripheral portion of the device except for a circular portion having a diameter of about 100 μm in the central portion of the device. Since the current is concentrated in a narrow portion having a diameter of about 100 μm at the center of the element, the response speed of ON / OFF of light with respect to ON / OFF of the current can be increased, and therefore, it can be used as a light source for optical communication.
[0068]
The area S of the portion where the p-side electrode 6 and the n-type current blocking layer 8 are not formed is determined by the required brightness and the value of the response speed. In other words, when the response speed may be slow but high luminance is required, S is increased. Conversely, when the luminance may be low but the response speed needs to be increased, S is decreased.
[0069]
Regarding the relationship between the area S and the luminance B, even if the area S is increased, the luminance B does not change much. This is because, when the area S is increased, the current density decreases, and the luminance B is proportional to the current amount.
[0070]
On the other hand, regarding the relationship between the area S and the response speed τ, when the area S is reduced, the response speed τ is improved. However, if it is too small, the adverse effect of increasing the resistance occurs. As an example, when the area S = 100 μmφ, the current I = 20 mA and the forward voltage VF= 1.95 V, S = 50 μmφ, I = 20 mA, and forward voltage VF= 2.2 V, and the response speed τ is improved by about 20%. However, the forward voltage VFIncreases by 0.25 V, and therefore, in the present invention, the area S = 100 μmφ is often used. As an example of a specific numerical value of the response speed τ, by setting the area S = 100 μmφ, the response speed τ17.1 μs could be improved to 4.4 μs.
[0071]
The light emitting layer is In0.1Ga0.9By using As, a semiconductor light emitting element having an emission wavelength of 950 nm can be obtained, which is effective as a light source for wireless communication using infrared light. On the other hand, the light-emitting layer is Ga0.9Al0.1By using As, a semiconductor light emitting device having an emission wavelength of 850 nm can be obtained. By using two semiconductor light emitting elements having different emission wavelengths as light sources, wavelength multiplex wireless communication using infrared light can be performed. Further, by changing the emission wavelength between the upstream signal and the downstream signal, full-duplex wireless communication using infrared light can be performed.
[0072]
Further, since the light emitting area is small, it is easy to make the light emitted from the semiconductor light emitting element enter the optical fiber. In particular, when a plastic optical fiber (APF) having a core is used as the optical fiber, the light emitting layer 3 is made of In.0.5(GaxAl1-x)0.5By setting P and adjusting the composition ratio x of Al between 0 and 1, a semiconductor light emitting device having an emission wavelength of 550 nm to 680 nm with a small APF transmission loss can be obtained. This semiconductor light emitting device is effective as a light source for optical fiber communication using an APF.
[0073]
In the above description, the case where the crystal thin film lattice-matched to the substrate is used for the first cladding layer, the light-emitting layer, and the second cladding layer, but it is clear that the effect is not changed even if the lattice mismatch crystal thin film is used. is there.
[0074]
Also, although the case of GaAs has been described as the substrate, insulating substrates such as sapphire, group IV semiconductors such as Si (silicon) and SiC (silicon carbide), and group II-VI compound semiconductors such as ZnSe may be used. good.
[0075]
Further, the case where P is used as the group V element has been described, but the same effect can be obtained by using other group V elements such as As, N, and Sb.
[0076]
In summary, when a plurality of window layers having different impurity concentrations are stacked, the main constituent elements constituting the window layers move rapidly on the crystal surface during the crystal growth process as a group III element, and have a strong bond with the group V element. It is important to add In. However, since In reduces the band gap of the semiconductor, the amount of addition needs to be in a range that keeps the transmittance of light generated in the light emitting layer high.
[0077]
【The invention's effect】
According to the semiconductor light emitting device of claim 1 of the present invention, a substrate, a first cladding layer made of at least a group III-V compound semiconductor crystal, a light emitting layer, and a second cladding layer of a conductivity type opposite to the first cladding layer. , And a window layer are laminated in this order, a lower electrode is formed on the substrate, and an upper electrode is formed on the window layer.DepartsA first window layer closer to the light layer and a second window layer farther from the light emitting layer;Consists ofThe second window layer is a semiconductor layer having a higher impurity concentration than the first window layer, and has an interface between the first window layer and the second window layer, and a portion near the interface of the first window layer.Is,In the first window layer From the part adjacent to the part ( High composition ratio of indium) element,Portion of the second window layer near the interfaceIs beforeNote2 window layersAdjacent to the part inpartMore InThe composition ratio of the elementshigh,The first and second window layers are made of In. w Ga x4 Al 1-w-x4 P (where 0 ≦ w ≦ 1, 0 ≦ x4 ≦ 1)It is characterized by the following.
[0078]
Therefore, crystal defects (crystal defects called hillocks) on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting element configuration can be greatly reduced, and as a result, semiconductor light emission using this wafer can be achieved. It is possible to reduce the occurrence of defective products due to electrode peeling during device fabrication, and to increase the production yield of semiconductor light emitting devices.
[0079]
According to the semiconductor light emitting device of the second aspect, each layer of the semiconductor has the following configuration.
Semiconductor substrate: GaAs,
First cladding layer: In0.5(Gax1Al1-x1)0.5P (however, 0 ≦ x1 ≦ 1),
Active layer: In0.5(Gax2Al1-x2)0.5P (however, 0 ≦ x2 <1) or GayAl1-yAs (however, 0 ≦ y ≦ 1) or InzGa1-zAs (where 0 ≦ z <1),
Second cladding layer: In0.5(Gax3Al1-x3)0.5P (however, 0 ≦ x3 ≦ 1).
[0080]
Therefore, compared to the conventional GaP, by adding In or Al, it is possible to provide a wafer configuration capable of reducing crystal defects on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting element configuration.
[0081]
Claims1Semiconductor light emitting device as describedToAccording to, HalfIt is possible to provide a wafer manufacturing means capable of reducing crystal defects on an electrode forming surface of a window layer of a wafer having a conductive light emitting element configuration. If In is excessively added to the window layer, the resistivity increases as compared with the conventional GaP, and the operating voltage (forward voltage VF) Increases, but by increasing the composition ratio of the In element only in the second window layer, crystal defects are reduced and the composition ratio of the In element in the first window layer is low, so that the operating voltage is lowered. be able to.
[0082]
Furthermore, from claim 12Wherein the substrate, a first cladding layer made of a III-V compound semiconductor crystal, a light emitting layer, a second cladding layer of the opposite conductivity type, and a window layer are crystal-grown in this order, An electrode is formed on each of the substrate and the window layer. The window layer has at least a first window layer near the light emitting layer and a second window layer far from the light emitting layer, and the second window layer is the first window layer. A semiconductor light emitting device having a higher impurity concentration, wherein a composition ratio of a main constituent element of the group III-V compound semiconductor crystal in the first window layer and the second window layer or an impurity concentration in the second window layer is By changing the density near the interface between the first window layer and the second window layer to uniformly disperse the main constituent elements in the crystal growth process, crystal defects on the electrode forming surface of the window layer can be reduced. In particular, as a means for uniformly dispersing the main constituent elements in the crystal growth process, the In composition ratio in the first window layer and the second window layer in the vicinity of the interface between the first window layer and the second window layer is determined by the interface. It is characterized in that it is higher than the In composition ratio in each layer away from the vicinity.
[0083]
Claims3According to the semiconductor light emitting device according to the above,There is an interface between the second cladding layer and the first window layer,Of the first window layerThe portion near the interface is closer to the portion than the portion in the first window layer.Composition ratio of In elementButHighIIt is characterized by the following.
[0084]
Therefore, a crystal defect on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting device configuration is claimed.1With respect to the above means, it is possible to provide a wafer manufacturing means that can be further reduced. Further, since there are many crystal defects near the interface between the second cladding layer and the first window layer (about 0.1 μm thick), the operating voltage is significantly increased by increasing the In composition ratio only near this interface. And crystal defects can be reduced.
[0085]
Claims3The semiconductor light emitting device according to the invention described in (1), as means for uniformly dispersing the main constituent elements in the crystal growth process, in addition to the vicinity of the interface between the first window layer and the second window layer, the light emitting layer and the first The In composition ratio in the first window layer near the interface of the window layer is higher than the In composition ratio in the first window layer far from the vicinity of the interface.
[0086]
Claims4According to the described semiconductor light emitting device, the substrate, the first cladding layer made of at least a group III-V compound semiconductor crystal, the light emitting layer, the second cladding layer of the opposite conductivity type to the first cladding layer, and the window layer are provided. Electrodes are formed on one side of the substrate and the window layer, respectively.DepartsA first window layer closer to the light layer and a second window layer farther from the light emitting layer;Consists ofThe second window layer is a semiconductor layer having a higher impurity concentration than the first window layer, and near the interface between the first window layer and the second window layer;As you move away from the light emitting layerGradually increasing the impurity concentration in the second window layerThe In composition ratio in the second window layer near the interface between the first window layer and the second window layer is gradually increased substantially in proportion to the increase in impurity concentration.It is characterized by having.
[0087]
Therefore, it is possible to provide a wafer manufacturing means for reducing crystal defects on the electrode forming surface of the window layer without reducing the transmittance of the window layer of the wafer having the semiconductor light emitting element structure with respect to the emission wavelength. In the conventional example, crystal defects were easily generated in the vicinity of the interface where the impurity concentration was sharply changed.However, by gradually increasing the impurity concentration, the transmittance and the resistivity were not different from those of the conventional example, so the operating voltage was also low. The effect was slightly smaller than that in the case where In was added, but the crystal defects could be reduced to about 1/2 and the yield could be improved by about 7%.
[0088]
Claims5According to the above described semiconductor light emitting device, the impurity concentration in the first window layer near the interface between the second cladding layer and the first window layer is gradually increased.
[0089]
Therefore, crystal defects on the electrode forming surface of the window layer can be determined without reducing the transmittance of the window layer of the wafer having the semiconductor light emitting element configuration with respect to the emission wavelength.4It is possible to provide a wafer manufacturing means for further reducing the number of wafers as compared with the means. In the vicinity of the interface between the cladding layer and the window layer, crystal defects are likely to occur, but the effect is slightly smaller than that in the case where In is increased by increasing the impurity concentration near the interface to increase the transmittance and the operating voltage. The crystal defects could be reduced to about 3/10.
[0090]
Further, in the semiconductor light emitting device according to claim 4, the In composition ratio in the second window layer near the interface between the first window layer and the second window layer is gradually increased almost in proportion to the increase in the impurity concentration.AndYou.
[0091]
Therefore, a crystal defect on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting device configuration is claimed.3,5With respect to the means described above, a wafer manufacturing means that can be further reduced can be provided. As a result, the yield could be improved by about 50%.
[0092]
Claims6According to the semiconductor light emitting device described above, a current blocking layer is provided on the interface between the second cladding layer and the first window layer, and the shape of the current blocking layer is substantially similar to the shape of the upper electrode. It is characterized by being.
[0093]
Therefore, it is possible to provide a semiconductor light emitting device having few crystal defects on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting device configuration, good yield, and low reactive current. As a result, the brightness of the semiconductor light emitting device could be increased by about 40%.
[0094]
Claims7Semiconductor light emitting device as describedToAccording to this, the current blocking layer has the following configuration.
Current blocking layer: InvAlx6Ga1-v-x6P (however, 0 ≦ v ≦ 1, 0 ≦ x6 ≦ 1).
[0095]
Therefore, it is possible to provide a semiconductor light emitting device having few crystal defects on the electrode forming surface of the window layer of the wafer having the semiconductor light emitting device structure, good yield, and low reactive current. Since the InAlGaP current blocking layer containing In and Al is provided between the cladding layer and the window layer, crystal defects can be further reduced.TwoIt could be reduced to the extent.
[0096]
Claims8Semiconductor light emitting device as describedToAccording to the present invention, the current blocking layer is provided at a central portion or a peripheral portion of the semiconductor light emitting device.
[0097]
Accordingly, a semiconductor light emitting device having few crystal defects on the electrode forming surface of the window layer, a high yield, and high luminance, or a semiconductor light emitting device having a fast response of light ON / OFF to current ON / OFF (fast modulation speed). Can be provided. Further, when the current blocking layer is provided in the peripheral portion of the semiconductor light emitting element, the current is concentrated in the central portion, and the current density of the light emitting portion increases, so that it is possible to select a small operating current. The response speed is determined by setting the area S = 100 μmφ, which makes it possible to obtain7The light emitting response speed τ of the semiconductor light emitting device described above is 17.1 μs.8The emission response speed τ of the described semiconductor light emitting device could be improved to 4.4 μs.
[Brief description of the drawings]
1A and 1B are diagrams illustrating a semiconductor light emitting device according to a first embodiment of the present invention, wherein FIG. 1A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 1B is an In composition ratio in a thickness direction of a window layer. FIG.
FIG. 2 is a diagram illustrating the dependency of the hillock density on the In composition ratio in a GaP single layer on a GaAs substrate according to the present invention.
3A and 3B are diagrams illustrating a semiconductor light emitting device according to a second embodiment of the present invention, wherein FIG. 3A is a schematic sectional view of the semiconductor light emitting device, and FIG. 3B is an In composition ratio in a thickness direction of a window layer. FIG.
4A and 4B are diagrams illustrating a semiconductor light emitting device according to a third embodiment of the present invention, wherein FIG. 4A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 4B is an In composition ratio in a thickness direction of a window layer. FIG.
5A and 5B are diagrams illustrating a semiconductor light emitting device according to a fourth embodiment of the present invention, wherein FIG. 5A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 5B is an In composition ratio in the thickness direction of the window layer. FIG.
6A and 6B are diagrams illustrating a semiconductor light emitting device according to a fifth embodiment of the present invention. FIG. 6A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 6B is a diagram illustrating a p-type impurity in a thickness direction of a window layer. It is a figure showing distribution of density.
7A and 7B are diagrams illustrating a semiconductor light emitting device according to a sixth embodiment of the present invention, in which FIG. 7A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 7B is an In composition ratio in a thickness direction of a window layer. FIG. 6 is a diagram showing a distribution of the p-type impurity concentration of the first window layer 61 and the second window layer 62.
8A and 8B are diagrams illustrating a semiconductor light emitting device according to Embodiment 7 of the present invention, wherein FIG. 8A is a schematic cross-sectional view of the semiconductor light emitting device, and FIG. 8B is an In composition ratio in the thickness direction of the window layer. FIG. 4C is a diagram showing the distribution of the p-type impurity concentration in the first window layer, the second window layer, and the second cladding layer.
FIG. 9 is a schematic sectional view illustrating a semiconductor light emitting device according to an eighth embodiment of the present invention.
FIG. 10 is a schematic sectional view illustrating a semiconductor light emitting device according to a ninth embodiment of the present invention.
FIG. 11 is a schematic sectional view of a semiconductor light emitting device of Conventional Example 1.
FIG. 12 is a schematic sectional view of a semiconductor light emitting device of Conventional Example 2.
[Explanation of symbols]
100 Semiconductor light-emitting device according to Embodiment 1 of the present invention
200 Semiconductor Light Emitting Element of Second Embodiment of Present Invention
300 Semiconductor Light-Emitting Element of Third Embodiment of Present Invention
400 Semiconductor Light-Emitting Element of Fourth Embodiment of Present Invention
500 Semiconductor Light-Emitting Element of Embodiment 5 of the Present Invention
600 Semiconductor Light-Emitting Element of Sixth Embodiment of Present Invention
700 Semiconductor Light Emitting Element of Embodiment 7 of the Present Invention
800 Semiconductor light emitting device of embodiment 8 of the present invention
900 Semiconductor light emitting device according to embodiment 9 of present invention
1 n-type GaAs substrate
2 n-type In0.5Al0.5P clad layer
3 Undoped In0.5(Ga0.55Al0.45)0.5P light emitting layer
4 p-type In0.5Al0.5P clad layer
5 Window layer
5a Electrode formation surface
6 p-side electrode (upper electrode)
7 n-side electrode (lower electrode)
8 n-type current blocking layer
11 p-type GaP first window layer
12 p-type GaP second window layer
21 p-type In0.01Ga0.99P first window layer
22 p-type In0.01Ga0.99P second window layer
31 p-type In0.01Al0.2Ga0.79P first window layer
32 p-type In0.01Al0.2Ga0.79P second window layer
41 First window layer
61 1st window layer
62 Second window layer
71 p-type In0.01Ga0.99P first window layer
72 Second window layer

Claims (8)

基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、
該基板には下部電極、および該窓層には上部電極が形成され、
該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とからなり、該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、
前記第1窓層と第2窓層の界面があり、
前記第1窓層の前記界面近傍の部分前記第1窓層における前記部分と隣接する部分よりIn ( インジウム)元素の組成比が高く
前記第2窓層の前記界面近傍の部分は、前記第2窓層における前記部分と隣接する部分よりIn元素の組成比が高く
前記第1,第2窓層はIn w Ga x4 Al 1-w-x4 P(但し、0≦w≦1、0≦x4≦1)からなることを特徴とする半導体発光素子。
A substrate, a first cladding layer made of at least a group III-V compound semiconductor crystal, a light-emitting layer, a second cladding layer having a conductivity type opposite to that of the first cladding layer, and a window layer are laminated in this order;
A lower electrode on the substrate, and an upper electrode on the window layer;
The window layer is composed of a first window layer closer to the light emission layer and the light emitting layer farther the second window layer, said second window layer is a semiconductor layer having high impurity concentration than the first window layer,
There is an interface between the first window layer and the second window layer,
A portion of the first window layer near the interface has a higher composition ratio of In ( indium) element than a portion of the first window layer adjacent to the portion ,
The vicinity of the interface portion of the second window layer has a high composition ratio of In element than the portion and the adjacent portion of the previous SL second window layer,
The first, the second window layer In w Ga x4 Al 1-w -x4 P ( where, 0 ≦ w ≦ 1,0 ≦ x4 ≦ 1) semiconductor light emitting device characterized by comprising a.
請求項1記載の半導体発光素子において、
前記半導体の各層は次の構成よりなることを特徴とする半導体発光素子。
半導体基板:GaAs、
第1クラッド層:In0.5(Gax1Al1-x10.5P(但し、0≦x1≦1)、
活性層:In0.5(Gax2Al1-x20.5P(但し、0≦x2<1)、または、GayAl1-yAs(但し、0≦y≦1)、または、InzGa1-zAs(但し、0≦z<1)、
第2クラッド層:In0.5(Gax3Al1-x30.5P(但し、0≦x3≦1)。
The semiconductor light emitting device according to claim 1,
Each of the semiconductor layers has the following configuration.
Semiconductor substrate: GaAs,
First cladding layer: In 0.5 (Ga x1 Al 1-x1 ) 0.5 P (0 ≦ x1 ≦ 1),
Active layer: In 0.5 (Ga x2 Al 1 -x2) 0.5 P ( where, 0 ≦ x2 <1), or, Ga y Al 1-y As ( where, 0 ≦ y ≦ 1), or, an In z Ga 1 -z As (where 0 ≦ z <1),
Second cladding layer: In 0.5 (Ga x3 Al 1-x3 ) 0.5 P (where 0 ≦ x3 ≦ 1 ).
請求項1記載の半導体発光素子において、
前記第2クラッド層と前記第1窓層の界面があり、
前記第1窓層の前記界面近傍の部分は、前記第1窓層における前記部分と隣接する部分よりIn元素の組成比こと特徴とする半導体発光素子。
The semiconductor light emitting device according to claim 1,
There is an interface between the second cladding layer and the first window layer,
Wherein the vicinity of the interface portion of the first window layer, the semiconductor light emitting element according to the part and have a composition ratio of In element higher than adjacent portions This and wherein in the first window layer.
基板と、少なくともIII−V族化合物半導体結晶よりなる第1クラッド層、発光層、前記第1クラッド層と反対導電型の第2クラッド層、及び窓層、がこの順序で積層されており、
該基板および該窓層の片面にはそれぞれ電極が形成され、
該窓層は発光層に近い第1窓層と発光層より遠い第2窓層とからなり
該第2窓層は該第1窓層より不純物濃度の高い半導体層であって、
前記第1窓層と第2窓層の界面近傍において、前記発光層から離れるにしたがって前記第2窓層内の不純物濃度を漸次増加させ
前記第1窓層と第2窓層の界面近傍おける前記第2窓層内のIn組成比を不純物濃度の増加にほぼ比例して漸次増加させたことを特徴とする半導体発光素子。
A substrate, a first cladding layer made of at least a group III-V compound semiconductor crystal, a light-emitting layer, a second cladding layer having a conductivity type opposite to that of the first cladding layer, and a window layer are laminated in this order;
Electrodes are formed on one surface of the substrate and the window layer, respectively.
The window layer is composed of a first window layer closer to the light emission layer and farther from the light-emitting layer and the second window layer,
The second window layer is a semiconductor layer having a higher impurity concentration than the first window layer,
Near the interface between the first window layer and the second window layer, gradually increasing the impurity concentration in the second window layer as the distance from the light emitting layer increases ;
A semiconductor light emitting device wherein an In composition ratio in the second window layer near an interface between the first window layer and the second window layer is gradually increased almost in proportion to an increase in impurity concentration .
請求項4記載の半導体発光素子において、
前記第2クラッド層と前記第1窓層の界面近傍の前記第1窓層内の不純物濃度を漸次増加させたことを特徴とする半導体発光素子。
The semiconductor light emitting device according to claim 4,
A semiconductor light emitting device wherein an impurity concentration in the first window layer near an interface between the second cladding layer and the first window layer is gradually increased.
請求項1記載の半導体発光素子において、
前記第2クラッド層と前記第1窓層との界面上に電流阻止層を配設し、且つ、該電流阻止層の形状は上部電極の形状とほぼ相似形であることを特徴とする半導体発光素子。
The semiconductor light emitting device according to claim 1,
A semiconductor light emitting device, wherein a current blocking layer is provided on an interface between the second cladding layer and the first window layer, and the shape of the current blocking layer is substantially similar to the shape of the upper electrode. element.
請求項6記載の半導体発光素子において、
前記電流阻止層が次の構成よりなることを特徴とする半導体発光素子。
電流阻止層:InvAlx6Ga1-v-x6P(但し、0≦v≦1、0≦x6≦1)。
The semiconductor light emitting device according to claim 6,
A semiconductor light emitting device, wherein the current blocking layer has the following configuration.
Current blocking layer: In v Al x6 Ga 1-v-x6 P (where 0 ≦ v ≦ 1, 0 ≦ x6 ≦ 1).
請求項6記載の半導体発光素子において、
前記電流阻止層が半導体発光素子の中央部または周辺部に設けられていることを特徴とする半導体発光素子。
The semiconductor light emitting device according to claim 6,
The semiconductor light emitting device, wherein the current blocking layer is provided at a central portion or a peripheral portion of the semiconductor light emitting device.
JP27323898A 1998-09-28 1998-09-28 Semiconductor light emitting device Expired - Fee Related JP3587699B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27323898A JP3587699B2 (en) 1998-09-28 1998-09-28 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27323898A JP3587699B2 (en) 1998-09-28 1998-09-28 Semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JP2000101132A JP2000101132A (en) 2000-04-07
JP3587699B2 true JP3587699B2 (en) 2004-11-10

Family

ID=17525053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27323898A Expired - Fee Related JP3587699B2 (en) 1998-09-28 1998-09-28 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JP3587699B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100588377B1 (en) * 2005-05-10 2006-06-09 삼성전기주식회사 Vertically structured gan type light emitting diode and method of manufacturing the same
JP5586372B2 (en) * 2010-08-10 2014-09-10 昭和電工株式会社 Light emitting diode, light emitting diode lamp, and lighting device
JP2012119585A (en) 2010-12-02 2012-06-21 Showa Denko Kk Light-emitting diode, light-emitting diode lamp and luminaire
JP2012186194A (en) * 2011-03-03 2012-09-27 Showa Denko Kk Light-emitting diode

Also Published As

Publication number Publication date
JP2000101132A (en) 2000-04-07

Similar Documents

Publication Publication Date Title
US6057562A (en) High efficiency light emitting diode with distributed Bragg reflector
US6169296B1 (en) Light-emitting diode device
US5789768A (en) Light emitting diode having transparent conductive oxide formed on the contact layer
JPH07254732A (en) Semiconductor light emitting device
JPH06296040A (en) Manufacture of light-emitting diode
JP3240097B2 (en) Semiconductor light emitting device
US7528417B2 (en) Light-emitting diode device and production method thereof
JP2000244013A (en) Nitride semiconductor element
JPH04212479A (en) Semiconductor light-emitting device
JPH0614564B2 (en) Semiconductor light emitting element
JP2000286451A (en) Nitride semiconductor device
JP2002232005A (en) Light emitting element
JP3587699B2 (en) Semiconductor light emitting device
JPH04213878A (en) Semiconductor light-emitting element
EP2101361B1 (en) Semiconductor light emitting device and method for manufacturing same, and epitaxial wafer
KR100329054B1 (en) Semiconductor light emitting element and method for fabricating the same
JP2003008058A (en) AlGaInP EPITAXIAL WAFER, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT USING THE SAME
JPH0974221A (en) Semiconductor light emitting element
KR100644151B1 (en) Light-emitting diode device and production method thereof
JP3240099B2 (en) Semiconductor light emitting device and method of manufacturing the same
US6245588B1 (en) Semiconductor light-emitting device and method of manufacturing the same
JP4139321B2 (en) Manufacturing method of light emitting diode
WO2004070851A1 (en) Light-emitting diode device and production method thereof
JP3005115B2 (en) Semiconductor light emitting device
JP3536976B2 (en) Light emitting element

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040127

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040325

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040803

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040810

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070820

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080820

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080820

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090820

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees