WO2014040334A1 - 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管 - Google Patents

一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管 Download PDF

Info

Publication number
WO2014040334A1
WO2014040334A1 PCT/CN2012/083427 CN2012083427W WO2014040334A1 WO 2014040334 A1 WO2014040334 A1 WO 2014040334A1 CN 2012083427 W CN2012083427 W CN 2012083427W WO 2014040334 A1 WO2014040334 A1 WO 2014040334A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
region
oxide layer
gate
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/083427
Other languages
English (en)
French (fr)
Inventor
孙伟锋
刘斯扬
祝靖
钱钦松
徐申
陆生礼
时龙兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to US14/349,632 priority Critical patent/US9159818B2/en
Publication of WO2014040334A1 publication Critical patent/WO2014040334A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Definitions

  • the invention relates to the field of high voltage power semiconductor devices, in particular to an N-type silicon-on-insulator lateral insulated gate bipolar transistor capable of improving current density suitable for high voltage applications, and is suitable for plasma flat panel display devices and half bridge driving circuits. And driver chips such as automotive production.
  • power semiconductor devices have received more and more attention as the basic electronic components for energy control and conversion in electronic power systems.
  • the technical requirements for improving the performance of power semiconductor devices are mainly in terms of device integration, high withstand voltage, high current, and good isolation from low voltage circuit parts.
  • the specific type of power semiconductor device determines the power amplifier's ability to handle high voltage and large current.
  • the structure and manufacturing process of the power semiconductor device are also important factors.
  • the insulated gate bipolar devices in the 1980s have high current processing capability of high voltage triodes and gate voltage control characteristics of insulated gate field effect transistors.
  • Input impedance, high switching speed, small driving power, large current driving capability and low on-resistance are the near-ideal power semiconductor devices with broad development and application prospects.
  • Insulator silicon in this situation Silicon On Insulator, SOI
  • SOI-LIGBT Insulator-on-silicon laterally insulated gate bipolar transistor
  • the core electronic components of integrated circuits are widely used in converter systems with DC voltages of 600V and above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, etc.
  • the silicon-on-insulator laterally insulated gate bipolar device has a current density that is not high enough compared to the vertical device. This problem is usually solved by increasing the area of the lateral device to achieve high current drive capability, but increasing the area to consume more chips. The area is at the cost and the cost is increased.
  • the invention introduces a high current N-type silicon-on-insulator laterally-insulated gate bipolar transistor, and the current density is greatly improved compared with the ordinary insulator-on-silicon N-type laterally insulated gate bipolar transistor.
  • the invention provides a high current N-type silicon-on-insulator laterally insulated gate bipolar transistor.
  • a high current N-type silicon-on-insulator laterally insulated gate bipolar transistor comprising: a P-type silicon substrate, and a buried oxygen layer on the P-type silicon substrate, on the buried oxide layer
  • An N-type epitaxial layer is disposed, and an N-type central buffer well region is disposed in the N-type epitaxial layer, and a first N-type base region, a P-type emitter region, and a second N-type base are sequentially disposed in the N-type central buffer well region.
  • a first base metal is connected to the first N-type base region, an emitter metal is connected to the P-type emitter region, and a second base metal is connected to the second N-type base region at the N-type center.
  • the first outer side of the buffer well region is respectively provided with a first P-type body region and a second P-type body region, and the first P-type body region and the second P-type body region are symmetric with respect to the N-type central buffer well region, in the first P-type
  • the first N-type source region, the first P-type body contact region and the second N-type source region are sequentially disposed in the body region, and the third N-type source region and the second P-type are sequentially disposed in the second P-type body region.
  • the body contact region and the fourth N-type source region are in the first N-type source region, the first P-type body contact region, the second N-type source region, the third N-type source region, the second P-type body contact region, and Connected to the source of gold on the four N-type source regions Is a first N-type buffer well region outside the first P-type body region, a first P-type drain region in the first N-type buffer well region, and a first connection on the first P-type drain region a drain metal and a first drain metal connected to the first base metal, a second N-type buffer well region outside the second P-type body region, and a second N-type buffer well region a second P-type drain region, a second drain metal is connected to the second P-type drain region, and the second drain metal is connected to the second base metal, and the first surface of the N-type epitaxial layer 3 is provided a gate oxide layer, a first field oxide layer, a second gate oxide layer, a second field oxide layer, a third gate
  • a first polysilicon gate is disposed on the first gate oxide layer and the first polysilicon gate extends to an upper surface of the first field oxide layer
  • a second polysilicon gate is disposed on the second gate oxide layer
  • a second polysilicon gate extends to an upper surface of the second field oxide layer
  • a third polysilicon gate is disposed on the third gate oxide layer
  • the third polysilicon gate extends to an upper surface of the third field oxide layer
  • a fourth polysilicon gate is disposed on the fourth gate oxide layer and the fourth polysilicon gate extends to the upper surface of the fourth field oxide layer, in the first polysilicon gate, the second polysilicon gate, and the third a gate metal is connected to the polysilicon gate and the fourth polysilicon gate, and the third field oxide layer, the third polysilicon gate, the first N-type source region, the first P-type body contact region, and the second N Source region, first P-type drain region, first polysilicon gate, first field oxide layer, P-type emitter region, first N-
  • the present invention has the following advantages:
  • the transistor of the present invention has a symmetrical structure including a first N-type laterally insulated gate bipolar transistor symmetrically symmetrical, a first N-type lateral double-diffused metal oxide field effect transistor, and a first PNP-type high voltage bipolar transistor.
  • the collector regions of the bipolar transistor and the second PNP type high voltage bipolar transistor are connected by a metal layer, and the drain of the first N-type laterally insulated gate bipolar transistor and the first PNP type high voltage are respectively passed through the metal layer.
  • the bases of the bipolar transistors are connected together, the drain of the second N-type laterally insulated gate bipolar transistor is connected to the base of the second PNP-type high voltage bipolar transistor, and the first PNP type high voltage bipolar type PNP transistor and the emitter of the second type high-voltage bipolar transistor as the output.
  • the structure of the transistor is shown in Figure 2.
  • the drain current of the first N-type laterally insulated gate bipolar transistor and the drain current of the first N-type lateral double-diffused metal oxide field effect transistor are concentrated to form a first PNP type high voltage bipolar transistor
  • the base current, the drain current of the second N-type laterally insulated gate bipolar transistor and the drain current of the second N-type lateral double-diffused metal oxide field effect transistor form a second PNP type high voltage bipolar transistor
  • the base current, amplified by the PNP-type high-voltage bipolar transistor, the current output from the emitter of the PNP-type high-voltage bipolar transistor will amplify the base current, thereby increasing the current density of the entire device.
  • the equivalent circuit diagram of the transistor is shown in FIG. 3.
  • FIG. 4 shows the comparison of current densities of the N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention and the general-area N-type insulated gate bipolar transistor of the same area. It can be seen that the current density of the N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention has an increase in current density of 25% or more compared to a general N-type insulated gate bipolar transistor.
  • the device of the present invention does not increase the original layout area of the device compared with the conventional device while increasing the current density.
  • the device of the invention does not affect the withstand voltage level of the device while increasing the current density, and the basic performance requirements of the device can still meet the requirements.
  • 5 is a graph showing the comparison of the off-state breakdown voltages of the N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention and the general-purpose N-type insulated gate bipolar transistor of the same area, and the N-type of the present invention can be seen in the figure.
  • the off-state breakdown voltage of the silicon-on-insulator laterally insulated gate bipolar transistor can be kept consistent with a general N-type insulated gate bipolar transistor of the same area.
  • the device of the present invention adopts the SOI process, and does not require additional process steps, and is fully compatible with the existing CMOS process.
  • Figure 1 shows a conventional N-type silicon-on-insulator laterally insulated gate bipolar transistor cross-sectional structure.
  • FIG. 2 is a cross-sectional view showing an N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention.
  • FIG. 3 is an equivalent circuit diagram of an N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention.
  • FIG. 4 is a comparison diagram of drain current densities of an N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention and a conventional silicon-on-insulator N-type insulated gate bipolar transistor of the same area.
  • FIG. 5 is a comparison diagram of an off-state reverse breakdown voltage of an N-type silicon-on-insulator laterally insulated gate bipolar transistor of the present invention and an off-state reverse breakdown voltage of a conventional silicon-on-insulator N-type insulated gate bipolar transistor.
  • a high current N-type silicon-on-insulator laterally insulated gate bipolar transistor comprising: a P-type substrate 1 on which a buried oxide layer 2 is provided.
  • An N-type epitaxial layer 3 is disposed on the buried oxide layer 2
  • an N-type central buffer well region 22 is disposed in the N-type epitaxial layer 3, wherein the N-type central buffer well region 22 is sequentially provided with a first
  • the N-type base region 19, the P-type emitter region 20 and the second N-type base region 19' are connected to the first base metal region 19 with a first base metal 18, and the P-type emitter region 20 is connected with an emitter.
  • the metal 21 has a second base metal 18' connected to the second N-type base region 19', and a first P-type body region 16 and a second P-type body respectively disposed on both outer sides of the N-type central buffer well region 22.
  • the first P-type body region 16 and the second P-type body region 16' are symmetric with respect to the N-type central buffer well region 22, and the first N-type source region 13 is sequentially disposed in the first P-type body region 16.
  • the first P-type body contact region 14 and the second N-type source region 15 are sequentially provided with a third N-type source region 13', a second P-type body contact region 14', and a portion in the second P-type body region 16'.
  • N-type source regions 15' in the first N-type source region 13, the first P-type body connection
  • the contact region 14, the second N-type source region 15, the third N-type source region 13', the second P-type body contact region 14', and the fourth N-type source region 15' are connected to the source metal 12, at the first
  • a first N-type buffer well region 4 is disposed outside the P-type body region 16
  • a first P-type drain region 5 is disposed in the first N-type buffer well region 4, and a first connection is connected to the first P-type drain region 5.
  • the buffer well region 4' is provided with a second P-type drain region 5', and a second drain metal 6' is connected to the second P-type drain region 5' and the second drain metal 6' is connected to the second base
  • the pole metal 18' is connected, and a first gate oxide layer 24, a first field oxide layer 26, a second gate oxide layer 24', a second field oxide layer 26', and a third gate oxide are disposed on the surface of the N-type epitaxial layer 3.
  • one end of the first gate oxide layer 24 is opposite to one end of the first field oxide layer 26 and is located at the N-type center buffer Between the well region 22 and the first P-type body region 16, the other of the first gate oxide layer 24 Extending to the second N-type source region 15 and ending at the outer boundary of the second N-type source region 15, the other end of the first field oxide layer 26 extends and enters the N-type central buffer well region 22, and the second gate oxide layer 24' One end of the second field oxide layer 26' is opposite to the end of the second field oxide layer 26' and is located between the N-type central buffer well region 22 and the second P-type body region 16'.
  • the other end of the second gate oxide layer 24' is directed to the third N-type source.
  • the region 13' extends and terminates at the outer boundary of the third N-type source region 13'
  • the other end of the second field oxide layer 26' extends and enters the N-type central buffer well region 22
  • the third gate oxide layer 11 has one end
  • One end of the three field oxide layer 8 is located between the first P-type body region 16 and the first N-type buffer well region 4
  • the other end of the third gate oxide layer 11 extends toward the first N-type source region 13 and ends at The outer boundary of the first N-type source region 13, the other end of the third field oxide layer 8 extends toward the first P-type drain region 5 and terminates at the outer boundary of the first P-type drain region 5, and the fourth gate oxide layer 11'
  • One end of the fourth field oxide layer 8' abuts between the second P-type body region 16' and the second N-type buffer well region 4', and the other end of the fourth gate oxide layer 11' faces the fourth N Type
  • the polysilicon gate 25' and the second polysilicon gate 25' extend to the upper surface of the second field oxide layer 26', and the third polysilicon gate 10 is disposed on the third gate oxide layer 11 and the third polycrystal
  • the silicon gate 10 extends to the upper surface of the third field oxide layer 8
  • the fourth polysilicon gate 10' is disposed on the fourth gate oxide layer 11'
  • the fourth polysilicon gate 10' extends to the fourth field oxide layer.
  • a gate metal 17 is connected to the first polysilicon gate 25, the second polysilicon gate 25', the third polysilicon gate 10, and the fourth polysilicon gate 10'.
  • a three-field oxide layer 8 a third polysilicon gate 10, a first N-type source region 13, a first P-type body contact region 14, a second N-type source region 15, and a first P-type drain region 5, first Polysilicon gate 25, first field oxide layer 26, P-type emitter region 20, first N-type base region 1 9.
  • a second N-type base region 19', a second field oxide layer 26', a second polysilicon gate 25', a third N-type source region 13', a second P-type body contact region 14', and a fourth N A passivation layer 7 is provided on the surface of the source region 15', the fourth polysilicon gate 10', the fourth field oxide layer 8', and the second P-type drain region 5'.
  • the spacing between the P-type emitter region 20 of the N-type silicon-on-insulator laterally-insulated gate bipolar transistor and the first N-type base region 19 and the second N-type base region 19' is 1 micrometer to 2 micrometers, and the first N
  • the distance between the type base region 19 and the left edge of the N-type central buffer well region 22 is 1 micrometer to 2 micrometers, and the distance between the second N-type base region 19' and the right edge of the N-type central buffer well region 22 is 1 micrometer to 2 Micron.
  • the invention is prepared by the following method:
  • a conventional SOI layer is formed on a P-type substrate, an N-type epitaxial layer 3 is formed on the SOI layer, and then a transistor is fabricated, including by implanting high-energy phosphorus ions on the N-type epitaxial layer 3, and forming after high-temperature annealing.
  • the first N-type buffer well region 4, the second N-type buffer well region 4' and the N-type central buffer well region 22 are formed by high-energy boron ion implantation to form a first P-type body region 16 and a second P-type body by high-temperature annealing.
  • the first field oxide layer 26, the second field oxide layer 26', the third field oxide layer 8 and the fourth field oxide layer 8' are grown at a high temperature, followed by a third gate oxide layer 11 and a first gate. Growth of the oxide layer 24, the second gate oxide layer 24' and the fourth gate oxide layer 11', and then depositing the third polysilicon gate 10, the first polysilicon gate 25, the second polysilicon gate 25', and The fourth polysilicon gate 10' etches the polysilicon gate, and the heavily doped first P-type drain region 5, the first N-type source region 13, and the first P are fabricated by high-dose boron ion and phosphorus ion implantation.
  • the body contact region 14, the second N-type source region 15, the first N-type base region 19, the P-type emitter region 20, the second N-type base region 19', the third N-type source region 13', and the second P-type Body contact a region 14', a fourth N-type source region 15' and a second P-type drain region 5', depositing silicon dioxide, etching the electrode contact region, depositing a metal, etching the metal and extracting the electrode, and finally passivating deal with.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管，包括：P型衬底（1），在P型衬底（1）上设有埋氧层（2），在埋氧层（2）上设有N型外延层（3），在N型外延层（3）内部设有N型缓冲阱区（4，4'），P型体区（16，16'）和N型中心缓冲阱区（22），在N型缓冲阱区内设有P型漏区（5，5'），在P型体区（16，16）中设有N型源区（13，13'，15，15'）和P型体接触区（14，14'），在N型中心缓冲阱区（22）内设有N型基区（19，19'）和P型发射区（20），在N型外延层（3）的表面设有栅氧化层（24，24'，11，11'）和场氧化层（26，26'，8，8'），在栅氧化层（24，24'，11，11'）的表面设有多晶硅栅（25，25'，10，10'），晶体管表面一定范围内还设有钝化层（7）和金属层（6，6'，12，17，18，18'，21），其特征在于：晶体管为对称结构，P型漏区（5，5'）上的漏极金属（6，6'）分别与对应的N型基区（19，19'）上的基极金属（18，18'）通过金属层连通，并从P型发射区（20）输出，可以在不增加晶体管面积的基础上有效提高电流密度。

Description

一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管 技术领域
本发明涉及高压功率半导体器件领域，具体来说，是一种适用于高压应用的能够提高电流密度的N型绝缘体上硅横向绝缘栅双极型晶体管，适用于等离子平板显示设备、半桥驱动电路以及汽车生产领域等驱动芯片。
背景技术
随着电子电力技术的不断发展，功率半导体器件作为电子电力系统中能量控制和转化的基本电子元器件，受到越来越多的关注。提高功率半导体器件性能的技术要求主要体现在器件的可集成性、高耐压、大电流和与低压电路部分的良好的隔离能力这些方面。功率半导体器件具体的种类决定功率集成电路处理高电压、大电流能力的大小，另外功率半导体器件的结构和制造工艺也是重要的影响因素。
随着功率半导体器件的理论研究和制造工艺水平的不断提高，80年代出现的绝缘栅双极型器件集高压三极管的大电流处理能力和绝缘栅场效应晶体管栅压控制特性于一身，具有高的输入阻抗、高的开关速度、小的驱动功率，大的电流驱动能力和低的导通阻抗等优点，是近乎理想的功率半导体器件，具有广泛的发展和应用前景。
功率半导体器件的可集成性、高耐压、大电流的需求解决后，它的隔离性成为主要矛盾。在这种形势下绝缘体上硅（Silicon On Insulator, SOI）工艺技术问世了，其独特的绝缘埋层把器件与衬底完全隔离，在很大程度上减轻了硅器件的寄生效应，大大提高了器件和电路的性能 。绝缘体上硅横向绝缘栅双极型晶体管（SOI-LIGBT）是一种典型的基于SOI工艺的器件，具有耐压高、驱动电流能力强、开关速度快和功率损耗低等优点，已逐渐成为功率集成电路的核心电子元件，广泛应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
绝缘体上硅横向绝缘栅双极型器件与纵向器件相比，电流密度不够高，这个问题通常以加大横向器件的面积从而获得高的电流驱动能力解决，但是增大面积以耗费更多的芯片面积为代价，同时增加了成本。本发明介绍了一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管，与相同面积的普通绝缘体上硅N型横向绝缘栅双极型晶体管相比，电流密度出现较大幅度提高。
 技术问题
本发明提供一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管。
 技术解决方案
本发明采用如下技术方案：一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管，包括：P型硅衬底，在P型硅衬底上设有埋氧层，在埋氧层上设有N型外延层，在N型外延层内设有N型中心缓冲阱区，在N型中心缓冲阱区内顺序设有第一N型基区、P型发射区及第二N型基区，在第一N型基区上连接有第一基极金属，在P型发射区上连接有发射极金属，在第二N型基区上连接有第二基极金属，在N型中心缓冲阱区的两外侧分别设有第一P型体区及第二P型体区且第一P型体区和第二P型体区对称于N型中心缓冲阱区，在第一P型体区内顺序设有第一N型源区、第一P型体接触区及第二N型源区，在第二P型体区内顺序设有第三N型源区、第二P型体接触区及第四N型源区，在第一N型源区、第一P型体接触区、第二N型源区、第三N型源区、第二P型体接触区及第四N型源区上连接有源极金属，在第一P型体区外侧设有第一N型缓冲阱区，在第一N型缓冲阱区内设有第一P型漏区，在第一P型漏区上连接有第一漏极金属且第一漏极金属与所述的第一基极金属连接，在第二P型体区外侧设有第二N型缓冲阱区，在第二N型缓冲阱区内设有第二P型漏区，在第二P型漏区上连接有第二漏极金属且第二漏极金属与所述的第二基极金属连接，在N型外延层3的表面设有第一栅氧化层、第一场氧化层、第二栅氧化层、第二场氧化层、第三栅氧化层、第三场氧化层、第四栅氧化层及第四场氧化层，第一栅氧化层的一端与第一场氧化层的一端相抵且位于N型中心缓冲阱区与第一P型体区之间，第一栅氧化层的另一端向第二N型源区延伸并止于第二N型源区的外边界，第一场氧化层的另一端延伸并进入N型中心缓冲阱区，第二栅氧化层的一端与第二场氧化层的一端相抵且位于N型中心缓冲阱区与第二P型体区之间，第二栅氧化层的另一端向第三N型源区延伸并止于第三N型源区的外边界，第二场氧化层的另一端延伸并进入N型中心缓冲阱区，第三栅氧化层的一端与第三场氧化层的一端相抵且位于第一P型体区与第一N型缓冲阱区之间，第三栅氧化层的另一端向第一N型源区延伸并止于第一N型源区的外边界，第三场氧化层的另一端向第一P型漏区延伸并止于第一P型漏区的外边界，第四栅氧化层的一端与第四场氧化层的一端相抵且位于第二P型体区与第二N型缓冲阱区之间，第四栅氧化层的另一端向第四N型源区延伸并止于第四N型源区的外边界，第四场氧化层的另一端向第二P型漏区延伸并止于第二P型漏区的外边界，在第一栅氧化层上设有第一多晶硅栅且第一多晶硅栅延伸至第一场氧化层的上表面，在第二栅氧化层上设有第二多晶硅栅且第二多晶硅栅延伸至第二场氧化层的上表面，在第三栅氧化层上设有第三多晶硅栅且第三多晶硅栅延伸至第三场氧化层的上表面，在第四栅氧化层上设有第四多晶硅栅且第四多晶硅栅延伸至第四场氧化层的上表面，在第一多晶硅栅、第二多晶硅栅、第三多晶硅栅及第四多晶硅栅上连接有栅极金属，在第三场氧化层、第三多晶硅栅、第一N型源区、第一P型体接触区、第二N型源区、第一P型漏区、第一多晶硅栅、第一场氧化层、P型发射区、第一N型基区、第二N型基区、第二场氧化层、第二多晶硅栅、第三N型源区、第二P型体接触区、第四N型源区、第四多晶硅栅、第四场氧化层及第二P型漏区的表面设有钝化层，在所述的N型外延层内设有N型横向绝缘栅双极型晶体管，PNP型高压双极型晶体管和N型横向双扩散金属氧化层场效应晶体管，连接于所述的N型横向绝缘栅双极型晶体管漏极的漏极金属通过金属层与连接于PNP型高压双极型晶体管基极的基极金属连接，并通过所述的发射极金属输出。
 有益效果
与现有技术相比，本发明具有如下优点：
（1）、本发明晶体管为对称型结构，其中包括左右对称的第一N型横向绝缘栅双极型晶体管、第一N型横向双扩散金属氧化层场效应晶体管、第一PNP型高压双极型晶体管、第二PNP型高压双极型晶体管、第二N型横向双扩散金属氧化层场效应晶体管及第二N型横向绝缘栅双极型晶体管，第一N型横向绝缘栅双极型晶体管、第一N型横向双扩散金属氧化层场效应晶体管、第二N型横向双扩散金属氧化层场效应晶体管及第二N型横向绝缘栅双极型晶体管的源极区和第一PNP型高压双极型晶体管及第二PNP型高压双极型晶体管的集电区通过金属层连接在一起，通过金属层分别将第一N型横向绝缘栅双极型晶体管的漏极和第一PNP型高压双极型晶体管基极连接在一起，第二N型横向绝缘栅双极型晶体管的漏极和第二PNP型高压双极型晶体管基极连接在一起，以第一PNP型高压双极型晶体管及第二PNP型高压双极型晶体管的发射极作为输出。晶体管的结构参见附图2。采用这种结构，使得第一N型横向绝缘栅双极型晶体管的漏极电流和第一N型横向双扩散金属氧化层场效应晶体管的漏极电流汇聚形成第一PNP型高压双极型晶体管的基极电流，第二N型横向绝缘栅双极型晶体管的漏极电流和第二N型横向双扩散金属氧化层场效应晶体管的漏极电流汇聚形成第二PNP型高压双极型晶体管的基极电流，经PNP型高压双极型晶体管的放大作用，从PNP型高压双极型晶体管发射极输出的电流将对基极电流进行放大，从而提高整个器件的电流密度。晶体管的等效电路图参见附图3，图4显示了本发明的N型绝缘体上硅横向绝缘栅双极型晶体管与相同面积的一般N型绝缘栅双极型晶体管的电流密度的比较，从图中可以看出，本发明的N型绝缘体上硅横向绝缘栅双极型晶体管的电流密度相比一般N型绝缘栅双极型晶体管，电流密度有25%以上幅度的提高。
（2）、本发明器件在提高电流密度的同时，与传统器件相比，并不增加器件原来的版图面积。
（3）、本发明器件在提高电流密度的同时，并不影响器件的耐压水平，器件的基本性能要求仍能满足要求。图5显示了本发明的N型绝缘体上硅横向绝缘栅双极型晶体管与相同面积的一般的N型绝缘栅双极型晶体管的关态击穿电压比较图，图中可见本发明的N型绝缘体上硅横向绝缘栅双极型晶体管的关态击穿电压可以保持与相同面积的一般N型绝缘栅双极型晶体管一致。
（4）、本发明器件采用SOI工艺，制作并不需要额外工艺步骤，与现有的CMOS工艺完全兼容。
 附图说明
图1所示为传统的N型绝缘体上硅横向绝缘栅双极型晶体管剖面结构。
图2所示为本发明的N型绝缘体上硅横向绝缘栅双极型晶体管剖面结构。
图3是本发明的N型绝缘体上硅横向绝缘栅双极型晶体管的等效电路图。
图4是本发明的N型绝缘体上硅横向绝缘栅双极型晶体管与相同面积的传统的绝缘体上硅N型绝缘栅双极型晶体管的漏极电流密度比较图。
图5是本发明的N型绝缘体上硅横向绝缘栅双极型晶体管关态反向击穿电压和传统的绝缘体上硅N型绝缘栅双极型晶体管的关态反向击穿电压比较图。
 本发明的实施方式
下面结合附图2，对本发明做详细说明，一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管，包括：P型衬底1，在P型衬底1上设有埋氧层2，在埋氧层2上设有N型外延层3，在N型外延层3内设有N型中心缓冲阱区22，其特征在于，在N型中心缓冲阱区22内顺序设有第一N型基区19、P型发射区20及第二N型基区19’，在第一N型基区19上连接有第一基极金属18，在P型发射区20上连接有发射极金属21，在第二N型基区19’上连接有第二基极金属18’，在N型中心缓冲阱区22的两外侧分别设有第一P型体区16及第二P型体区16’且第一P型体区16和第二P型体区16’对称于N型中心缓冲阱区22，在第一P型体区16内顺序设有第一N型源区13、第一P型体接触区14及第二N型源区15，在第二P型体区16’内顺序设有第三N型源区13’、第二P型体接触区14’及第四N型源区15’，在第一N型源区13、第一P型体接触区14、第二N型源区15、第三N型源区13’、第二P型体接触区14’及第四N型源区15’上连接有源极金属12，在第一P型体区16外侧设有第一N型缓冲阱区4，在第一N型缓冲阱区4内设有第一P型漏区5，在第一P型漏区5上连接有第一漏极金属6且第一漏极金属6与所述的第一基极金属18连接，在第二P型体区16’外侧设有第二N型缓冲阱区4’，在第二N型缓冲阱区4’设有第二P型漏区5’，在第二P型漏区5’上连接有第二漏极金属6’且第二漏极金属6’与所述的第二基极金属18’连接，在N型外延层3的表面设有第一栅氧化层24、第一场氧化层26、第二栅氧化层24’、第二场氧化层26’、第三栅氧化层11、第三场氧化层8、第四栅氧化层11’及第四场氧化层8’，第一栅氧化层24的一端与第一场氧化层26的一端相抵且位于N型中心缓冲阱区22与第一P型体区16之间，第一栅氧化层24的另一端向第二N型源区15延伸并止于第二N型源区15的外边界，第一场氧化层26的另一端延伸并进入N型中心缓冲阱区22，第二栅氧化层24’的一端与第二场氧化层26’的一端相抵且位于N型中心缓冲阱区22与第二P型体区16’之间，第二栅氧化层24’的另一端向第三N型源区13’延伸并止于第三N型源区13’的外边界，第二场氧化层26’的另一端延伸并进入N型中心缓冲阱区22，第三栅氧化层11的一端与第三场氧化层8的一端相抵且位于第一P型体区16与第一N型缓冲阱区4之间，第三栅氧化层11的另一端向第一N型源区13延伸并止于第一N型源区13的外边界，第三场氧化层8的另一端向第一P型漏区5延伸并止于第一P型漏区5的外边界，第四栅氧化层11’的一端与第四场氧化层8’的一端相抵且位于第二P型体区16’与第二N型缓冲阱区4’之间，第四栅氧化层11’的另一端向第四N型源区15’延伸并止于第四N型源区15’的外边界，第四场氧化层8’的另一端向第二P型漏区5’延伸并止于第二P型漏区5’的外边界，在第一栅氧化层24上设有第一多晶硅栅25且第一多晶硅栅25延伸至第一场氧化层26的上表面，在第二栅氧化层24’上设有第二多晶硅栅25’且第二多晶硅栅25’延伸至第二场氧化层26’的上表面，在第三栅氧化层11上设有第三多晶硅栅10且第三多晶硅栅10延伸至第三场氧化层8的上表面，在第四栅氧化层11’上设有第四多晶硅栅10’且第四多晶硅栅10’延伸至第四场氧化层8’的上表面，在第一多晶硅栅25、第二多晶硅栅25’、第三多晶硅栅10及第四多晶硅栅10’上连接有栅极金属17，在第三场氧化层8、第三多晶硅栅10、第一N型源区13、第一P型体接触区14、第二N型源区15、及第一P型漏区5、第一多晶硅栅25、第一场氧化层26、P型发射区20、第一N型基区19、第二N型基区19’、第二场氧化层26’、第二多晶硅栅25’、第三N型源区13’、第二P型体接触区14’、第四N型源区15’、第四多晶硅栅10’、第四场氧化层8’及第二P型漏区5’的表面设有钝化层7。
所述的N型绝缘体上硅横向绝缘栅双极型晶体管的P型发射区20与第一N型基区19、第二N型基区19’的间距为1微米~2微米，第一N型基区19与N型中心缓冲阱区22的左边沿的间距为1微米~2微米，第二N型基区19’与N型中心缓冲阱区22的右边沿的间距为1微米~2微米。
本发明采用如下方法来制备：
首先在P型衬底上进行常规的SOI层制作，在SOI层上制作N型外延层3，然后是晶体管的制作，包括在N型外延层3上通过注入高能量磷离子，高温退火后形成第一N型缓冲阱区4、第二N型缓冲阱区4’及N型中心缓冲阱区22，通过高能量硼离子注入，高温退火形成第一P型体区16及第二P型体区16’，高温下生长第一场氧化层26、第二场氧化层26’、第三场氧化层8及第四场氧化层8’，接下来是第三栅氧化层11、第一栅氧化层24、第二栅氧化层24’及第四栅氧化层11’的生长，之后淀积第三多晶硅栅10、第一多晶硅栅25、第二多晶硅栅25’及第四多晶硅栅10’，刻蚀出多晶硅栅，通过高剂量的硼离子和磷离子注入，制作重掺杂的第一P型漏区5、第一N型源区13、第一P型体接触区14、第二N型源区15、第一N型基区19、P型发射区20、第二N型基区19’、第三N型源区13’、第二P型体接触区14’、第四N型源区15’及第二P型漏区5’，淀积二氧化硅，刻蚀电极接触区后淀积金属，再刻蚀金属并引出电极，最后进行钝化处理。

Claims (3)

  1. 一种大电流N型绝缘体上硅横向绝缘栅双极型晶体管，包括：P型硅衬底（1），在P型硅衬底（1）上设有埋氧层（2），在埋氧层（2）上设有N型外延层（3），在N型外延层（3）内设有N型中心缓冲阱区（22），在N型中心缓冲阱区（22）内设有P型发射区（20），在P型发射区（20）上连接有发射极金属（21），其特征在于，在N型中心缓冲阱区（22）内设有第一N型基区（19）及第二N型基区（19’），所述第一N型基区（19）与第二N型基区（19’）分别位于P型发射区（20）的两外侧且对称于P型发射区（20），在第一N型基区（19）上连接有第一基极金属（18），在第二N型基区（19’）上连接有第二基极金属（18’），在N型中心缓冲阱区（22）的两外侧分别设有第一P型体区（16）及第二P型体区（16’）且第一P型体区（16）和第二P型体区（16’）对称于N型中心缓冲阱区（22），在第一P型体区（16）内顺序设有第一N型源区（13）、第一P型体接触区（14）及第二N型源区（15），在第二P型体区（16’）内顺序设有第三N型源区（13’）、第二P型体接触区（14’）及第四N型源区（15’），在第一N型源区（13）、第一P型体接触区（14）、第二N型源区（15）、第三N型源区（13’）、第二P型体接触区（14’）及第四N型源区（15’）上连接有源极金属（12），在第一P型体区（16）外侧设有第一N型缓冲阱区（4），在第一N型缓冲阱区（4）内设有第一P型漏区（5），在第一P型漏区（5）上连接有第一漏极金属（6）且第一漏极金属（6）与所述的第一基极金属（18）连接，在第二P型体区（16’）外侧设有第二N型缓冲阱区（4’），在第二N型缓冲阱区（4’）内设有第二P型漏区（5’），在第二P型漏区（5’）上连接有第二漏极金属（6’）且第二漏极金属（6’）与所述的第二基极金属（18’）连接，并且，第一N型缓冲阱区（4）和第二N型缓冲阱区（4’）对称于N型中心缓冲阱区（22），在N型外延层（3）的表面设有第一栅氧化层（24）、第一场氧化层（26）、第二栅氧化层（24’）、第二场氧化层（26’）、第三栅氧化层（11）、第三场氧化层（8）、第四栅氧化层（11’）及第四场氧化层（8’），第一栅氧化层（24）的一端与第一场氧化层（26）的一端相抵且位于N型中心缓冲阱区（22）与第一P型体区（16）之间，第一栅氧化层（24）的另一端向第二N型源区（15）延伸并止于第二N型源区（15）的外边界，第一场氧化层（26）的另一端延伸并进入N型中心缓冲阱区（22），第二栅氧化层（24’）的一端与第二场氧化层（26’）的一端相抵且位于N型中心缓冲阱区（22）与第二P型体区（16’）之间，第二栅氧化层（24’）的另一端向第三N型源区（13’）延伸并止于第三N型源区（13’）的外边界，第二场氧化层（26’）的另一端延伸并进入N型中心缓冲阱区（22），第三栅氧化层（11）的一端与第三场氧化层（8）的一端相抵且位于第一P型体区（16）与第一N型缓冲阱区（4）之间，第三栅氧化层（11）的另一端向第一N型源区（13）延伸并止于第一N型源区（13）的外边界，第三场氧化层（8）的另一端向第一P型漏区（5）延伸并止于第一P型漏区（5）的外边界，第四栅氧化层（11’）的一端与第四场氧化层（8’）的一端相抵且位于第二P型体区（16’）与第二N型缓冲阱区（4’）之间，第四栅氧化层（11’）的另一端向第四N型源区（15’）延伸并止于第四N型源区（15’）的外边界，第四场氧化层（8’）的另一端向第二P型漏区（5’）延伸并止于第二P型漏区（5’）的外边界，在第一栅氧化层（24）上设有第一多晶硅栅（25）且第一多晶硅栅（25）延伸至第一场氧化层（26）的上表面，在第二栅氧化层（24’）上设有第二多晶硅栅（25’）且第二多晶硅栅（25’）延伸至第二场氧化层（26’）的上表面，在第三栅氧化层（11）上设有第三多晶硅栅（10）且第三多晶硅栅（10）延伸至第三场氧化层（8）的上表面，在第四栅氧化层（11’）上设有第四多晶硅栅（10’）且第四多晶硅栅（10’）延伸至第四场氧化层（8’）的上表面，在第一多晶硅栅（25）、第二多晶硅栅（25’）、第三多晶硅栅（10）及第四多晶硅栅（10’）上连接有栅极金属（17），在第三场氧化层（8）、第三多晶硅栅（10）、第一N型源区（13）、第一P型体接触区（14）第二N型源区（15）、第一P型漏区（5）、第一多晶硅栅（25）、第一场氧化层（26）、P型发射区（20）、第一N型基区（19）、第二N型基区（19’）、第二场氧化层（26’）、第二多晶硅栅（25’）、第三N型源区（13’）、第二P型体接触区（14’）、第四N型源区（15’）、第四多晶硅栅（10’）、第四场氧化层（8’）及第二P型漏区（5’）的表面设有钝化层（7）。
  2. 根据权利要求1所述的大电流N型绝缘体上硅横向绝缘栅双极型晶体管，其特征在于，晶体管为对称型结构，内设有第一N型横向绝缘栅双极型晶体管、第一N型横向双扩散金属氧化层场效应晶体管、第一PNP型高压双极型晶体管、第二PNP型高压双极型晶体管、第二N型横向双扩散金属氧化层场效应晶体管及第二N型横向绝缘栅双极型晶体管，所述第一N型横向绝缘栅双极型晶体管与第二N型横向绝缘栅双极型晶体管分别位于N型中心缓冲阱区（22）的两外侧且对称于N型中心缓冲阱区（22），所述第一N型横向绝缘栅双极型晶体管的漏区采用所述第一P型漏区（5），源区采用所述第一N型源区（13），所述第二N型横向绝缘栅双极型晶体管的漏区采用所述第二P型漏区（5’），源区采用所述第四N型源区（15’），所述第一N型横向双扩散金属氧化层场效应晶体管与第二N型横向双扩散金属氧化层场效应晶体管分别位于P型发射区（20）两外侧且对称于P型发射区（20），所述第一N型横向双扩散金属氧化层场效应晶体管的漏区采用所述第一N型基区（19），源区采用所述第二N型源区（15），所述第二N型横向双扩散金属氧化层场效应晶体管的漏区采用所述第二N型基区（19’），源区采用所述第三N型源区（13’），所述第一PNP型高压双极型晶体管发射区采用所述P型发射区（20），基区采用所述第一N型基区（19），集电区采用所述第一P型体接触区（14），所述第一P型体接触区（14）同时为所述的第一N型横向绝缘栅双极型晶体管及第一N型横向双扩散金属氧化层场效应晶体管的体接触区，所述第二PNP型高压双极型晶体管发射区采用所述P型发射区（20），基区采用所述第二N型基区（19’），集电区采用所述第二P型体接触区（14’），所述第二P型体接触区（14’）同时为所述的第二N型横向双扩散金属氧化层场效应晶体管及第二N型横向绝缘栅双极型晶体管的体接触区，所述第一N型横向绝缘栅双极型晶体管、第一N型横向双扩散金属氧化层场效应晶体管、第二N型横向双扩散金属氧化层场效应晶体管及第二N型横向绝缘栅双极型晶体管的栅极通过栅极金属（17）引出，所述第一N型横向绝缘栅双极型晶体管第一漏极金属（6）通过金属层与所述第一PNP型高压双极型晶体管第一基极金属（18）连接，所述第二N型横向绝缘栅双极型晶体管第二漏极金属（6’）通过金属层与所述第二PNP型高压双极型晶体管第二基极金属（18’）连接，并通过所述的发射极金属（21）输出。
  3. 根据权利要求1、2所述的大电流N型绝缘体上硅横向绝缘栅双极型晶体管，其特征在于，P型发射区（20）与第一N型基区（19）、第二N型基区（19’）的间距为1微米~2微米，第一N型基区（19）与N型中心缓冲阱区（22）的左边沿的间距为1微米~2微米，第二N型基区（19’）与N型中心缓冲阱区（22）的右边沿的间距为1微米~2微米。
PCT/CN2012/083427 2012-09-14 2012-10-24 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管 Ceased WO2014040334A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/349,632 US9159818B2 (en) 2012-09-14 2012-10-24 High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210343012.5 2012-09-14
CN201210343012.5A CN102956636B (zh) 2012-09-14 2012-09-14 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管

Publications (1)

Publication Number Publication Date
WO2014040334A1 true WO2014040334A1 (zh) 2014-03-20

Family

ID=47765224

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/083427 Ceased WO2014040334A1 (zh) 2012-09-14 2012-10-24 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管

Country Status (3)

Country Link
US (1) US9159818B2 (zh)
CN (1) CN102956636B (zh)
WO (1) WO2014040334A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510685B2 (en) * 2017-09-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention columns for bipolar junction transistors
CN114614802B (zh) * 2022-03-03 2023-06-20 电子科技大学 一种具有快速开启功能的GaN驱动器
CN116190434A (zh) * 2022-12-28 2023-05-30 电子科技大学 一种抗总剂量辐射高压三极管结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101431096A (zh) * 2008-12-11 2009-05-13 电子科技大学 一种soi ligbt器件
CN102097441A (zh) * 2010-12-17 2011-06-15 电子科技大学 用于等离子显示屏驱动芯片的soi器件
CN102194818A (zh) * 2011-04-26 2011-09-21 电子科技大学 一种基于p型外延层的bcd集成器件及其制造方法
CN202076269U (zh) * 2010-08-27 2011-12-14 东南大学 一种绝缘体上硅可集成大电流n型组合半导体器件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386327A (en) * 1979-12-20 1983-05-31 Tokyo Shibaura Denki Kabushiki Kaisha Integrated circuit Clapp oscillator using transistor capacitances
US5731603A (en) * 1995-08-24 1998-03-24 Kabushiki Kaisha Toshiba Lateral IGBT
US7209384B1 (en) * 2005-12-08 2007-04-24 Juhan Kim Planar capacitor memory cell and its applications
JP5443702B2 (ja) * 2008-04-08 2014-03-19 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
US8278683B2 (en) * 2008-08-06 2012-10-02 Texas Instruments Incorporated Lateral insulated gate bipolar transistor
CN101969050B (zh) * 2010-08-27 2013-04-24 东南大学 一种绝缘体上硅可集成大电流n型组合半导体器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101431096A (zh) * 2008-12-11 2009-05-13 电子科技大学 一种soi ligbt器件
CN202076269U (zh) * 2010-08-27 2011-12-14 东南大学 一种绝缘体上硅可集成大电流n型组合半导体器件
CN102097441A (zh) * 2010-12-17 2011-06-15 电子科技大学 用于等离子显示屏驱动芯片的soi器件
CN102194818A (zh) * 2011-04-26 2011-09-21 电子科技大学 一种基于p型外延层的bcd集成器件及其制造方法

Also Published As

Publication number Publication date
CN102956636B (zh) 2015-02-04
CN102956636A (zh) 2013-03-06
US20140306266A1 (en) 2014-10-16
US9159818B2 (en) 2015-10-13

Similar Documents

Publication Publication Date Title
US8754442B2 (en) Silicon on insulator integrated high-current N type combined semiconductor device
WO2014071673A1 (zh) 一种大电流密度的横向超薄绝缘栅双极型晶体管
CN108447913B (zh) 一种集成肖特基二极管的ldmos器件
CN102194818B (zh) 一种基于p型外延层的bcd集成器件及其制造方法
CN114695564B (zh) 一种高压碳化硅功率场效应晶体管及高低压集成电路
CN101431097B (zh) 一种薄层soi ligbt器件
CN101777581B (zh) P型超结横向双扩散半导体金属氧化物晶体管
CN101976670A (zh) 一种绝缘体上硅可集成大电流p型组合半导体器件
WO2014040334A1 (zh) 一种大电流n型绝缘体上硅横向绝缘栅双极型晶体管
CN101771081B (zh) N型超结横向双扩散半导体金属氧化物晶体管
CN109698196A (zh) 功率半导体器件
CN119451182B (zh) 一种具有低电阻与密勒电容的非对称沟槽SiC MOSFET器件
CN101819993B (zh) 降低热载流子效应的p型横向绝缘栅双极型器件
CN103872111A (zh) 一种igbt及其制作方法
CN202434525U (zh) 一种n型绝缘体上硅横向绝缘栅双极型器件
CN201918387U (zh) 一种绝缘体上硅可集成大电流p型组合半导体器件
CN102956696B (zh) 一种大电流p型绝缘体上硅横向绝缘栅双极型晶体管
CN102214679B (zh) 形成于绝缘体上硅中的自隔离式高压半桥结构
CN201570500U (zh) P型超结横向双扩散半导体金属氧化物晶体管
CN101969062B (zh) 一种提高电流密度的绝缘体上硅n型半导体组合器件
CN102760761A (zh) 一种抗闩锁n型绝缘体上硅横向绝缘栅双极型晶体管
CN201667336U (zh) 降低热载流子效应的n型横向绝缘栅双极型器件
CN102437181A (zh) 一种n型绝缘体上硅横向绝缘栅双极型器件
CN106158940A (zh) 一种具有部分埋氧结构的igbt器件及其制造方法
CN101969064B (zh) 一种提高电流密度的绝缘体上硅p型半导体组合器件

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14349632

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12884496

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12884496

Country of ref document: EP

Kind code of ref document: A1