WO2014030659A1 - Insulating substrate、multilayer ceramic insulating substrate, joined structure of power semiconductor device and insulating substrate, and power semiconductor module - Google Patents

Insulating substrate、multilayer ceramic insulating substrate, joined structure of power semiconductor device and insulating substrate, and power semiconductor module Download PDF

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WO2014030659A1
WO2014030659A1 PCT/JP2013/072234 JP2013072234W WO2014030659A1 WO 2014030659 A1 WO2014030659 A1 WO 2014030659A1 JP 2013072234 W JP2013072234 W JP 2013072234W WO 2014030659 A1 WO2014030659 A1 WO 2014030659A1
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insulating substrate
power semiconductor
semiconductor device
metal plate
solder
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PCT/JP2013/072234
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French (fr)
Japanese (ja)
Inventor
智 谷本
浩二 早川
秀和 谷澤
佐藤　伸二
康平 松井
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日産自動車株式会社
京セラ株式会社
サンケン電気株式会社
富士電機株式会社
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Priority to JP2014531645A priority Critical patent/JP6154383B2/en
Publication of WO2014030659A1 publication Critical patent/WO2014030659A1/en

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    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important

Definitions

  • the present invention relates to an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that have high resistance to thermal cycle stress with a large temperature difference.
  • the passive components and coolers that make up the system can be miniaturized, and it is expected that a compact, lightweight, and low-priced power electronics system can be realized.
  • a high semiconductor junction temperature Tj eg, Tj> 200 ° C.
  • Patent Document 1 a power semiconductor module disclosed in Japanese Patent Laid-Open No. 2008-270353 (Patent Document 1) has been proposed.
  • the power semiconductor module a combination of a semiconductor element, an insulating portion, and a heat sink is used.
  • Tj ⁇ 40 ° C. to 250 ° C.
  • ⁇ Tj 290 ° C.
  • the present invention has been made in order to solve such a conventional problem, and the object of the present invention is to be used in an environment of a thermal cycle where the semiconductor junction temperature (Tj) is high and the temperature range ( ⁇ Tj) is wide. It is another object of the present invention to provide an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that operate with high reliability.
  • the insulating substrate according to one embodiment of the present invention includes a ceramic substrate and a low heat stretchable metal plate attached to at least one surface of the ceramic substrate.
  • the low thermal stretchable metal plate includes a pair of Cu plates having substantially the same thickness and a low thermal expansion metal plate provided between the pair of Cu plates and having a thermal expansion coefficient lower than that of the Cu plate.
  • FIG. 1 is a cross-sectional view showing a main part of an insulating substrate according to first to third embodiments of the present invention.
  • FIG. 2 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fifth embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a main part of a joined structure of a power semiconductor device and an insulating substrate according to the sixth embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a main part of an insulating substrate according to first to third embodiments of the present invention.
  • FIG. 2 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a main part of a multilayer ceramic
  • FIG. 5 is a characteristic view which shows the thermal test result of the joining structure body of the power semiconductor device which concerns on 6th Embodiment of this invention, and an insulated substrate, and the joining structure body concerning a comparative example.
  • 6A and 6B show a power semiconductor module according to a seventh embodiment of the present invention, in which FIG. 6A is a plan view and FIG. FIG. 7 is a cross-sectional view showing a main part of a power semiconductor module according to the eighth embodiment of the present invention.
  • the insulating substrate according to the first embodiment solves the problem of “Cu plate peeling”. This problem may occur in a conventional power semiconductor module in which Cu plates are attached to both sides of a SiN insulating substrate.
  • FIG. 1 is a sectional view showing an insulating substrate according to the first embodiment of the present invention.
  • the insulating substrate 100 according to the first embodiment is provided with a ceramic substrate 21 made of SiN (silicon nitride) at substantially the center in the thickness direction.
  • the thickness of the ceramic substrate 21 is desirably 0.1 mm or more and 2 mm or less, and preferably 0.31 mm.
  • low thermal stretchable metal plates 12-1 and 12-2 are joined to both surfaces (lower surface and upper surface) of the ceramic substrate 21, respectively.
  • the low heat stretchable metal plate is made of, for example, a CIC clad metal plate.
  • the low thermal stretchable metal plates 12-1 and 12-2 are referred to as CIC clad metal plates 12-1 and 12-2.
  • Each of the CIC clad metal plates 12-1 and 12-2 has the same configuration.
  • the thickness of each CIC clad metal plate 12-1 (12-2) is desirably 0.1 mm or more and 2 mm or less, and preferably 0.37 mm.
  • the CIC clad metal plates 12-1 and 12-2 are a pair of oxygen-free copper plates (Cu plates 14, 14) on both sides of an Inver (registered trademark) alloy plate 13 (containing main components Fe and 36.5 vol% Ni). 15) is a three-layer metal plate joined using a metallurgical method. Further, since the linear expansion coefficient of the Invar alloy plate 13 is as small as about 1.2 ppm / ° C., the Cu plates 14 and 15 having approximately the same thickness (an error of about ⁇ 1% to + 1%) on both sides of the Invar alloy plate 13. The CIC clad metal plates 12-1 and 12-2 sandwiched between the layers have lower stretchability (or lower synthetic thermal expansion) than the Cu plate alone.
  • the thicknesses of the Cu plate 14 and the Cu plate 15 provided on the CIC clad metal plates 12-1 and 12-2 are preferably at least 5 ⁇ m or more and 10 ⁇ m or more in order to maintain good heat conduction and electrical conduction. It is more desirable.
  • each of the Cu plates 14 and 15 with respect to the Invar alloy plate 13 from the viewpoint of reducing the thermal stress applied to the interface between the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2.
  • the thickness ratio (C / I ratio) is preferably made as small as possible to suppress the difference from the linear expansion coefficient of SiN (ceramic substrate 21).
  • the thickness of each of the pair of Cu plates 14 and 15 is desirably 1/2 or less, more desirably 1/5 or less of the thickness of the Invar alloy plate 13.
  • the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 are joined by an active metal joining method using a brazing agent (not shown) such as Ti—Cu—Ag or Ti—Cu—Ag—Ni. Can be done with.
  • a brazing agent such as Ti—Cu—Ag or Ti—Cu—Ag—Ni.
  • the Ni plating film 16 for mounting is formed on the outermost Cu surface of the CIC clad metal plates 12-1 and 12-2. Cover.
  • the Ni plating film 16 is not an essential component in the insulating substrate 100 according to the first embodiment.
  • the inventors manufactured an insulating substrate (sample of the first embodiment) and conducted a thermal cycle test.
  • the inventors also produced an insulating substrate (a sample of a comparative example) according to a comparative example.
  • the sample of the comparative example is an insulating substrate using an oxygen-free Cu plate having a length of 17 mm, a width of 8.5 mm, a thickness of 0.3 mm, and a surface plated with Ni instead of the CIC clad metal plates 12-1 and 12-2. It is.
  • a similar thermal cycle test was performed on the sample of the comparative example.
  • the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12 formed by sandwiching the Invar alloy plate 13 between the two Cu plates 14 and 15 are used.
  • -2 is attached to both surfaces of a ceramic substrate 21 such as SiN to constitute the insulating substrate 100.
  • the thickness of the ceramic substrate 21 is set to 0.1 mm or more and 2 mm or less, durability against repeated temperature changes can be further improved.
  • the CIC clad metal plates 12-1 and 12-2 are three-layer metal plates in which a pair of Cu plates 14 and 15 are bonded to both sides of an Invar alloy plate (low thermal expansion metal plate) 13 using a metallurgical method. is there. Thereby, it is possible to prevent the Cu plates 14 and 15 from being separated from the Invar alloy plate 13.
  • the thicknesses of the Cu plate 14 and the Cu plate 15 included in the CIC clad metal plates 12-1 and 12-2 are 5 ⁇ m or more, good heat conduction and electrical conduction can be maintained.
  • the thickness ratio (C / I ratio) of each of the Cu plates 14 and 15 to the Invar alloy plate 13 is set to 1/2 or less.
  • the low thermal stretchable metal plates 12-1 and 12-2 are attached to both surfaces of the ceramic substrate 21.
  • the present invention is not limited to any one of the ceramic substrates 21. It is also possible to adopt a configuration in which only one surface is attached.
  • the ceramic substrate 21 in the second embodiment is made of a ceramic material selected from the group consisting of alumina (Al 2 O 3 ), aluminum nitride (AlN), and beryllia (BeO).
  • the thickness of the ceramic substrate 21 is preferably 0.1 mm to 2 mm. Since the insulating substrate according to the second embodiment is the same as the configuration shown in FIG. 1 except that the ceramic substrate is a ceramic material other than SiN, a detailed description of the configuration is omitted.
  • Beryllia (BeO) has the advantage of having the highest thermal conductivity among the above three ceramic materials, but has the disadvantage of being toxic.
  • Alumina Al 2 O 3
  • the mechanical strength is lower than SiN and higher than AlN.
  • Aluminum nitride (AlN) has a very high thermal conductivity as compared with alumina and SiN, and is suitable as a material used for the insulating substrate of the present embodiment from the viewpoint of heat removal design of a semiconductor chip that generates heat.
  • mechanical strength is weak compared with SiN and alumina. For this reason, there is a drawback that the Cu plate is more easily peeled off in a shorter time than SiN against a thermal cycle stress where the maximum semiconductor junction temperature Tjmax is 200 ° C. or higher and the temperature range ( ⁇ Tj) is 250 ° C. or higher.
  • AlN aluminum nitride
  • the inventors configured an insulating substrate 100 using aluminum nitride (AlN) as the ceramic substrate 21 shown in FIG. 1, and performed the following thermal cycle test using the insulating substrate 100.
  • the insulating substrate 100 is configured by attaching the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12-2 to both surfaces of the AlN ceramic substrate 21. is doing. Thereby, compared with the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the AlN ceramic substrate due to repeated temperature changes.
  • a direct Cu joining method (DCB method) can also be used.
  • the low heat stretchable metal plates 12-1 and 12-2 are CIC clad metal plates.
  • the low heat stretchable metal plates 12-1 and 12-2 are not limited to CIC clad metal plates. If it is a metal plate having low thermal stretchability, a CMC clad metal plate in which a metal plate other than the Invar alloy plate 13 is sandwiched between Cu plates 14 and 15 can be used as the low thermal stretch metal plates 12-1 and 12-2. .
  • the material of the metal plate other than the Invar alloy plate is “M”.
  • the total thickness of the CMC clad metal plate is desirably 0.1 mm or more and 2 mm or less, and the thickness of the Cu plates 14 and 15 is desirably at least 5 ⁇ m or more, preferably 10 ⁇ m or more.
  • the ratio (C / M ratio) of each of the Cu plates 14 and 15 to the metal plate other than the Invar alloy plate is desirably 1/2 or less, preferably 1/5 or less, like the CIC clad metal plate. desirable.
  • An example of the material (M) of the metal plate constituting the CMC clad metal plate is molybdenum (Mo).
  • Mo molybdenum
  • super invar containing main components Fe, Ni 32 vol% and Co 5 vol%) and stainless steel invar (containing main components Fe and Co 54 vol%) can be used as the material “M” of the metal plate.
  • an insulating substrate is formed by attaching a CMC clad metal plate as a low thermal stretchable conductor plate to both surfaces of a ceramic substrate such as SiN. This makes it possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the ceramic substrate due to repeated temperature changes as compared with the insulating substrate according to the comparative example.
  • any one of silicon nitride (SiN), alumina (Al 2 O 3 ), aluminum nitride (AlN), and beryllia (BeO) can be used as the ceramic substrate 21. Therefore, the mechanical strength can be increased and the strength of the entire insulating substrate can be improved.
  • Invar containing main component Fe, Ni 36.5 vol%), molybdenum (Mo), Super Invar (containing main components Fe, Ni 32 vol% and Co 5 vol%), stainless steel invar (containing main components Fe, Co 54 vol%) Use one of these.
  • thermal expansion caused by temperature change can be suppressed, stress applied to the low heat stretchable metal plate can be reduced, and peeling can be prevented from occurring.
  • FIG. 2 is a cross-sectional view showing a configuration of a multilayer (for example, two layers) ceramic insulating substrate 200 according to the fourth embodiment.
  • the multilayer ceramic insulating substrate 200 includes two insulating substrates that are stacked one above the other, that is, a first insulating substrate member 31 a and a second insulating substrate member 31 b.
  • the basic configuration of each of the insulating substrate members 31a and 31b is substantially the same as that of the insulating substrate 100 shown in FIG.
  • the invar alloy plate 13 and the Cu plates 14 and 15 are the same as those in the first to third embodiments described above, and the description of the configuration is omitted.
  • the first insulating substrate member 31a includes a ceramic substrate 21a, a low heat stretchable metal plate 12a-1 attached to the upper surface of the ceramic substrate 21a, and a low heat stretchable metal plate 12a- attached to the lower surface of the ceramic substrate 21a.
  • the second insulating substrate member 31b includes a ceramic substrate 21b, a low heat stretchable metal plate 12b-1 attached to the upper surface of the ceramic substrate 21b, and a low heat stretchable metal attached to the lower surface of the ceramic substrate 21b. Plate 12b-2.
  • the wax material Ti—Cu—Ag or Ti—Cu—Ag—Ni (not shown) is composed of the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretchable metal of the second insulating substrate member 31b.
  • the plate 12b-1 is joined.
  • the advantage of applying the multilayer ceramic insulating substrate 200 is that an intermediate layer conductive plate (low thermal stretchable metal plates 12a-2 and 12b-1 in the example shown in FIG. 2) can be used as wiring. Thereby, the floating inductance of the multilayer ceramic insulating substrate 200 can be reduced, and the mounting area of the multilayer ceramic insulating substrate 200 can be reduced.
  • a via window 17 is opened at a predetermined position of the ceramic substrate 21a, and a via window metal plate 18 (for example, Cu) embedded in the via window 17 is used to form an upper portion.
  • the low heat stretchable metal plate 12a-1 may be electrically connected to the lower low heat stretchable metal plate 12a-2.
  • the joining of the low heat stretchable metal plate 12a-1 and the via window metal plate 18 and the joining of the via window metal plate 18 and the low heat stretchable metal plate 12a-2 are performed using an active metal brazing material Ti—Cu— (not shown). Bonding can be performed using Ag, Ti-Cu-Ag-Ni, or the like.
  • the first insulating substrate member 31a and the second insulating substrate member 31b are separately manufactured by the same method as the insulating substrate 100 shown in the first to third embodiments. At this time, the Ni plating 16 shown in FIG. 2 is not provided.
  • the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretch of the second insulating substrate member 31b are used.
  • the conductive metal plate 12b-1 is bonded together.
  • Ni plating 16 is coated on the surfaces (upper surface and lower surface) of the low heat stretchable metal plates 12a-1 and 12b-2. As a result, the multilayer ceramic insulating substrate 200 shown in FIG. 2 is completed. In order to improve the wettability of the high-temperature solder, an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.
  • each of the first insulating substrate member 31a and the second insulating substrate member 31b is the insulating substrate 100 of the first embodiment in which a SiN ceramic substrate and a CIC clad metal plate are combined.
  • Tj ⁇ 40 ° C. to 300 ° C.
  • the first insulating substrate member 31a, and the CIC clad metal plate as the low thermal stretchable metal plate are attached to both surfaces of the ceramic substrates 21a and 21b such as SiN.
  • the second insulating substrate member 31b is manufactured.
  • the multilayer ceramic insulating substrate 200 is configured by laminating the first insulating substrate member 31a and the second insulating substrate member 31b.
  • the multilayer (two-layer) ceramic insulating substrate 200 in which the two insulating substrate members 31a and 31b are stacked is illustrated.
  • the number of layers is not limited to two, and three or more layers are also possible.
  • SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used.
  • the CIC clad metal plate is shown as an example of the low heat stretchable metal plates 12a-1 and 12b-2, the CMC clad metal plate exemplified in the third embodiment can also be used.
  • FIG. 3 is a cross-sectional view showing the configuration of the multilayer ceramic insulating substrate 300 according to the fifth embodiment, which is an improved configuration of the structure of the multilayer ceramic insulating substrate 200 shown in FIG.
  • the multilayer ceramic insulating substrate 300 includes a first ceramic substrate 21a and a second ceramic substrate 21b.
  • a low heat stretchable metal plate 12a-1 is attached to the upper surface of the first ceramic substrate 21a, and a low heat stretchable metal plate 12b-2 is attached to the lower surface of the second ceramic substrate 21b.
  • An intermediate metal plate 19 is provided between the first ceramic substrate 21a and the second ceramic substrate 21b.
  • the thickness of the intermediate metal plate 19 is not less than 0.1 mm and not more than 2 mm, preferably not less than 0.2 mm and not more than 1 mm.
  • the low heat stretchable metal plates 12a-1 and 12b-2 are the same as the CIC clad metal plate or CMC clad metal plate described in the first to third embodiments. A description of the configuration of the Invar alloy plate 13 and the Cu plates 14 and 15 in FIG. 3 is omitted. Here, a CMC clad metal plate will be described as an example.
  • a via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 is embedded in the via window 17.
  • the low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 are connected to each other through a via window metal plate 18.
  • the via window metal plate 18 and the low heat stretchable metal plate 12a-1 are joined by an active metal brazing material Ti—Cu—Ag, Ti—Cu—Ag—Ni (not shown) or the like.
  • an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.
  • the active metal brazing material is placed on the low heat stretchable metal plate 12b-2 placed on the susceptor of the firing furnace, and the ceramic substrate 21b is placed thereon. Further thereon, an active metal wax material, an intermediate metal plate 19, an active metal wax material, a ceramic substrate 21a, an active metal wax material, and a low heat stretchable metal plate 12a-1 are laminated in this order. However, when the ceramic substrate 21a is placed, the via window metal plate 18 is simultaneously installed in the via window 17.
  • the multilayer ceramic insulating substrate 300 shown in FIG. 3 is completed.
  • the inventors manufactured a sample of the multilayer ceramic insulating substrate 300 according to the fifth embodiment and conducted a thermal cycle test.
  • a sample of the multilayer ceramic insulating substrate 300 includes SiN ceramic substrates 21a and 21b and low thermal stretchable metal plates (CMC clad metal plates) 12a-1 and 12b-2.
  • a Cu plate (thickness: about 0.31 mm) is used as the via window metal plate 18 and the intermediate metal plate 19.
  • the intermediate metal plate (Cu) 19 that is not the low heat stretchable metal plate does not peel from the ceramic substrates 21a and 21b.
  • the reason is that the thermal stress generated at the interface between the ceramic and Cu due to the difference in thermal expansion is divided into the interface between the upper ceramic substrate 21a and the lower ceramic substrate 21b, and the thermal stress generated at each interface is This is because it has been halved.
  • a CMC clad metal plate as a low heat stretchable metal plate is attached to one surface of ceramic substrates 21a, 21b such as SiN, and further, between the ceramic substrates 21a, 21b.
  • An intermediate metal plate 19 is provided.
  • the multilayer ceramic insulating substrate 300 was configured.
  • the intermediate metal plate 19 is a Cu single plate, and the multilayer ceramic substrate
  • the insulating substrate 300 has a thin thickness and a good conductive Cu thickness. Therefore, the multilayer ceramic insulating substrate 300 according to the fifth embodiment is advantageous in that it can be made cheaper than the multilayer ceramic insulating substrate 200 and the heat conduction in the thickness direction can be improved.
  • a via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 such as Cu is embedded in the via window 17.
  • a via window metal plate 18 such as Cu is embedded in the via window 17.
  • the low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 can be electrically connected via the via window metal plate 18.
  • SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used.
  • bonded structure 400 a power semiconductor device / insulated substrate bonded structure 400 (hereinafter, abbreviated as “bonded structure 400”) according to a sixth embodiment.
  • bonded structure 400 An example in which a SiC (silicon carbide) power element is used as the power semiconductor device 41 described in the sixth to eighth embodiments will be described.
  • the power semiconductor device 41 includes other wide band gap semiconductor elements such as GaN (gallium nitride) elements, diamond elements, ZnO (zinc oxide) elements, and Si semiconductor elements (SOI elements and sensor elements) for high-temperature applications. Etc.
  • ceramic elements having mechanical and thermal properties similar to those of the power semiconductor device, specifically, passive elements and functional elements such as ceramic chip capacitors and ceramic thermistors can be applied.
  • the joint structure 400 according to the sixth embodiment includes an insulating substrate 101 and a power semiconductor device 41 joined by a heat-resistant solder layer 42 as shown in FIG. Since the insulating substrate 101 has the same structure as that of the insulating substrate 100 shown in FIG. 1, the same reference numerals are given and detailed description of the structure is omitted.
  • FIG. 4 shows an example in which the insulating substrate 101 includes the SiN ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 shown in the first embodiment.
  • the insulating substrate 101 may include the other ceramic substrate described in the second embodiment and the other low thermal stretchable CMC clad metal plate described in the third embodiment.
  • the power semiconductor device 41 is, for example, a transistor using SiC or a diode.
  • An ohmic contact 23 such as Ni silicide is provided on the back surface of the power semiconductor device 41.
  • a mounting electrode 22 made of a laminated film of Ti (titanium) / Ni (nickel) / Ag (silver) or the like is formed.
  • the heat-resistant solder layer 42 mechanically and electrically joins the low thermal stretchable metal plate 12-1 and the power semiconductor device 41.
  • the heat-resistant solder layer 42 has a solidus temperature that is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the power semiconductor device 41 and a liquidus temperature that is at least 30 higher than the instantaneous heat-resistant temperature 450 ° C. of the SiC power semiconductor device 41.
  • the heat-resistant solder layer 42 includes eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, Bi solder, etc. Consists of.
  • the heat-resistant solder layer 42 is not limited to this, and the solder material having a hypoeutectic composition or a hypereutectic composition can be used without departing from the eutectic composition.
  • the power semiconductor device 41 (chip) and the insulating substrate 101 are ultrasonically cleaned with an organic solvent such as acetone or isopropyl alcohol to remove contaminants adhering to the surfaces of these components.
  • an organic solvent such as acetone or isopropyl alcohol to remove contaminants adhering to the surfaces of these components.
  • the eutectic Au—Ge solder is not a paste but a plate, the eutectic Au—Ge solder is cleaned in the same manner.
  • the insulating substrate 101 is installed on the reflow stand of the reduced pressure reflow apparatus, and the eutectic Au—Ge solder is placed at a predetermined position of the low heat stretchable metal plate, that is, the CIC clad metal plate 12-1. If the eutectic Au—Ge solder is paste-like, the eutectic Au—Ge solder paste is dropped onto a predetermined position of the CIC clad metal plate 12-1 using a syringe or the like. Then, the power semiconductor device 41 is placed on the eutectic Au—Ge solder and is stationary.
  • a template-type carbon jig is used. It is desirable to use
  • the reflow process is executed. First, the door of the vacuum reflow device is closed and the sample chamber is evacuated. When the pressure in the sample chamber becomes 5 mbar or less, an inert gas is introduced. This operation is performed several times to replace the air in the sample chamber with an inert gas. As a result, the sample chamber is filled with the inert gas.
  • the reflow table or the entire sample chamber is heated to raise the temperature of the material to approximately 200 ° C., and this temperature is maintained for about 2 minutes.
  • an inert gas containing formic acid vapor may be introduced to promote removal of contaminating organic substances.
  • the introduction of inert gas is stopped, the exhaust is resumed, and the sample chamber is decompressed to 5 mbar or less.
  • the reflow table (or the entire sample chamber) is further heated to raise the temperature of the insulating substrate 101, the Au—Ge solder 42, and the power semiconductor device 41 to a reflow temperature of 410 ° C. and reflow.
  • the holding time is about 1 minute.
  • the reflow apparatus When the reflow is completed, an inert gas is introduced into the sample chamber and temperature reduction is started. When the temperature inside the chamber is lowered to a sufficiently low temperature, the finished product, that is, the joint structure 400 according to the present embodiment is taken out from the reflow apparatus.
  • the chip size of the power semiconductor device 41 was 2 mm in length, 2 mm in width, and 0.3 mm in thickness.
  • a sample of a joined structure (solder layer is Au—Ge) including an insulating substrate using oxygen-free Cu alone instead of a CIC clad metal plate was produced, and a thermal cycle test similar to the above was performed.
  • the bond strength (shear strength) is plotted as a function of cycle number. As described above, in the sample of the bonded structure according to the comparative example, it is understood that the shear strength rapidly deteriorates as the number of cycles increases. This was the problem of the comparative example. Note that the bonding strength in the comparative example indicates the bonding strength between the oxygen-free Cu simple substance and the power semiconductor device.
  • the deterioration rate of the shear strength is moderate even if the number of cycles is increased.
  • the number of cycles decreasing to the IEC60749-19 standard regarding the shear strength of the electronic component was predicted.
  • the standard of the cycle life required empirically for an electronic component used in a relatively harsh environment is 3000 cycles. Therefore, the joint structure 400 according to the present embodiment has a life that is about three times as long as this guideline.
  • the bonding strength in the present embodiment indicates the bonding strength between the Cu plate of the CIC clad metal plate and the power semiconductor device.
  • a power semiconductor device chip is bonded onto the low thermal stretchable metal plate 12-1 of the insulating substrate 101 shown in the first to fifth embodiments.
  • the bonded structure 400 is configured. As a result, rapid deterioration of the bonding strength between the power semiconductor device 41 and the insulating substrate 101 can be suppressed, and the cycle life can be greatly extended.
  • the insulating substrate 101 and the power semiconductor device 41 are joined using the heat-resistant solder layer 42. Thereby, even when a temperature change is repeated, the problem that the heat-resistant solder layer 42 deteriorates and peels can be solved.
  • one semiconductor material selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), diamond (C), and zinc oxide (ZnO) is used.
  • SiC silicon carbide
  • GaN gallium nitride
  • C diamond
  • ZnO zinc oxide
  • the bonding structure 400 according to the present embodiment the example in which the insulating substrate 101 shown in the first to third embodiments is applied has been described. However, the multilayer ceramic insulating substrate according to the fourth and fifth embodiments is employed. You may do it.
  • FIG. 6 shows a configuration of a power semiconductor module 500 according to the seventh embodiment, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view.
  • the power semiconductor module 500 according to this embodiment includes a bonded structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in FIG.
  • the metal heat sink 50 joined to the lower surface with the heat-resistant solder 60, and the water cooling cooler 70 provided in the lower surface of the metal heat sink 50 are provided.
  • a power semiconductor device 41 is provided on the upper surface of the insulating substrate 100 via a heat-resistant solder layer 42.
  • a metal heat sink 50 and a water-cooled cooler 70 are provided on the lower surface of the insulating substrate 100.
  • the metal heat sink 50 (54) is configured to have a larger area than the insulating substrate 100 (21) when viewed in plan from the stacking direction.
  • the metal heat sink 50 is configured by stacking Cu layers 54 and 56 on both sides of the Mo layer 52.
  • the Mo layer 52 is disposed between the pair of Cu layers 54 and 56.
  • the metal heat sink 50 is fixed to the water-cooled cooler 70 with screws 90.
  • the low heat stretchable metal plate 12-1 and the power semiconductor device 41 are electrically connected by an aluminum wire 29.
  • the cooling water 72 is supplied from the inlet 70a of the water-cooled cooler 70 and discharged from the outlet 70b. As a result, the metal heat sink 50 is cooled, and the heat generated in the power semiconductor device 41 can be released.
  • the joint structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in the fourth embodiment is used.
  • Tj semiconductor junction temperature
  • ⁇ Tj wide temperature range
  • FIG. 7 is a cross-sectional view of a power semiconductor module 600 according to the eighth embodiment.
  • the power semiconductor module 600 includes a power semiconductor device according to the fourth embodiment shown in FIG. 4, a bonded structure 400 of an insulating substrate, and cooling fins 71.
  • the insulating substrate 100 shown in FIG. 7 includes a ceramic substrate 21 such as SiN, and low heat stretchable metal plates 12-1 and 12-2 attached to both surfaces of the ceramic substrate 21.
  • the power semiconductor device 41 is, for example, a SiC power semiconductor device.
  • the power semiconductor device 41 is connected to the low heat stretchable metal plate 12-1 by a heat resistant solder layer.
  • the power semiconductor device 41 and the low thermal stretchable metal plate 12-1 are electrically connected by an aluminum wire 29.
  • cooling fins 71 made of Cu or aluminum are provided via a heat-resistant solder layer 60. Ni plating (not shown) is applied to at least the upper surface of the cooling fin 71.
  • the solidus temperature is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the SiC power semiconductor device 41, and the liquidus temperature is higher than the liquidus temperature of the heat resistant solder layer 60.
  • a solder material that is at least 30 ° C. lower is selected. Examples of the solder material described above include eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, and Bi solder. .
  • the material of the heat resistant solder layer 60 is not limited to these. If the heat-resistant solder layer 42 is eutectic Au—Ge solder, the eutectic Au—Sn solder, eutectic Bi—Ag solder, or Bi solder is suitable as the heat resistant solder layer 60.
  • the size of the power semiconductor module 600 viewed from the stacking direction can be greatly reduced.
  • the joining structure 400 is directly connected to the cooling fin 71, the heat sink can be omitted. That is, in the eighth embodiment of the present invention, it is possible to reduce the size and weight of the device. As a result, it is possible to reduce the cost of the module.
  • the example in which the insulating substrate 100 shown in the first to third embodiments is applied has been described.
  • the multilayer ceramic insulating substrates 200 and 300 shown in the fourth and fifth embodiments are used. It is also possible to apply.
  • the insulating substrate, the multilayer ceramic insulating substrate, the joined structure of the power semiconductor device and the insulating substrate, and the power semiconductor module according to the embodiment have been described, but the present invention is not limited to this, and the configuration of each part is , Can be replaced with any configuration having the same function.
  • a highly reliable insulating substrate can be realized in a cooling / heating cycle with a high semiconductor junction temperature (Tj) and a wide temperature range ( ⁇ Tj).
  • Tj semiconductor junction temperature
  • ⁇ Tj wide temperature range
  • Embodiment of this invention can be utilized for the power semiconductor module which can endure a temperature cycle.

Abstract

This insulating substrate (100) has a ceramic substrate (21), and low-thermal expansion/contraction metal plates (12-1, 12-2) bonded to at least one surface of the ceramic substrate (21). The low-thermal expansion/contraction metal plates (12-1, 12-2) are provided with a pair of Cu plates (14, 15) of substantially equal thickness, and a low-thermal expansion metal plate (13) disposed between the pair of Cu plates (14, 15), and having a lower coefficient of thermal expansion than the Cu plates (14, 15).

Description

絶縁基板、多層セラミック絶縁基板、パワー半導体装置と絶縁基板の接合構造体、及びパワー半導体モジュールInsulating substrate, multilayer ceramic insulating substrate, joined structure of power semiconductor device and insulating substrate, and power semiconductor module
　本発明は、温度差が大きい冷熱サイクルストレスに対して、高い耐性を有する絶縁基板、多層セラミック絶縁基板、パワー半導体装置と絶縁基板の接合構造体、及びパワー半導体モジュールに関する。 The present invention relates to an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that have high resistance to thermal cycle stress with a large temperature difference.
　炭化珪素（ＳｉＣ）や窒化ガリウム（ＧａＮ）、ダイヤモンド（Ｃ）等のワイドバンドギャップ半導体を用いたパワー半導体装置は、高い半導体接合温度（Ｔｊ）であっても、シリコン（Ｓｉ）やガリウム砒素（ＧａＡｓ）を用いたパワー半導体装置に比べてオン抵抗が低く、高速スイッチイングが可能であるという利点がある。このため、半導体装置の小チップ化が可能である。また、小チップ化と同時に、システムを構成する受動部品や冷却器の小型化を図ることができ、小型軽量で低価格なパワーエレクトロニクスシステムが実現できると期待されている。 A power semiconductor device using a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond (C), etc., even at a high semiconductor junction temperature (Tj), silicon (Si) or gallium arsenide ( Compared with a power semiconductor device using GaAs), the on-resistance is low, and there is an advantage that high-speed switching is possible. For this reason, it is possible to reduce the size of the semiconductor device. At the same time as miniaturization, the passive components and coolers that make up the system can be miniaturized, and it is expected that a compact, lightweight, and low-priced power electronics system can be realized.
　このようなパワーエレクトロニクスシステムを現実に具体化させるためには、高い半導体接合温度Ｔｊ（例えば、Ｔｊ＞２００℃）、且つ、広い温度範囲ΔＴｊ（例えば、Ｔｊ＝－４０℃～３００℃）において高い信頼性で作動するパワー半導体モジュールが実現されなくてはならない。 In order to actualize such a power electronics system, a high semiconductor junction temperature Tj (eg, Tj> 200 ° C.) and a wide temperature range ΔTj (eg, Tj = −40 ° C. to 300 ° C.) are high. A power semiconductor module that operates reliably must be realized.
　このような問題を解決するために、特開２００８－２７０３５３号公報（特許文献１）に開示されたパワー半導体モジュールが提案されている。該パワー半導体モジュールでは、半導体素子と、絶縁部と、放熱板の組み合わせとしている。 In order to solve such a problem, a power semiconductor module disclosed in Japanese Patent Laid-Open No. 2008-270353 (Patent Document 1) has been proposed. In the power semiconductor module, a combination of a semiconductor element, an insulating portion, and a heat sink is used.
　そして、特許文献１に開示されたパワー半導体モジュールでは、半導体接合温度（Ｔｊ）の最大値が２００℃、温度範囲（ΔＴｊ＝２４０℃）の冷熱サイクル試験で、２０００サイクル程度に耐えられる信頼度を有することが開示されている。 The power semiconductor module disclosed in Patent Document 1 has a reliability that can withstand about 2000 cycles in a thermal cycle test in which the maximum semiconductor junction temperature (Tj) is 200 ° C. and the temperature range (ΔTj = 240 ° C.). It is disclosed to have.
特開２００８－２７０３５３号JP 2008-270353 A
　しかしながら、特許文献１に開示されたパワー半導体モジュールでは、より高い最高温度Ｔｊ、且つ、より大きな温度範囲（例えば、Ｔｊ＝－４０℃～２５０℃、ΔＴｊ＝２９０℃）の環境で作動させようとした場合、以下に示す問題があった。パワー半導体モジュールを構成するパワー半導体装置と絶縁基板接合構造体との間の接合部分が、極めて少ないサイクル数で故障し、実際上この温度領域では実用に供することができない。 However, the power semiconductor module disclosed in Patent Document 1 tries to operate in an environment having a higher maximum temperature Tj and a larger temperature range (for example, Tj = −40 ° C. to 250 ° C., ΔTj = 290 ° C.). In this case, there are the following problems. The joint between the power semiconductor device constituting the power semiconductor module and the insulating substrate joining structure fails with an extremely small number of cycles, and practically cannot be put to practical use in this temperature region.
　本発明は、このような従来の課題を解決するためになされたものであり、その目的とするところは、半導体接合温度（Ｔｊ）が高く且つ温度範囲（ΔＴｊ）が広い冷熱サイクルの環境下においても高い信頼性で作動する絶縁基板、多層セラミック絶縁基板、パワー半導体装置と絶縁基板の接合構造体、及びパワー半導体モジュールを提供することにある。 The present invention has been made in order to solve such a conventional problem, and the object of the present invention is to be used in an environment of a thermal cycle where the semiconductor junction temperature (Tj) is high and the temperature range (ΔTj) is wide. It is another object of the present invention to provide an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that operate with high reliability.
　本発明の一態様に係わる絶縁基板は、セラミック基板と、セラミック基板の少なくとも一方の面に貼り付けられた低熱伸縮性金属板と、を有する。低熱伸縮性金属板は、厚みがほぼ等しい一対のＣｕ板と、一対のＣｕ板の間に設けられた、Ｃｕ板よりも熱膨張係数が低い低熱膨張金属板と、を備える。 The insulating substrate according to one embodiment of the present invention includes a ceramic substrate and a low heat stretchable metal plate attached to at least one surface of the ceramic substrate. The low thermal stretchable metal plate includes a pair of Cu plates having substantially the same thickness and a low thermal expansion metal plate provided between the pair of Cu plates and having a thermal expansion coefficient lower than that of the Cu plate.
図１は、本発明の第１～第３実施形態に係る絶縁基板の要部を示す断面図である。FIG. 1 is a cross-sectional view showing a main part of an insulating substrate according to first to third embodiments of the present invention. 図２は、本発明の第４実施形態に係る多層セラミック絶縁基板の要部を示す断面図である。FIG. 2 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention. 図３は、本発明の第５実施形態に係る多層セラミック絶縁基板の要部を示す断面図である。FIG. 3 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fifth embodiment of the present invention. 図４は、本発明の第６実施形態に係るパワー半導体装置と絶縁基板の接合構造体の要部を示す断面図である。FIG. 4 is a cross-sectional view showing a main part of a joined structure of a power semiconductor device and an insulating substrate according to the sixth embodiment of the present invention. 図５は、本発明の第６実施形態に係るパワー半導体装置と絶縁基板の接合構造体、及び比較例に係わる接合構造体の冷熱試験結果を示す特性図である。FIG. 5: is a characteristic view which shows the thermal test result of the joining structure body of the power semiconductor device which concerns on 6th Embodiment of this invention, and an insulated substrate, and the joining structure body concerning a comparative example. 図６は、本発明の第７実施形態に係るパワー半導体モジュールを示し、（ａ）は平面図、（ｂ）は要部断面図である。6A and 6B show a power semiconductor module according to a seventh embodiment of the present invention, in which FIG. 6A is a plan view and FIG. 図７は、本発明の第８実施形態に係るパワー半導体モジュールの要部を示す断面図である。FIG. 7 is a cross-sectional view showing a main part of a power semiconductor module according to the eighth embodiment of the present invention.
　以下、本発明の実施形態を図面に基づいて説明する。なお、以下では、絶縁基板、多層セラミック絶縁基板、パワー半導体装置と絶縁基板の接合構造体、及びパワー半導体モジュールの構成を種々の模式図（断面図、平面図等）を参照して説明するが、これらの模式図は理解を促進するために、厚さと平面寸法との関係や各層の厚さの比率等は誇張して記載している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following, the configuration of the insulating substrate, the multilayer ceramic insulating substrate, the power semiconductor device / insulating substrate bonding structure, and the power semiconductor module will be described with reference to various schematic views (cross-sectional views, plan views, etc.). In order to facilitate understanding, these schematic diagrams exaggerate the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like.
［第１実施形態に係る絶縁基板の説明］
　以下、第１実施形態に係る絶縁基板について説明する。第１実施形態に係る絶縁基板は、「Ｃｕ板が剥離する」という問題を解決する。この問題は、ＳｉＮ絶縁基板の両面にＣｕ板を貼り付けた従来のパワー半導体モジュールにおいて発生し得る。 [Description of Insulating Substrate According to First Embodiment]
Hereinafter, the insulating substrate according to the first embodiment will be described. The insulating substrate according to the first embodiment solves the problem of “Cu plate peeling”. This problem may occur in a conventional power semiconductor module in which Cu plates are attached to both sides of a SiN insulating substrate.
　図１は、本発明の第１実施形態に係る絶縁基板を示す断面図である。図１に示すように、第１実施形態に係る絶縁基板１００は、厚み方向のほぼ中央にＳｉＮ（窒化珪素）からなるセラミック基板２１が設けられている。セラミック基板２１の厚みは、０．１ｍｍ以上２ｍｍ以下であることが望ましく、０．３１ｍｍとするのが好適である。 FIG. 1 is a sectional view showing an insulating substrate according to the first embodiment of the present invention. As shown in FIG. 1, the insulating substrate 100 according to the first embodiment is provided with a ceramic substrate 21 made of SiN (silicon nitride) at substantially the center in the thickness direction. The thickness of the ceramic substrate 21 is desirably 0.1 mm or more and 2 mm or less, and preferably 0.31 mm.
　また、セラミック基板２１の両面（下面、及び上面）には、それぞれ低熱伸縮性金属板１２-1，１２-2が接合されている。低熱伸縮性金属板は、例えば、ＣＩＣクラッド金属板からなる。以下、低熱伸縮性金属板１２-1，１２-2を、ＣＩＣクラッド金属板１２-1，１２-2と称する。各ＣＩＣクラッド金属板１２-1，１２-2は同一の構成を備えている。ＣＩＣクラッド金属板１２-1（１２-2）の各々の厚みは０．１ｍｍ以上２ｍｍ以下であることが望ましく、好ましくは０．３７ｍｍである。ここで、ＣＩＣクラッド金属板１２-1，１２-2は、インバー（Ｉｎｖｅｒ；登録商標）合金板１３（主成分Ｆｅ、Ｎｉ３６．５vol％含有）の両面に一対の無酸素銅板（Ｃｕ板１４，１５）を金属学的方法を用いて接合させた３層金属板である。また、インバー合金板１３の線膨張率は１．２ｐｐｍ／℃程度と小さいことから、インバー合金板１３の両面をこれと略同じ厚み（誤差－１％～＋１％程度）のＣｕ板１４，１５で挟んだＣＩＣクラッド金属板１２-1，１２-2は、Ｃｕ板単体に比べて低い伸縮性（或いは低い合成熱膨張性）を有する。 Further, low thermal stretchable metal plates 12-1 and 12-2 are joined to both surfaces (lower surface and upper surface) of the ceramic substrate 21, respectively. The low heat stretchable metal plate is made of, for example, a CIC clad metal plate. Hereinafter, the low thermal stretchable metal plates 12-1 and 12-2 are referred to as CIC clad metal plates 12-1 and 12-2. Each of the CIC clad metal plates 12-1 and 12-2 has the same configuration. The thickness of each CIC clad metal plate 12-1 (12-2) is desirably 0.1 mm or more and 2 mm or less, and preferably 0.37 mm. Here, the CIC clad metal plates 12-1 and 12-2 are a pair of oxygen-free copper plates (Cu plates 14, 14) on both sides of an Inver (registered trademark) alloy plate 13 (containing main components Fe and 36.5 vol% Ni). 15) is a three-layer metal plate joined using a metallurgical method. Further, since the linear expansion coefficient of the Invar alloy plate 13 is as small as about 1.2 ppm / ° C., the Cu plates 14 and 15 having approximately the same thickness (an error of about −1% to + 1%) on both sides of the Invar alloy plate 13. The CIC clad metal plates 12-1 and 12-2 sandwiched between the layers have lower stretchability (or lower synthetic thermal expansion) than the Cu plate alone.
　ＣＩＣクラッド金属板１２-1，１２-2に設けられるＣｕ板１４及びＣｕ板１５の厚みは、熱伝導、電気伝導の良さを保持するため、少なくとも５μｍ以上であることが望ましく、１０μｍ以上であることがより望ましい。また、後述する冷熱サイクルにおいて、セラミック基板２１と、ＣＩＣクラッド金属板１２-1，１２-2との界面に加えられる熱応力を軽減する観点から、インバー合金板１３に対するＣｕ板１４，１５の各々の厚さの比率（Ｃ／Ｉ比）はできるだけ小さくして、ＳｉＮ（セラミック基板２１）の線膨張率との差を抑制するのが望ましい。具体的には、一対のＣｕ板１４，１５の各々の１枚の厚さは、インバー合金板１３の厚さの１／２以下が望ましく、１／５以下とすることがより望ましい。 The thicknesses of the Cu plate 14 and the Cu plate 15 provided on the CIC clad metal plates 12-1 and 12-2 are preferably at least 5 μm or more and 10 μm or more in order to maintain good heat conduction and electrical conduction. It is more desirable. In addition, in the cooling cycle described later, each of the Cu plates 14 and 15 with respect to the Invar alloy plate 13 from the viewpoint of reducing the thermal stress applied to the interface between the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2. The thickness ratio (C / I ratio) is preferably made as small as possible to suppress the difference from the linear expansion coefficient of SiN (ceramic substrate 21). Specifically, the thickness of each of the pair of Cu plates 14 and 15 is desirably 1/2 or less, more desirably 1/5 or less of the thickness of the Invar alloy plate 13.
　セラミック基板２１と、ＣＩＣクラッド金属板１２-1，１２-2との接合は、Ｔｉ-Ｃｕ-Ａｇや、Ｔｉ-Ｃｕ-Ａｇ-Ｎｉ等の蝋剤（図示省略）を用いた活性金属接合法で実行することができる。セラミック基板２１にＣＩＣクラッド金属板１２-1，１２-2を接合させた後、ＣＩＣクラッド金属板１２-1，１２-2の最も外側のＣｕの表面には、実装用のＮｉめっき膜１６を被覆する。なお、Ｎｉめっき膜１６は、第１実施形態に係る絶縁基板１００において必須の構成ではない。 The ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 are joined by an active metal joining method using a brazing agent (not shown) such as Ti—Cu—Ag or Ti—Cu—Ag—Ni. Can be done with. After the CIC clad metal plates 12-1 and 12-2 are bonded to the ceramic substrate 21, the Ni plating film 16 for mounting is formed on the outermost Cu surface of the CIC clad metal plates 12-1 and 12-2. Cover. The Ni plating film 16 is not an essential component in the insulating substrate 100 according to the first embodiment.
　次に、第１実施形態に係る絶縁基板１００の作用について説明する。本実施形態に係る絶縁基板１００の効果を検証するために、発明者らは、絶縁基板（第１実施形態のサンプル）を製作し、冷熱サイクル試験を実施した。第１実施形態のサンプルは、縦２０ｍｍ、横１８ｍｍ、厚み０．３１ｍｍのＳｉＮセラミック基板２１の両面それぞれに、縦１７ｍｍ、横８．５ｍｍ、厚み０．３７ｍｍ、Ｃ／Ｉ比＝１／８のＣＩＣクラッド金属板１２-1，１２-2を貼り付けた絶縁基板（本実施形態のサンプル）である。 Next, the operation of the insulating substrate 100 according to the first embodiment will be described. In order to verify the effect of the insulating substrate 100 according to the present embodiment, the inventors manufactured an insulating substrate (sample of the first embodiment) and conducted a thermal cycle test. The sample of the first embodiment has a length of 17 mm, a width of 8.5 mm, a thickness of 0.37 mm, and a C / I ratio = 1/8 on each side of the SiN ceramic substrate 21 having a length of 20 mm, a width of 18 mm, and a thickness of 0.31 mm. This is an insulating substrate (sample of this embodiment) to which CIC clad metal plates 12-1 and 12-2 are attached.
　発明者らは、比較例に係わる絶縁基板（比較例のサンプル）も作製した。比較例のサンプルは、ＣＩＣクラッド金属板１２-1，１２-2の代わりに、縦１７ｍｍ、横８．５ｍｍ、厚み０．３ｍｍ、表面にＮｉめっきを施した無酸素Ｃｕ板を用いた絶縁基板である。比較例のサンプルについて同様な冷熱サイクル試験を実施した。 The inventors also produced an insulating substrate (a sample of a comparative example) according to a comparative example. The sample of the comparative example is an insulating substrate using an oxygen-free Cu plate having a length of 17 mm, a width of 8.5 mm, a thickness of 0.3 mm, and a surface plated with Ni instead of the CIC clad metal plates 12-1 and 12-2. It is. A similar thermal cycle test was performed on the sample of the comparative example.
　試験の結果、Ｔｊ＝－４０℃～２５０℃（ΔＴｊ＝２９０℃）の冷熱サイクル試験においては、比較例のサンプルでは、１５０サイクル未満で全数がＣｕ板剥離による故障となった。これに対して、第１実施形態のサンプルでは、１万サイクルを越えても剥離の発生は起こらず、冷熱サイクル試験を終了した。また、Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）の冷熱サイクル試験においては、比較例に係わる絶縁基板は、６０サイクル未満でＣｕ剥離による故障を引き起こした。一方、第１実施形態に係る絶縁基板１００では７３００サイクルに達しても故障が発生していないことが判明した。 As a result of the test, in the thermal cycle test of Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.), all of the samples of the comparative examples failed due to Cu plate peeling in less than 150 cycles. On the other hand, in the sample of the first embodiment, no peeling occurred even after exceeding 10,000 cycles, and the thermal cycle test was completed. In the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the insulating substrate according to the comparative example caused a failure due to Cu peeling in less than 60 cycles. On the other hand, it was found that no failure occurred in the insulating substrate 100 according to the first embodiment even when it reached 7300 cycles.
　以上の冷熱サイクル試験の結果から、本発明の第１実施形態に係る絶縁基板１００によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、Ｃｕ（導体）板がＳｉＮセラミック基板から剥離するという問題を解決できることが判明した。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られた。 From the results of the above thermal cycle test, according to the insulating substrate 100 according to the first embodiment of the present invention, the Cu (conductor) plate in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that can solve the problem of peeling from the SiN ceramic substrate. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or less and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　このようにして、本発明の第１実施形態では、インバー合金板１３を２枚のＣｕ板１４，１５で挟持して形成される低熱伸縮性金属板（ＣＩＣクラッド金属板）１２-1，１２-2を、ＳｉＮ等のセラミック基板２１の両面に貼り付けて絶縁基板１００を構成している。このため、比較例に係わる絶縁基板に比べ、繰り返しの温度変化によりＣｕ（導体）板がＳｉＮセラミック基板から剥離するというトラブルの発生を回避することが可能となる。 Thus, in the first embodiment of the present invention, the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12 formed by sandwiching the Invar alloy plate 13 between the two Cu plates 14 and 15 are used. -2 is attached to both surfaces of a ceramic substrate 21 such as SiN to constitute the insulating substrate 100. For this reason, compared with the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the SiN ceramic substrate due to repeated temperature changes.
　本実施形態では、セラミック基板２１の厚みを０．１ｍｍ以上２ｍｍ以下としているので、より一層繰り返しの温度変化に対する耐久性を向上させることができる。 In the present embodiment, since the thickness of the ceramic substrate 21 is set to 0.1 mm or more and 2 mm or less, durability against repeated temperature changes can be further improved.
　ＣＩＣクラッド金属板１２-1，１２-2は、インバー合金板（低熱膨張金属板）１３の両面に一対のＣｕ板１４，１５を、金属学的方法を用いて接合させた３層金属板である。これにより、Ｃｕ板１４，１５がインバー合金板１３から剥離することを防止することができる。 The CIC clad metal plates 12-1 and 12-2 are three-layer metal plates in which a pair of Cu plates 14 and 15 are bonded to both sides of an Invar alloy plate (low thermal expansion metal plate) 13 using a metallurgical method. is there. Thereby, it is possible to prevent the Cu plates 14 and 15 from being separated from the Invar alloy plate 13.
　ＣＩＣクラッド金属板１２-1，１２-2が備えるＣｕ板１４及びＣｕ板１５の厚みを５μｍ以上としているので、熱伝導、電気伝導の良さを保持することができる。 Since the thicknesses of the Cu plate 14 and the Cu plate 15 included in the CIC clad metal plates 12-1 and 12-2 are 5 μm or more, good heat conduction and electrical conduction can be maintained.
　インバー合金板１３に対するＣｕ板１４，１５の各々の厚みの比率（Ｃ／Ｉ比）を１／２以下としている。これにより、冷熱サイクルにおいてセラミック基板２１と、ＣＩＣクラッド金属板１２-1，１２-2との界面に加えられる熱応力を軽減することができ、セラミック基板２１からＣＩＣクラッド金属板１２-1，１２-2が剥離することを防止することができる。 The thickness ratio (C / I ratio) of each of the Cu plates 14 and 15 to the Invar alloy plate 13 is set to 1/2 or less. As a result, the thermal stress applied to the interface between the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 in the thermal cycle can be reduced, and the CIC clad metal plates 12-1 and 12 from the ceramic substrate 21 can be reduced. -2 can be prevented from peeling off.
　なお、第１実施形態では、セラミック基板２１の両面に低熱伸縮性金属板１２-1，１２-2を貼り付ける構成としたが、本発明は、低熱伸縮性金属板をセラミック基板２１のいずれか一方の面にのみ貼り付ける構成とすることも可能である。 In the first embodiment, the low thermal stretchable metal plates 12-1 and 12-2 are attached to both surfaces of the ceramic substrate 21. However, the present invention is not limited to any one of the ceramic substrates 21. It is also possible to adopt a configuration in which only one surface is attached.
［第２実施形態に係る絶縁基板の説明］
　第１実施形態では、セラミック基板２１の母材として、破壊靭性や曲げ強度を含む機械的強度に優れているＳｉＮ（窒化珪素）を用いる例について説明した。第２実施形態では、セラミック基板２１の母材としてＳｉＮ以外のセラミック材料を用いる例を説明する。 [Description of Insulating Substrate According to Second Embodiment]
In the first embodiment, an example in which SiN (silicon nitride) excellent in mechanical strength including fracture toughness and bending strength is used as the base material of the ceramic substrate 21 has been described. In the second embodiment, an example in which a ceramic material other than SiN is used as the base material of the ceramic substrate 21 will be described.
　具体的に、第２実施形態におけるセラミック基板２１は、アルミナ（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）、ベリリア（ＢｅＯ）からなる群より選ばれるセラミック材料からなる。セラミック基板２１の厚みは０．１ｍｍ～２ｍｍであることが望ましい。第２実施形態に係る絶縁基板は、セラミック基板がＳｉＮ以外のセラミック材料であること以外は、図１に示した構成と同一であるので、詳細な構成についての説明を省略する。 Specifically, the ceramic substrate 21 in the second embodiment is made of a ceramic material selected from the group consisting of alumina (Al 2 O 3 ), aluminum nitride (AlN), and beryllia (BeO). The thickness of the ceramic substrate 21 is preferably 0.1 mm to 2 mm. Since the insulating substrate according to the second embodiment is the same as the configuration shown in FIG. 1 except that the ceramic substrate is a ceramic material other than SiN, a detailed description of the configuration is omitted.
　ベリリア（ＢｅＯ）は、上記した３つのセラミック材料の中では最も熱伝導度が高いという利点がある反面、毒性があるという欠点がある。 Beryllia (BeO) has the advantage of having the highest thermal conductivity among the above three ceramic materials, but has the disadvantage of being toxic.
　アルミナ（Ａｌ２Ｏ３）は、ＳｉＮやＡｌＮと対比すると材料費が廉価であるという利点がある。機械的強度はＳｉＮよりも低く、ＡｌＮよりも高い。 Alumina (Al 2 O 3 ) has an advantage that the material cost is low compared with SiN or AlN. The mechanical strength is lower than SiN and higher than AlN.
　窒化アルミニウム（ＡｌＮ）は、熱伝導がアルミナやＳｉＮと対比して非常に高く、発熱する半導体チップの抜熱設計の観点から、本実施形態の絶縁基板に用いる材料として好適である。その反面、ＳｉＮやアルミナと対比すると機械的強度が弱い。このため、半導体接合温度の最大値Ｔｊmaxが２００℃以上、温度範囲（ΔＴｊ）が２５０℃以上の冷熱サイクルストレスに対して、ＳｉＮよりも短期間にＣｕ板の剥離が起きやすいという欠点がある。 Aluminum nitride (AlN) has a very high thermal conductivity as compared with alumina and SiN, and is suitable as a material used for the insulating substrate of the present embodiment from the viewpoint of heat removal design of a semiconductor chip that generates heat. On the other hand, mechanical strength is weak compared with SiN and alumina. For this reason, there is a drawback that the Cu plate is more easily peeled off in a shorter time than SiN against a thermal cycle stress where the maximum semiconductor junction temperature Tjmax is 200 ° C. or higher and the temperature range (ΔTj) is 250 ° C. or higher.
　以上の諸点を勘案すると、上記した３つのセラミック材料のうち、最も実用性に富むものは、窒化アルミニウム（ＡｌＮ）であると考えられる。発明者らは、図１に示すセラミック基板２１として窒化アルミニウム（ＡｌＮ）を用いて絶縁基板１００を構成し、絶縁基板１００を用いて以下の冷熱サイクル試験を行った。 Considering the above points, aluminum nitride (AlN) is considered to be the most practical of the above three ceramic materials. The inventors configured an insulating substrate 100 using aluminum nitride (AlN) as the ceramic substrate 21 shown in FIG. 1, and performed the following thermal cycle test using the insulating substrate 100.
　縦２０ｍｍ、横１８ｍｍ、厚み０．６４ｍｍのＡｌＮセラミック基板２１の両面のそれぞれに、縦１７ｍｍ、横８．５ｍｍ、厚み０．３７ｍｍ、Ｃ／Ｉ比＝１／８のＣＩＣクラッド金属板１２-1，１２-2を貼り付けた絶縁基板１００を製作し、冷熱サイクル試験を実施した。試験結果は以下のとおりである。 A CIC clad metal plate 12-1 having a length of 17 mm, a width of 8.5 mm, a thickness of 0.37 mm, and a C / I ratio of 1/8 on both surfaces of an AlN ceramic substrate 21 having a length of 20 mm, a width of 18 mm, and a thickness of 0.64 mm. , 12-2 is manufactured, and a thermal cycle test is performed. The test results are as follows.
　Ｔｊ＝－４０℃～２５０℃（ΔＴｊ＝２９０℃）の冷熱サイクル試験を実施した。その結果、第１実施形態で示したＳｉＮセラミック基板を用いた場合と同様に、１万サイクルを越えても剥離の発生は起こらなかった。また、Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）の冷熱サイクル試験を実施した。その結果、７３００サイクル経過しても故障が発生していないことが判明した。 A thermal cycle test of Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.) was performed. As a result, as in the case of using the SiN ceramic substrate shown in the first embodiment, no peeling occurred even after 10,000 cycles. Further, a thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.) was performed. As a result, it was found that no failure occurred even after 7300 cycles.
　以上の冷熱サイクル試験の結果から、本発明の第２実施形態に係る絶縁基板１００によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、Ｃｕ（導体）板がＡｌＮセラミック基板から剥離するという問題を解決できることが判明した。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られた。 From the results of the above thermal cycle test, according to the insulating substrate 100 according to the second embodiment of the present invention, the Cu (conductor) plate in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that can solve the problem of peeling from the AlN ceramic substrate. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or less and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　このようにして、本発明の第２実施形態では、ＡｌＮのセラミック基板２１の両面に低熱伸縮性金属板（ＣＩＣクラッド金属板）１２-1，１２-2を貼り付けて、絶縁基板１００を構成している。これにより、比較例に係わる絶縁基板と比べ、繰り返しの温度変化によりＣｕ（導体）板がＡｌＮセラミック基板から剥離するというトラブルの発生を回避することが可能となる。 In this manner, in the second embodiment of the present invention, the insulating substrate 100 is configured by attaching the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12-2 to both surfaces of the AlN ceramic substrate 21. is doing. Thereby, compared with the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the AlN ceramic substrate due to repeated temperature changes.
　なお、第２実施形態に係るＣＩＣクラッド金属板１２-1，１２-2の接合方法として、直接Ｃｕ接合法（ＤＣＢ法）を使用することもできる。 In addition, as a joining method of the CIC clad metal plates 12-1 and 12-2 according to the second embodiment, a direct Cu joining method (DCB method) can also be used.
［第３実施形態に係る絶縁基板の説明］
　次に、第３実施形態に係る絶縁基板について説明する。前述した第１及び第２実施形態では、低熱伸縮性金属板１２-1，１２-2をＣＩＣクラッド金属板とした。低熱伸縮性金属板１２-1，１２-2はＣＩＣクラッド金属板に限らない。低熱伸縮性を有する金属板であれば、インバー合金板１３以外の金属板をＣｕ板１４，１５で挟持したＣＭＣクラッド金属板を低熱伸縮性金属板１２-1，１２-2として用いることもできる。インバー合金板以外の金属板の材料を「Ｍ」とする。ＣＭＣクラッド金属板の総厚みは０．１ｍｍ以上２ｍｍ以下であることが望ましく、Ｃｕ板１４，１５の厚みは少なくとも５μｍ以上、好ましくは１０μｍ以上であることが望ましい。インバー合金板以外の金属板に対するＣｕ板１４，１５の各々の厚さの比率（Ｃ／Ｍ比）は、ＣＩＣクラッド金属板と同様に、１／２以下が望ましく、好ましくは１／５以下が望ましい。 [Description of Insulating Substrate According to Third Embodiment]
Next, an insulating substrate according to the third embodiment will be described. In the first and second embodiments described above, the low heat stretchable metal plates 12-1 and 12-2 are CIC clad metal plates. The low heat stretchable metal plates 12-1 and 12-2 are not limited to CIC clad metal plates. If it is a metal plate having low thermal stretchability, a CMC clad metal plate in which a metal plate other than the Invar alloy plate 13 is sandwiched between Cu plates 14 and 15 can be used as the low thermal stretch metal plates 12-1 and 12-2. . The material of the metal plate other than the Invar alloy plate is “M”. The total thickness of the CMC clad metal plate is desirably 0.1 mm or more and 2 mm or less, and the thickness of the Cu plates 14 and 15 is desirably at least 5 μm or more, preferably 10 μm or more. The ratio (C / M ratio) of each of the Cu plates 14 and 15 to the metal plate other than the Invar alloy plate is desirably 1/2 or less, preferably 1/5 or less, like the CIC clad metal plate. desirable.
　ＣＭＣクラッド金属板を構成する金属板の材料（Ｍ）の一例は、モリブデン（Ｍｏ）である。このほかに、スーパーインバー（主成分Ｆｅ、Ｎｉ３２vol％及びＣｏ５vol％含有）や、ステンレスインバー（主成分Ｆｅ、Ｃｏ５４vol％含有）を金属板の材料「Ｍ」として用いることができる。 An example of the material (M) of the metal plate constituting the CMC clad metal plate is molybdenum (Mo). In addition, super invar (containing main components Fe, Ni 32 vol% and Co 5 vol%) and stainless steel invar (containing main components Fe and Co 54 vol%) can be used as the material “M” of the metal plate.
　発明者らは、Ｃｕ-Ｍｏ-Ｃｕの積層構造からなるＣＭＣクラッド金属板（低熱伸縮性金属板１２-1，１２-2）とＳｉＮセラミック基板２１とを備える絶縁基板のサンプルを製作した。そして、Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）の冷熱サイクル試験を実施した。その結果、２０００サイクル以上経過しても、低熱伸縮性金属板１２-1，１２-2の剥離不良はないという結果が得られた。 The inventors manufactured a sample of an insulating substrate including a CMC clad metal plate (low thermal stretchable metal plates 12-1 and 12-2) having a laminated structure of Cu—Mo—Cu and a SiN ceramic substrate 21. Then, a thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.) was performed. As a result, even if 2000 cycles or more passed, the result that there was no peeling defect of the low thermal stretchable metal plates 12-1 and 12-2 was obtained.
　以上の冷熱サイクル試験の結果から、本発明の第３実施形態に係る絶縁基板によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、Ｃｕ（導体）板がＳｉＮセラミック基板から剥離するという問題を解決できることが判明した。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られた。 From the results of the above thermal cycle test, according to the insulating substrate according to the third embodiment of the present invention, the Cu (conductor) plate is used in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling from the SiN ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or less and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　このようにして、本発明の第３実施形態では、ＳｉＮ等のセラミック基板の両面に低熱伸縮性導体板としてのＣＭＣクラッド金属板を貼り付けることにより絶縁基板を形成する。これにより、比較例に係わる絶縁基板と対比して、繰り返しの温度変化によりＣｕ（導体）板がセラミック基板から剥離するというトラブルの発生を回避することが可能となる。 Thus, in the third embodiment of the present invention, an insulating substrate is formed by attaching a CMC clad metal plate as a low thermal stretchable conductor plate to both surfaces of a ceramic substrate such as SiN. This makes it possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the ceramic substrate due to repeated temperature changes as compared with the insulating substrate according to the comparative example.
　また、本実施形態では、セラミック基板２１として、窒化珪素（ＳｉＮ）、アルミナ（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）、ベリリア（ＢｅＯ）のうちのいずれかを用いることができる。よって、機械的な強度を強くすることができ、絶縁基板全体の強度を向上させることができる。 In the present embodiment, any one of silicon nitride (SiN), alumina (Al 2 O 3 ), aluminum nitride (AlN), and beryllia (BeO) can be used as the ceramic substrate 21. Therefore, the mechanical strength can be increased and the strength of the entire insulating substrate can be improved.
　低熱膨張金属板として、インバー（主成分Ｆｅ、Ｎｉ３６．５vol％含有）、モリブデン（Ｍｏ）、スーパーインバー（主成分Ｆｅ、Ｎｉ３２vol％及びＣｏ５vol％含有）、ステンレスインバー（主成分Ｆｅ、Ｃｏ５４vol％含有）のうちの一つを用いる。これにより、温度変化により生じる熱膨張を抑えることができ、低熱伸縮性金属板に加わるストレスを軽減し、剥離が発生することを防止できる。 As a low thermal expansion metal plate, Invar (containing main component Fe, Ni 36.5 vol%), molybdenum (Mo), Super Invar (containing main components Fe, Ni 32 vol% and Co 5 vol%), stainless steel invar (containing main components Fe, Co 54 vol%) Use one of these. Thereby, thermal expansion caused by temperature change can be suppressed, stress applied to the low heat stretchable metal plate can be reduced, and peeling can be prevented from occurring.
［第４実施形態に係る多層セラミック絶縁基板の説明］
　次に、本発明の第４実施形態に係る多層セラミック絶縁基板について説明する。前述した第１～第３実施形態では、１枚の各種セラミック基板２１の両面に低熱伸縮性金属板１２-1，１２-2を貼り付けた単層セラミック絶縁基板について説明した。第４実施形態では、２以上の単層セラミック絶縁基板を積層した多層セラミック絶縁基板について説明する。 [Description of Multilayer Ceramic Insulating Substrate According to Fourth Embodiment]
Next, a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention is described. In the above-described first to third embodiments, the single-layer ceramic insulating substrate in which the low heat stretchable metal plates 12-1 and 12-2 are bonded to both surfaces of the various ceramic substrates 21 has been described. In the fourth embodiment, a multilayer ceramic insulating substrate in which two or more single-layer ceramic insulating substrates are stacked will be described.
　図２は、第４実施形態に係る多層（例えば、２層）セラミック絶縁基板２００の構成を示す断面図である。図２に示すように、多層セラミック絶縁基板２００は、上下に積層された２つの絶縁基板、即ち、第１絶縁基板部材３１ａ及び第２絶縁基板部材３１ｂを有している。絶縁基板部材３１ａ，３１ｂの各々の基本構成は、図１に示した絶縁基板１００と略同一である。なお、図２において、インバー合金板１３、Ｃｕ板１４，１５は、前述した第１～第３実施形態と同様であるので、構成の説明を省略する。 FIG. 2 is a cross-sectional view showing a configuration of a multilayer (for example, two layers) ceramic insulating substrate 200 according to the fourth embodiment. As shown in FIG. 2, the multilayer ceramic insulating substrate 200 includes two insulating substrates that are stacked one above the other, that is, a first insulating substrate member 31 a and a second insulating substrate member 31 b. The basic configuration of each of the insulating substrate members 31a and 31b is substantially the same as that of the insulating substrate 100 shown in FIG. In FIG. 2, the invar alloy plate 13 and the Cu plates 14 and 15 are the same as those in the first to third embodiments described above, and the description of the configuration is omitted.
　第１絶縁基板部材３１ａは、セラミック基板２１ａと、セラミック基板２１ａの上面に貼り付けられた低熱伸縮性金属板１２ａ-1と、セラミック基板２１ａの下面に貼り付けられた低熱伸縮性金属板１２ａ-2とを備える。同様に、第２絶縁基板部材３１ｂは、セラミック基板２１ｂと、セラミック基板２１ｂの上面に貼り付けられた低熱伸縮性金属板１２ｂ-1と、セラミック基板２１ｂの下面に貼り付けられた低熱伸縮性金属板１２ｂ-2とを備える。 The first insulating substrate member 31a includes a ceramic substrate 21a, a low heat stretchable metal plate 12a-1 attached to the upper surface of the ceramic substrate 21a, and a low heat stretchable metal plate 12a- attached to the lower surface of the ceramic substrate 21a. And 2. Similarly, the second insulating substrate member 31b includes a ceramic substrate 21b, a low heat stretchable metal plate 12b-1 attached to the upper surface of the ceramic substrate 21b, and a low heat stretchable metal attached to the lower surface of the ceramic substrate 21b. Plate 12b-2.
　そして、図示省略の蝋材Ｔｉ-Ｃｕ-ＡｇやＴｉ-Ｃｕ-Ａｇ-Ｎｉは、第１絶縁基板部材３１ａの低熱伸縮性金属板１２ａ-2と、第２絶縁基板部材３１ｂの低熱伸縮性金属板１２ｂ-1とを接合している。 The wax material Ti—Cu—Ag or Ti—Cu—Ag—Ni (not shown) is composed of the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretchable metal of the second insulating substrate member 31b. The plate 12b-1 is joined.
　多層セラミック絶縁基板２００を適用する利点は、中間層の導体板（図２に示す例では低熱伸縮性金属板１２ａ-2，１２ｂ-1）を配線として活用することができる。これにより、多層セラミック絶縁基板２００の浮遊インダクタンスを縮減し、多層セラミック絶縁基板２００の実装面積を低減することができる。この利点をより一層効果的にするためには、セラミック基板２１ａの所定位置にビア窓１７を開口して、ビア窓１７に埋設したビア窓金属板１８（例えば、Ｃｕ）を介して、上部の低熱伸縮性金属板１２ａ-1と下部の低熱伸縮性金属板１２ａ-2とを電気的に接続すれば良い。低熱伸縮性金属板１２ａ-1とビア窓金属板１８との接合、及び、ビア窓金属板１８と低熱伸縮性金属板１２ａ-2との接合は、図示省略の活性金属蝋材Ｔｉ-Ｃｕ-ＡｇやＴｉ-Ｃｕ-Ａｇ-Ｎｉ等を用いて接合することができる。 The advantage of applying the multilayer ceramic insulating substrate 200 is that an intermediate layer conductive plate (low thermal stretchable metal plates 12a-2 and 12b-1 in the example shown in FIG. 2) can be used as wiring. Thereby, the floating inductance of the multilayer ceramic insulating substrate 200 can be reduced, and the mounting area of the multilayer ceramic insulating substrate 200 can be reduced. In order to make this advantage even more effective, a via window 17 is opened at a predetermined position of the ceramic substrate 21a, and a via window metal plate 18 (for example, Cu) embedded in the via window 17 is used to form an upper portion. The low heat stretchable metal plate 12a-1 may be electrically connected to the lower low heat stretchable metal plate 12a-2. The joining of the low heat stretchable metal plate 12a-1 and the via window metal plate 18 and the joining of the via window metal plate 18 and the low heat stretchable metal plate 12a-2 are performed using an active metal brazing material Ti—Cu— (not shown). Bonding can be performed using Ag, Ti-Cu-Ag-Ni, or the like.
　次に、図２に記載した多層セラミック絶縁基板２００の製造方法について説明する。初めに、第１～第３実施形態に示した絶縁基板１００と同様の方法で、第１絶縁基板部材３１ａと第２絶縁基板部材３１ｂをそれぞれ別個に製作する。なお、この時点で、図２に示すＮｉめっき１６は設けられていない。 Next, a method for manufacturing the multilayer ceramic insulating substrate 200 shown in FIG. 2 will be described. First, the first insulating substrate member 31a and the second insulating substrate member 31b are separately manufactured by the same method as the insulating substrate 100 shown in the first to third embodiments. At this time, the Ni plating 16 shown in FIG. 2 is not provided.
　次いで、活性金属蝋材Ｔｉ-Ｃｕ-ＡｇやＴｉ-Ｃｕ-Ａｇ-Ｎｉ等を用いて、第１絶縁基板部材３１ａの低熱伸縮性金属板１２ａ-2と、第２絶縁基板部材３１ｂの低熱伸縮性金属板１２ｂ-1とを貼り合わせる。 Next, using the active metal brazing material Ti—Cu—Ag, Ti—Cu—Ag—Ni or the like, the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretch of the second insulating substrate member 31b are used. The conductive metal plate 12b-1 is bonded together.
　その後、低熱伸縮性金属板１２ａ-1と１２ｂ-2の表面（上面、及び下面）に、Ｎｉめっき１６を被覆する。その結果、図２に示す多層セラミック絶縁基板２００が完成する。なお、高温はんだの濡れ性を改善するために、Ｎｉめっき１６の上にＡｕめっき層やＡｇめっき層、Ｃｕめっき層を被覆してもよい。 Thereafter, Ni plating 16 is coated on the surfaces (upper surface and lower surface) of the low heat stretchable metal plates 12a-1 and 12b-2. As a result, the multilayer ceramic insulating substrate 200 shown in FIG. 2 is completed. In order to improve the wettability of the high-temperature solder, an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.
　発明者らは、図２に示す多層セラミック絶縁基板２００のサンプルを製作し、冷熱サイクル試験を実施した。多層セラミック絶縁基板２００のサンプルにおいて、第１絶縁基板部材３１ａ、及び第２絶縁基板部材３１ｂの各々は、ＳｉＮセラミック基板とＣＩＣクラッド金属板とを組み合わせた第１実施形態の絶縁基板１００である。その結果、Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）の冷熱サイクル試験おいて、１０００サイクル以上経過しても低熱伸縮性金属板１２ａ-1，１２ａ-2，１２ｂ-1，１２ｂ-2がセラミック基板２１ａ，２１ｂから剥離するという不良が発生しないことが判明した。 The inventors manufactured a sample of the multilayer ceramic insulating substrate 200 shown in FIG. 2 and conducted a thermal cycle test. In the sample of the multilayer ceramic insulating substrate 200, each of the first insulating substrate member 31a and the second insulating substrate member 31b is the insulating substrate 100 of the first embodiment in which a SiN ceramic substrate and a CIC clad metal plate are combined. As a result, in the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the low thermal stretchable metal plates 12a-1, 12a-2, 12b-1, 12b− It has been found that the defect that 2 peels from the ceramic substrates 21a and 21b does not occur.
　以上の冷熱サイクル試験の結果から、本発明の第４実施形態に係る多層セラミック絶縁基板２００によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、Ｃｕ（導体）板がＳｉＮセラミック基板から剥離するという問題を解決できることが判明した。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られた。 From the results of the above thermal cycle test, according to the multilayer ceramic insulating substrate 200 according to the fourth embodiment of the present invention, Cu (conductor) in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling of the plate from the SiN ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or less and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　このようにして、本発明の第４実施形態では、ＳｉＮ等のセラミック基板２１ａ，２１ｂの両面に低熱伸縮性金属板としてのＣＩＣクラッド金属板を貼り付けることにより、第１絶縁基板部材３１ａ、及び第２絶縁基板部材３１ｂを製作する。そして、第１絶縁基板部材３１ａ、及び第２絶縁基板部材３１ｂを積層して多層セラミック絶縁基板２００を構成する。これにより、比較例に係わる絶縁基板と対比して、繰り返しの温度変化によりＣｕ（導体）板がＳｉＮ絶縁基板から剥離するというトラブルの発生を回避することが可能となる。 Thus, in the fourth embodiment of the present invention, the first insulating substrate member 31a, and the CIC clad metal plate as the low thermal stretchable metal plate are attached to both surfaces of the ceramic substrates 21a and 21b such as SiN. The second insulating substrate member 31b is manufactured. Then, the multilayer ceramic insulating substrate 200 is configured by laminating the first insulating substrate member 31a and the second insulating substrate member 31b. Thereby, in contrast to the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate peels off from the SiN insulating substrate due to repeated temperature changes.
　なお、第４実施形態では、２つの絶縁基板部材３１ａ，３１ｂを積層した多層（２層）セラミック絶縁基板２００を例示したが、２層に限らず、３層以上とすることも可能である。セラミック基板２１ａ、２１ｂの例としてＳｉＮを示したが、第２実施形態で例示した材料は全て使用し得る。低熱伸縮性金属板１２ａ-1と１２ｂ-2の例としてＣＩＣクラッド金属板を示したが、第３実施形態で例示したＣＭＣクラッド金属板も使用し得る。 In the fourth embodiment, the multilayer (two-layer) ceramic insulating substrate 200 in which the two insulating substrate members 31a and 31b are stacked is illustrated. However, the number of layers is not limited to two, and three or more layers are also possible. Although SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used. Although the CIC clad metal plate is shown as an example of the low heat stretchable metal plates 12a-1 and 12b-2, the CMC clad metal plate exemplified in the third embodiment can also be used.
［第５実施形態に係る多層セラミック絶縁基板の説明］
　次に、第５実施形態に係る多層セラミック絶縁基板について説明する。図３は、第５実施形態に係る多層セラミック絶縁基板３００の構成を示す断面図であり、図２に示した多層セラミック絶縁基板２００の構造を改良した構成とされている。 [Description of Multilayer Ceramic Insulating Substrate According to Fifth Embodiment]
Next, a multilayer ceramic insulating substrate according to the fifth embodiment will be described. FIG. 3 is a cross-sectional view showing the configuration of the multilayer ceramic insulating substrate 300 according to the fifth embodiment, which is an improved configuration of the structure of the multilayer ceramic insulating substrate 200 shown in FIG.
　図３に示すように、第５実施形態に係る多層セラミック絶縁基板３００は、第１セラミック基板２１ａ、及び第２セラミック基板２１ｂを有する。第１セラミック基板２１ａの上面には低熱伸縮性金属板１２ａ-1が貼り付けられ、第２セラミック基板２１ｂの下面には低熱伸縮性金属板１２ｂ-2が貼り付けられている。 As shown in FIG. 3, the multilayer ceramic insulating substrate 300 according to the fifth embodiment includes a first ceramic substrate 21a and a second ceramic substrate 21b. A low heat stretchable metal plate 12a-1 is attached to the upper surface of the first ceramic substrate 21a, and a low heat stretchable metal plate 12b-2 is attached to the lower surface of the second ceramic substrate 21b.
　第１セラミック基板２１ａと第２セラミック基板２１ｂの間には、中間金属板１９が設けられている。中間金属板１９の厚みは、０．１ｍｍ以上２ｍｍ以下であり、好ましくは０．２ｍｍ以上１ｍｍ以下である。 An intermediate metal plate 19 is provided between the first ceramic substrate 21a and the second ceramic substrate 21b. The thickness of the intermediate metal plate 19 is not less than 0.1 mm and not more than 2 mm, preferably not less than 0.2 mm and not more than 1 mm.
　低熱伸縮性金属板１２ａ-1及び１２ｂ-2は、第１～第３実施形態で説明したＣＩＣクラッド金属板或いはＣＭＣクラッド金属板と同一である。図３におけるインバー合金板１３，Ｃｕ板１４，１５についての構成説明を省略する。ここでは、ＣＭＣクラッド金属板を例に取り説明する。 The low heat stretchable metal plates 12a-1 and 12b-2 are the same as the CIC clad metal plate or CMC clad metal plate described in the first to third embodiments. A description of the configuration of the Invar alloy plate 13 and the Cu plates 14 and 15 in FIG. 3 is omitted. Here, a CMC clad metal plate will be described as an example.
　セラミック基板２１ａにビア窓１７が開口され、ビア窓１７にビア窓金属板１８が埋設されている。低熱伸縮性金属板１２ａ-1と中間金属板１９とは、ビア窓金属板１８を介して所定の位置で接続されている。 A via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 is embedded in the via window 17. The low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 are connected to each other through a via window metal plate 18.
　セラミック基板２１ａ，２１ｂと中間金属板１９との間、ビア窓金属板１８と中間金属板１９との間、セラミック基板２１ａ，２１ｂと低熱伸縮性金属板１２ａ-1，１２ｂ-2との間、及びビア窓金属板１８と低熱伸縮性金属板１２ａ-1との間は、図示省略の活性金属蝋材Ｔｉ-Ｃｕ-ＡｇやＴｉ-Ｃｕ-Ａｇ-Ｎｉ等により、接合されている。なお、高温はんだの濡れ性を改善するためにＮｉめっき１６の上に、Ａｕめっき層やＡｇめっき層、Ｃｕめっき層を被覆してもよい。 Between the ceramic substrates 21a, 21b and the intermediate metal plate 19, between the via window metal plate 18 and the intermediate metal plate 19, between the ceramic substrates 21a, 21b and the low heat stretchable metal plates 12a-1, 12b-2, The via window metal plate 18 and the low heat stretchable metal plate 12a-1 are joined by an active metal brazing material Ti—Cu—Ag, Ti—Cu—Ag—Ni (not shown) or the like. In order to improve the wettability of the high-temperature solder, an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.
　次に、図３に記載した多層セラミック絶縁基板３００の製造方法について説明する。初めに、焼成炉のサセプタに置いた低熱伸縮性金属板１２ｂ-2の上に活性金属蝋材を載置し、その上にセラミック基板２１ｂを載せる。更にその上に、順に、活性金属蝋材と中間金属板１９、活性金属蝋材、セラミック基板２１ａ、活性金属蝋材、低熱伸縮性金属板１２ａ-1を積層する。但し、セラミック基板２１ａを載置するときには、ビア窓１７内部にビア窓金属板１８を同時に設置するものとする。 Next, a method for manufacturing the multilayer ceramic insulating substrate 300 shown in FIG. 3 will be described. First, the active metal brazing material is placed on the low heat stretchable metal plate 12b-2 placed on the susceptor of the firing furnace, and the ceramic substrate 21b is placed thereon. Further thereon, an active metal wax material, an intermediate metal plate 19, an active metal wax material, a ceramic substrate 21a, an active metal wax material, and a low heat stretchable metal plate 12a-1 are laminated in this order. However, when the ceramic substrate 21a is placed, the via window metal plate 18 is simultaneously installed in the via window 17.
　上記の積層体が完成すると、その上部に荷重となる錘を設置する。その後、炉内を還元雰囲気、或いは不活性雰囲気にして、活性金属蝋材の融点（または液相線）以上の温度まで加熱してから室温まで徐々に冷却する。その結果、図３に示す多層セラミック絶縁基板３００が完成する。 When the above laminate is completed, a weight to be a load is installed on the top. Thereafter, the inside of the furnace is made a reducing atmosphere or an inert atmosphere, heated to a temperature equal to or higher than the melting point (or liquidus) of the active metal wax material, and then gradually cooled to room temperature. As a result, the multilayer ceramic insulating substrate 300 shown in FIG. 3 is completed.
　発明者らは、第５実施形態に係わる多層セラミック絶縁基板３００のサンプルを製作し、冷熱サイクル試験を実施した。多層セラミック絶縁基板３００のサンプルは、ＳｉＮのセラミック基板２１ａ，２１ｂと、低熱伸縮性金属板（ＣＭＣクラッド金属板）１２ａ-1，１２ｂ-2とを備える。ビア窓金属板１８及び中間金属板１９としてＣｕ板（厚み約０．３１ｍｍ）を用いる。その結果、Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）の冷熱サイクル試験において、１０００サイクル以上経過しても、低熱伸縮性金属板１２ａ-1，１２ｂ-2、及び中間金属板１９がセラミック基板２１ａ，２１ｂから剥離する不良は見られなかった。 The inventors manufactured a sample of the multilayer ceramic insulating substrate 300 according to the fifth embodiment and conducted a thermal cycle test. A sample of the multilayer ceramic insulating substrate 300 includes SiN ceramic substrates 21a and 21b and low thermal stretchable metal plates (CMC clad metal plates) 12a-1 and 12b-2. A Cu plate (thickness: about 0.31 mm) is used as the via window metal plate 18 and the intermediate metal plate 19. As a result, in the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the low thermal stretchable metal plates 12a-1, 12b-2 and the intermediate metal plate 19 are not damaged even after 1000 cycles. Defects that peeled off from the ceramic substrates 21a and 21b were not observed.
　以上の冷熱サイクル試験の結果から、第５実施形態に係る多層セラミック絶縁基板３００によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、Ｃｕ（導体）板がセラミック基板から剥離するという問題を解決できることが判明した。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られた。 From the results of the thermal cycle test described above, according to the multilayer ceramic insulating substrate 300 according to the fifth embodiment, the Cu (conductor) plate is used in the thermal cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling from the ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or less and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　なお、低熱伸縮性金属板ではない中間金属板（Ｃｕ）１９がセラミック基板２１ａ，２１ｂから剥離しない。その理由は、熱膨張差によってセラミックとＣｕとの界面に発生する熱応力が、上部のセラミック基板２１ａとの界面と、下部のセラミック基板２１ｂとの界面に二分され、各界面発生する熱応力が半減したためである。 Note that the intermediate metal plate (Cu) 19 that is not the low heat stretchable metal plate does not peel from the ceramic substrates 21a and 21b. The reason is that the thermal stress generated at the interface between the ceramic and Cu due to the difference in thermal expansion is divided into the interface between the upper ceramic substrate 21a and the lower ceramic substrate 21b, and the thermal stress generated at each interface is This is because it has been halved.
　このようにして、本発明の第５実施形態では、ＳｉＮ等のセラミック基板２１ａ，２１ｂの片面に低熱伸縮性金属板としてのＣＭＣクラッド金属板を貼り付け、更に、各セラミック基板２１ａ，２１ｂの間に中間金属板１９を設ける。これにより、多層セラミック絶縁基板３００を構成した。比較例に係わる絶縁基板と対比して、繰り返しの温度変化によりＣｕ（導体）板がセラミック基板から剥離するというトラブルの発生を回避することが可能となる。 Thus, in the fifth embodiment of the present invention, a CMC clad metal plate as a low heat stretchable metal plate is attached to one surface of ceramic substrates 21a, 21b such as SiN, and further, between the ceramic substrates 21a, 21b. An intermediate metal plate 19 is provided. Thus, the multilayer ceramic insulating substrate 300 was configured. In contrast to the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the ceramic substrate due to repeated temperature changes.
　第５実施形態に係る多層セラミック絶縁基板３００と、第４実施形態の多層セラミック絶縁基板２００の構造を対比すると、第５実施形態では、中間金属板１９がＣｕ単板であり、且つ、多層セラミック絶縁基板３００全体の厚みが薄く、且つ、良伝導性のＣｕの厚みが厚い、という特徴を有している。従って、第５実施形態に係る多層セラミック絶縁基板３００は、多層セラミック絶縁基板２００に対してコスト的に廉価とすることができ、更に、厚み方向の熱伝導を良好にできるという利点がある。 When the structure of the multilayer ceramic insulating substrate 300 according to the fifth embodiment is compared with the structure of the multilayer ceramic insulating substrate 200 according to the fourth embodiment, in the fifth embodiment, the intermediate metal plate 19 is a Cu single plate, and the multilayer ceramic substrate The insulating substrate 300 has a thin thickness and a good conductive Cu thickness. Therefore, the multilayer ceramic insulating substrate 300 according to the fifth embodiment is advantageous in that it can be made cheaper than the multilayer ceramic insulating substrate 200 and the heat conduction in the thickness direction can be improved.
　セラミック基板２１ａにビア窓１７を開口し、ビア窓１７に例えばＣｕ等のビア窓金属板１８を埋設する。これにより、ビア窓金属板１８を介して、低熱伸縮性金属板１２ａ-1と中間金属板１９とを電気的に接続することが可能となる。なお、セラミック基板２１ａ、２１ｂの例としてＳｉＮを示したが、第２実施形態で例示した材料は全て使用し得る。 A via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 such as Cu is embedded in the via window 17. As a result, the low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 can be electrically connected via the via window metal plate 18. Although SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used.
［第６実施形態に係るパワー半導体装置と絶縁基板の接合構造体の説明］
　次に、図４を参照して、第６実施形態に係るパワー半導体装置と絶縁基板の接合構造体４００（以下、「接合構造体４００」と略す）について説明する。第６乃至第８実施形態で説明するパワー半導体装置４１として、ＳｉＣ（炭化珪素）パワー素子を使用する例を示す。しかし、パワー半導体装置４１は、ＧａＮ（窒化ガリウム）素子、ダイヤモンド素子、ＺｎＯ（酸化亜鉛）素子等の他のワイドバンドギャップ半導体素子や高温用途を目的としたＳｉ半導体素子（ＳＯＩ素子やセンサ素子）等であってもよい。更に、パワー半導体装置と類似の機械的熱的性質を有するセラミック製の素子、具体的には、セラミックチップコンデンサやセラミックサーミスタ等の受動素子や機能素子を適用することもできる。 [Description of Bonded Structure of Power Semiconductor Device and Insulating Substrate According to Sixth Embodiment]
Next, with reference to FIG. 4, a power semiconductor device / insulated substrate bonded structure 400 (hereinafter, abbreviated as “bonded structure 400”) according to a sixth embodiment will be described. An example in which a SiC (silicon carbide) power element is used as the power semiconductor device 41 described in the sixth to eighth embodiments will be described. However, the power semiconductor device 41 includes other wide band gap semiconductor elements such as GaN (gallium nitride) elements, diamond elements, ZnO (zinc oxide) elements, and Si semiconductor elements (SOI elements and sensor elements) for high-temperature applications. Etc. Further, ceramic elements having mechanical and thermal properties similar to those of the power semiconductor device, specifically, passive elements and functional elements such as ceramic chip capacitors and ceramic thermistors can be applied.
　第６実施形態に係る接合構造体４００は、図４に示すように、耐熱はんだ層４２により接合された絶縁基板１０１及びパワー半導体装置４１を備える。なお、絶縁基板１０１は、図１に示した絶縁基板１００と同一の構造であるので、同一符号を付して詳細な構成説明を省略する。 The joint structure 400 according to the sixth embodiment includes an insulating substrate 101 and a power semiconductor device 41 joined by a heat-resistant solder layer 42 as shown in FIG. Since the insulating substrate 101 has the same structure as that of the insulating substrate 100 shown in FIG. 1, the same reference numerals are given and detailed description of the structure is omitted.
　また、図４は、絶縁基板１０１が第１実施形態で示したＳｉＮセラミック基板２１とＣＩＣクラッド金属板１２-1、１２-2とを備える例を示す。絶縁基板１０１は、第２実施形態で説明した他のセラミック基板や、第３実施形態で説明した他の低熱伸縮性のＣＭＣクラッド金属板を備えていてもよい。 FIG. 4 shows an example in which the insulating substrate 101 includes the SiN ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 shown in the first embodiment. The insulating substrate 101 may include the other ceramic substrate described in the second embodiment and the other low thermal stretchable CMC clad metal plate described in the third embodiment.
　パワー半導体装置４１は、例えば、ＳｉＣを用いたトランジスタ、或いはダイオード等である。また、パワー半導体装置４１の裏面には、Ｎｉシリサイド等のオーミックコンタクト２３が設けられている。オーミックコンタクト２３の下面には、Ｔｉ（チタン）／Ｎｉ（ニッケル）／Ａｇ（銀）等の積層膜からなる実装電極２２が形成されている。 The power semiconductor device 41 is, for example, a transistor using SiC or a diode. An ohmic contact 23 such as Ni silicide is provided on the back surface of the power semiconductor device 41. On the lower surface of the ohmic contact 23, a mounting electrode 22 made of a laminated film of Ti (titanium) / Ni (nickel) / Ag (silver) or the like is formed.
　耐熱はんだ層４２は、低熱伸縮性金属板１２-1と、パワー半導体装置４１を機械的、電気的に接合している。耐熱はんだ層４２は、固相線温度がパワー半導体装置４１の半導体接合温度の最大値Ｔｊmaxより少なくとも３０℃以上高く、液相線温度がＳｉＣパワー半導体装置４１の瞬時耐熱温度４５０℃よりも少なくとも３０℃以上低い金属材料からなる。具体的には、耐熱はんだ層４２は、共晶Ａｕ-Ｇｅはんだ、共晶Ａｕ-Ｓｉはんだ、共晶Ａｕ-Ｓｎはんだ、共晶Ｚｎ-Ａｌはんだ、共晶Ｂｉ-Ａｇはんだ、Ｂｉはんだ、等からなる。なお、耐熱はんだ層４２は、これに限定されるものではなく、共晶組成から大きく逸脱しない範囲で前記はんだ材の亜共晶組成、過共晶組成のものを用いることできる。 The heat-resistant solder layer 42 mechanically and electrically joins the low thermal stretchable metal plate 12-1 and the power semiconductor device 41. The heat-resistant solder layer 42 has a solidus temperature that is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the power semiconductor device 41 and a liquidus temperature that is at least 30 higher than the instantaneous heat-resistant temperature 450 ° C. of the SiC power semiconductor device 41. It is made of a metal material that is lower than ℃ Specifically, the heat-resistant solder layer 42 includes eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, Bi solder, etc. Consists of. The heat-resistant solder layer 42 is not limited to this, and the solder material having a hypoeutectic composition or a hypereutectic composition can be used without departing from the eutectic composition.
　次に、耐熱はんだ層４２として共晶Ａｕ-Ｇｅはんだを用いた場合を例にして、第６実施形態に係る接合構造体４００の製造方法について説明する。 Next, a method for manufacturing the joint structure 400 according to the sixth embodiment will be described using a case where eutectic Au—Ge solder is used as the heat-resistant solder layer 42 as an example.
　始めに、パワー半導体装置４１（チップ）及び絶縁基板１０１をアセトン、イソプロピルアルコール等の有機溶剤で超音波洗浄し、これら部品の表面に付着している汚染物を除去する。共晶Ａｕ-Ｇｅはんだが、ペースト状のものではなく、板状のものである場合には、共晶Ａｕ-Ｇｅはんだも同様にして洗浄する。 First, the power semiconductor device 41 (chip) and the insulating substrate 101 are ultrasonically cleaned with an organic solvent such as acetone or isopropyl alcohol to remove contaminants adhering to the surfaces of these components. When the eutectic Au—Ge solder is not a paste but a plate, the eutectic Au—Ge solder is cleaned in the same manner.
　続いて、減圧リフロー装置のリフロー台に絶縁基板１０１を設置し、低熱伸縮性金属板、即ち、ＣＩＣクラッド金属板１２-1の所定の位置に共晶Ａｕ-Ｇｅはんだを載置する。もし、共晶Ａｕ-Ｇｅはんだがペースト状のものである場合は、シリンジ等を利用してＣＩＣクラッド金属板１２-1の所定の位置に共晶Ａｕ-Ｇｅはんだのペーストを滴下する。そして、共晶Ａｕ-Ｇｅはんだの上にパワー半導体装置４１を置き、静止させる。 Subsequently, the insulating substrate 101 is installed on the reflow stand of the reduced pressure reflow apparatus, and the eutectic Au—Ge solder is placed at a predetermined position of the low heat stretchable metal plate, that is, the CIC clad metal plate 12-1. If the eutectic Au—Ge solder is paste-like, the eutectic Au—Ge solder paste is dropped onto a predetermined position of the CIC clad metal plate 12-1 using a syringe or the like. Then, the power semiconductor device 41 is placed on the eutectic Au—Ge solder and is stationary.
　ここで、絶縁基板１０１の接合させるべき位置に共晶Ａｕ-Ｇｅはんだと半導体素子を正確に載置し、リフロープロセス中のパワー半導体装置４１の位置ずれを防止するために、テンプレート式カーボン治具を使用することが望ましい。 Here, in order to accurately place the eutectic Au—Ge solder and the semiconductor element at the position to be bonded to the insulating substrate 101 and prevent the position of the power semiconductor device 41 during the reflow process, a template-type carbon jig is used. It is desirable to use
　上記準備が終了したならば、リフロー工程を実行する。初めに、減圧リフロー装置の扉を閉め、試料室の排気を行う。試料室内の圧力が５ミリバール以下になったら、不活性ガスを導入する。この操作を数回行い、試料室内の空気を不活性ガスで置換する。これにより、試料室は不活性ガスで充満することになる。 When the above preparation is completed, the reflow process is executed. First, the door of the vacuum reflow device is closed and the sample chamber is evacuated. When the pressure in the sample chamber becomes 5 mbar or less, an inert gas is introduced. This operation is performed several times to replace the air in the sample chamber with an inert gas. As a result, the sample chamber is filled with the inert gas.
　そして、リフロー台或いは試料室全体を加熱して、上記材料の温度を概ね２００℃に昇温し、約２分間この温度を保持する。このとき、蟻酸蒸気を含む不活性ガスを導入して汚染有機物の除去を促進してもよい。 Then, the reflow table or the entire sample chamber is heated to raise the temperature of the material to approximately 200 ° C., and this temperature is maintained for about 2 minutes. At this time, an inert gas containing formic acid vapor may be introduced to promote removal of contaminating organic substances.
　その後、不活性ガスの導入を停止し、排気を再開して試料室を５ミリバール以下に減圧する。リフロー台（または試料室全体）を更に加熱して、絶縁基板１０１とＡｕ-Ｇｅはんだ４２とパワー半導体装置４１をリフロー温度４１０℃まで昇温させ、リフローさせる。保持時間は約１分である。 After that, the introduction of inert gas is stopped, the exhaust is resumed, and the sample chamber is decompressed to 5 mbar or less. The reflow table (or the entire sample chamber) is further heated to raise the temperature of the insulating substrate 101, the Au—Ge solder 42, and the power semiconductor device 41 to a reflow temperature of 410 ° C. and reflow. The holding time is about 1 minute.
　リフローが終了したら、試料室に不活性ガスを導入し降温を開始する。チャンバ内部の温度が十分低い温度まで下がったところで、完成品、即ち、本実施形態に係る接合構造体４００をリフロー装置から取り出す。 When the reflow is completed, an inert gas is introduced into the sample chamber and temperature reduction is started. When the temperature inside the chamber is lowered to a sufficiently low temperature, the finished product, that is, the joint structure 400 according to the present embodiment is taken out from the reflow apparatus.
　なお、Ａｕ-Ｇｅ以外のはんだを用いるときも上記製造プロセスとほぼ同じである。変更するのは、ほとんどの場合リフロー温度とその保持時間のみで良い。 In addition, when using solder other than Au-Ge, the manufacturing process is almost the same. In most cases, only the reflow temperature and its holding time need be changed.
　発明者らは、上記の方法を用いて接合構造体４００のサンプルを作製し、Ｔｊ＝－４０℃～２５０℃（ΔＴｊ＝２９０℃）の冷熱サイクル試験を行った。サイクル数は自動車等の比較的酷環境利用される電子部品に適用される３０００サイクルとした。パワー半導体装置４１のチップサイズは縦２ｍｍ、横２ｍｍ、厚み０．３ｍｍとした。比較例として、ＣＩＣクラッド金属板代わりに無酸素Ｃｕ単体を用いた絶縁基板を備える接合構造体（はんだ層はＡｕ－Ｇｅ）のサンプルを作製し、上記と同様の冷熱サイクル試験を行った。 The inventors prepared a sample of the bonded structure 400 using the above method, and performed a thermal cycle test at Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.). The number of cycles was set to 3000 cycles applied to electronic parts that are used in relatively harsh environments such as automobiles. The chip size of the power semiconductor device 41 was 2 mm in length, 2 mm in width, and 0.3 mm in thickness. As a comparative example, a sample of a joined structure (solder layer is Au—Ge) including an insulating substrate using oxygen-free Cu alone instead of a CIC clad metal plate was produced, and a thermal cycle test similar to the above was performed.
　図５は、Ｔｊ＝－４０℃～２５０℃（ΔＴｊ＝２９０℃）の冷熱サイクル試験の結果を示す図である。図５では、接合の強さ（せん断強度）をサイクル数の関数としてプロットしている。比較例に係わる接合構造体のサンプルでは、前述したように、サイクル数の増加に伴ってせん断強度が急速に劣化していることが理解される。これが比較例が抱える課題であった。なお、比較例における接合の強さは、無酸素Ｃｕ単体とパワー半導体装置との接合強度を示す。 FIG. 5 is a diagram showing the results of a thermal cycle test at Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.). In FIG. 5, the bond strength (shear strength) is plotted as a function of cycle number. As described above, in the sample of the bonded structure according to the comparative example, it is understood that the shear strength rapidly deteriorates as the number of cycles increases. This was the problem of the comparative example. Note that the bonding strength in the comparative example indicates the bonding strength between the oxygen-free Cu simple substance and the power semiconductor device.
　これに対し、本実施形態に係る接合構造体４００のサンプルでは、サイクル数が増加しても、せん断強度の劣化速度は緩やかである。プロットの減少傾向を最小２乗法で直線近似することにより、電子部品のせん断強度に関するＩＥＣ６０７４９－１９規格まで低下するサイクル数を予測した。その結果、約９０００サイクルという結果が得られた。比較的過酷な環境下で用いられる電子部品に、経験的に必要とされるサイクル寿命の目安は３０００サイクルである。よって、本実施形態に係る接合構造体４００は、この目安となる寿命の３倍程度となっている。なお、本実施形態における接合の強さは、ＣＩＣクラッド金属板のＣｕ板とパワー半導体装置との接合強度を示す。 On the other hand, in the sample of the bonded structure 400 according to the present embodiment, the deterioration rate of the shear strength is moderate even if the number of cycles is increased. By approximating the decreasing tendency of the plot to a straight line by the method of least squares, the number of cycles decreasing to the IEC60749-19 standard regarding the shear strength of the electronic component was predicted. As a result, a result of about 9000 cycles was obtained. The standard of the cycle life required empirically for an electronic component used in a relatively harsh environment is 3000 cycles. Therefore, the joint structure 400 according to the present embodiment has a life that is about three times as long as this guideline. The bonding strength in the present embodiment indicates the bonding strength between the Cu plate of the CIC clad metal plate and the power semiconductor device.
　上記の試験結果から明らかなように、第６実施形態では、第１～第５実施形態に示した絶縁基板１０１の低熱伸縮性金属板１２-1の上にパワー半導体装置チップを接合させることにより接合構造体４００を構成する。これにより、パワー半導体装置４１と絶縁基板１０１との間の接合強度の急速な劣化を抑制し、サイクル寿命を大幅に延ばすことが可能となる。 As is apparent from the above test results, in the sixth embodiment, a power semiconductor device chip is bonded onto the low thermal stretchable metal plate 12-1 of the insulating substrate 101 shown in the first to fifth embodiments. The bonded structure 400 is configured. As a result, rapid deterioration of the bonding strength between the power semiconductor device 41 and the insulating substrate 101 can be suppressed, and the cycle life can be greatly extended.
　絶縁基板１０１とパワー半導体装置４１を、耐熱はんだ層４２を用いて接合する。これにより、温度変化が繰り返された場合でも、耐熱はんだ層４２が劣化して剥離するという問題を解消することができる。 The insulating substrate 101 and the power semiconductor device 41 are joined using the heat-resistant solder layer 42. Thereby, even when a temperature change is repeated, the problem that the heat-resistant solder layer 42 deteriorates and peels can be solved.
　パワー半導体装置４１を、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンド（Ｃ）、及び酸化亜鉛（ＺｎＯ）からなる群より選ばれる１つの半導体材料を用いる。これにより、オン抵抗を低くでき、ひいてはスイッチイング速度を高速化することができる。 For the power semiconductor device 41, one semiconductor material selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), diamond (C), and zinc oxide (ZnO) is used. As a result, the on-resistance can be lowered, and consequently the switching speed can be increased.
　なお、本実施形態に係る接合構造体４００では、第１～第３実施形態に示した絶縁基板１０１を適用する例について説明したが、第４，第５実施形態に係る多層セラミック絶縁基板を採用しても良い。 In the bonding structure 400 according to the present embodiment, the example in which the insulating substrate 101 shown in the first to third embodiments is applied has been described. However, the multilayer ceramic insulating substrate according to the fourth and fifth embodiments is employed. You may do it.
［第７実施形態に係るパワー半導体モジュールの説明］
　次に、本発明の第７実施形態に係るパワー半導体モジュールについて説明する。図６は、第７実施形態に係るパワー半導体モジュール５００の構成を示し、図６（ａ）は平面図、（ｂ）は断面図を示している。図６（ａ），（ｂ）に示すように、本実施形態に係るパワー半導体モジュール５００は、図４に示したパワー半導体装置４１と絶縁基板１００の接合構造体４００と、接合構造体４００の下面に耐熱はんだ６０により接合された金属製放熱板５０と、金属製放熱板５０の下面に設けられた水冷冷却器７０とを備える。 [Description of Power Semiconductor Module According to Seventh Embodiment]
Next, a power semiconductor module according to a seventh embodiment of the invention will be described. FIG. 6 shows a configuration of a power semiconductor module 500 according to the seventh embodiment, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view. As shown in FIGS. 6A and 6B, the power semiconductor module 500 according to this embodiment includes a bonded structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in FIG. The metal heat sink 50 joined to the lower surface with the heat-resistant solder 60, and the water cooling cooler 70 provided in the lower surface of the metal heat sink 50 are provided.
　絶縁基板１００の上面には、耐熱はんだ層４２を介してパワー半導体装置４１が設けられている。絶縁基板１００の下面には、金属製放熱板５０及び水冷冷却器７０が設けられている。図６に示すように、金属製放熱板５０（５４）は、積層方向から平面視した際に、絶縁基板１００（２１）よりも面積が大きく構成されている。 A power semiconductor device 41 is provided on the upper surface of the insulating substrate 100 via a heat-resistant solder layer 42. A metal heat sink 50 and a water-cooled cooler 70 are provided on the lower surface of the insulating substrate 100. As shown in FIG. 6, the metal heat sink 50 (54) is configured to have a larger area than the insulating substrate 100 (21) when viewed in plan from the stacking direction.
　金属製放熱板５０は、Ｍｏ層５２の両面にＣｕ層５４，５６が積層されて構成される。１対のＣｕ層５４，５６の間にＭｏ層５２が配置されている。そして、金属製放熱板５０は、ネジ９０により水冷冷却器７０に固定されている。また、低熱伸縮性金属板１２-1と、パワー半導体装置４１は、アルミワイヤ２９により電気的に接続されている。 The metal heat sink 50 is configured by stacking Cu layers 54 and 56 on both sides of the Mo layer 52. The Mo layer 52 is disposed between the pair of Cu layers 54 and 56. The metal heat sink 50 is fixed to the water-cooled cooler 70 with screws 90. The low heat stretchable metal plate 12-1 and the power semiconductor device 41 are electrically connected by an aluminum wire 29.
　冷却水７２は水冷冷却器７０の入口７０ａから供給され、出口７０ｂから排出される。これにより、金属製放熱板５０は冷却され、パワー半導体装置４１で発生する熱を放出することが可能となる。 The cooling water 72 is supplied from the inlet 70a of the water-cooled cooler 70 and discharged from the outlet 70b. As a result, the metal heat sink 50 is cooled, and the heat generated in the power semiconductor device 41 can be released.
　こうして、第７実施形態に係るパワー半導体モジュール５００では、第４実施形態で示したパワー半導体装置４１と絶縁基板１００の接合構造体４００を用いている。これにより、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、パワー半導体モジュール５００を作動させると非常に少ないサイクルで故障してしまうという問題を解決することができる。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られる。 Thus, in the power semiconductor module 500 according to the seventh embodiment, the joint structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in the fourth embodiment is used. As a result, it is possible to solve the problem that if the power semiconductor module 500 is operated in a cooling cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj), the power semiconductor module 500 fails in a very few cycles. Specifically, high reliability is obtained at the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
［第８実施形態に係るパワー半導体モジュールの説明］
　図７は、第８実施形態に係るパワー半導体モジュール６００の断面図である。パワー半導体モジュール６００は、図４で示した第４実施形態に係るパワー半導体装置と絶縁基板の接合構造体４００と、冷却フィン７１とを備える。図７に示す絶縁基板１００は、ＳｉＮ等のセラミック基板２１と、セラミック基板２１の両面に貼り付けられた低熱伸縮性金属板１２-1，１２-2とを有する。パワー半導体装置４１は、例えば、ＳｉＣパワー半導体装置である。パワー半導体装置４１は、耐熱はんだ層４２により低熱伸縮性金属板１２-1に接続されている。パワー半導体装置４１と低熱伸縮性金属板１２-1の間は、アルミワイヤ２９により電気的に接続されている。 [Description of Power Semiconductor Module According to Eighth Embodiment]
FIG. 7 is a cross-sectional view of a power semiconductor module 600 according to the eighth embodiment. The power semiconductor module 600 includes a power semiconductor device according to the fourth embodiment shown in FIG. 4, a bonded structure 400 of an insulating substrate, and cooling fins 71. The insulating substrate 100 shown in FIG. 7 includes a ceramic substrate 21 such as SiN, and low heat stretchable metal plates 12-1 and 12-2 attached to both surfaces of the ceramic substrate 21. The power semiconductor device 41 is, for example, a SiC power semiconductor device. The power semiconductor device 41 is connected to the low heat stretchable metal plate 12-1 by a heat resistant solder layer. The power semiconductor device 41 and the low thermal stretchable metal plate 12-1 are electrically connected by an aluminum wire 29.
　低熱伸縮性金属板１２-2の下面には、耐熱はんだ層６０を介して、Ｃｕ製、或いはアルミ製の冷却フィン７１が設けられている。冷却フィン７１の少なくとも上面には、図示省略のＮｉめっきが施されている。 On the lower surface of the low heat stretchable metal plate 12-2, cooling fins 71 made of Cu or aluminum are provided via a heat-resistant solder layer 60. Ni plating (not shown) is applied to at least the upper surface of the cooling fin 71.
　耐熱はんだ層６０の材料としては、固相線温度がＳｉＣパワー半導体装置４１の半導体接合温度の最大値Ｔｊmaxより少なくとも３０℃以上高く、液相線温度が耐熱はんだ層６０の液相線温度よりも少なくとも３０℃以上低いはんだ材料が選択される。前記したはんだ材料として、例えば、共晶Ａｕ-Ｇｅはんだ、共晶Ａｕ-Ｓｉはんだ、共晶Ａｕ-Ｓｎはんだ、共晶Ｚｎ-Ａｌはんだ、共晶Ｂｉ-Ａｇはんだ、Ｂｉはんだを挙げることができる。なお、耐熱はんだ層６０の材料は、これらに限定されるものではない。仮に、耐熱はんだ層４２が共晶Ａｕ-Ｇｅはんだである場合には、耐熱はんだ層６０としては、共晶Ａｕ-Ｓｎはんだ、或いは、共晶Ｂｉ-Ａｇはんだ、Ｂｉはんだが適している。 As a material of the heat resistant solder layer 60, the solidus temperature is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the SiC power semiconductor device 41, and the liquidus temperature is higher than the liquidus temperature of the heat resistant solder layer 60. A solder material that is at least 30 ° C. lower is selected. Examples of the solder material described above include eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, and Bi solder. . The material of the heat resistant solder layer 60 is not limited to these. If the heat-resistant solder layer 42 is eutectic Au—Ge solder, the eutectic Au—Sn solder, eutectic Bi—Ag solder, or Bi solder is suitable as the heat resistant solder layer 60.
　従って、繰り返して生じる温度変化により耐熱はんだ層６０が劣化することを防止でき、低熱伸縮性金属板１２-2が剥離することを防止できる。なお、冷却フィン７１には、図示省略の小型空冷ファンが接続され、放熱の効率を向上させている。 Therefore, it is possible to prevent the heat-resistant solder layer 60 from deteriorating due to repeated temperature changes, and to prevent the low heat stretchable metal plate 12-2 from peeling off. Note that a small air cooling fan (not shown) is connected to the cooling fin 71 to improve the heat radiation efficiency.
　図７の構成から明らかなように、第８実施形態に係るパワー半導体モジュール６００は、第４実施形態で示したパワー半導体装置４１と絶縁基板１００の接合構造体４００を用いている。これにより、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、パワー半導体モジュール６００を作動させると非常に少ないサイクルで故障してしまうという問題を解決することができる。具体的には、半導体接合温度の最大値Ｔｊmax＝３００℃以下、温度範囲Ｔｊ＝－４０℃～３００℃（ΔＴｊ＝３４０℃）で高い信頼性が得られる。 As is clear from the configuration of FIG. 7, the power semiconductor module 600 according to the eighth embodiment uses the joint structure 400 of the power semiconductor device 41 and the insulating substrate 100 described in the fourth embodiment. As a result, it is possible to solve the problem that if the power semiconductor module 600 is operated in a cooling cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj), the power semiconductor module 600 will fail in very few cycles. Specifically, high reliability is obtained at the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).
　第８実施形態に係るパワー半導体モジュール６００は、放熱板にねじ留め機構を備えないので、積層方向から見たパワー半導体モジュール６００の大きさを大幅に縮小できる。本実施形態では、接合構造体４００が冷却フィン７１に直結しているので、放熱板を省略することができる。即ち、本発明の第８実施形態では、装置の小型化と重量の軽量化を達成することが可能である。その結果、モジュールのコストダウンを図ることが可能となる。 Since the power semiconductor module 600 according to the eighth embodiment does not include the screwing mechanism on the heat sink, the size of the power semiconductor module 600 viewed from the stacking direction can be greatly reduced. In this embodiment, since the joining structure 400 is directly connected to the cooling fin 71, the heat sink can be omitted. That is, in the eighth embodiment of the present invention, it is possible to reduce the size and weight of the device. As a result, it is possible to reduce the cost of the module.
　なお、第８実施形態では、上述した第１～第３実施形態に示した絶縁基板１００を適用する例について説明したが、第４，第５実施形態に示した多層セラミック絶縁基板２００、３００を適用することも可能である。 In the eighth embodiment, the example in which the insulating substrate 100 shown in the first to third embodiments is applied has been described. However, the multilayer ceramic insulating substrates 200 and 300 shown in the fourth and fifth embodiments are used. It is also possible to apply.
　以上、実施形態に係わる絶縁基板、多層セラミック絶縁基板、パワー半導体装置と絶縁基板の接合構造体、及びパワー半導体モジュールを説明したが、本発明はこれに限定されるものではなく、各部の構成は、同様の機能を有する任意の構成のものに置き換えることができる。 As described above, the insulating substrate, the multilayer ceramic insulating substrate, the joined structure of the power semiconductor device and the insulating substrate, and the power semiconductor module according to the embodiment have been described, but the present invention is not limited to this, and the configuration of each part is , Can be replaced with any configuration having the same function.
　特願２０１２－１８４４６０号（出願日：２０１２年８月２３日）の全内容は、ここに援用される。 The entire contents of Japanese Patent Application No. 2012-184460 (filing date: August 23, 2012) are incorporated herein by reference.
　以上、実施例に沿って本発明の内容を説明したが、本発明はこれらの記載に限定されるものではなく、種々の変形及び改良が可能であることは、当業者には自明である。 As mentioned above, although the content of the present invention has been described according to the embodiments, the present invention is not limited to these descriptions, and it is obvious to those skilled in the art that various modifications and improvements are possible.
　本発明の実施形態によれば、高い半導体接合温度（Ｔｊ）、且つ広い温度範囲（ΔＴｊ）の冷熱サイクルにおいて、信頼性の高い絶縁基板を実現することができる。その結果、Ｃｕ板の片方或いは双方がセラミック基板から剥離するという故障の発生を回避することができる。本発明の実施形態は、温度サイクルに耐えることが可能なパワー半導体モジュールに利用することができる。 According to the embodiment of the present invention, a highly reliable insulating substrate can be realized in a cooling / heating cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). As a result, it is possible to avoid the occurrence of a failure in which one or both of the Cu plates are separated from the ceramic substrate. Embodiment of this invention can be utilized for the power semiconductor module which can endure a temperature cycle.
　１２（１２ａ，１２ｂ）　低熱伸縮性金属板（ＣＩＣクラッド金属板）
　１３　インバー合金板（低熱膨張金属板）
　１４，１５　Ｃｕ板
　１７　ビア窓
　１８　ビア窓金属板
　１９　中間金属板
　２１（２１ａ，２１ｂ）　セラミック基板
　４１　パワー半導体装置
　５０　金属製放熱板
　７０　水冷冷却器
　７１　冷却フィン
　９０　ネジ
　１００　絶縁基板
　２００，３００　多層セラミック絶縁基板
　４００　パワー半導体装置と絶縁基板の接合構造体
　５００，６００　パワー半導体モジュール 12 (12a, 12b) Low heat stretchable metal plate (CIC clad metal plate)
13 Invar alloy plate (low thermal expansion metal plate)
14, 15 Cu plate 17 Via window 18 Via window metal plate 19 Intermediate metal plate 21 (21a, 21b) Ceramic substrate 41 Power semiconductor device 50 Metal heat sink 70 Water-cooled cooler 71 Cooling fin 90 Screw 100 Insulating substrate 200, 300 Multi-layer Ceramic insulating substrate 400 Joining structure of power semiconductor device and insulating substrate 500,600 Power semiconductor module

Claims (16)

  1. 　セラミック基板と、
    　前記セラミック基板の少なくとも一方の面に貼り付けられた低熱伸縮性金属板と、を有し、
    　前記低熱伸縮性金属板は、
    　厚みがほぼ等しい一対のＣｕ板と、
    　前記一対のＣｕ板の間に設けられた、前記Ｃｕ板よりも熱膨張係数が低い低熱膨張金属板と、を備える
    ことを特徴とする絶縁基板。     A ceramic substrate;
    A low thermal stretchable metal plate affixed to at least one surface of the ceramic substrate,
    The low heat stretchable metal plate is
    A pair of Cu plates having substantially the same thickness;
    An insulating substrate comprising: a low thermal expansion metal plate provided between the pair of Cu plates and having a thermal expansion coefficient lower than that of the Cu plate.
  2. 　前記セラミック基板の厚みは、０．１ｍｍ以上２ｍｍ以下であることを特徴とする請求項１に記載の絶縁基板。 The insulating substrate according to claim 1, wherein the thickness of the ceramic substrate is 0.1 mm or more and 2 mm or less.
  3. 　前記セラミック基板は、窒化珪素、アルミナ、窒化アルミニウム、ベリリアからなる群より選ばれる１つの材料からなることを特徴とする請求項１または請求項２のいずれかに記載の絶縁基板。 3. The insulating substrate according to claim 1, wherein the ceramic substrate is made of one material selected from the group consisting of silicon nitride, alumina, aluminum nitride, and beryllia.
  4. 　前記Ｃｕ板の厚みは、５μｍ以上であることを特徴とする請求項１～請求項３のいずれか１項に記載の絶縁基板。 The insulating substrate according to any one of claims 1 to 3, wherein the Cu plate has a thickness of 5 袖 m or more.
  5. 　前記一対のＣｕ板のそれぞれの１枚の厚さは、前記低熱膨張金属板の厚さの１／２以下であることを特徴とする請求項１記載の絶縁基板。 The insulating substrate according to claim 1, wherein the thickness of each of the pair of Cu plates is ½ or less of the thickness of the low thermal expansion metal plate.
  6. 　前記低熱膨張金属板は、インバー、モリブデン、スーパーインバー、ステンレスインバーからなる群より選ばれる１つの材料であることを特徴とする請求項１～請求項５のいずれか１項に記載の絶縁基板。 The insulating substrate according to any one of claims 1 to 5, wherein the low thermal expansion metal plate is one material selected from the group consisting of invar, molybdenum, super invar, and stainless invar.
  7. 　前記一対のＣｕ板と前記低熱膨張金属板とは、金属学的方法で接合されていることを特徴とする請求項１～請求項６のいずれか１項に記載の絶縁基板。 The insulating substrate according to any one of claims 1 to 6, wherein the pair of Cu plates and the low thermal expansion metal plate are joined by a metallurgical method.
  8. 　請求項１～請求項７のいずれか１項に記載した絶縁基板を、複数接合させて成ることを特徴とする多層セラミック絶縁基板。 A multilayer ceramic insulating substrate comprising a plurality of the insulating substrates according to any one of claims 1 to 7 joined together.
  9. 　厚みがほぼ等しい複数のセラミック基板と、
    　前記複数のセラミック基板の間に配置された中間金属板と、
    　最上部及び最下部に位置するセラミック基板の外面にそれぞれ貼り付けられた低熱伸縮性金属板と、を有し、
    　前記低熱伸縮性金属板は、
    　厚みがほぼ等しい一対のＣｕ板と、
    　前記一対のＣｕ板の間に設けられた、前記Ｃｕ板よりも熱膨張係数が低い低熱膨張金属板と、を備える
    ことを特徴とする多層セラミック絶縁基板。     A plurality of ceramic substrates having substantially the same thickness;
    An intermediate metal plate disposed between the plurality of ceramic substrates;
    Low heat stretchable metal plates each affixed to the outer surface of the ceramic substrate located at the top and bottom,
    The low heat stretchable metal plate is
    A pair of Cu plates having substantially the same thickness;
    A multilayer ceramic insulating substrate comprising: a low thermal expansion metal plate having a lower thermal expansion coefficient than the Cu plate, which is provided between the pair of Cu plates.
  10. 　少なくとも一つの前記セラミック基板の両面にそれぞれ配設された低熱伸縮性金属板と中間金属板、或いは、一対の中間金属板とが、前記セラミック基板の両面を貫通するビア窓に埋設されたビア窓金属板を介して電気的に接続されていることを特徴とする請求項９に記載の多層セラミック絶縁基板。 Via window in which a low heat stretchable metal plate and an intermediate metal plate or a pair of intermediate metal plates respectively disposed on both surfaces of at least one ceramic substrate are embedded in via windows penetrating both surfaces of the ceramic substrate The multilayer ceramic insulating substrate according to claim 9, wherein the multilayer ceramic insulating substrate is electrically connected via a metal plate.
  11. 　請求項１～請求項７のいずれか１項に記載の絶縁基板と、
    　パワー半導体装置と、
    　前記絶縁基板と前記パワー半導体装置との間を接合する耐熱はんだ層と、
    を備えることを特徴とするパワー半導体装置と絶縁基板の接合構造体。     An insulating substrate according to any one of claims 1 to 7,
    A power semiconductor device;
    A heat resistant solder layer for bonding between the insulating substrate and the power semiconductor device;
    A bonded structure of a power semiconductor device and an insulating substrate, comprising:
  12. 　前記パワー半導体装置は、炭化珪素、窒化ガリウム、ダイヤモンド、酸化亜鉛からなる群より選ばれる少なくとも１つのワイドバンドギャップ半導体からなることを特徴とする請求項１１に記載のパワー半導体装置と絶縁基板の接合構造体。 12. The power semiconductor device according to claim 11, wherein the power semiconductor device is made of at least one wide band gap semiconductor selected from the group consisting of silicon carbide, gallium nitride, diamond, and zinc oxide. Structure.
  13. 　前記耐熱はんだ層のはんだは、その固相線温度が前記パワー半導体装置の最大使用温度Ｔｊmaxよりも少なくとも３０℃以上高く、且つ、その液相線温度が前記パワー半導体装置の瞬時耐熱温度よりも少なくとも３０℃以上低い金属材料からなることを特徴とする請求項１１または請求項１２のいずれかに記載のパワー半導体装置と絶縁基板の接合構造体。 The solder of the heat resistant solder layer has a solidus temperature at least 30 ° C. higher than the maximum operating temperature Tjmax of the power semiconductor device, and a liquidus temperature of at least the instantaneous heat resistant temperature of the power semiconductor device. The power semiconductor device and the insulating substrate bonded structure according to claim 11, wherein the power semiconductor device is made of a metal material having a temperature lower by 30 ° C. or more.
  14. 　前記耐熱はんだ層のはんだは、共晶Ａｕ-Ｇｅはんだ、共晶Ａｕ-Ｓｉはんだ、共晶Ａｕ-Ｓｎはんだ、共晶Ｚｎ-Ａｌはんだ、共晶Ｂｉ-Ａｇはんだ、Ｂｉはんだからなる群より選ばれるはんだであることを特徴とする請求項１１または請求項１２のいずれかに記載のパワー半導体装置と絶縁基板の接合構造体。 The solder of the heat-resistant solder layer is selected from the group consisting of eutectic Au-Ge solder, eutectic Au-Si solder, eutectic Au-Sn solder, eutectic Zn-Al solder, eutectic Bi-Ag solder, Bi solder. The joined structure of the power semiconductor device and the insulating substrate according to claim 11, wherein the solder structure is a solder.
  15. 　請求項１１に記載のパワー半導体装置と絶縁基板の接合構造体と、
    　水冷冷却器と、
    　前記パワー半導体装置と絶縁基板の接合構造体と、前記水冷冷却器との間に配設され、且つ平面視面積が前記パワー半導体装置と絶縁基板の接合構造体より大きい金属製放熱板と、
    　前記パワー半導体装置と絶縁基板の接合構造体と、前記金属製放熱板との間を接合する耐熱はんだと、
    　前記金属製放熱板と前記水冷冷却器との間を固定するネジと、
    を備えることを特徴とするパワー半導体モジュール。     A joined structure of the power semiconductor device according to claim 11 and an insulating substrate,
    A water-cooled cooler,
    A metal heatsink disposed between the power semiconductor device and the insulating substrate and the water-cooled cooler and having a larger area in plan view than the power semiconductor device and insulating substrate.
    A joined structure of the power semiconductor device and the insulating substrate, and a heat-resistant solder that joins between the metal heat sink;
    A screw for fixing between the metal radiator plate and the water-cooled cooler;
    A power semiconductor module comprising:
  16. 　請求項１１に記載のパワー半導体装置と絶縁基板の接合構造体と、
    　空冷冷却フィンと、
    　前記パワー半導体装置と絶縁基板の接合構造体と、前記空冷冷却フィンとの間を接合する耐熱はんだ層と、
    を備えることを特徴とするパワー半導体モジュール。     A joined structure of the power semiconductor device according to claim 11 and an insulating substrate,
    Air cooling fins,
    A joined structure of the power semiconductor device and the insulating substrate, and a heat-resistant solder layer that joins between the air-cooled cooling fins;
    A power semiconductor module comprising:
PCT/JP2013/072234 2012-08-23 2013-08-21 Insulating substrate、multilayer ceramic insulating substrate, joined structure of power semiconductor device and insulating substrate, and power semiconductor module WO2014030659A1 (en)

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