WO2014015637A1

WO2014015637A1 - Display panel and fabrication method therefor, and display device

Info

Publication number: WO2014015637A1
Application number: PCT/CN2012/087239
Authority: WO
Inventors: 林鸿涛; 封宾; 刘家荣
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2012-07-26
Filing date: 2012-12-23
Publication date: 2014-01-30
Also published as: CN102799033A; CN102799033B

Abstract

A display panel comprises an array substrate and a colour filter substrate, the array substrate comprising a plurality of data lines (10), the colour filter substrate comprising a common electrode (13), and the array substrate also comprising a shielding electrode (11) which is disposed above the plurality of data lines (10) and between which and the common electrode (13) an electric field is formed. The display panel can not only eliminate the defect that leakage of light will be generated during side-viewing or pressing, but also further reduce the width of a black matrix, thereby increasing the aperture ratio of a unit pixel.

Description

Display panel, manufacturing method thereof, and display device

Embodiments of the present invention relate to a display panel, a method of fabricating the display panel, and a display device including the display panel. Background technique

With the development of display manufacturing technology, liquid crystal display technology has developed rapidly, and has gradually replaced the traditional picture tube display and become the mainstream of future flat panel displays. In the field of liquid crystal display technology, TFT-LCD (Thin Film Transistor Liquid Crystal Display) is widely used in televisions, computers, etc. due to its large size, high integration, powerful functions, flexible technology, and low cost. Mobile phones and other fields.

Among them, TN (Twisted Nematic) display panel has become the most widely used entry-level liquid crystal display panel due to its low production cost, and is widely used in mainstream low-end display panels on the market.

The display panel is made up of an array substrate (i.e., a TFT substrate) and a color filter substrate (i.e., a CF substrate) assembled and filled with liquid crystal. Generally, the array substrate is formed with a gate line (ie, a scan line), a data line (ie, a signal line), a TFT, a via, and a pixel electrode (ie, a display electrode), wherein the plurality of gate lines and the plurality of gate lines a plurality of pixel units are defined by crossing the data lines, each of the pixel units includes a TFT element (including a gate electrode, a semiconductor layer, a source electrode and a drain electrode) and a pixel electrode; and a black matrix is formed on the color filter substrate ( BM), RGB, and common electrodes.

The pixel electrode in the array substrate cooperates with a gate line, a data line, a TFT, and a via to store an electric charge and form an electric field with a common electrode in the color filter substrate to drive the pixel electrode and the common electrode. The liquid crystal molecules are deflected to display different images. For example, when the gate line performs progressive scanning, the data line sequentially charges the pixel electrode in the pixel unit of the scanned row, and after the scanning ends, the pixel electrode of the row will maintain the charged load until the next frame is scanned again. Time. The voltage of the data line is constantly changing within one frame and is used to charge the pixel electrodes of each row.

As shown in FIG. 1, in order to avoid capacitive coupling between the pixel electrode 8 and the data line 10, the pixel electrode 8 is generally spaced apart from the data line 10, so that between the pixel electrode 8 and the data line 10, An electric field is formed between the common electrode 13 and the data line 10. S/B is a shield bar for avoiding light leakage on both sides of the data line. It can be formed simultaneously with the gate line metal material and the gate line, or can be connected with the storage capacitor line to double as a storage capacitor. Since the data line 10 sequentially charges the pixel electrode 8 of each scanning line, its own voltage constantly changes, resulting in a voltage difference between the electric field between the pixel electrode 8 and the data line 10 and between the common electrode 13 and the data line 10. The voltage difference of the electric field also constantly changes, and the RMS ( Root Mean Square) value of the electric field between the pixel electrode 8 and the data line 10 and the electric field between the common electrode 13 and the data line 10 is in the middle. The state, not the extreme value, causes the liquid crystal molecules above and on both sides of each data line 10 to be effectively deflected. For the display panel of the normally white mode, since the RMS value cannot be at a maximum value, each data is caused. The liquid crystal molecules above and on both sides of the line cannot be deflected to the upright state (relative to the substrate); for the display panel of the normally black mode, since the RMS value cannot be at a minimum value, it will cause the top of each data line and The liquid crystal molecules on both sides cannot be deflected to a horizontal state (relative to the substrate), thus allowing dark state inspection of both the normally white mode display panel and the normally black mode display panel. , Prone to light leakage in a side view or pressed, the formation of bad quality.

In order to overcome the above drawbacks, the prior art generally uses a method of increasing the width of the black matrix in the color filter substrate to avoid or mitigate light leakage, but this method tends to lower the aperture ratio of the unit pixel. SUMMARY OF THE INVENTION A display panel capable of eliminating light leakage defects during side view or pressing, a method of manufacturing the display panel, and a display device including the display panel are provided.

According to an aspect of the present invention, a display panel includes an array substrate and a color filter substrate, the array substrate includes a plurality of data lines, and the color filter substrate includes a common electrode, wherein the array The substrate further includes a shield electrode disposed above the plurality of data lines and forming an electric field with the common electrode.

In one embodiment, the array substrate further includes an insulating layer disposed between the shield electrode and the plurality of data lines.

In one embodiment, the display panel uses a display panel of a normally white mode, and the shield electrode is at a low potential relative to the common electrode; or the display panel uses a display panel of a normally black mode, the shield electrode and The potentials of the common electrodes are equal or not much different. In an embodiment, when the display panel is in the display panel of the normally white mode, the array substrate includes a plurality of the shielding electrodes, and the array substrate further includes a plurality of gate lines, the plurality of gate lines Arranged with the plurality of data lines, each of the shielding electrodes is disposed above the data line between the adjacent two gate lines, and is connected to any one of the adjacent two gate lines.

In an embodiment, when the display panel is configured with a display panel of a normally black mode, the array substrate further includes a plurality of gate lines and a plurality of common electrode lines, the plurality of gate lines and the plurality of data lines a line crossing arrangement, the plurality of common electrode lines are respectively connected to the common electrode, and each common electrode line is disposed in parallel with the plurality of gate lines; the array substrate includes one of the shielding electrodes, the shielding electrode Connected to any one of the plurality of common electrode lines; or, the array substrate includes a plurality of the shield electrodes, each of the shield electrodes being disposed above the data lines between the adjacent two gate lines, and adjacent to A common electrode line is connected; or the array substrate includes a plurality of the shielding electrodes, each of the shielding electrodes is disposed above one of the data lines and connected to any one of the plurality of common electrode lines.

According to another aspect of an embodiment of the present invention, there is provided a display device comprising any of the above display panels.

According to another aspect of the present invention, a method for fabricating a display panel, the method comprising the steps of: fabricating an array substrate and a color filter substrate, the step of fabricating the array substrate includes the steps of forming a plurality of data lines, The step of fabricating the color filter substrate includes the step of forming a common electrode, wherein the step of fabricating the array substrate further includes the step of forming a shield electrode, wherein the shield electrode is located above the plurality of data lines and can be connected to the common electrode An electric field is formed.

In one embodiment, the step of fabricating the array substrate further includes the step of forming an insulating layer between the shield electrode and the plurality of data lines.

In one embodiment, the step of fabricating the array substrate further includes the step of forming a plurality of gate lines, wherein the plurality of gate lines are disposed to intersect the plurality of data lines; in the step of forming the shield electrodes, There are a plurality of shielding electrodes, each of which is located above the data line between the adjacent two gate lines and is connected to any one of the adjacent two gate lines.

In one embodiment, the step of fabricating the array substrate further includes the steps of forming a plurality of gate lines and a plurality of common electrode lines, wherein the plurality of gate lines are disposed across the plurality of data lines, the plurality of The common electrode lines are respectively connected to the common electrode, and each common electrode line is disposed in parallel with the gate line; in the step of forming the shield electrode, the shielding electrode is one, and the shielding electrode and the plurality of common electrode lines are Either connected; or, in the step of forming a shield electrode, the shield electrode is a plurality of shielding electrodes are disposed above the data lines between the adjacent two gate lines and connected to an adjacent one of the common electrode lines; or, in the step of forming the shielding electrodes, the shielding electrodes are plurality of Each shield electrode is located above one of the data lines and connected to any of the plurality of common electrode lines.

In one embodiment, the step of fabricating the array substrate further includes the step of forming a pixel electrode, wherein the shielding electrode and the pixel electrode are completed in the same patterning process, and the shielding electrode and the pixel electrode do not overlap each other; The shielding electrode is the same material as the pixel electrode. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic view showing the working principle of a display panel in the prior art;

2 is a schematic view showing the working principle of the display panel in the first embodiment of the present invention;

3 is a cross-sectional view of the array substrate after the first patterning process is completed in the first embodiment of the present invention;

4a to 4g are schematic views showing stages of the structure of the array substrate in the second patterning process in the first embodiment of the present invention;

5a and 5b are schematic structural views of an array substrate after completing a third patterning process in the first embodiment of the present invention;

6a and 6b are schematic structural views of an array substrate after the fourth patterning process is completed in the first embodiment of the present invention;

FIG. 7 is a schematic flow chart of a method for fabricating an array substrate according to a first embodiment of the present invention.

1 _substrate; 2a - gate electrode; 2b _ gate line; 3 _ gate insulating layer; 4 - ohmic contact layer; 5 - semiconductor layer; 6a - source electrode; 6b - drain electrode; 7 - passivation layer; Pixel electrode; 9-photoresist; 10 - data line; 11 - shield electrode; 12 - liquid crystal molecule; 13 - common electrode; 14 - first via; 15 - second via. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. Obviously, The described embodiments are a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the words "a" or "an" do not denote a quantity limitation, but rather mean that there is at least one. The words "including" or "comprising", etc., are intended to mean that the elements or objects preceding "including" or "comprising" are intended to encompass the elements or Component or object. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationship may also change accordingly.

The display panel includes an array substrate and a color filter substrate. The array substrate includes a plurality of data lines, and the color filter substrate includes a common electrode, wherein the array substrate further includes a shield electrode disposed above the plurality of data lines, and the shield electrode and the common electrode An electric field is formed such that a region of the display panel corresponding to the shield electrode is opaque.

The display device uses the above display panel.

The manufacturing method of the display panel includes the steps of forming an array substrate and a color filter substrate, the step of fabricating the array substrate includes the step of forming a plurality of data lines, and the step of fabricating the color filter substrate includes the step of forming a common electrode, wherein The step of fabricating the array substrate further includes the step of forming a shield electrode, the shield electrode being located above the plurality of data lines and forming an electric field with the common electrode such that a region of the display panel corresponding to the shield electrode is opaque.

First embodiment

In this embodiment, the display panel uses a display panel of a normally white mode, that is, when the display panel does not apply a voltage (there is no electric field between the pixel electrode and the common electrode or forms a weak electric field), the display panel corresponding to the liquid crystal molecule is effective. The display area (the display panel can be generally divided into two parts, that is, the effective display area and the peripheral area); when the voltage is applied (a strong electric field is formed between the pixel electrode and the common electrode), the effective display area of the display panel corresponding to the liquid crystal molecule opaque. In this embodiment, the display panel includes an array substrate and a color filter substrate. The array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines, wherein the plurality of gate lines are disposed to intersect with the plurality of data lines, and each of the common electrode lines is disposed in parallel with the gate lines; The color filter substrate includes a common electrode. The array substrate further includes a shielding electrode disposed above the plurality of data lines, and an electric field is formed between the shielding electrode and the common electrode such that a region of the display panel corresponding to the shielding electrode is opaque. For example, the shield electrode is disposed directly above the plurality of data lines.

In this embodiment, the shield electrode is at a low potential with respect to the common electrode, so that a strong electric field is formed between the shield electrode and the common electrode. Since the display panel in the embodiment uses the display panel of the normally white mode, if the shield electrode is at a low potential relative to the common electrode (the low potential is generally -7ν~-10ν), the shield electrode and the common electrode can be used ( A strong electric field is formed between the potential of the common electrode, generally 5v~7v, and the strong electric field can drive the liquid crystal molecules in the corresponding region of the shielding electrode to remain in an upright state, so that the shielding electrode corresponds to the display panel. The area (ie, the effective display area) is opaque, that is, the shield electrode can be connected to the component at the low potential in the display panel; and the scanning time of the entire display panel displaying one frame of image (eg, the screen refresh rate of the display device is 60 Hz) , the scan time of one frame of image is 17ms), because the gate line corresponding to each row of pixels is only at a high potential during the scan time of the row (the potential difference with the common electrode is not large or no potential difference), and the rest The non-scanning time is at a low potential relative to the common electrode, so connecting the shield electrode to the gate line ensures that the shield electrode is at a large The common electrode is at a low potential for most of the time. Therefore, in this embodiment, for example, the shielding electrode is used in plurality, and each shielding electrode is disposed above the data line between the adjacent two gate lines, and in the adjacent two gate lines Either connected so that the shield electrode is at a low potential.

In this embodiment, the array substrate further includes an insulating layer disposed between the shielding electrode and the plurality of data lines such that the shielding electrode and the plurality of data lines are not electrically connected to each other.

As shown in FIG. 2, since the shield electrode 11 is disposed above the data line 10, the electric field forming the electric field with the pixel electrode 8 and the common electrode 13, respectively, is not the data line 10 but the shield electrode 11, and for the normally white mode display panel A strong electric field is formed between the shield electrode 11 and the common electrode 13, so that liquid crystal molecules located above and on both sides of the shield electrode 11 can be effectively deflected to an upright state (relative to the substrate), and the area of the display panel corresponding to the shield electrode 11 is made. The opaque light also makes the area of the display panel corresponding to the data line 10 opaque, thereby overcoming the defect that the display panel in the prior art is prone to light leakage in the case of side view or pressing. The embodiment further provides a display device including the above display panel.

The embodiment further provides a method for fabricating the above display panel, comprising the steps of fabricating an array substrate and a color filter substrate. The step of fabricating a color filter substrate includes the steps of forming a common electrode; the step of fabricating the array substrate includes the steps of forming a plurality of gate lines, a plurality of data lines, a plurality of common electrode lines, and pixel electrodes, wherein the plurality of a gate line is disposed to intersect with the plurality of data lines, wherein the plurality of common electrode lines are respectively connected to the common electrode, and each of the common electrode lines is disposed in parallel with the gate line, wherein the step of fabricating the array substrate The method further includes the step of forming a shield electrode, wherein the shield electrode is located above the plurality of data lines, and an electric field can be formed with the common electrode such that the region i of the display panel corresponding to the shield electrode is opaque.

For example, in the step of forming the shield electrode, a plurality of shield electrodes are formed, and each shield electrode is located above the data line between the adjacent two gate lines, and the adjacent two gate lines Any one of them is connected such that a strong electric field is formed between the shield electrode and the common electrode, so that the area of the display panel corresponding to the shield electrode is opaque.

For example, the step of fabricating the array substrate may further include the step of forming an insulating layer between the shield electrode and the plurality of data lines such that the shield electrode and the plurality of data lines are not electrically connected to each other.

For example, the shielding electrode and the pixel electrode are completed in the same patterning process, and the shielding electrode and the pixel electrode do not overlap each other; the shielding electrode and the pixel electrode have the same material. Therefore, the method for manufacturing a display panel according to the embodiment of the present invention does not increase the cost, the process, or the material of the multilayer structure of the prior art.

As shown in FIG. 3 to FIG. 7 , the manufacturing method of the display panel in the embodiment includes the following steps: slOl, forming a gate electrode 2a, a gate line 2b, and a dummy gate line on the substrate 1 by a first patterning process (ie, , dummy gate line, not shown in the figure).

For example, as shown in Fig. 3, a gate metal film is deposited on the substrate 1, and then a photoresist is applied thereon, and the photoresist is exposed and developed using a mask. Wherein, the photoresist retention region corresponds to a region where the gate electrode 2a, the gate line 2b and the dummy gate line are formed, and the uncovered gate metal film is etched through the photoresist retention region as a mask, and then passes through the light. The photoresist stripping process peels off the photoresist, thereby forming the gate electrode 2a, the gate line 2b, and the dummy gate line.

Sl02, a gate insulating layer 3, an ohmic contact layer 4, a semiconductor layer 5, a source electrode 6a, a drain electrode 6b, and a data line 10 are formed on the substrate on which the step s101 is completed by a second patterning process. In this step, The gate insulating layer 3, the ohmic contact layer 4, the semiconductor layer 5, the source electrode 6a, the drain electrode 6b, and the data line 10 are patterned in a multi-step etching process (one of the core processes of the slit lithography process) Formed in the process.

For example, the step sl02 includes the following steps:

S102-1, as shown in Fig. 4a, sequentially deposits a gate insulating layer 3, an ohmic contact film 4, a semiconductor thin film 5, and a source/drain metal thin film 6, on the substrate on which the step slO1 is completed.

S102-2, as shown in FIG. 4b, applying a layer of photoresist 9 on the substrate on which step S102-1 is completed, and exposing and developing the photoresist 9 with a halftone mask or a gray tone mask. The thickness of the photoresist directly above the gate electrode 2a is made thinner than the thickness of the photoresist located on both sides of the gate electrode 2a.

Si 02-3, as shown in Fig. 4c, the substrate is subjected to a first etching to complete the step S102-2 to form the ohmic contact layer 4 and the semiconductor layer 5, and the drain metal film 6 is also partially etched.

S102-4, as shown in Fig. 4d, the photoresist on the substrate on which the step S102-3 is completed is subjected to ashing treatment until the middle portion of the drain metal thin film 6 is exposed. Since the thickness of the photoresist directly above the gate electrode 2a is thinner than the thickness of the photoresist on both sides of the gate electrode 2a, when the photoresist is ashed, the photoresist directly above the gate electrode 2a is After being completely ashed, the photoresist on both sides of the gate electrode 2a also retains a certain thickness, so that the portion of the metal thin film 6 is exposed.

S102-5, as shown in Fig. 4e, performs a second etching on the substrate on which step sl02-4 is completed to form source electrode 6a, drain electrode 6b and data line 10.

S102-6, as shown in Fig. 4f, the remaining photoresist (i.e., the photoresist on both sides of the gate electrode 2a) is peeled off by a photoresist stripping process. Figure 4f is a cross-sectional view taken along line A-A in Figure 4g.

Sl03, forming a passivation layer 7, a first via hole 14 and a second via hole 15 through a third patterning process on the substrate on which the step S102 is completed, wherein the first via hole 14 is located above the drain electrode 6b, and the second pass The hole 15 is located above the gate line 2b. It should be noted that the passivation layer 7 is the above-mentioned insulating layer between the shield electrode and the plurality of data lines.

For example, as shown in FIG. 5a and FIG. 5b, a passivation layer film is deposited on the substrate of step S102, and then a layer of photoresist is applied thereon, and the photoresist is exposed and developed with a mask. Wherein, the photoresist retention region corresponds to a region where the passivation layer 7, the first via hole 14 and the second via hole 15 are formed, and then the exposed passivation layer film is etched, and finally the photoresist is After peeling, the passivation layer 7, the first via hole 14, and the second via hole 15 are formed.

Sl04, forming the pixel electrode 8 through the fourth patterning process on the substrate on which the step sl03 is completed The electrode 11 is shielded.

For example, as shown in FIG. 6a and FIG. 6b, a transparent pixel electrode film is deposited on the substrate of step S103, and then a layer of photoresist is applied thereon, and the photoresist is exposed and developed by using a mask. The photoresist retention region corresponds to a region where the pixel electrode 8 and the shield electrode 11 are formed, and the uncovered transparent pixel electrode film is etched by using the photoresist retention region as a mask, and finally The photoresist strip is peeled off, thereby forming the pixel electrode 8 and the shield electrode 11; the pixel electrode 8 is connected to the drain electrode 6b through the first via hole 14, and the shield electrode 11 is connected to the gate line 2b through the second via hole 15 .

As can be seen from FIG. 6a, in the method, the gate electrode 2b of the shield electrode 11 and its adjacent side (the side is defined to the left side) is connected by the second via hole 15, and the dummy gate line formed in the step s101 is located at the leftmost Outside the gate line of the side, the shield electrode is adjacent to the leftmost gate line; if the shield electrode 11 is adjacent to the other side (the side is defined as the right side), the gate line 2b passes through the second pass. If the holes 15 are connected, it is not necessary to form a dummy gate line in the step s101.

Example 2

In this embodiment, the display panel uses a display panel of a normally black mode, that is, when the display panel does not apply a voltage (there is no electric field between the pixel electrode and the common electrode or forms a weak electric field), the display panel corresponding to the liquid crystal molecule is effective. The display area is opaque; when a voltage is applied (a strong electric field is formed between the pixel electrode and the common electrode), the effective display area of the display panel corresponding to the liquid crystal molecules is transparent.

1) In the present embodiment, the difference between the display panel and the display panel of the first embodiment is that the shield electrode in the embodiment is connected to the common electrode line, thereby ensuring that the potential of the shield electrode is equal to the potential of the common electrode.

In the display panel of the embodiment, the display panel of the normally black mode is used, and the shielding electrode and the common electrode are equal in electric potential, so that there is no electric field between the shielding electrode and the common electrode, and the liquid crystal molecules in the corresponding region of the shielding electrode are driven. Keeping tending to be parallel, and arranged in the -45° direction from the common electrode and gradually and uniformly twisted to the horizontal arrangement state of the pixel electrode in the +45° direction (the whole is twisted by 90°) so that the The area of the display panel corresponding to the shielding electrode is opaque, that is, the shielding electrode can be connected to the same potential component of the common electrode in the array substrate; because the plurality of common electrode lines and the color film substrate are common in the array substrate The electrodes are connected by a conductive silver paste or a gold ball in a peripheral region of the display panel, so that the plurality of common electrode lines are equipotential to the common electrode. Therefore, in the embodiment, the shield electrode is connected to the common electrode line, which can ensure Shield electrode and public electricity The pole potentials are equal.

Since each of the common electrode lines is disposed in parallel with the gate lines, each of the data lines is disposed perpendicular to the plurality of common electrode lines, and the shield electrodes are disposed above the plurality of data lines. For example, the shield electrode is disposed directly above the plurality of data lines.

In this embodiment, the shielding electrode may be used in one, and the shielding electrode is connected to any one of the plurality of common electrode lines such that the shielding electrode and the common electrode are equal in potential;

Alternatively, the shielding electrode may also be used in plurality, each shielding electrode is disposed above the data line between two adjacent gate lines, and is connected to an adjacent one of the common electrode lines, so that the shielding The electrode has the same potential as the common electrode;

Alternatively, the shielding electrode may also be used in plurality, the number of the shielding electrodes is the same as the number of data lines, and each shielding electrode is disposed above one data line, and is connected to any one of the plurality of common electrode lines. Connected so that the shield electrode is at the same potential as the common electrode.

For the display panel of the normally black mode, if there is no electric field or a weak electric field between the shield electrode and the common electrode, the liquid crystal molecules located above and on both sides of the shield electrode can be effectively deflected to a horizontal state (relative to the substrate). And the area of the display panel corresponding to the shielding electrode is opaque, so that the area of the display panel corresponding to the data line is opaque, thereby overcoming the light leakage of the display panel in the prior art in the case of side view or pressing. Defects.

In this embodiment, the array substrate may further include an insulating layer disposed between the shielding electrode and the plurality of data lines, so that the shielding electrode and the plurality of data lines are not electrically connected to each other.

2) The difference between the manufacturing method of the display panel in the embodiment and the manufacturing method in the embodiment 1 is:

In the step of forming the shield electrode, if one of the shield electrodes is formed, the shield electrode is connected to any one of the plurality of common electrode lines such that there is no electric field between the shield electrode and the common electrode, thereby shielding The area of the display panel corresponding to the electrode is opaque;

Alternatively, in the step of forming the shield electrode, if a plurality of shield electrodes are formed, each shield electrode is located above the data line between the adjacent two gate lines, and adjacent to a common common electrode line Connected so that there is no electric field between the shield electrode and the common electrode, so that the area i of the display panel corresponding to the shield electrode is opaque;

Alternatively, in the step of forming the shield electrode, if a plurality of shield electrodes are formed, and the number of the shield electrodes is the same as the number of the data lines, each shield electrode is located on one data line Upper, and connected to any one of the plurality of common electrode lines, so that there is no electric field between the shielding electrode and the common electrode, so that the area of the display panel corresponding to the shielding electrode is opaque.

The specific manufacturing method of the display panel of this embodiment differs from Embodiment 1 in that: a common electrode line (ie, a Vcom line, not shown in the figure) is simultaneously formed in the first patterning process; Forming a passivation layer 7, a first via hole 14 and a third via hole (not shown), and the third via hole is located above the common electrode line; the shield electrode 11 formed in the fourth patterning process passes the third The via is connected to the common electrode line.

Other structures, methods, and functions in this embodiment are the same as those in Embodiment 1, and will not be described again.

The display panel of the embodiment of the invention is particularly suitable for a display panel in which a pixel electrode and a common electrode are located on different substrates, such as a TN type display panel and a VA (Vertical Alignment) type display panel.

Beneficial effects:

1) The display panel of the embodiment of the present invention has a shielding electrode disposed above the data line. For the display panel of the normally white mode, a strong electric field is formed between the shielding electrode and the common electrode, and the shielding electrode is located above and on both sides of the shielding electrode. The liquid crystal molecules can be effectively deflected to an upright state (relative to the substrate) such that the area of the display panel corresponding to the shield electrode is opaque; for the display panel of the normally black mode, there is no electric field or formation between the shield electrode and the common electrode The weak electric field, the liquid crystal molecules located above and on both sides of the shielding electrode can be effectively deflected to a horizontal state (relative to the substrate), so that the area of the display panel corresponding to the shielding electrode is opaque; therefore, the display panel of the embodiment of the present invention overcomes The display panel of the prior art (including the normally white mode and the normally black mode display panel) is highly susceptible to light leakage in the case of side view or pressing; and at the same time, it can be further reduced by overcoming the defect of light leakage. The width of the black matrix can increase the aperture ratio of the pixel unit.

2) The shielding electrode in the display panel of the embodiment of the invention is the same as the material of the pixel electrode, and the two are completed in the same patterning process, that is, the shielding electrode can be fabricated while the pattern of the pixel electrode is being formed. Graphics. Therefore, while solving the light leakage problem, the display panel does not increase the cost, the process, or the material of the multilayer structure with respect to the existing manufacturing process.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

A display panel includes an array substrate and a color filter substrate, the array substrate includes a plurality of data lines, the color filter substrate includes a common electrode, wherein the array substrate further includes a shield electrode, and the shield electrode is disposed at An electric field is formed above the plurality of data lines and between the common electrodes.

The display panel according to claim 1, wherein the array substrate further comprises an insulating layer disposed between the shield electrode and the plurality of data lines.

3. The display panel according to claim 1 or 2, wherein

The display panel uses a display panel of a normally white mode, and the shield electrode is at a low potential with respect to the common electrode;

Alternatively, the display panel uses a display panel of a normally black mode, and the potential of the shield electrode and the common electrode are equal or not much different.

The display panel according to claim 3, wherein when the display panel is in the display panel of the normally white mode, the array substrate includes a plurality of the shielding electrodes, and the array substrate further includes a plurality of grids a plurality of gate lines intersecting the plurality of data lines, each of the shield electrodes being disposed above a data line between two adjacent gate lines, and any one of the adjacent two gate lines One connected.

The display panel according to claim 3, wherein when the display panel is in a display panel of a normally black mode, the array substrate further includes a plurality of gate lines and a plurality of common electrode lines, the plurality of a gate line is disposed to intersect with the plurality of data lines, the plurality of common electrode lines are respectively connected to the common electrode, and each of the common electrode lines is disposed in parallel with the plurality of gate lines;

The array substrate includes one of the shield electrodes, and the shield electrode is connected to any one of a plurality of common electrode lines;

Or the array substrate includes a plurality of the shielding electrodes, each shielding electrode is disposed above a data line between two adjacent gate lines, and is connected to an adjacent one of the common electrode lines;

Alternatively, the array substrate includes a plurality of the shield electrodes, each of which is disposed above a data line and connected to any one of the plurality of common electrode lines.

A display device comprising a display panel, wherein the display panel comprises the display panel according to any one of claims 1-5.

A method for manufacturing a display panel, comprising the steps of: fabricating an array substrate and a color filter substrate, wherein the step of fabricating the array substrate comprises the step of forming a plurality of data lines, and the step of fabricating the color filter substrate The step of forming a common electrode, wherein the step of fabricating the array substrate further comprises the step of forming a shield electrode, wherein the shield electrode is located above the plurality of data lines and can form an electric field with the common electrode.

8. The manufacturing method according to claim 7, wherein the step of fabricating the array substrate further comprises the step of forming an insulating layer, the insulating layer being located between the shield electrode and the plurality of data lines.

9. The manufacturing method according to claim 7, wherein the step of fabricating the array substrate further comprises the step of forming a plurality of gate lines, wherein the plurality of gate lines are disposed across the plurality of data lines; In the step of shielding the electrodes, the shielding electrodes are plural, and each of the shielding electrodes is located above the data line between the adjacent two gate lines, and is connected to any one of the adjacent two gate lines.

The manufacturing method according to claim 7, wherein the step of fabricating the array substrate further comprises the steps of forming a plurality of gate lines and a plurality of common electrode lines, wherein the plurality of gate lines and the plurality of data lines a line crossing arrangement, the plurality of common electrode lines are respectively connected to the common electrode, and each common electrode line is disposed in parallel with the gate line;

In the step of forming a shield electrode, the shield electrode is one, and the shield electrode is connected to any one of a plurality of common electrode lines;

Or, in the step of forming the shielding electrode, the shielding electrode is a plurality of, each shielding electrode is located above the data line between the adjacent two gate lines, and is connected to an adjacent one of the common electrode lines; or In the step of forming the shield electrode, the plurality of shield electrodes are located, and each of the shield electrodes is located above one of the data lines and connected to any one of the plurality of common electrode lines.

The manufacturing method according to any one of claims 7 to 10, wherein the step of fabricating the array substrate further comprises the step of forming a pixel electrode, wherein the shielding electrode and the pixel electrode are completed in the same patterning process And the shielding electrode and the pixel electrode do not overlap each other; the shielding electrode and the pixel electrode have the same material.