CN113671749B

CN113671749B - Method for reducing afterimage in image

Info

Publication number: CN113671749B
Application number: CN202111045657.6A
Authority: CN
Inventors: 李利霞; 池宝林; 严允晟; 任贵宁; 赵国; 赵迎春; 谢忠憬; 申海燕; 肖军城
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2023-03-31
Anticipated expiration: 2041-09-07
Also published as: CN113671749A

Abstract

A method for reducing afterimage in a liquid crystal display includes: providing a display panel comprising two pixel areas, a data wire routing area and a gap area, wherein the two pixel areas are respectively provided with a pixel electrode, the data wire routing area is internally provided with a data wire and a DBS (direct bus) common electrode or a black matrix positioned on the data wire, and the gap area is internally provided with an array substrate side common electrode; and providing a pixel electrode full black potential signal and a pixel electrode full white potential signal to the pixel electrodes in the two pixel regions, and providing a color filter common electrode first potential signal and the DBS common electrode or the array substrate side common electrode second potential signal, wherein a first electric field is formed between the pixel electrode and the DBS common electrode or the array substrate side common electrode, a second electric field is formed between the color filter common electrode and the DBS common electrode or the array substrate side common electrode, and the second electric field is staggered with the first electric field.

Description

Method for reducing afterimage in image

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a method for reducing image retention in an image.

Background

Liquid Crystal Displays (LCDs) are widely used, and for example, in Personal computers, liquid Crystal televisions, mobile phones, or Personal Digital Assistants (PDAs), the LCD can be traced. The liquid crystal display has gradually merged into the life of people, and the liquid crystal display is more and more attracted by the huge commercial opportunity and market behind the liquid crystal display.

In the liquid crystal display process, an afterimage phenomenon, also called Image Sticking (Image Sticking), is easily generated, which is a phenomenon that the same still picture is displayed for a long time and the previous picture is left after the display content is changed. In all display modes of the liquid crystal display, there is an afterimage problem either lightly or heavily.

The afterimage evaluation is generally performed using a video 10 including a black and white checkerboard pattern as shown in fig. 1, and is classified into two types, i.e., area (Area) afterimage and Line (Line) afterimage, according to the state of the afterimage occurring after switching the video 10. Among them, in the current high-resolution liquid crystal panel, the occurrence of wired afterimages is common. Fig. 2 shows the residual line image at the junction of two adjacent black-and-white pattern pixels 12 (as shown in the area a of fig. 1-2) after the image 10 of fig. 1 is converted to a gray-scale image, which is caused by the difference in brightness due to the ion movement at the junction of two adjacent black-and-white pattern pixels 12.

Therefore, a solution to the above problem is needed to effectively avoid or reduce the undesirable image sticking phenomenon in the image, such as line sticking, so as to improve the display quality of the liquid crystal panel.

Disclosure of Invention

In order to solve the above technical problem, the present disclosure provides a method for reducing image retention in an image.

According to some embodiments, the present disclosure provides a method for reducing afterimage in a liquid crystal display, comprising the steps of:

providing a liquid crystal display comprising a display panel, the display panel comprising: two adjacent pixel regions; a data line routing area arranged between the two pixel areas; and a gap region arranged between the two pixel regions and the data line routing region; the two pixel areas are respectively provided with a pixel electrode, the Data line routing area is internally provided with a Data line and a black matrix (DBS) common electrode (hereinafter referred to as DBS common electrode) or a black matrix positioned on the Data line and used for reducing the Data line, and the gap area is internally provided with an array substrate side common electrode; and providing a pixel electrode full black potential signal and a pixel electrode full white potential signal to the pixel electrodes in the two adjacent pixel regions, and providing a color filter common electrode first potential signal and providing the DBS common electrode or the array substrate side common electrode second potential signal, wherein the first potential signal and the second potential signal have different potentials, a first electric field is formed between the pixel electrode and the DBS common electrode or the array substrate side common electrode, a second electric field is formed between the color filter common electrode and the DBS common electrode or the array substrate side common electrode, and the second electric field is staggered with the first electric field.

In certain embodiments, the second electric field is perpendicular to the first electric field.

In certain embodiments, the first potential is lower than the second potential. The first potential signal is a potential signal of 0 volt (V), and a potential difference of less than 7 volts exists between the first potential signal and the second potential signal. The potential difference between the first potential signal and the second potential signal is 1-2 volts.

In some embodiments, the first potential is higher than the second potential. The first potential signal is a potential signal of 0 volt (V), and a potential difference of less than 7 volts exists between the first potential signal and the second potential signal. The potential difference between the first potential signal and the second potential signal is 1-2 volts.

In some embodiments, the first electric field is a lateral electric field formed by the pixel electrode toward the DBS common electrode or the array substrate-side common electrode.

In some embodiments, the first electric field is a lateral electric field formed by the DBS common electrode or the array substrate-side common electrode toward the pixel electrode.

The method for reducing the residual image in the image has the advantages that the electric field between the color filter common electrode and the DBS common electrode or the array substrate side common electrode is formed in the display panel, the electric field and the electric field which is formed between the pixel electrode and the DBS common electrode or the adjacent array substrate side common electrode and faces or deviates from the DBS common electrode or the adjacent array substrate side common electrode are staggered, so that positive ions induced by a first electric field of the formed pixel electrode which receives the full white potential signal and faces the DBS common electrode or the adjacent array substrate side common electrode are blocked, the positive ions are prevented from further diffusing to the pixel electrode which receives the full black potential signal, the residual problem of a line residual image which is found at the joint of the pixels of two adjacent black and white patterns in a gray-scale image is reduced or avoided, and the display quality of the liquid crystal panel is improved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1-2 are schematic diagrams of image retention in an image.

FIG. 3 is a schematic top view of a pixel in a liquid crystal display according to an embodiment of the disclosure.

FIG. 4 is an enlarged view of area B in FIG. 3 according to one embodiment of the present disclosure.

Fig. 5 isbase:Sub>A schematic cross-sectional view of linebase:Sub>A-base:Sub>A' in fig. 4.

FIGS. 6-7 are schematic diagrams of electric fields according to an embodiment of the present disclosure.

FIGS. 8-9 are schematic diagrams of electric fields according to another embodiment of the present disclosure.

FIG. 10 is an enlarged view of area B in FIG. 3 according to another embodiment of the present disclosure.

Fig. 11 is a schematic sectional view of line B-B' in fig. 10.

FIGS. 12-13 are schematic electrical field diagrams of yet another embodiment of the present disclosure.

FIGS. 14-15 are schematic diagrams of electric fields according to yet another embodiment of the present disclosure.

FIG. 16 is a block diagram illustrating an embodiment of a method for reducing image retention.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in the present invention, such as [ upper ], [ lower ], [ top ], [ bottom ], [ left ], [ right ], [ inner ], [ outer ], [ side ], refer to the directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.

Fig. 3, fig. 4 and fig. 5 are schematic diagrams of a liquid crystal display according to an embodiment of the disclosure. Fig. 3 isbase:Sub>A schematic top view ofbase:Sub>A pixel inbase:Sub>A liquid crystal display according to an embodiment of the disclosure, fig. 4 is an enlarged view of an area B in fig. 3 according to an embodiment of the disclosure, and fig. 5 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A linebase:Sub>A-base:Sub>A' in fig. 4. As shown in fig. 3 to 5, the liquid crystal display includes a display panel (see fig. 5) including a plurality of data line routing areas 11 and a plurality of pixel areas 12 which are repeatedly arranged. For convenience of explanation, fig. 3 and fig. 5 only show two arbitrary adjacent pixel regions 12 and one Data line routing region 11 disposed therebetween, and a Data line 16 and a common electrode 18 (hereinafter referred to as a DBS common electrode 18) of a black matrix (DBS) on the reduced Data line on the Data line 16 are disposed in the Data line routing region 11. Each pixel region 12 is provided with a pixel electrode 20 disposed on the same layer as the DBS common electrode 18, and the pixel electrode 20 has a comb-finger or fishbone shape as viewed from above. A gap region (a region between the data line routing region 11 and the pixel region 12) is provided between the DBS common electrode 18 and the pixel electrode 20, and a substrate corresponding to the gap region (e.g., a substrate structure 51 in the array substrate 50 in fig. 5) is provided with the array substrate side common electrode 14.

As shown in fig. 3, the data line 16 and the DBS common electrode 18 extend in a vertical direction, a side of the pixel electrode 20 close to the gap region is parallel to the data line 16 and the DBS common electrode 18, and the array substrate side common electrode 14 is disposed in the substrate structure 51 of the array substrate 50 between the data line 16 and the pixel electrode 20.

As shown in fig. 5, the display panel includes a color filter substrate 30, a liquid crystal layer 40 and the array substrate 50. The color filter substrate 30 includes a substrate 31 and a color filter common electrode 32 formed on a surface of the substrate 31 facing the array substrate 50. The array substrate 50 includes an array substrate side common electrode 14 formed in the substrate structure 51, and a dielectric layer 52, a data line 16, a DBS common electrode 18 and a pixel electrode 20 formed on the substrate structure 51. Here, the array substrate side common electrode 14 and the data line 16 are designed in different layers and the dielectric layer 52 covers the data line 16, and the DBS common electrode 18 and the pixel electrode 20 are disposed on the dielectric layer 52.

Specifically, the display panel of the lcd shown in fig. 3-5 further includes a scan line routing area (not shown) intersecting the data line routing area 11, a scan line intersecting the data line 16 and insulated from the data line routing area, and a thin film transistor (not shown) on the scan line. The thin film transistors may be disposed on the substrate structure 51 of the array substrate 50 and electrically connected to the scan lines, the data lines 16 and the pixel electrodes 20, respectively. The thin film transistor, the scanning line, the array substrate side common electrode 14, the data line 16, the DBS common electrode 18, and the pixel electrode 20 are all the constituent structure of the array substrate 50.

In order to avoid or reduce the occurrence of undesirable in-image afterimage phenomena such as line afterimage in the display panel of the liquid crystal display, the present disclosure reduces or eliminates the afterimage such as line afterimage in the image by providing different potential signals to the DBS common electrode 18, the pixel electrode 20 and the color filter common electrode 32.

FIGS. 6-7 are schematic diagrams of electric fields according to an embodiment of the present disclosure. For convenience of illustration, fig. 6 to 7 respectively show a perspective view and a cross-sectional view including only the data line 16, the color filter common electrode 32, the DBS common electrode 18, and the pixel electrode 20. Here, when the display panel performs the image operation of the black and white checkerboard pattern as shown in fig. 1, in addition to providing the full black potential signal (L0) to the left pixel electrode 20 and the full white potential signal (L255) to the right pixel electrode 20 in the two adjacent pixels respectively so that the horizontal electric field 112 facing the DBS common electrode 18 is formed between the pixel electrode 20 and the DBS common electrode 18, respectively, the first potential signal and the second potential signal to the color filter common electrode 32 and the DBS common electrode 18 are provided, respectively. Here, the first potential signal supplied to the color filter common electrode 32 is not at the same potential as the second potential signal supplied to the DBS common electrode 18, but at a higher potential than the second potential signal, so that a vertical electric field 100 is formed from the color filter common electrode 32 toward the DBS common electrode 18. Accordingly, by forming the vertical electric field 100 between the color filter common electrode 32 and the DBS common electrode 18, the positive ions 110 induced by the lateral electric field 112 from the right pixel electrode 20 formed to receive the full white potential signal (L255) toward the DBS common electrode 18 are blocked, and the positive ions 110 are prevented from further diffusing to the left pixel electrode 20 receiving the full black potential signal (L0), so that the problem of the line remnant remaining at the junction of two adjacent black-and-white patterned pixels 12 in the gray-scale image shown in fig. 2 is reduced or avoided, thereby reducing the in-image remnant and improving the display quality of the liquid crystal panel. In one embodiment, the first potential signal is, for example, a 0 volt (V) potential signal, and a potential difference of less than 7V exists between the first potential signal and the second potential signal, and the potential difference between the first potential signal and the second potential signal is preferably 1-2V.

In addition, fig. 8-9 are schematic diagrams of electric fields according to another embodiment of the present disclosure. For convenience of illustration, fig. 8 to 9 respectively show a perspective view and a cross-sectional view including only the data line 16, the color filter common electrode 32, the DBS common electrode 18, and the pixel electrode 20.

As shown in fig. 8-9, when the display panel performs the image operation of the black and white checkerboard pattern as shown in fig. 1, in addition to providing the left pixel electrode 20 full black potential signal (L0) and the right pixel electrode 20 full white potential signal (L255) respectively in two adjacent pixels to form the lateral electric field 112 facing the DBS common electrode 18 between the pixel electrode 20 and the DBS common electrode 18, respectively, the first potential signal and the second potential signal of the color filter common electrode 32 and the DBS common electrode 18 are also provided respectively. Here, the first potential signal supplied to the color filter common electrode 32 is not at the same potential as the second potential signal supplied to the DBS common electrode 18, but at a lower potential than the second potential signal, so that the vertical electric field 100 is formed from the DBS common electrode 18 toward the color filter common electrode 32. Accordingly, by forming the vertical electric field 100 between the DBS common electrode 18 and the color filter common electrode 32, the positive ions 110 induced by the lateral electric field 112 from the formed DBS common electrode 18 toward the right pixel electrode 20 receiving the full black signal (L255) are blocked, and the positive ions 110 are prevented from further diffusing to the left pixel electrode 20 receiving the full black signal (L0), so that the problem of line sticking at the junction of two adjacent black-and-white pattern pixels 12 in the gray-scale image shown in fig. 2 is reduced or avoided, and the display quality of the liquid crystal panel is improved. In one embodiment, the first potential signal is, for example, a 0 volt (V) potential signal, and a potential difference of less than 7V exists between the first potential signal and the second potential signal, and the potential difference between the first potential signal and the second potential signal is preferably 1-2V.

The display panel of the lcd in the embodiments of fig. 3-9 is a display panel including the DBS common electrode 18. However, the technology of the present disclosure is also applicable to a display panel of a liquid crystal display without using the DBS common electrode 18 to reduce or avoid the problem of line afterimage residue found at the intersection of two adjacent black-and-white pixels 12 in the gray-scale image as shown in fig. 2, thereby reducing the afterimage in the image and improving the display quality of the liquid crystal panel.

Fig. 10 and 11 are schematic diagrams of a liquid crystal display according to another embodiment of the disclosure. Here, the lcd is a display panel of an lcd without the DBS common electrode 18, and the schematic top view of the pixels in the lcd is similar to that shown in fig. 3, so that the display is not shown again. Fig. 10 is an enlarged view of an area B in fig. 3 to illustrate the difference between the present embodiment and the previous embodiment according to another embodiment of the present disclosure, and fig. 11 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A linebase:Sub>A-base:Sub>A' in fig. 10. As shown in fig. 10 to 11, the liquid crystal display includes a display panel (see fig. 11) including a plurality of data line routing areas 11 and a plurality of pixel areas 12 which are repeatedly arranged. For convenience of illustration, fig. 3 and 11 only show two arbitrary adjacent pixel regions 12 and one data line routing region 11 disposed therebetween, and a data line 16 and a Black Matrix (BM) 18' for shielding light disposed on the data line 16 are disposed in the data line routing region 11. Each pixel region 12 is provided with a pixel electrode 20 disposed on the same layer as the black matrix 18', and the pixel electrode 20 has a comb-finger or fishbone shape when viewed from above. A gap region (a region between the data line routing region 11 and the pixel region 12) is provided between the black matrix 18' and the pixel electrode 20, and a substrate corresponding to the gap region (e.g., a substrate structure 51 in the array substrate 50 in fig. 5) is provided with an array substrate side common electrode 14.

As shown in fig. 10, in the present embodiment, the data lines 16 and the black matrix 18 'extend in a vertical direction, one side of the pixel electrodes 20 near the gap regions is parallel to the data lines 16 and the black matrix 18', and the array substrate-side common electrode 14 is disposed in the substrate structure 51 of the array substrate 50 between the data lines 16 and the pixel electrodes 20.

As shown in fig. 11, the display panel includes a color filter substrate 30, a liquid crystal layer 40 and the array substrate 50. The color filter substrate 30 includes a substrate 31 and a color filter common electrode 32 formed on a surface of the substrate 31 facing the array substrate 50. The array substrate 50 includes an array substrate side common electrode 14 formed in the substrate structure 51, and a dielectric layer 52, a data line 16, a black matrix 18' and a pixel electrode 20 formed on the substrate structure 51. Here, the array substrate side common electrode 14 and the data line 16 are designed in different layers and the dielectric layer 52 covers the data line 16, and the black matrix 18' and the pixel electrode 20 are disposed on the dielectric layer 52.

Specifically, the display panel of the lcd shown in fig. 10-11 further includes a scan line routing area (not shown) intersecting the data line routing area 11, a scan line intersecting the data line 16 and insulated from the data line routing area, and a thin film transistor (not shown) on the scan line. The thin film transistors may be disposed on the substrate structure 51 of the array substrate 50 and electrically connected to the scan lines, the data lines 16 and the pixel electrodes 20, respectively. The thin film transistor, the scanning line, the array substrate side common electrode 14, the data line 16, the black matrix 18', and the pixel electrode 20 are all constituent structures of the array substrate 50.

In order to prevent or reduce the occurrence of an undesirable in-image afterimage phenomenon such as a line afterimage in a display panel of a liquid crystal display, the present disclosure reduces or eliminates the in-image afterimage such as a line afterimage by providing different potential signals of the array substrate side common electrode 14, the pixel electrode 20, and the color filter common electrode 32.

FIGS. 12-13 are schematic diagrams of electric fields according to yet another embodiment of the present disclosure. For the purpose of convenience of explanation, a schematic perspective view and a schematic sectional view including only the color filter common electrode 32, the array substrate-side common electrode 14, and the pixel electrode 20 are shown in fig. 12 to 13, respectively. Here, when the display panel performs the image operation of the black-and-white checkerboard pattern as shown in fig. 1, in addition to providing the left pixel electrode 20 full black potential signal (L0) and the right pixel electrode 20 full white potential signal (L255) in the two adjacent pixels, respectively, to form the lateral electric fields 112 facing each other between each pixel electrode 20 and the array substrate side common electrode 14 adjacent thereto, the color filter common electrode 32 and the array substrate side common electrode 14 adjacent to each pixel electrode 20 are provided with the first potential signal and the second potential signal, respectively. Here, the first potential signal supplied to the color-filter common electrode 32 is not the same potential as the second potential signal supplied to the array-substrate-side common electrode 14 adjacent to each pixel electrode 20, but the potential of the first potential signal is higher than that of the second potential signal, so that a vertical electric field 100' is formed from the color-filter common electrode 32 toward the array-substrate-side common electrode 14 adjacent to each pixel electrode 20. By forming the vertical electric field 100' between the color filter common electrode 32 and the array substrate side common electrode 14 adjacent to each pixel electrode 20, the positive ions 110 induced by the lateral electric field 112 from the right pixel electrode 20 receiving the full white potential signal (L255) toward the adjacent array substrate side common electrode 14 are blocked, and the positive ions 110 are prevented from further diffusing to the left pixel electrode 20 receiving the full black potential signal (L0), so that the problem of line afterimage sticking at the junction of two adjacent black and white pattern pixels 12 in the gray-scale image shown in fig. 2 is reduced or avoided, and the image afterimage is reduced and the display quality of the liquid crystal panel is improved. In one embodiment, the first potential signal is, for example, a 0 volt (V) potential signal, and a potential difference of less than 7V exists between the first potential signal and the second potential signal, and the potential difference between the first potential signal and the second potential signal is preferably 1-2V.

In addition, fig. 14-15 are schematic diagrams of electric fields according to still another embodiment of the present disclosure. For the purpose of convenience of explanation, a schematic perspective view and a schematic cross-sectional view including only the array substrate-side common electrode 14, the color filter common electrode 32, and the pixel electrode 20 are shown in fig. 14 to 15, respectively.

As shown in fig. 14-15, when the display panel performs the image operation of the black-and-white checkerboard pattern as shown in fig. 1, in addition to providing the left pixel electrode 20 full black potential signal (L0) and the right pixel electrode 20 full white potential signal (L255) respectively in the two adjacent pixels to form the transverse electric field 112 between each pixel electrode 20 and the adjacent array substrate side common electrode 14, the first potential signal and the second potential signal of the color filter common electrode 32 and the array substrate side common electrode 14 adjacent to each pixel electrode 20 are also provided respectively. Here, the first potential signal supplied to the color filter common electrode 32 is not the same potential as the second potential signal supplied to the array substrate-side common electrode 14 adjacent to each pixel electrode 20, but the potential of the first potential signal is lower than that of the second potential signal, so that a vertical electric field 100' is formed from the array substrate-side common electrode 14 of each pixel electrode 20 toward the color filter common electrode 32. Thus, by forming the vertical electric field 100' between the color filter common electrode 32 and the array substrate-side common electrode 14 adjacent to each pixel electrode 20, the positive ions 110 induced by the lateral electric field 112 of the right pixel electrode 20 away from the adjacent array substrate-side common electrode 14, which is formed to receive the full white potential signal (L255), are blocked, and the positive ions 110 are prevented from further diffusing to the left pixel electrode 20, which receives the full black potential signal (L0), so that the line residual image problem found at the intersection of two adjacent black-and-white pattern pixels 12 in the image shown in fig. 2 is reduced or avoided, thereby reducing the image residual image and improving the display quality of the liquid crystal panel. In one embodiment, the first potential signal is, for example, a 0 volt (V) potential signal, and a potential difference of less than 7V exists between the first potential signal and the second potential signal, and the potential difference between the first potential signal and the second potential signal is preferably 1-2V.

In summary, the present disclosure provides a method for reducing image retention, which is suitable for a display panel of a liquid crystal display with or without a DBS common electrode 18, so as to reduce or avoid the problem of line retention at the intersection of two adjacent black and white pixels 12 in a gray-scale image as shown in fig. 2, thereby reducing image retention and improving the display quality of the liquid crystal panel.

Referring to fig. 16, a method for reducing image retention in an image according to an embodiment of the present disclosure is shown, which includes the following steps:

first, in step S10, a liquid crystal display including a display panel is provided, wherein the display panel includes two adjacent pixel regions 12 and a data line routing region 11 disposed between the two pixel regions 12. The Data line routing region 11 is provided with a Data line 16 and a black matrix (DBS) common electrode 18 (hereinafter referred to as DBS common electrode 18) or a black matrix 18' on the Data line 16. Each pixel region 12 is provided with a pixel electrode 20, and a gap region is provided between each pixel region 12 and its adjacent data line routing region 11, and an array substrate side common electrode 14 is provided in the gap region.

Next, in step S12, a full black potential signal (L0) is provided to one pixel electrode (for example, the left pixel electrode 20) and a full white potential signal (L255) is provided to the other pixel electrode (for example, the right pixel electrode 20) in the two adjacent pixel regions 12, and a first potential signal and a second potential signal are provided to the color filter common electrode 32 and the DBS common electrode 18 or the array substrate side common electrode 14 adjacent to the pixel electrode 20, respectively, and the potentials of the first potential signal and the second potential signal are different. In this way, a first electric field (e.g., a lateral electric field) facing toward or away from the DBS common electrode 18 or the array substrate-side common electrode 14 adjacent thereto is formed between the pixel electrode 20 and the DBS common electrode 18 or the array substrate-side common electrode 14 adjacent thereto, and a second electric field (e.g., a vertical electric field) interleaved with the first electric field is formed between the color filter common electrode 32 and the DBS common electrode 18 or the array substrate-side common electrode 14, respectively. In one embodiment, the second electric field is perpendicular to the first electric field. By this means, the formation of the second electric field can block the positive ions 110 induced by the first electric field from the right pixel electrode 20 receiving the full white potential signal (L255) toward the DBS common electrode 18 or the adjacent array substrate side common electrode 14, and prevent the positive ions 110 from further diffusing to the left pixel electrode 20 receiving the full black potential signal (L0), thereby reducing or avoiding the problem of line afterimage sticking at the junction of two adjacent black and white pattern pixels 12 in the gray-scale image shown in fig. 2, and further reducing the in-image afterimage and improving the display quality of the liquid crystal panel. The first potential signal is, for example, a potential signal of 0 volt (V), and a potential difference of less than 7V exists between the first potential signal and the second potential signal, and the potential difference between the first potential signal and the second potential signal is preferably 1-2V.

The present disclosure has the beneficial effect of providing a method for reducing image retention, wherein an electric field between the color filter common electrode and the DBS common electrode or the array substrate-side common electrode is formed in the display panel, and the electric field between the pixel electrode and the DBS common electrode or the adjacent array substrate-side common electrode are staggered toward or away from the DBS common electrode or the adjacent array substrate-side common electrode 14, so as to block positive ions induced by the first electric field of the pixel electrode receiving the full white potential signal (L255) toward the DBS common electrode or the adjacent array substrate-side common electrode, and prevent the positive ions from further diffusing to the pixel electrode receiving the full black potential signal (L0), thereby reducing or avoiding the problem of line retention found at the junction of two adjacent black and white pattern pixels 12 in the gray-scale image shown in fig. 2, and further reducing image retention and improving the display quality of the liquid crystal panel.

Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention.

Claims

1. A method for reducing image retention in an image, comprising: the method for reducing the afterimage in the image comprises the following steps:

providing a liquid crystal display comprising a display panel, the display panel comprising:

two adjacent pixel regions;

a data line routing area arranged between the two pixel areas; and

a gap region disposed between the two pixel regions and the data line routing region;

the two pixel areas are respectively provided with a pixel electrode, the data wire routing area is internally provided with a data wire and a DBS public electrode or a black matrix positioned on the data wire, and the gap area is internally provided with an array substrate side public electrode;

and

providing a pixel electrode full black potential signal and a full white potential signal to the pixel electrodes in the two adjacent pixel regions, providing a color filter common electrode first potential signal and providing the DBS common electrode or the array substrate side common electrode second potential signal, wherein the first potential signal and the second potential signal have different potentials, a first electric field is formed between the pixel electrode and the DBS common electrode or the array substrate side common electrode, a second electric field is formed between the color filter common electrode and the DBS common electrode or the array substrate side common electrode, and the second electric field is staggered with the first electric field.

2. The method of claim 1, wherein: the second electric field is perpendicular to the first electric field.

3. The method of claim 1, wherein: the first potential is lower than the second potential.

4. The method of claim 3, wherein: the first potential signal is a potential signal of 0 volt (V), and a potential difference of less than 7 volts exists between the first potential signal and the second potential signal.

5. The method of claim 4, wherein: the potential difference between the first potential signal and the second potential signal is 1-2 volts.

6. The method of claim 1, wherein: the first potential is higher than the second potential.

7. The method of claim 6, wherein: the first potential signal is a potential signal of 0 volt (V), and a potential difference of less than 7 volts exists between the first potential signal and the second potential signal.

8. The method of claim 7, wherein: the potential difference between the first potential signal and the second potential signal is 1-2 volts.

9. The method of claim 1, wherein: the first electric field is a lateral electric field formed by the pixel electrode toward the DBS common electrode or the array substrate-side common electrode.

10. The method of claim 1, wherein: the first electric field is a lateral electric field formed by the DBS common electrode or the array substrate-side common electrode toward the pixel electrode.