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Definitions

• the invention is in the field of Semiconductor Devices.
• Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed.
• An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor.
• Figure 1 illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device.
• semiconductor device 100 includes a SONOS gate stack 104 including a conventional ONO portion 106 formed over a silicon substrate 102.
• Semiconductor device 100 further includes source and drain regions 110 on either side of SONOS gate stack 104 to define a channel region 112.
• SONOS gate stack 104 includes a poly-silicon gate layer 108 formed above and in contact with ONO portion 106.
• Polysilicon gate layer 108 is electrically isolated from silicon substrate 102 by ONO portion 106.
• ONO portion 106 typically includes a tunnel oxide layer 106A, a nitride or oxynitride charge-trapping layer 106B, and a top oxide layer 106C overlying nitride or oxynitride layer 106B.
• One problem with conventional SONOS transistors is the poor data retention in the nitride or oxy-nitride layer 106B that limits semiconductor device 100 lifetime and its use in several applications due to leakage current through the layer.
• One attempt to address this problem focused on the use of silicon-rich SONOS layers, which enable a large initial separation between program and erase voltages at the beginning of life but result a rapid deterioration of charge storing ability.
• FIGS 2 and 3 are plots of Threshold Voltage (V) as a function of Retention Time (Sec) for conventional nonvolatile charge trap memory devices.
• VTP programming threshold voltage
• VTE erase threshold voltage
• Figure 3 a reduced separation between VTP 302 and VTE 304 is obtained for an oxygen-rich layer.
• line 306 the overall useful lifetime of device is not appreciably extended by this approach.
• Figure 1 illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device.
• Figure 2 is a plot of Threshold Voltage (V) as a function of Retention
• FIG. 3 is a plot of Threshold Voltage (V) as a function of Retention
• Figure 4 illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 5 illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6A illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6B illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6C illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6D illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6E illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6F illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6G illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 6H illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 61 illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 7A illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 7B illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 7C illustrates a cross-sectional view representing a step in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Figure 8A illustrates a cross-sectional view of a nonvolatile charge trap memory device including an O O stack.
• Figure 8B illustrates a cross-sectional view of a nonvolatile charge trap memory device including an ONONO stack.
• Figure 9 depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device including a split multilayer charge-trapping region.
• Figure 10A illustrates a non-planar multigate device including a split charge-trapping region.
• Figure 10B illustrates a cross-sectional view of the non-planar multigate device of Figure. 10A.
• Figures 11 A and 1 IB illustrate a non-planar multigate device including a split charge-trapping region and a horizontal nanowire channel.
• Figure 11C illustrates a cross-sectional view of a vertical string of non- planar mul tigate devices of Figure 11 A.
• Figures 12A and 12B illustrate a non-planar multigate device including a split charge-trapping region and a vertical nanowire channel.
• a nonvolatile charge trap memory device and a method to form the same is described herein.
• numerous specific details are set forth, such as specific dimensions, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
• the device may include a substrate having a channel region and a pair of source and drain regions.
• a gate stack may be formed above the substrate over the channel region and between the pair of source and drain regions.
• the gate stack includes a multi-layer charge-trapping region having a first deuterated layer.
• the multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
• the multi-layer charge-trapping region may include a partially deuterated charge-trapping layer having a deuterium concentration less than that of the first deuterated layer.
• a nonvolatile charge trap memory device including a multi-layer charge trapping region having a deuterated layer may exhibit improved programming and erase speed and data retention.
• a deuterated layer is formed between the charge-trapping layer of the multi-layer charge trapping region and the tunnel dielectric layer.
• the deuterated layer is essentially trap-free and mitigates hot electron degradation during erase and program cycles.
• a trap-free layer between the tunnel dielectric layer and the charge-trapping layer of a multi-layer charge-trapping region, the Vt shift from erase and program cycles may be reduced and the retention may be increased.
• a second deuterated layer is also formed between the charge-trapping layer of the multi-layer charge-trapping region and a top dielectric layer of the gate stack.
• a nonvolatile charge trap memory device may include a multi-layer charge-trapping region having a deuterated layer.
• Figure 4 illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• semiconductor device 400 includes a gate stack 404 formed over a substrate 402.
• Semiconductor device 400 further includes source and drain regions 410 in substrate 402 on either side of gate stack 404, defining a channel region 412 in substrate 402 underneath gate stack 404.
• Gate stack 404 includes a tunnel dielectric layer 404A, a multi-layer charge-trapping region 404B, a top dielectric layer 404C and a gate layer 404D.
• gate layer 404D is electrically isolated from substrate 402.
• Multi-layer charge-trapping region404B includes a deuterated layer 406 between a charge-trapping layer 408 of multi-layer charge-trapping region 404B and tunnel dielectric layer 404A.
• a pair of dielectric spacers 414 isolates the sidewalls of gate stack 404.
• Semiconductor device 400 may be any nonvolatile charge trap memory device.
• semiconductor device 400 is a Flash-type device wherein the charge-trapping layer is a conductor layer or a semiconductor layer.
• semiconductor device 400 is a SONOS- type device wherein the charge-trapping layer is an insulator layer.
• SONOS stands for “Semiconductor-Oxide-Nitride-Oxide-Semiconductor,” where the first “Semiconductor” refers to the channel region material, the first “Oxide” refers to the tunnel dielectric layer, “Nitride” refers to the charge-trapping dielectric layer, the second “Oxide” refers to the top dielectric layer (also known as a blocking dielectric layer) and the second “Semiconductor” refers to the gate layer.
• a SONOS-type device is not limited to these specific materials, as described below.
• Substrate 402 and, hence, channel region 412 may be composed of any material suitable for semiconductor device fabrication.
• substrate 402 is a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material.
• substrate 402 includes a bulk layer with a top epitaxial layer.
• the bulk layer is composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon- germanium, a III-V compound semiconductor material and quartz
• the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon, germanium, silicon-germanium and a III-V compound semiconductor material.
• substrate 402 includes a top epitaxial layer on a middle insulator layer which is above a lower bulk layer.
• the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon (i.e.
• the insulator layer is composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride and silicon oxy-nitride.
• the lower bulk layer is composed of a single crystal which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material and quartz.
• Substrate 402 and, hence, channel region 412 may include dopant impurity atoms. In a specific embodiment, channel region 412 is doped P-type and, in an alternative embodiment, channel region 412 is doped N-type.
• Source and drain regions 410 in substrate 402 may be any regions having opposite conductivity to channel region 412.
• source and drain regions 410 are N-type doped regions while channel region 412 is a P-type doped region.
• substrate 402 and, hence, channel region 412 is composed of boron-doped single-crystal silicon having a boron concentration in the range of 1 x 10 15 - 1 x 10 19 atoms/cm 3 .
• Source and drain regions 410 are composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5 x 10 16 -5 x 10 19 atoms/cm 3 .
• source and drain regions 410 have a depth in substrate 402 in the range of 80-200 nanometers.
• source and drain regions 410 are P-type doped regions while channel region 412 is an N-type doped region.
• Tunnel dielectric layer 404A may be any material and have any thickness suitable to allow charge carriers to tunnel into the charge-trapping layer under an applied gate bias while mamtaining a suitable barrier to leakage when the device is unbiased.
• tunnel dielectric layer 404A is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxy-nitride, or a combination thereof.
• tunnel dielectric layer 404A is formed by chemical vapor deposition or atomic layer deposition and is composed of a dielectric layer which may include, but is not limited to, silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
• tunnel dielectric layer 404A has a thickness in the range of 1-10 nanometers. In a particular embodiment, tunnel dielectric layer 404A has a thickness of approximately 2 nanometers.
• Multi-layer charge-trapping region 404B may be composed of any material and have any thickness suitable to store charge and, hence, raise the threshold voltage of gate stack 404.
• multi-layer charge-trapping region 404B is formed by a chemical vapor deposition process and is composed of a dielectric material which may include, but is not limited to, stoichiometric silicon nitride, silicon—rich silicon nitride and silicon oxy-nitride.
• multi-layer charge-trapping region 404B includes a deuterated layer 406 between tunnel dielectric layer 404A and charge trapping layer 408, as depicted in Figure 4.
• Deuterated layer 406 and charge-trapping layer 408 may be composed of a deuterated derivative and a non-deuterated derivative, respectively, of the same material.
• deuterated layer 406 is a deuterated derivative of silicon oxy-nitride
• charge-trapping layer 408 is formed from the hydrogenated derivative of silicon oxy-nitride.
• the total thickness of multi-layer charge-trapping region 404B is in the range of 5 - 10 nanometers.
• the ratio of thicknesses of deuterated layer 406: charge-trapping layer 408 is approximately 1:1, respectively.
• Multi-layer charge-trapping region 404B may have an abrupt interface between deuterated layer 406 and charge-trapping layer 408. That is, in accordance with an embodiment of the present invention, charge-trapping layer 408 is deuterium-free. Alternatively, a gradient of deuterium atom concentration moving from high concentration of deuterium in deuterated layer 406 ranging to low concentration of deuterium in charge-trapping layer 408 may be formed. Thus, in accordance with an alternative embodiment of the present invention, charge-trapping layer 408 is a partially deuterated layer, but having a deuterium concentration less than that of deuterated layer 406.
• Top dielectric layer 404C may be any material and have any thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of gate stack 404.
• top dielectric layer 404C is formed by a chemical vapor deposition process and is composed of silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof.
• top dielectric layer 404C is formed by atomic layer deposition and is composed of a high-k dielectric layer which may include, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
• top dielectric layer 404C has a thickness in the range of 1-20 nanometers.
• Gate layer 404D may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SONOS-type transistor.
• gate layer 404D is formed by a chemical vapor deposition .process and is composed of doped poly-crystalline silicon.
• gate layer 404D is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel.
• a nonvolatile charge trap memory device may include a multi-layer charge-trapping region having more than one deuterated layer.
• Figure 5 illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present inven tion.
• semiconductor device 500 includes a gate stack 504 formed over a substrate 502.
• Semiconductor device 500 further includes source and drain regions 510 in substrate 502 on either side of gate stack 504, defining a channel region 512 in substrate 502 underneath gate stack 504.
• Gate stack 504 includes a tunnel dielectric layer 504A, a multi-layer charge-trapping region 5048, a top dielectric layer 504C and a gate layer 504D.
• gate layer 504D is electrically isolated from substrate 502.
• Multi-layer charge-trapping region 504B includes a first deuterated layer 506 and a second deuterated layer 516 sandwiching charge-trapping layer 508 of multi-layer charge trapping region 504 B.
• a pair of dielectric spacers 514 isolates the sidewalls of gate stack 504.
• Semiconductor device 500 may be any semiconductor device described in association with semiconductor device 400 from Figure 4.
• Substrate 502, source and drain regions 510 and channel region 512 may be composed of any material and dopant impurity atoms described in association with substrate 402, source and drain regions 410 and channel region 412, respectively, from Figure 4.
• Tunnel dielectric layer 504A, top dielectric layer 504C and gate layer 504D may be composed of any material described in association with tunnel dielectric layer 404A, top dielectric layer 404C and gate layer 404D, respectively, from Figure 4.
• semiconductor device in contrast to semiconductor device 400, semiconductor device includes a multi-layer charge-trapping region 5048 having second deuterated layer 516 above charge trapping layer 508, as depicted in Figure 5.
• First deuterated layer 506 and charge-trapping layer 508 may be composed of any material described in association with deuterated layer 406 and charge-trapping layer 408, respectively, from Figure 4.
• second deuterated layer 516 may also be composed of any material described in association with deuterated layer 406 from Figure 4.
• the total thickness of multilayer charge- trapping region 504B is in the range of 5 - 10 nanometers, i.e.
• multi-layer charge-trapping region 504B has a thickness in the same range as multi-layer charge trapping region 404B from Figure 4.
• the relative ratios of thicknesses of deuterated layers and the charge- trapping layer may differ from those of semiconductor device 400.
• the ratio of thicknesses of first deuterated layer 506:charge-trapping layer 508:second deuterated layer 516 is approximately 1:2:1, respectively.
• multilayer charge-trapping region 504B may have an abrupt interface between first deuterated layer 506 and charge-trapping layer 508.
• second abrupt interface may exist between second deuterated layer 516 and charge-trapping layer 508.
• charge-trapping layer 508 is deuterium-free.
• a gradient of deuterium atom concentration moving from high concentration of deuterium in first and second deuterated layers 506 and 516 ranging to low concentration of deuterium in charge-trapping layer 508 may be formed.
• charge- trapping layer 508 is a partially deuterated layer, but having a deuterium concentration less than that of deuterated layers 506 and 516.
• a nonvolatile charge trap memory device may be fabricated to include a multi-layer charge-trapping region having a deuterated layer.
• Figures 6A-I illustrate cross-sectional views representing steps in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• Substrate 602 may be composed of any material and have any characteristics described in association with substrates 402 and 502 from Figures 4 and 5, respectively.
• tunnel dielectric layer 620 is formed on the top surface of substrate 602.
• Tunnel dielectric layer 620 may be formed from any material, from any process, and have any thickness described in association with tunnel dielectric layers 404A and 504A from Figures 4 and 5, respectively.
• multi-layer charge-trapping region 622 is formed on the top surface of tunnel dielectric layer 620.
• multi-layer charge-trapping region 622 includes a deuterated layer 624 between tunnel dielectric layer 620 and a charge-trapping layer 626, as depicted in Figure 6C.
• Deuterated layer 624 and charge-trapping layer 626 may be composed of any materials and have any thicknesses described in association with deuterated layer 406 and charge-trapping layer 408, respectively, from Figure 4.
• Multi-layer charge-trapping region 622 and, hence, deuterated layer 624 and charge-trapping layer 626 may be formed by any process suitable to provide substantially uniform coverage above tunnel dielectric layer 620.
• multilayer charge-trapping region 622 is formed by a chemical vapor deposition process.
• deuterated layer 624 is formed first using deuterated formation gases and, subsequently, charge-trapping layer 626 is formed next using non-deuterated formation gases.
• multi-layer charge-trapping region 622 is composed substantially of silicon oxy-nitride, wherein deuterated layer 624 is first formed using formation gases such as, but not limited to, deuterated silane (SiD 4 ), deuterated dichlorosilane (Sil ⁇ Ch), nitrous oxide (N 2 0), deuterated ammonia (ND 3 ) and oxygen (O 2 ).
• Charge-trapping layer 626 is then formed using formation gases such as, but not limited to, non-deuterated-bis (tert-butylamino) silane (non-deuterated-BTBAS), silane embodiment, deuterated layer 624 and charge-trapping layer 626 are formed in the same process step, i.e., they are formed in the same process chamber with a seamless transition from deuterated formation gases to non-deuterated formation gases.
• formation gases such as, but not limited to, non-deuterated-bis (tert-butylamino) silane (non-deuterated-BTBAS)
• silane embodiment deuterated layer 624 and charge-trapping layer 626 are formed in the same process step, i.e., they are formed in the same process chamber with a seamless transition from deuterated formation gases to non-deuterated formation gases.
• An abrupt deuterated and non-deuterated junction may be present at the interface of deuterated layer 624 and charge-trapping layer 626.
• charge-trapping layer 626 remains deuterium free.
• some of the deuterium present in deuterated layer 624 may migrate to charge-trapping layer 626 during the deposition of charge-trapping layer 626 or during subsequent high temperature process steps. That is, a gradient of deuterium atom concentration moving from high concentration of deuterium in deuterated layer 624 ranging to low concentration of deuterium in charge-trapping layer 626 may be formed.
• charge trapping layer 626 becomes a partially deuterated layer, but having a deuterium concentration less than that of deuterated layer 624.
• deuterated formation gases are employed to form a partially deuterated charge-trapping layer 626 having a deuterium concentration less than that of deuterated layer 624.
• top dielectric layer 628 is formed on the top surface of multi-layer charge-trapping region 622.
• Top dielectric layer 628 may be formed from any material, from any process, and have any thickness described in association with top dielectric layers 404C and 504C from Figures 4 and 5, respectively.
• top dielectric layer 628 is formed by using deuterated formation gases.
• deuterated top dielectric layer 628 subsequently acts as a source of deuterium to form a trap-free layer in multi-layer charge-trapping region 622 during a subsequent anneal process.
• deuterated top dielectric layer 628 is formed using formation gases such as, but not limited to, SiD4, SiD2Cl 2 and N 2 0.
• a gate layer 630 is formed on the top surface of top dielectric layer 628.
• Gate layer 630 may be formed from any material and from any process described in association with gate layers 404D and 504D from Figures 4 and 5, respectively.
• a gate stack 632 may be formed above substrate 602.
• gate stack 632 is patterned to form a patterned gate stack 604 above substrate 602.
• Patterned gate stack 604 includes a patterned tunnel dielectric layer 604A, a patterned multi-layer charge-trapping region 604B, a patterned top dielectric layer 604C, and a patterned gate layer 604D.
• Patterned multi-layer charge trapping region 604B includes a patterned deuterated layer 606 and a patterned charge trapping layer 608.
• Gate stack 632 may be patterned to form patterned gate stack 604 by any process suitable to provide substantially vertical sidewalls for gate stack 604 with high selectivity to substrate 602.
• gate stack 632 is patterned to form patterned gate stack 604 by a lithography and etch process.
• the etch process is an anisotropic etch process utilizing gases such as, but not limited to, carbon tetrafluoride (CF 4 ), O 2 , hydrogen bromide (HBr) and chlorine (Cl 2 ).
• Source and drain tip extension regions 650 will ultimately become part of source and drain regions subsequently formed, as described below.
• channel region 612 may be defined, as depicted in Figure 6G.
• the conductivity type and the concentration of dopant impurity atoms used to form source and drain tip extension regions 650 are substantially the same as those used to form source and drain regions, described below.
• Source and drain regions 610 are formed by implanting dopant impurity atoms 660 into the exposed portions of substrate 604. Source and drain regions 610 may have any characteristics as those described in association with source and drain regions 410 and 510 from Figures 4 and 5, respectively. In accordance with an embodiment of the present invention, the profile of source and drain regions 610 is defined by dielectric spacers 614, patterned gate stack 604 and source and drain tip extension regions 650, as depicted in Figure 61.
• a nonvolatile charge trap memory device may be fabricated to include a multi-layer charge-trapping region having more than one deuterated layer.
• Figures 7A-C illustrate cross-sectional views representing steps in the formation of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.
• a tunnel dielectric layer 720 formed on the top surface of a substrate 702 is provided.
• Substrate 702 may be composed of any material and have any characteristics described in association with substrates 402 and 502 from Figures 4 and 5, respectively.
• Tunnel dielectric layer 720 may be formed from any material, from any process, and have any thickness described in association with tunnel dielectric layers 404A and 504A from Figures 4 and 5, respectively.
• a multi-layer charge-trapping region 722 is formed on the top surface of tunnel dielectric layer 720.
• multi-layer charge-trapping region 722 includes a first deuterated layer 724 between tunnel dielectric layer 720 and a charge-trapping layer 726. Additionally multi-layer charge-trapping region 722 includes a second deuterated layer 727 on the top surface of charge-trapping layer 726, as depicted in Figure 7B.
• First deuterated layer 724, charge-trapping layer 726, and second deuterated layer 727 may be composed of any materials and have any thicknesses described in association with first deuterated layer 506, charge-trapping layer 508, and second deuterated layer 516, respectively, from Figure 5.
• Multi-layer charge-trapping region 722 and, hence, first and second deuterated layers 724 and 727 and charge-trapping layer 726 may be formed by any process suitable to provide substantially uniform coverage above tunnel dielectric layer 720.
• multi-layer charge-trapping region 722 is formed by a chemical vapor deposition process.
• first deuterated layer 724 is formed first using deuterated formation gases
• charge-trapping layer 726 is formed next using non-deuterated formation gases
• second deuterated layer 727 is formed using deuterated formation gases.
• multi-layer charge-trapping region 722 is composed substantially of silicon oxy-nitride, wherein first deuterated layer 724 is formed first using formation gases such as, but not limited to, SiD 4 , SiD 2 Cl 2 , N 2 O, ND 3 and O 2 .
• Formation gases such as, but not limited to, SiD 4 , SiD 2 Cl 2 , N 2 O, ND 3 and O 2 .
• Charge-trapping layer 626 is then formed using formation gases such as, but not limited to, non-deuterated- BTBAS, SiH 4 , SiH 2 Cl 2 , N 2 O, NH 3 and O 2 .
• second deuterated layer 727 is formed using formation gases such as, but not limited to, SiD 4 , SiD 2 Cl 2 , N 2 O, ND 3 and O 2 .
• first deuterated layer 724, charge-trapping layer 726 and second deuterated layer 727 are formed in the same process step, i.e. in the same process chamber with a seamless transition from deuterated formation gases to non-deuterated formation gases and back to deuterated formation gases.
• An abrupt deuterated and non-deuterated junction may be present at the interfaces of first deuterated layer 724, second deuterated layer 727 and charge-trapping layer 726.
• charge trapping layer 726 remains deuterium-free.
• some of the deuterium present in first and second deuterated layers 724 and 727 may migrate to charge-trapping layer 726 during the deposition of charge-trapping layer 726 and second deuterated layer 727 or during subsequent high temperature process steps. That is, a gradient of deuterium atom concentration moving from high concentration of deuterium in first and second deuterated layers 724 and 727 ranging to low concentration of deuterium in charge- trapping layer 726 may be formed.
• charge-trapping layer 726 becomes a partially deuterated layer, but having a deuterium concentration less than that of first and second deuterated layers 724.
• deuterated formation gases are employed to form a partially deuterated charge-trapping layer 726 having a deuterium concentration less than that of deuterated layer 724.
• a patterned gate stack 704 is formed over a substrate 702. Source and drain regions 710 are formed on either side of patterned gate stack 704, defining a channel region 712.
• Patterned gate stack 704 includes a patterned tunnel dielectric layer 704A, a patterned multi-layer charge-trapping region 704B, a patterned top dielectric layer 704C and a patterned gate layer 704D.
• Patterned multi-layer charge-trapping region 704B includes a patterned first deuterated layer 706 and a patterned second deuterated layer 716 sandwiching patterned charge-trapping layer 708.
• the present disclosure is directed to charge trap memory devices including one or more deuterated layers and a split multi-layer charge-trapping region with two or more nitride containing layers.
• Figure 8A is a block diagram illustrating a cross-sectional side view of one such embodiment.
• the memory device 800 includes a gate stack
• the device 800 further includes one or more diffusion regions 810, such as source and drain regions or structures, aligned to the gate stack 802 and separated by a channel region 812.
• diffusion regions 810 such as source and drain regions or structures
• a thin, tunnel dielectric layer 814 that separates or electrically isolates the gate stack from the channel region 812, a top or blocking dielectric layer 816, and a gate layer 818.
• the multi-layer charge-trapping region 804 generally includes at least two layers having differing compositions of silicon, oxygen and nitrogen.
• the multi-layer charge-trapping region includes a first nitride layer 820 comprising a substantially trap-free, silicon-rich, oxygen-rich nitride, and a second nitride layer 822 comprising a trap-dense, silicon-rich, nitrogen-rich, and oxygen-lean nitride. It has been found that a silicon-rich, oxygen-rich, first nitride layer 820 decreases the charge loss rate after programming and after erase, which is manifested in a small voltage shift in the retention mode.
• a silicon-rich, nitrogen-rich, and oxygen-lean second nitride layer 816 improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory devices made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device.
• the multi-layer charge-trapping region 804 further includes one or more deuterated layers.
• the multi-layer charge-trapping region 804 includes a first deuterated layer 824 separating the first nitride layer 820 from the tunnel dielectric layer 814, and a second deuterated layer 826 separating the second nitride layer 822 from the blocking dielectric layer 818.
• the first and second deuterated layers 824, 826 can be composed of a deuterated derivative of the same material used to form the first and second nitride layers 820, 822.
• the first and second deuterated layers 824, 826 can be composed of a deuterated derivative of silicon oxynitride.
• the total thickness of multi-layer charge-trapping region 804 is in the range of 5 - 10 nanometers, the thicknesses of the individual deuterated layers and nitride layers is approximately equal.
• Multi-layer charge-trapping region 804 may have an abrupt interface between the first deuterated layer 824 and the first nitride layer 820. That is, in accordance with one embodiment, the first nitride layer 820. Alternatively, a gradient of deuterium atom concentration moving from high concentration of deuterium in the first deuterated layer 824 ranging to low concentration of deuterium in the first nitride layer 820 may be formed. Thus, in accordance with an alternative embodiment, the first nitride layer 820 is a partially deuterated layer, but having a deuterium concentration less than that of the first deuterated layer 824.
• Substrate 808 and, hence, channel region 812 may be composed of any material suitable for semiconductor device fabrication.
• substrate 802 is a bulk substrate composed of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material.
• substrate 808 includes a bulk layer with a top epitaxial layer composed of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, a ⁇ -V compound semiconductor material and quartz in and on which the memory device 800 is fabricated.
• Substrate 808 and, hence, channel region 812 may include dopant impurity atoms.
• the channel region 812 includes polycrystalline silicon or polysilicon and is doped P-type, or, in an alternative embodiment, doped N-type. In another specific embodiment, the channel region 812 includes recrystallized polysilicon and is doped either P-type or N-type.
• Source and drain regions 810 in substrate 808 may be any regions having opposite conductivity to channel region 812. For example, in one embodiment, the source and drain regions 810 are N-type doped regions while channel region 812 is a P-type doped region.
• the substrate 808 and, hence, channel region 812 is composed of boron-doped silicon having a boron concentration in the range of 1 x 10 15 - 1 x 10 19 atoms/cm 3 .
• Source and drain regions 810 are composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5 x 10 16 -5 x 10 19 atoms/cm 3 .
• source and drain regions 810 have a depth in substrate 808 in the range of 80-200 nanometers.
• source and drain regions 810 are P-type doped regions while channel region 812 is an N-type doped region.
• the tunnel dielectric layer 814 may be any material and have any thickness suitable to allow charge carriers to tunnel into the multi-layer charge-trapping region 804 under an applied gate bias while maintaining a suitable barrier to leakage when the memory device 800 is unbiased.
• tunnel dielectric layer 814 is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxy-nitride, or a combination thereof.
• tunnel dielectric layer 814 is formed by chemical vapor deposition or atomic layer deposition and is composed of a dielectric layer which may include, but is not limited to, silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
• tunnel dielectric layer 814 has a thickness in the range of 1-10 nanometers. In a particular embodiment, tunnel dielectric layer 814 has a thickness of approximately 2 nanometers.
• the blocking dielectric layer 816 may be any material and have any thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of gate stack 802.
• the blocking dielectric layer 816 is formed by a chemical vapor deposition process and is composed of silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof.
• the blocking dielectric layer 816 is formed by atomic layer deposition and is composed of a high-k dielectric layer which may include, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
• the blocking dielectric layer 816 has a thickness in the range of 1-20 nanometers.
• Gate layer 818 may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SONOS-type transistor, including doped polysilicon and a metal-containing material. In a specific embodiment, the gate layer 818 has a thickness in the range of 1-20 nanometers.
• the multi-layer charge- trapping region 804 further includes an intermediate oxide or anti-tunneling layer 828 comprising an oxide separating the first nitride layer 820 from the second nitride layer 822.
• an erase of the memory device 800 holes migrate toward the blocking dielectric layer 816, but the majority of trapped hole charges form in the second nitride layer 822. Electron charge accumulates at the boundaries of the second nitride layer 822 after programming, and thus there is less accumulation of charge at the lower boundary of the first nitride layer 820.
• the anti-tunneling layer 828 the probability of tunneling by trapped electron charges in the second layer 822 is substantially reduced. This may result in lower leakage current than for the conventional memory devices.
• the multi-layer charge-trapping region may include a number, n, of nitride layers, any or all of which may have differing stoichiometric compositions of oxygen, nitrogen and/or silicon.
• n nitride layers
• multi-layer charge storing structures having up to five, and possibly more, nitride layers each with differing stoichiometric compositions are contemplated. At least some of these layers will be separated from the others by one or more relatively thin oxide layers.
• the method begins with forming a tunnel dielectric layer over a silicon containing layer on a surface of a substrate (900).
• the tunnel dielectric layer comprises silicon dioxide (SiO 2 ) and is formed or deposited a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process in which hydrogen (H 2 ) and oxygen (0 2 ) gas are introduced into a process chamber to form radicals at a surface of the substrate to consume a portion of the substrate form the tunnel dielectric layer without an ignition event to pyrolyze the 3 ⁇ 4 and O 2 .
• the first deuterated layer is then formed on a surface of the tunneling dielectric layer (902).
• the first deuterated layer can be formed or deposited in a low pressure CVD process using a process gas comprising a silicon source, such as silane (SiH4), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCl 4 ) or Bis-TertiaryButylAmino Silane (BTBAS), an oxygen source, such as oxygen ( O 2 ) or N 2 O, and a nitrogen source containing deuterium, such as deuterated-ammonia (ND 3 ).
• a silicon source such as silane (SiH4), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCl 4 ) or Bis-TertiaryButylA
• the first nitride or nitride containing layer of the multi-layer charge- trapping region is formed on a surface of the first deuterated layer (904).
• the first nitride layer is formed or deposited in a low pressure CVD process using a silicon source, such as silane (SiH 4 ), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCU) or Bis-TertiaryButylArnino Silane (BTBAS), a nitrogen source, such as nitrogen (N 2 ), ammonia (NH 3 ), nitrogen trioxide (NO3) or nitrous oxide (N 2 O), and an oxygen-containing gas, such as oxygen (O 2 ) or N 2 O.
• a silicon source such as silane (SiH 4 ), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2
• the first nitride layer can be deposited over the first deuterated layer by placing the substrate in a deposition chamber and introducing a process gas including N 2 O, NH 3 and DCS, while maintaining the chamber at a pressure of from about 5 milliTorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes.
• a process gas including N 2 O, NH 3 and DCS
• the process gas can include a first gas mixture of N 2 0 and N3 ⁇ 4 mixed in a ratio of from about 8: 1 to about 1 :8 and a second gas mixture of DCS and NH 3 mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (seem). It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, oxygen-rich, first nitride layer.
• an anti-tunneling layer is then formed or deposited on a surface of the first nitride layer (906).
• the anti-tunneling layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process.
• the radical oxidation process involves flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a batch- processing chamber or furnace to effect growth of the anti-tunneling layer by oxidation consumption of a portion of the first nitride layer.
• the second nitride layer of the multi-layer charge-trapping region is then formed on a surface of the anti-tunneling layer (908).
• the second nitride layer can be deposited over the anti-tunneling layer in a CVD process using a process gas including N 2 O, NH 3 and DCS, at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes.
• the process gas can include a first gas mixture of N 2 0 and NH 3 mixed in a ratio of from about 8:1 to about 1 :8 and a second gas mixture of DCS and NH 3 mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 20 seem. It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, nitrogen-rich, and oxygen-lean second nitride layer.
• the second nitride layer can be deposited over the anti-tunneling layer in a CVD process using a process gas including BTBAS and ammonia ( ⁇ H 3 ) mixed at a ratio of from about 7:1 to about 1:7 to further include a concentration of carbon selected to increase the number of traps therein.
• the selected concentration of carbon in the second oxynitride layer can include a carbon concentration of from about 5% to about 15%.
• the method of fabricating the memory device can further include forming the second deuterated layer on the second nitride layer (910).
• the second deuterated layer can be formed or deposited in a low pressure CVD process using a process gas comprising a silicon source, such as silane (SiH 4 ), chlorosilane (S-H 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCl 4 ) or Bis-TertiaryButylAmino Silane (BTBAS), an oxygen source, such as oxygen (O 2 ) or N 2 O, and a nitrogen source containing deuterium, such as deuterated-ammonia (ND 3 ).
• a silicon source such as silane (SiH 4 ), chlorosilane (S-H 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCl 4 ) or Bis
• a top or blocking dielectric layer is formed on a surface of the second nitride layer of the multi-layer charge-trapping region or the second deuterated layer (912).
• the blocking dielectric layer can include any suitable dielectric material including a high K dielectric, silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof.
• the blocking dielectric layer includes a relatively thick layer of SiO 2 thermally grown or deposited using a CVD process.
• the process involves exposing the substrate to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as 0 2 or N 2 O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650°C to about 850°C.
• a silicon source such as silane, chlorosilane, or dichlorosilane
• an oxygen-containing gas such as 0 2 or N 2 O
• the blocking dielectric layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process.
• a gate layer is formed on a surface of the blocking dielectric layer
• the gate layer is formed by a CVD process and is composed of doped polysilicon.
• the gate layer is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel.
• multigate or multigate-surface memory devices including charge-trapping regions overlying two or more sides of a channel region formed on or above a surface of a substrate, and methods of fabricating the same.
• Multigate devices include both planar and non-planar devices.
• a planar multigate device (not shown) generally includes a double-gate planar device in which a number of first layers are deposited to form a first gate below a subsequently formed channel region, and a number of second layers are deposited thereover to form a second gate.
• a non-planar multigate device generally includes a horizontal or vertical channel region formed on or above a surface of a substrate and surrounded on three or more sides by a gate.
• Figure 10A illustrates one embodiment of a non-planar multigate memory device including a charge-trapping region.
• the memory device 1000 commonly referred to as a finFET, includes a channel region 1002 formed from a thin film or layer of semiconducting material overlying a surface 1004 on a substrate 1006 connecting a source 1008 and a drain 1010 of the memory device.
• the channel region 1002 is enclosed on three sides by a fin which forms a gate 1012 of the device.
• the thickness of the gate 1012 (measured in the direction from source to drain) determines the effective channel l ength of the device.
• the non-planar multigate memory device 1000 of Figure 10A can include a split charge-trapping region with one or more deuterated layers.
• Figure 10B is a cross-sectional view of a portion of the non- planar memory device of Figure 10A including a portion of the substrate 1006, channel region 1002 and the gate stack 1012 illustrating a multi-layer charge-trapping region 1014.
• the gate 1012 further includes a tunnel dielectric layer 1016 overlying the raised channel region 1002, a blocking dielectric 1018 and a gate layer 1020 overlying the blocking layer to form a control gate of the memory device 1000.
• the gate layer 1020 can include a metal or a doped polysilicon.
• the channel region 1002 and gate 1012 can be formed directly on substrate 1006 or on an insulating or dielectric layer 1022, such as a buried oxide layer, formed on or over the substrate.
• the multi-layer charge- trapping region 1014 includes at least a first deuterated layer 1024 overlying the tunnel dielectric layer 1016, a first nitride layer 1026 overlying the first deuterated layer 1024, and a second nitride layer 1028 disposed on or above the first nitride layer.
• the second nitride layer 1028 includes a silicon-rich, oxygen-lean nitride layer and includes a majority of a charge traps distributed in multiple charge-trapping layers, while the first nitride layer 1026 includes an oxygen-rich nitride or silicon oxynitride, and is oxygen- rich relative to the top charge-trapping layer to reduce the number of charge traps therein.
• oxygen-rich it is meant wherein a concentration of oxygen in the first nitride layer 1026 is from about 15 to about 40%, whereas a concentration of oxygen in top charge- trapping layer 1026 is less than about 5%.
• the multi-layer charge-trapping region 1014 further includes at least one thin, intermediate oxide or anti-tunneling layer 1030 separating the second nitride layer 1028 from the first nitride layer 1026.
• the anti-tunneling layer 1030 substantially reduces the probability of electron charge that accumulates at the boundaries of the second nitride layer 1028 during programming from tunneling into the first nitride layer 1026.
• first nitride layer 1026 and the second nitride layer 1028 can include silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O NH 3 and DCS NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.
• the second nitride layer of the multi-layer charge-trapping region is then formed on the middle oxide layer.
• the second nitride layer 1028 has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first nitride layer 1026, and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 O/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean second nitride layer 1028.
• the anti-tunneling layer can be formed by oxidation of the first nitride layer 1026, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800- 900 degrees Celsius using a batch reactor tool. A mixture of H 2 and O 2 gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min -1 hour using a batch process.
• the multi-layer charge-trapping region 1014 further includes a second deuterated layer 1032 overlying the second nitride layer 1028 and separating the second nitride layer from the blocking dielectric layer 1018.
• the second deuterated layer 1032 has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer 1024.
• the memory device can include a nanowire channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device.
• nanowire channel it is meant a conducting channel region formed in a thin strip of crystalline silicon material, having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and more preferably less than about 6 nm.
• the channel region can be formed to have ⁇ 100> surface crystalline orientation relative to a long axis of the channel region.
• the memory device 1100 includes a horizontal nanowire channel region 1102 formed from a thin film or layer of semiconducting material on or overlying a surface on a substrate 1106, and connecting a source 1108 and a drain 1110 of the memory device.
• the device has a gate-all- around (GAA) structure in which the nanowire channel region 1102 is enclosed on all sides by a gate 1112 of the device.
• the thickness of the gate 1112 determines the effective channel region length of the device.
• the non-planar multigate memory device 1100 of Figure 11 A can include a split multi-layer charge-trapping region.
• Figure 11B is a cross-sectional view of a portion of the non-planar memory device of Figure 11 A including a portion of the substrate 1106, nanowire channel region 1102 and the gate 1112 illustrating a split multi-layer charge-trapping region.
• the gate 1112 includes, in addition to a split multi-layer charge-trapping region, a tunnel dielectric layer 1114 overlying the nanowire channel region 1102, a blocking dielectric 1116 and a gate layer 1118 overlying the blocking layer to form a control gate of the memory device 1100.
• the gate layer 1118 can comprise a metal or a doped polysilicon.
• the split multi-layer charge-trapping region includes at least a first deuterated layer 1120 overlying the tunnel dielectric layer 1114, an inner or first nitride layer 1122 or layer comprising nitride overlying the first deuterated layer 1120, and an outer or second nitride layer 1124 or layer comprising nitride overlying the first nitride layer 1122.
• the second nitride layer 1124 comprises a silicon-rich, oxygen- lean nitride layer and comprises a majority of a charge traps distributed in split multilayer charge-trapping region, while the first nitride layer 1122 comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the second nitride layer 1124 to reduce the number of charge traps therein.
• the multi-layer charge-trapping region further includes at least one thin, intermediate oxide or anti-tunneling layer 1126 separating the second nitride layer 1124 from the first nitride layer 1122.
• the anti-tunneling layer 1126 substantially reduces the probability of electron charge that accumulates at the boundaries of the second nitride layer 1124 during programming from tunneling into the first nitride layer 1122.
• first nitride layer 1122 and the second nitride layer 1124 can comprise silicon nitride or silicon oxynitride.
• the first nitride layer 1122 can be formed, for example, by a CVD process including N 2 O/NH 3 and DCS/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich first nitride layer.
• the second nitride layer 1124 has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first nitride layer 1122, and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 O/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean second nitride layer.
• the anti-tunneling layer can be formed by oxidation of the first nitride layer 1122, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800- 900 degrees Celsius using a batch reactor tool. A mixture of 3 ⁇ 4 and 0 2 gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min -1 hour using a batch process.
• the multi-layer charge-trapping region 1014 further includes a second deuterated layer 1 128 overlying the second nitride layer 1124 and separating the second nitride layer from the blocking dielectric layer 1116.
• the second deuterated layer 1128 has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer 1120.
• FIG 11C illustrates a cross-sectional view of a vertical string of non- planar multigate devices 1100 of Figure 11A arranged in a Bit-Cost Scalable or BiCS architecture 1130.
• the architecture 1130 consists of a vertical string or stack of non- planar multigate devices 1100, where each device or cell includes a channel region 1102 overlying the substrate 1106, and connecting a source and a drain (not shown in this figure) of the memory device, and having a gate-all-around (GAA) structure in which the nanowire channel region 1102 is enclosed on all sides by a gate 1112.
• GAA gate-all-around
• the BiCS architecture reduces number of critical lithography steps compared to a simple stacking of layers, leading to a reduced cost per memory bit.
• the memory device is or includes a non-planar device comprising a vertical nanowire channel formed in or from a semiconducting material projecting above or from a number of conducting, semiconducting layers on a substrate.
• the memory device 1200 comprises a vertical nanowire channel region 1202 formed in a cylinder of semiconducting material connecting a source 1204 and drain 1206 of the device.
• the channel region 1202 is surrounded by a tunnel dielectric layer 1208, a multilayer charge-trapping region 1210, a blocking layer 1212 and a gate layer 1214 overlying the blocking layer to form a control gate of the memory device 1200.
• the channel region 1202 can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or can include an annular layer formed over a cylinder of dielectric filler material.
• the channel region 1202 can comprise poly silicon or recrystallized polysilicon to form a monocrystalline channel.
• the channel region 1202 includes a crystalline silicon, the channel can be formed to have ⁇ 100> surface crystalline orientation relative to a long axis of the channel.
• the multi-layer charge-trapping region 12 0 can be a split multi-layer charge-trapping region including at least a first deuterated layer 1216 overlying the tunnel dielectric layer 1208, an inner or first nitride layer 1218 or layer comprising nitride overlying the first deuterated layer 1216, and an outer or second nitride layer 1220 or layer comprising nitride overlying the first nitride layer 1218.
• the first and second nitride layers 1218, 1220 can be separated by an intermediate oxide or anti-tunneling layer 1222.
• first nitride layer 1218 and the second nitride layer 1220 can comprise silicon nitride or silicon oxynitride.
• the first nitride layer 1218 can be formed, for example, by a CVD process including N 2 O NH 3 and DCS/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich first nitride layer.
• the second nitride layer 1220 has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first nitride layer 1218, and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 O/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean second nitride layer.
• the multi-layer charge-trapping region 1210 further includes a second deuterated layer 1224 overlying the second nitride layer 1220 and separating the second nitride layer from the blocking dielectric layer 1212.
• the second deuterated layer 1224 has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer 1216.
• a nonvolatile charge trap memory device includes a substrate having a channel region and a pair of source and drain regions.
• a gate stack is above the substrate over the channel region and between the pair of source and drain regions.
• the gate stack includes a multi-layer charge-trapping region having a first deuterated layer.
• the multi-layer charge-trapping region further includes a deuterium-free charge-trapping layer.
• the multi-layer charge-trapping region includes a partially deuterated charge-trapping layer having a deuterium concentration less than that of the first deuterated layer.

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