WO2013183472A1 - Variable capacitance element, high-frequency device, and communication device - Google Patents

Variable capacitance element, high-frequency device, and communication device Download PDF

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Publication number
WO2013183472A1
WO2013183472A1 PCT/JP2013/064578 JP2013064578W WO2013183472A1 WO 2013183472 A1 WO2013183472 A1 WO 2013183472A1 JP 2013064578 W JP2013064578 W JP 2013064578W WO 2013183472 A1 WO2013183472 A1 WO 2013183472A1
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Prior art keywords
resistance
capacitance element
variable capacitance
capacitor
film
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PCT/JP2013/064578
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French (fr)
Japanese (ja)
Inventor
竹島裕
中磯俊幸
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201390000526.9U priority Critical patent/CN204442303U/en
Priority to JP2013557963A priority patent/JP5673865B2/en
Publication of WO2013183472A1 publication Critical patent/WO2013183472A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
    • G06K7/10237—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the reader and the record carrier being capable of selectively switching between reader and record carrier appearance, e.g. in near field communication [NFC] devices where the NFC device may function as an RFID reader or as an RFID tag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G06K19/0726—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07771—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G7/00—Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
    • H01G7/06—Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H04B5/26—
    • H04B5/45—
    • H04B5/77—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations

Definitions

  • the present invention relates to a variable capacitance element, a high-frequency device, and a communication apparatus used in an RFID (Radio Frequency Identification) system and a near field communication (NFC) system.
  • RFID Radio Frequency Identification
  • NFC near field communication
  • NFC is a short-range wireless communication standard using the 13 MHz band, and is expected to be installed in various terminals including mobile communication terminals.
  • an RF IC for NFC is built in the terminal body, and the RFIC for NFC is connected to an NFC antenna coil that is also built in the terminal body.
  • the antenna coil is connected to a capacitive element so as to resonate at a communication frequency, and the capacitive element and the antenna coil constitute an antenna circuit.
  • the antenna circuit, NFC RFIC, and the like constitute a wireless communication module (hereinafter referred to as “NFC module”).
  • the communication frequency of the NFC module is determined in advance, but the resonance frequency of the antenna circuit to be adjusted differs little by little depending on the use conditions and manufacturing variations.
  • the circuit configuration as the resonance circuit of the antenna circuit changes between the reader / writer mode and the card mode. Therefore, in order to maintain a predetermined resonance frequency in either mode, it is necessary to adjust the resonance circuit according to the mode.
  • the use conditions vary depending on the NFC module mounting environment.
  • the resonance frequency of the antenna circuit changes depending on whether or not metal is present near the NFC module.
  • Patent Document 1 As a method for adjusting the resonance frequency, it is known to configure a capacitor of an antenna circuit with a variable capacitance element that can change a capacitance value by an applied voltage (see Patent Document 1). Further, Patent Document 2 discloses a circuit in which the entire capacitance value is switched by selectively connecting a plurality of capacitors.
  • FIG. 12 shows an example of a communication circuit disclosed in Patent Document 2.
  • the non-contact IC unit 47 includes a non-contact IC chip, a capacitor Cin and parallel capacitors C101 to C103, an antenna parallel capacitor unit having switches SW1 to SW3, and an antenna L1.
  • the electric capacities of the capacitor Cin and the parallel capacitors C101 to C103 are fixed values.
  • SW1 to SW3 are circuits for switching ON / OFF of the connection of the parallel capacitors C101 to C103.
  • a resistance voltage dividing circuit is usually configured to generate the control voltage.
  • the resistance voltage dividing circuit is basically a circuit that allows a bleeder current to flow and extracts a voltage drop due to the resistance, power loss due to the bleeder current occurs.
  • the capacity is fixed to a predetermined value, power loss due to the bleeder current always occurs, which is a problem when applied to a low power consumption communication device using a battery as a power source.
  • the object of the present invention is to solve the problem of distortion due to active elements and the increase in size of the IC due to the complexity of the circuit configuration, to ensure reliability against impacts such as dropping, and to reduce power consumption.
  • An object of the present invention is to provide a variable capacitance element with a control voltage application circuit, a high-frequency device, and a communication apparatus.
  • variable capacitance element of the present invention is configured as follows.
  • a ferroelectric film having a ferroelectric film and a capacitor electrode sandwiching the ferroelectric film, the capacitance value of which varies according to a control voltage value applied between the capacitor electrodes;
  • a plurality of control terminals (for example, terminals to which external GPIO terminals are connected), each having a resistance voltage dividing circuit including a plurality of resistance elements each having a first end connected to a common connection point and a second end connected to the common connection;
  • a control voltage application circuit for applying a voltage at a point to the variable capacitance element,
  • the resistance voltage dividing circuit is composed of a plurality of sets of resistance voltage dividing circuits whose common connection points are independent from each other, and is non-conductive in a direct current state by the ferroelectric capacitor or another capacitor.
  • This configuration eliminates the problem of distortion because a switch that is an active element is not used, and the size of the IC is reduced with the simplification of the circuit configuration, and it is easy to ensure reliability against impacts such as dropping. Furthermore, since the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
  • the plurality of resistance elements are resistance patterns provided on a substrate, and the resistance pattern is a power of 2 on the basis of a resistance value of the plurality of resistance elements being the lowest of the resistance values. It is preferable to form so that it may become a ratio.
  • the value of the control data and the control voltage for the variable capacitance element can be in a linear relationship, and multi-stage setting can be easily performed with constant resolution.
  • variable capacitance element and the control voltage application circuit are formed on the substrate by a thin film process, and the plurality of resistance elements are formed on the same layer on the substrate by the same process. Preferably there is.
  • the number of parts is reduced, the routing of the data transmission line becomes very simple, and the communication circuit can be reduced in size and weight.
  • the ratio between the resistance elements is stabilized. Therefore, the voltage dividing ratio of the resistance voltage dividing circuit is constant, and a predetermined stable control voltage can always be applied to the variable capacitance element.
  • the variable capacitance element includes a plurality of RF resistance elements connected in parallel to both ends of the ferroelectric capacitor, and these RF resistance elements are provided in a layer different from the plurality of resistance elements. It is preferable.
  • the RF resistance element and the resistance-dividing resistance element can be independently set to optimum resistance values.
  • a high-frequency device includes a variable capacitance element according to any one of (1) to (4) and an RFIC connected to an external terminal of the variable capacitance element provided in one chip. It is. With this configuration, the number of components mounted on a circuit board and wiring space in an electronic device such as a communication device can be reduced, and the size can be reduced.
  • the communication device of the present invention is a communication device including an antenna coil, a variable capacitance element connected to the antenna coil, and an RFIC connected to the variable capacitance element,
  • the variable capacitance element is the variable capacitance element according to any one of (1) to (4),
  • the RFIC can take a state in which all of the external terminals connected to at least one of the plurality of resistance voltage dividing circuits are at a high potential or all at a low potential.
  • the active element switch is not used, so there is no problem of distortion, the IC size is reduced along with the simplification of the circuit configuration, and it is easy to ensure reliability against impacts such as dropping, Since the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
  • a ferroelectric capacitor in which a ferroelectric film is sandwiched between capacitor electrodes is used as a variable capacitance element for controlling the resonance frequency of the antenna coil, and a control voltage is applied to the ferroelectric capacitor.
  • a control voltage application circuit for applying a plurality of resistance elements having different resistance values are used. Therefore, although it is small in size, distortion is unlikely to occur and the frequency characteristics are stable and highly reliable control.
  • a variable capacitance element with a voltage application circuit and a high-frequency device can be realized.
  • variable capacitance element that requires mechanical control unlike a trimmer capacitor
  • a variable capacitance element with a control voltage application circuit that is highly reliable against an impact such as a drop despite being small, and A high-frequency device can be realized.
  • the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
  • FIG. 1 is an overall circuit diagram of the inside of the variable capacitor 101 according to the first embodiment.
  • FIG. 2 is a diagram illustrating a state where no bleeder current flows through the variable capacitance element 101 according to the first embodiment.
  • FIG. 3 is a diagram showing a relationship between an applied voltage step represented by a 5-bit binary signal inputted to the control terminals P21 to P25 and a capacitance variable ratio.
  • FIG. 4 is a cross-sectional view of the main part of the variable capacitance element 101.
  • FIG. 5 is a circuit diagram of the variable capacitance element 102 according to the second embodiment.
  • FIG. 6 is a circuit diagram of a communication apparatus 201 including a variable capacitance element with a control voltage application circuit and a high-frequency device according to the present invention.
  • FIG. 1 is an overall circuit diagram of the inside of the variable capacitor 101 according to the first embodiment.
  • FIG. 2 is a diagram illustrating a state where no bleeder current flows through the variable capacitance element 101 according
  • FIG. 7 is a three-side view of the RFIC 110 with a built-in variable capacitance element.
  • FIG. 8 is a cross-sectional view of the mounting rewiring board 20 with the variable capacitance element built-in RFIC 110 mounted thereon.
  • FIG. 9 is a circuit diagram of a communication apparatus according to the fourth embodiment.
  • FIG. 10 is a circuit diagram of a variable capacitor as a comparative example of the variable capacitor according to the first embodiment.
  • FIG. 11 is a diagram showing the potential of the control terminals P21 to P25 of the variable capacitance element shown in FIG. 10 and the bleeder current flowing through the resistance voltage dividing circuit.
  • FIG. 12 shows an example of a communication circuit disclosed in Patent Document 2.
  • FIG. 1 is an overall circuit diagram of the inside of the variable capacitor 101 according to the first embodiment.
  • the variable capacitance element 101 includes ferroelectric capacitors C1 to C6 and a control voltage application circuit that applies a control voltage to these ferroelectric capacitors C1 to C6.
  • the ferroelectric capacitors C1 to C6 constitute one series circuit, and the first end of the series circuit is connected to the port P11, and the second end is connected to the port P12.
  • the variable capacitance element 101 is an element in which the capacitance value between the port P11 and the port P12 changes.
  • the voltage applied between the common connection point CC1 and the ground terminal GND is a control voltage for the ferroelectric capacitors C1 to C4.
  • the voltage applied between the common connection point CC2 and the ground terminal GND is a control voltage for the ferroelectric capacitors C5 and C6.
  • RF resistance elements (hereinafter simply “resistances”) R0, R11 to R14, R21 to R23 and resistance voltage dividing resistance elements (hereinafter simply “resistances”) R31 to R35 constitute the control voltage application circuit.
  • a control voltage is applied to the ferroelectric capacitors C1 to C6 via resistors R11, R12, R13, R14 and resistors R21, R22, R23 in the control voltage application circuit.
  • the resistance values of the resistors R11 to R14 and R21 to R23 are equal.
  • resistors R0, R11 to R14, R21 to R23 apply a control voltage to the ferroelectric capacitors C1 to C6, and an RF signal applied between the ports P11 and P12 is connected to the common connection points CC1 and CC2 and the ground terminal. Suppresses leakage to GND.
  • the resistors R31, R32, and R33 constitute a first resistance voltage dividing circuit RDV1
  • the resistors R34 and R35 constitute a second resistance voltage dividing circuit RDV2.
  • the first ends of the resistors R31, R32, and R33 are connected to the control terminals P21, P22, and P23, respectively.
  • the second ends of these resistors R31, R32, R33 are connected to the common connection point CC1.
  • First ends of the resistors R34 and R35 are connected to control terminals P24 and P25, respectively.
  • the second ends of the resistors R34 and R35 are connected to the common connection point CC2.
  • the first resistance voltage dividing circuit RDV1 and the second resistance voltage dividing circuit RDV2 have the common connection points CC1 and CC2 independent of each other. That is, the first resistance voltage dividing circuit RDV1 and the second resistance voltage dividing circuit RDV2 are galvanically insulated by the ferroelectric capacitors C2 to C5 among the plurality of ferroelectric capacitors.
  • a high potential (hereinafter “H level”) or low potential (hereinafter “L level”) voltage (5-bit binary signal) is applied to the control terminals P21 to P25 from the outside.
  • H level high potential
  • L level low potential
  • a divided voltage by the first resistance voltage dividing circuit RDV1 is generated at the common connection point CC1.
  • a divided voltage by the second resistance voltage dividing circuit RDV2 is generated at the common connection point CC2 according to the voltage applied to the control terminals P24 and P25.
  • the first resistance voltage dividing circuit RDV1 and the ferroelectric capacitors C1, C2, C3, C4 belong to the first group G1.
  • the second resistance voltage dividing circuit RDV2 and the ferroelectric capacitors C5 and C6 belong to the second group G2.
  • the capacitance values of the ferroelectric capacitors C1 to C4 of the first group G1 are determined according to the applied voltages to the control terminals P21, P22, P23, and the second group G2 is determined according to the applied voltages to the control terminals P24, P25.
  • the capacitance values of the ferroelectric capacitors C4 and C5 are determined.
  • the capacitance value between the ports P11 and P12 is the value of the series combined capacitance of the ferroelectric capacitors C1 to C6.
  • FIG. 2 is a diagram illustrating a state where no bleeder current flows through the variable capacitance element 101 according to the first embodiment.
  • FIGS. 2A and 2C when the potentials of the control terminals P21, P22, and P23 are at the H level, no current flows in and out of the control terminals P21, P22, and P23.
  • FIGS. 2B and 2D even when the potentials of the control terminals P21, P22, and P23 are at the L level, no current flows in and out of the control terminals P21, P22, and P23.
  • FIGS. 2A and 2C when the potentials of the control terminals P21, P22, and P23 are at the H level, no current flows in and out of the control terminals P21, P22, and P23.
  • FIGS. 2B and 2D even when the potentials of the control terminals P21, P22, and P23 are at the L level, no current flows in and out of the control terminals P21, P22, and P23
  • the bleeder current does not flow if the binary signals for the first group G1 are all at H level or all at L level and the binary signals for the second group G2 are all at H level or all at L level.
  • FIG. 1 a circuit diagram of a variable capacitance element as a comparative example is shown in FIG.
  • one resistance voltage dividing circuit including resistors R31 to R35 is provided, and one ends of the resistors R21, R22, and R23 are connected to a common connection point CC of the resistance voltage dividing circuit via a resistor R4.
  • Others are the same as those of the variable capacitor 101 of the first embodiment.
  • FIG. 11 is a diagram showing the potential of the control terminals P21 to P25 of the variable capacitance element shown in FIG. 10 and the bleeder current flowing through the resistance voltage dividing circuit.
  • the control terminal P21 is at the H level and the control terminals P22 to P25 are at the L level, a parallel circuit of the resistors R32 to R35 and a series circuit of the resistor R31 are formed, and a bleeder current flows and flows to the common connection point CC. A divided voltage is generated.
  • FIG. 3 is a diagram showing a relationship between an applied voltage step represented by a 5-bit binary signal inputted to the control terminals P21 to P25 and a capacitance variable ratio.
  • the conditions (1), (2), (3), and (4) for the resistance value ratio and the capacitance ratio are as follows.
  • step 1 corresponds to when all of the control terminals P21 to P25 are at the L level
  • step 32 corresponds to when all of the control terminals P21 to P25 are at the H level.
  • the “capacity variable ratio” is a change rate based on the capacity at the time of step 1.
  • the resistance values of the resistors R31 to R35 are determined by a power of 2 or a ratio of almost a power of 2 with reference to the lowest one of the resistance values.
  • the ferroelectric capacitors C1 to C6 have nonlinearity in which the capacitance change ratio increases as the applied voltage increases. Therefore, in the case of a circuit configuration in which the magnitude of the control voltage can be switched linearly as in condition (4) IV, the capacitance-voltage characteristic of the ferroelectric capacitor itself appears as it is. That is, the capacitance variable width (sensitivity) for each step is different, so that it is difficult to finely adjust the capacitance value.
  • FIG. 4 is a cross-sectional view of the main part of the variable capacitance element 101.
  • the substrate SI is a Si substrate having a SiO 2 film formed on the surface.
  • a ferroelectric film and a Pt film are alternately formed in this order on the substrate SI in the order of the ferroelectric film FS1, the capacitor electrode PT1, the ferroelectric film FS2, the capacitor electrode PT2, and the ferroelectric film FS3 to form a capacitor portion. ing.
  • a moisture-resistant protective film PC1 is coated on the upper part of the laminated film of these ferroelectric films FS1, FS2, FS3 and capacitor electrodes PT1, PT2.
  • An organic protective film PC2 is further formed on the moisture-resistant protective film PC1.
  • a wiring film TI1 is formed on the organic protective film PC2. Further, the wiring film TI1 is connected to a predetermined portion of the capacitor electrodes PT1, PT2 through a contact hole. Further, the wiring film TI1 is formed so as to cover the periphery of the moisture-resistant protective film PC1 and the organic protective film PC2.
  • An interlayer insulating film SR1 is formed on the surface of the wiring film TI1.
  • a resistance film pattern RE1 is formed on the surface of the interlayer insulating film SR1.
  • the surface of the resistance film pattern RE1 is covered with an interlayer insulating film SR2, and the resistance film pattern RE2 is formed on the surface of the interlayer insulating film SR2.
  • the surface of the resistance film pattern RE2 is covered with an interlayer insulating film SR3.
  • the resistance films of these resistance film patterns RE1 and RE2 are formed by a thin film process (a process using photolithography and etching techniques) or a thick film process (a process using printing techniques such as screen printing).
  • the resistance value of each resistive element is determined by the width, length and thickness of the resistive film pattern.
  • a wiring film TI2 is formed on the surface of the interlayer insulating film SR3.
  • the wiring film TI2 is connected to the wiring film TI1 through a contact hole formed in the interlayer insulating films SR1, SR2, SR3.
  • the surface of the interlayer insulating film SR3 is covered with a solder resist film SR4.
  • An external connection electrode EE is formed in the opening of the solder resist film SR4 and on the surface of the wiring film TI2.
  • the ferroelectric film FS1 is an insulating film for adhesion and diffusion prevention with respect to the substrate SI and the moisture-resistant protective film PC1.
  • the ferroelectric film FS3 is an insulating film for adhesion to the moisture resistant protective film PC1.
  • a high melting point noble metal material having good conductivity and excellent oxidation resistance, for example, Pt and Au can be used.
  • a dielectric material having a high dielectric constant is used as the thin film material used for the ferroelectric films FS1, FS2, and FS3.
  • a dielectric material having a high dielectric constant is used as the thin film material used for the ferroelectric films FS1, FS2, and FS3.
  • perovskite compounds such as (Ba, Sr) TiO 3 (BST), SrTiO 3 , BaTiO 3 , Pb (Zr, Ti) O 3 , bismuth layered compounds such as SrBi 4 Ti 4 O 15 , etc. are used. be able to.
  • the wiring films TI1 and TI2 are composed of three layers of Ti / Cu / Ti, the Ti layer is formed to 100 nm, for example, and the Cu layer is formed to 1000 nm, for example.
  • the external connection electrode EE includes two layers of Au / Ni.
  • the first Ni layer is formed to 2000 nm, for example, and the second Au layer is formed to 200 nm, for example.
  • the moisture-resistant protective film PC1 prevents moisture released from the organic protective film PC2 from entering the capacitor portion.
  • This moisture-resistant protective film PC1 SiNx, SiO 2 , Al 2 O 3 , TiO 2 or the like can be used.
  • the organic protective film PC2 absorbs mechanical stress from the outside.
  • PBO polybenzoxazole
  • polyimide resin polyimide resin
  • epoxy resin or the like can be used.
  • the resistance material of the resistance film patterns RE1 and RE2 is, for example, nichrome.
  • the manufacturing method of the variable capacitance element 101 shown in FIG. 4 is as follows.
  • a thermal oxidation process is performed on the Si substrate to form an oxide layer made of SiO 2 having a thickness of 700 nm.
  • the thickness of the oxide layer is not particularly limited as long as a desired insulating property can be secured, but is preferably set within a range of 500 to 1000 nm.
  • a 50 nm-thickness ferroelectric film FS1 for adhesion and diffusion prevention is formed on the oxide layer by a chemical solution deposition (hereinafter referred to as “CSD”) method.
  • the film thickness of the ferroelectric film FS1 is not particularly limited as long as it can ensure desired adhesion and diffusion prevention properties, but is preferably set within a range of 10 to 100 nm.
  • ferroelectric film FS1 Some of the materials that can be used as the ferroelectric film FS1 are as described above, but the same material as that of the ferroelectric film FS2 for the capacitor is desirable.
  • the temperature of the hot plate is not particularly limited as long as desired drying characteristics can be obtained, but is preferably set within a range of 300 to 400 ° C.
  • the temperature of the heat treatment is not particularly limited as long as desired crystallization is performed, but is preferably set within a range of 600 to 700 ° C.
  • the heat treatment time is not particularly limited as long as desired crystallization is performed, but it is preferably set within a range of 10 to 60 minutes.
  • the capacitor electrode PT1, the ferroelectric film FS2, the capacitor electrode PT2, and the ferroelectric film FS3 are sequentially formed. Specifically, a capacitor electrode PT1 made of Pt or Au with a film thickness of 250 nm is formed by RF magnetron sputtering, then a ferroelectric film FS2 with a film thickness of 100 nm made of BST or the like is formed by CSD, and then A capacitor electrode PT2 made of Pt or Au with a film thickness of 250 nm is formed by RF magnetron sputtering. Further, a 100 nm-thick ferroelectric film FS3 made of BST or the like is formed by the CSD method.
  • the film thickness of the capacitor electrodes PT1 and PT2 is not particularly limited as long as a desired low resistance can be ensured, but is preferably set within a range of 100 to 500 nm. Further, the film thickness of the ferroelectric film FS2 is not particularly limited as long as it can secure a desired capacitance, but is preferably set within a range of 80 to 150 nm. Further, the film thickness of the ferroelectric film FS3 is not particularly limited as long as a desired adhesion can be secured, but is preferably set within a range of 80 to 150 nm.
  • each layer of the capacitor portion is patterned by a photolithography technique and a dry etching method (reactive ion etching (RIE) method). That is, after a photoresist is applied and prebaked, the photoresist is irradiated with ultraviolet light through a photomask, and exposure, development, and postbaking are performed to transfer the photomask pattern to the resist pattern. Next, the exposed portion is dry etched using Ar gas or CHF 3 gas.
  • RIE reactive ion etching
  • this capacitor part is heat-treated at a temperature of 800 ° C. for 30 minutes.
  • the temperature of this heat treatment is not particularly limited as long as desired heat treatment characteristics can be obtained, but it is preferably set within a temperature range of 800 to 900 ° C.
  • the heat treatment time is not particularly limited as long as desired heat treatment characteristics can be obtained, but is preferably set within a range of 10 to 60 minutes.
  • a moisture-resistant protective film PC1 made of an inorganic material having a film thickness of 600 nm is formed by a sputtering method so as to cover the upper surface and side surfaces of the capacitor portion and the side surface of the ferroelectric film FS1, and then photosensitive by a spin coating method.
  • a PBO (polybenzoxazole) film which is a resin material, is applied so as to cover the moisture-resistant protective film PC1, and then heated for 5 minutes at a temperature of 125 ° C., and subjected to exposure and development treatment. By heating for about an hour, the organic protective film PC2 having a predetermined pattern with a film thickness of 6000 nm is formed.
  • the film thickness of the moisture-resistant protective film PC1 is not particularly limited as long as a desired moisture-resistant protective property can be secured, but is preferably set within a range of 200 to 1000 nm. Further, the thickness of the organic protective film PC2 is not particularly limited as long as the desired mechanical stress absorbability can be secured, but is preferably set within a range of 2000 to 10000 nm.
  • the organic protective film PC2 As a mask and using CHF 3 gas, the organic protective film PC2, the moisture-resistant protective film PC1 and the ferroelectric film FS2 are subjected to dry etching to form a pattern, and contact holes (illustrated) reaching the capacitor electrode PT1.
  • the organic protective film PC2, the moisture-resistant protective film PC1 and the ferroelectric film FS3 are dry-etched to form a pattern, thereby forming a contact hole reaching the capacitor electrode PT2.
  • three metal layers to be the wiring film TI1 are formed by RF magnetron sputtering, and the wiring film TI1 is patterned by wet etching.
  • the interlayer insulating film SR1 is spin-coated to form a contact hole. Further, a resistance film to be the resistance element 14B of the variable capacitance element portion is formed by a thin film process such as sputtering or electron beam evaporation, and the resistance film is patterned by a lift-off method to form the resistance film pattern RE1. .
  • the interlayer insulating film SR2 is spin-coated, and a contact hole is formed at a position overlapping the contact hole of the interlayer insulating film SR1.
  • a resistance film to be the control voltage application circuit 14R is formed by a thin film process such as sputtering or electron beam evaporation, and the resistance film pattern RE2 is formed by patterning the resistance film by a lift-off method.
  • the interlayer insulating film SR3 is spin-coated, and a contact hole is formed at a position overlapping the contact hole of the interlayer insulating film SR2.
  • film formation and patterning are performed in the following steps.
  • the three metal layers to be the conductor inside the contact hole and the wiring film TI2 are formed by RF magnetron sputtering.
  • a metal layer to be the external connection electrode EE is formed by electrolytic plating.
  • the metal layer is patterned by a photolithography method and a wet etching method.
  • a solder resist film SR4 is formed by spin coating.
  • the solder resist film SR4 is patterned by a photolithography method and a wet etching method.
  • a variable capacitance element with a circuit can be configured.
  • the present invention is not limited to the above embodiment.
  • the film thickness, formation method, formation conditions, and the like of each layer shown in the above embodiment are merely examples, and it goes without saying that the thin film capacitor can be arbitrarily changed within a range that does not impair the intended function. Absent.
  • the capacitor portion has a single layer structure having one capacitance generation portion, but the same applies to the case of a multilayer structure having two or more capacitance generation portions. Needless to say.
  • variable capacitance element and the control voltage application circuit are formed on a semiconductor substrate by a thin film process. That is, the variable capacitance element part and the control voltage application circuit part are integrally formed on a common substrate.
  • the plurality of resistance elements constituting the control voltage application circuit are provided in the same layer and in the same process. Therefore, even if the resistance value of each resistance element deviates from a desired resistance value, variation in the ratio of each resistance value itself can be suppressed, and therefore the output voltage can be controlled with good reproducibility.
  • the variable capacitance element includes a plurality of RF resistance elements connected in parallel to both ends of each ferroelectric capacitor. These RF resistance elements are different from the resistance patterns constituting the control voltage application circuit. These RF resistance elements are also provided in the same layer in the same process.
  • the resistors R11 to R14 and R21 to R23 having the same resistance value are used. However, if the resistance value is sufficiently large with respect to the impedance of the ferroelectric capacitors C1 to C6, the resistors The values do not have to be particularly equal.
  • FIG. 5 is a circuit diagram of the variable capacitance element 102 according to the second embodiment.
  • the variable capacitance element 102 includes ferroelectric capacitors C1 to C6 and a control voltage application circuit that applies a control voltage to these ferroelectric capacitors C1 to C6.
  • a capacitor C0 is connected between a series circuit of ferroelectric capacitors C1 to C6 and a port P11, and a series circuit of ferroelectric capacitors C1 to C6 and a port P12 are connected.
  • a capacitor C7 is connected between the two.
  • the connection relationship of resistors R0, R11 to R13, R21 to R24 for applying a control voltage to the ferroelectric capacitors C1 to C6 is different from that in FIG.
  • the divided voltage by the resistance voltage dividing circuit RDV1 is applied to the ferroelectric capacitors C1 to C3, and the divided voltage by the resistance voltage dividing circuit RDV2 is applied to the ferroelectric capacitors C4 to C6.
  • Others are the same as in the first embodiment.
  • capacitors C0 and C7 act as direct current cut capacitors, and the influence on elements and circuits connected to ports P11 and P12 can be suppressed.
  • capacitors C0 and C7 act as direct current cut capacitors, and the influence on elements and circuits connected to ports P11 and P12 can be suppressed.
  • a series circuit of resistors R11 and R13 is not connected in parallel to the antenna coil. Therefore, the variable capacitance element 102 does not adversely affect the antenna characteristics.
  • an LC resonance circuit can be configured by the capacitance between the ports P11 and P12 and the antenna coil.
  • control terminals P21, P22, P23 are all at the H level or the L level and the control terminals P24, P25 are all at the H level or the L level, that is, when no bleeder current flows, the ports P11, P12 are connected.
  • the capacity of can be kept constant.
  • the capacitors C0 and C7 may also be ferroelectric capacitors. However, since the control voltage is not applied to the capacitors C0 and C7, the capacitance value is constant.
  • the resistance values of the resistors R11 to R13 and R21 to R24 in FIG. 5 are equal if the resistance values are sufficiently larger than the impedances of the ferroelectric capacitors C1 to C6. It does not have to be.
  • FIG. 6 is a circuit diagram of a communication apparatus 201 including a variable capacitance element with a control voltage application circuit and a high-frequency device according to the present invention.
  • the communication device 201 is an example of an NFC module.
  • the communication device 201 includes an RFIC 11, a control IC 12, an antenna coil 13, and a variable capacitance element 102.
  • the variable capacitance element 102 and the RFIC 11 constitute a variable capacitance element built-in RFIC 110.
  • the variable capacitor 102 is the variable capacitor shown in the second embodiment.
  • a circuit including the variable capacitance element built-in RFIC 110 and the antenna coil 13 corresponds to the “high frequency device” of the present invention.
  • the RFIC 11 includes a GPIO (General Purpose Input / Output) IO terminal 11P.
  • the control IC 12 includes a GPIO IO terminal 12P.
  • the RFIC 11 performs conversion between a baseband signal and a high-frequency signal.
  • the control IC 12 controls the RFIC 11 and inputs / outputs data including communication data.
  • variable capacitance element 102 The parallel circuit of the variable capacitance element 102 and the antenna coil 13 is connected to the two RX terminals (reception signal terminals) of the RFIC 11.
  • the variable capacitance element 102 is shown in FIG.
  • the IO terminal 11P of the RFIC 11 and the IO terminal 12P of the control IC 12 are connected by a signal line 15A, and the control terminals P21 to P25 of the variable capacitor 102 are connected to signal lines 15A and 15B.
  • the RFIC 11 and the control IC 12 input and output communication signals via the data transmission line 16.
  • the control IC 12 controls various settings of the RFIC 11 via the signal line 15A. Further, the RFIC 11 or the control IC 12 gives control data to the variable capacitance element 102 via the signal lines 15A and 15B.
  • the variable capacitance element 102 constitutes an antenna circuit which is an LC parallel resonance circuit together with the antenna coil 13, and sets the resonance frequency of the antenna circuit to a predetermined frequency.
  • the antenna coil 13 performs electromagnetic wave coupling with an antenna of a communication partner to perform transmission / reception for near field communication.
  • FIG. 7 is a three-sided view of the RFIC 110 with a built-in variable capacitance element.
  • This variable capacitance element built-in RFIC 110 is a bare chip separated from a wafer as shown in FIG. Solder balls SB are formed on the external connection electrodes (pads) EE of the IC.
  • FIG. 8 is a cross-sectional view of the mounting rewiring board 20 with the variable capacitance element built-in RFIC 110 mounted thereon.
  • a mounting terminal 22 is formed on the lower surface of the mounting rewiring board 20, and an electrode for mounting the variable capacitance element built-in RFIC 110 is formed on the upper surface.
  • a rewiring electrode 21 is formed inside the mounting rewiring substrate 20.
  • An antenna coil 13 (see FIG. 6) is formed on the substrate 20, and a high frequency device is configured by mounting the variable capacitance element built-in RFIC 110 on the substrate 20.
  • a module in which the variable capacitance element built-in RFIC 110 is mounted on the mounting rewiring board 20 may be mounted on the printed wiring board.
  • FIG. 9 is a circuit diagram of a communication apparatus according to the fourth embodiment.
  • a circuit connected to two TX terminals (transmission signal terminals) of the RFIC 11 is also shown.
  • the baseband circuit 18 communicates baseband signals with the RFIC 11.
  • the antenna coil 13 exchanges radio signals with the communication partner antenna by magnetic field coupling with the communication partner coil antenna.
  • the antenna coil 13 is formed by winding a loop electrode pattern a plurality of turns or a plurality of layers.
  • Capacitors C21 and C22 are elements for adjusting the degree of coupling between the RFIC 11 and the antenna coil 13.
  • the inductors L11 and L12 and the capacitors C11, C12, and C20 constitute a transmission filter.
  • the RFIC 11 when the communication circuit operates in the card mode, the RFIC 11 operates passively. Therefore, the power supply voltage is generated from the input signal to the RX terminal, the received signal is read, and a circuit (load) connected to the TX terminal is transmitted during transmission. Modulate the load. For example, when the communication circuit operates in the reader / writer mode, the RFIC 11 operates in an active manner.
  • the RX terminal is opened at the time of transmission to transmit a transmission signal from the TX terminal, and the TX terminal is opened at the time of reception to receive the RX terminal. Input the received signal.
  • the impedance of the communication circuit when the antenna coil 13 is viewed from the RFIC 11 changes according to the operation mode.
  • the variable capacitance element 102 is controlled so that the resonance frequency of the antenna circuit is optimized in accordance with this operation mode (so that the impedance when the antenna coil 13 is viewed from the RFIC 11 is matched).
  • ESD protection elements 17A and 17B are connected to both ends of the antenna coil 13 between the antenna coil 13 and the ground.
  • the baseband circuit 18 does not allow the bleeder current to flow through the resistance voltage dividing circuit in the variable capacitance element 102 during standby (in reception standby mode). That is, it waits at the frequency that is the condition. As a result, power consumption during standby can be reduced.
  • the number of resistance voltage dividing circuits whose common connection points are independent from each other is not limited to two, and may be three or more.
  • the common connection point of the plurality of resistance voltage dividing circuits only needs to be in a DC non-conductive state by a ferroelectric capacitor or another capacitor, and the ferroelectric capacitor and other capacitors are connected to the plurality of capacitors connected in series. May be mixed.
  • variable capacitance element may be independently connected in parallel to the antenna coil, but a capacitor may be inserted in series with the variable capacitance element. Moreover, you may connect in series with respect to the antenna coil.
  • the high-frequency device of the present invention is not limited to the RFID reader / writer, and may be configured as an RFID tag.
  • C1-C6 Ferroelectric capacitors C0, C7: Capacitors C11, C12, C20, C21, C22 ... Capacitors CC1, CC2 ... Common connection point EE ... External connection electrodes FS1, FS2, FS3 ... Ferroelectric film G1 ... First Group G2 ... Second group GND ... Ground terminals L11, L12 ... Inductors P11, P12 ... Ports P21-P25 ... Control terminals PC1 ... Moisture-resistant protective film PC2 ... Organic protective films PT1, PT2 ... Capacitor electrodes R0, R11-R14, R21- R24, R31 to R35... RF resistor element RDV1...
  • First resistor voltage divider circuit RDV2 Second resistor voltage divider circuit RE1, RE2... Resistive film pattern SB... Solder ball SI ... Substrate SR1, SR2, SR3. SR4 ... Solder resist film TI1, TI2 ... Wiring film 11 ... RFIC 11P ... IO terminal 12 ... Control IC 12P ... IO terminal 13 ... antenna coil 14B ... resistance element 14R of variable capacitance element section ... control voltage application circuit 15A, 15B ... signal line 16 ... data transmission line 17A, 17B ... ESD protection element 18 ... baseband circuit 20 ... for mounting Rewiring board 21 ... Rewiring electrode 22 ... Mounting terminals 101, 102 ... Variable capacitance element 110 ... RFIC with built-in variable capacitance element 201: Communication device

Abstract

Ferroelectric capacitors (C1-C6) are constituted as a serial circuit. A first end of the serial circuit is connected to a port (P11) and a second end is connected to a port (P12). Resistors (R31, R32, R33) constitute a first resistance voltage divider circuit (RDV1), and resistors (R34, R35) constitute a second resistance voltage divider circuit (RDV2). A voltage between a ground terminal (GND) and a common connection point (CC1) of the resistors (R31, R32, R33) is impressed as a control voltage for the ferroelectric capacitors (C1-C4). A voltage between the ground terminal (GND) and a common connection point (CC2) of the resistors (R34, R35) is impressed as a control voltage for the ferroelectric capacitors (C5, C6).

Description

可変容量素子、高周波デバイスおよび通信装置Variable capacitance element, high frequency device and communication apparatus
　本発明はＲＦＩＤ（Radio Frequency Identification）システムや近距離無線通信（NFC：Near Field Communication）システムに用いられる可変容量素子、高周波デバイスおよび通信装置に関するものである。 The present invention relates to a variable capacitance element, a high-frequency device, and a communication apparatus used in an RFID (Radio Frequency Identification) system and a near field communication (NFC) system.
　ＮＦＣは１３ＭＨｚ帯を利用した近距離無線通信規格の一つであり、携帯通信端末をはじめ、さまざまな端末への搭載が期待されている。一般的に、ＮＦＣを利用した携帯通信端末では、ＮＦＣ用のＲＦＩＣが端末本体に内蔵され、このＮＦＣ用のＲＦＩＣは同じく端末本体に内蔵されたＮＦＣ用のアンテナコイルに接続される。また、前記アンテナコイルは通信周波数で共振するように容量素子が接続されていて、この容量素子とアンテナコイルとでアンテナ回路が構成されている。そして、このアンテナ回路とＮＦＣ用ＲＦＩＣ等とで無線通信モジュール（以下、「ＮＦＣモジュール」）が構成されている。 NFC is a short-range wireless communication standard using the 13 MHz band, and is expected to be installed in various terminals including mobile communication terminals. In general, in a mobile communication terminal using NFC, an RF IC for NFC is built in the terminal body, and the RFIC for NFC is connected to an NFC antenna coil that is also built in the terminal body. The antenna coil is connected to a capacitive element so as to resonate at a communication frequency, and the capacitive element and the antenna coil constitute an antenna circuit. The antenna circuit, NFC RFIC, and the like constitute a wireless communication module (hereinafter referred to as “NFC module”).
　ＮＦＣモジュールの通信周波数は予め決められているが、その使用条件や製造ばらつきによって、合わせるべきアンテナ回路の共振周波数は少しずつ異なる。例えばリーダライタモードとカードモードとではアンテナ回路の共振回路としての回路構成が変わる。そのため、どちらのモードでも所定の共振周波数を維持するために、モードに応じて前記共振回路を調整する必要が生じる。また、ＮＦＣモジュールの搭載環境によっても使用条件が変化する。例えばＮＦＣモジュールの近くに金属が存在するか否かなどによってアンテナ回路の共振周波数は変化する。 The communication frequency of the NFC module is determined in advance, but the resonance frequency of the antenna circuit to be adjusted differs little by little depending on the use conditions and manufacturing variations. For example, the circuit configuration as the resonance circuit of the antenna circuit changes between the reader / writer mode and the card mode. Therefore, in order to maintain a predetermined resonance frequency in either mode, it is necessary to adjust the resonance circuit according to the mode. In addition, the use conditions vary depending on the NFC module mounting environment. For example, the resonance frequency of the antenna circuit changes depending on whether or not metal is present near the NFC module.
　ＮＦＣモジュールのアンテナの周波数帯域が十分に広い場合は、上記の使用条件の違いによる微調整は不要であるが、最近の端末の小型化にともない十分なアンテナサイズを確保することが難しく、アンテナサイズが小さくなると十分なアンテナ帯域幅を得ることができない。そのため、共振周波数を最適値となるように調整することが必要になる。 When the frequency band of the antenna of the NFC module is sufficiently wide, fine adjustment due to the difference in the use conditions described above is unnecessary, but it is difficult to secure a sufficient antenna size with the recent miniaturization of the terminal, and the antenna size When becomes smaller, sufficient antenna bandwidth cannot be obtained. For this reason, it is necessary to adjust the resonance frequency to be an optimum value.
　共振周波数の調整方法としては、印加電圧により容量値を変化させることのできる可変容量素子でアンテナ回路のキャパシタを構成することが知られている（特許文献１参照）。また、複数のキャパシタを選択的に接続することで全体の容量値を切り替えるようにした回路が特許文献２に示されている。 As a method for adjusting the resonance frequency, it is known to configure a capacitor of an antenna circuit with a variable capacitance element that can change a capacitance value by an applied voltage (see Patent Document 1). Further, Patent Document 2 discloses a circuit in which the entire capacitance value is switched by selectively connecting a plurality of capacitors.
　図１２は特許文献２に示されている通信回路の例である。ここで、非接触ＩＣ部４７は、非接触ＩＣチップ、コンデンサＣinと並列コンデンサＣ１０１～Ｃ１０３、スイッチＳＷ１～ＳＷ３を有するアンテナ並列コンデンサ部、およびアンテナＬ１で構成されている。コンデンサＣinおよび並列コンデンサＣ１０１～Ｃ１０３が有する電気容量は固定値である。ＳＷ１～ＳＷ３は並列コンデンサＣ１０１～Ｃ１０３の接続のＯＮ／ＯＦＦを切り換える回路である。非接触ＩＣ部４７が携帯電話機１に組み込まれた後に、不揮発メモリ搭載のコントロールＩＣ６２が非接触ＩＣ部４７に対して接続される。コントロールＩＣ６２は、非接触ＩＣ部４７のスイッチＳＷ１～ＳＷ３のＯＮ／ＯＦＦ状態を切り替える。 FIG. 12 shows an example of a communication circuit disclosed in Patent Document 2. Here, the non-contact IC unit 47 includes a non-contact IC chip, a capacitor Cin and parallel capacitors C101 to C103, an antenna parallel capacitor unit having switches SW1 to SW3, and an antenna L1. The electric capacities of the capacitor Cin and the parallel capacitors C101 to C103 are fixed values. SW1 to SW3 are circuits for switching ON / OFF of the connection of the parallel capacitors C101 to C103. After the non-contact IC unit 47 is incorporated in the mobile phone 1, the control IC 62 with a nonvolatile memory is connected to the non-contact IC unit 47. The control IC 62 switches the ON / OFF state of the switches SW1 to SW3 of the non-contact IC unit 47.
特開２００９－２９０６４４号公報JP 2009-290644 A 特開２０１０－１４７７４３号公報JP 2010-147743 A
　しかし、可変容量素子や切り替え回路を備える場合、これらのアクティブ素子を別途搭載するためのスペースが必要となるほか、アクティブ素子であるため歪みが発生しやすく、共振周波数が変化してしまうことがある。また、複数のコンデンサを切り替えて容量値を微小ステップで調整するためには、多数のコンデンサおよび切替用のスイッチが必要となる。そのため、回路構成が複雑化し、ＩＣのサイズも大きくなるという問題がある。 However, when a variable capacitance element and a switching circuit are provided, a space for separately mounting these active elements is required, and since the active elements are used, distortion is likely to occur and the resonance frequency may change. . Further, in order to adjust a capacitance value in a minute step by switching a plurality of capacitors, a large number of capacitors and switching switches are required. Therefore, there is a problem that the circuit configuration becomes complicated and the size of the IC also increases.
　また、トリマコンデンサで容量値をメカニカルに設定する構成を採ることもできるが、その容量値を変化させるために機械的な制御が必要であるため、ＲＦＩＤデバイスが複雑化・大型化してしまいやすく、また、落下等の衝撃に対する信頼性を確保できないことがある。 In addition, although it is possible to adopt a configuration in which the capacitance value is mechanically set with a trimmer capacitor, mechanical control is required to change the capacitance value, so that the RFID device is likely to be complicated and enlarged, In addition, reliability against impacts such as dropping may not be ensured.
　また、印加する制御電圧によって容量が変化する可変容量素子を用いる場合、制御電圧を生成ために通常は抵抗分圧回路が構成される。しかし、基本的に抵抗分圧回路はブリーダー電流を流して、抵抗による降下電圧を取り出す回路であるため、ブリーダー電流による電力損失が生じる。特に、容量を所定値に固定しているときでもブリーダー電流による電力損失が常に生じるので、バッテリーを電源とする低消費電力の通信装置に適用する場合に問題となる。 Also, when using a variable capacitance element whose capacitance changes according to the applied control voltage, a resistance voltage dividing circuit is usually configured to generate the control voltage. However, since the resistance voltage dividing circuit is basically a circuit that allows a bleeder current to flow and extracts a voltage drop due to the resistance, power loss due to the bleeder current occurs. In particular, even when the capacity is fixed to a predetermined value, power loss due to the bleeder current always occurs, which is a problem when applied to a low power consumption communication device using a battery as a power source.
　本発明の目的は、アクティブ素子による歪み、および回路構成の複雑化に伴うＩＣサイズの大型化の問題を解消し、落下等の衝撃に対する信頼性を確保するとともに、低消費電力化を図った、制御電圧印加回路付き可変容量素子、高周波デバイスおよび通信装置を提供することにある。 The object of the present invention is to solve the problem of distortion due to active elements and the increase in size of the IC due to the complexity of the circuit configuration, to ensure reliability against impacts such as dropping, and to reduce power consumption. An object of the present invention is to provide a variable capacitance element with a control voltage application circuit, a high-frequency device, and a communication apparatus.
（１）本発明の可変容量素子は次のように構成される。 (1) The variable capacitance element of the present invention is configured as follows.
　強誘電体膜およびこの強誘電体膜を挟み込むキャパシタ電極を有し、前記キャパシタ電極間に印加される制御電圧値に応じて容量値が変化する強誘電体キャパシタと、
　複数の制御端子（例えば外部のGPIO端子が繋がる端子）に第１端がそれぞれ接続され、第２端が共通接続点に接続された複数の抵抗素子による抵抗分圧回路を有し、前記共通接続点の電圧を前記可変容量素子に印加する制御電圧印加回路と、を備え、
　前記抵抗分圧回路は、共通接続点が互いに独立した複数組の抵抗分圧回路で構成され、且つ前記強誘電体キャパシタまたは他のキャパシタにより直流的に非導通状態であることを特徴とする。 A ferroelectric film having a ferroelectric film and a capacitor electrode sandwiching the ferroelectric film, the capacitance value of which varies according to a control voltage value applied between the capacitor electrodes;
A plurality of control terminals (for example, terminals to which external GPIO terminals are connected), each having a resistance voltage dividing circuit including a plurality of resistance elements each having a first end connected to a common connection point and a second end connected to the common connection; A control voltage application circuit for applying a voltage at a point to the variable capacitance element,
The resistance voltage dividing circuit is composed of a plurality of sets of resistance voltage dividing circuits whose common connection points are independent from each other, and is non-conductive in a direct current state by the ferroelectric capacitor or another capacitor.
　この構成により、アクティブ素子であるスイッチを用いないので、歪みの問題がなく、また回路構成の簡素化に伴ってＩＣサイズが小型化され、落下等の衝撃に対する信頼性を確保し易い。さらに、抵抗分圧回路に流れるブリーダー電流が抑制できるかまたは殆ど０にすることができるので低消費電力化が図れる。 This configuration eliminates the problem of distortion because a switch that is an active element is not used, and the size of the IC is reduced with the simplification of the circuit configuration, and it is easy to ensure reliability against impacts such as dropping. Furthermore, since the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
（２）前記複数の抵抗素子は基板上に設けられた抵抗パターンであり、前記抵抗パターンは、前記複数の抵抗素子の抵抗値が、それらの抵抗値のうち最も低いものを基準として２の累乗の比率となるように形成されていることが好ましい。 (2) The plurality of resistance elements are resistance patterns provided on a substrate, and the resistance pattern is a power of 2 on the basis of a resistance value of the plurality of resistance elements being the lowest of the resistance values. It is preferable to form so that it may become a ratio.
　この構成により、相対的に少ない数の制御端子で、制御データの値と可変容量素子に対する制御電圧とを線形関係にでき、分解能一定で多段階の設定が容易となる。 With this configuration, with a relatively small number of control terminals, the value of the control data and the control voltage for the variable capacitance element can be in a linear relationship, and multi-stage setting can be easily performed with constant resolution.
（３）前記可変容量素子と前記制御電圧印加回路は、前記基板上に薄膜プロセスによって形成されたものであり、前記複数の抵抗素子は前記基板上の同一層に同一プロセスで形成されたものであることが好ましい。 (3) The variable capacitance element and the control voltage application circuit are formed on the substrate by a thin film process, and the plurality of resistance elements are formed on the same layer on the substrate by the same process. Preferably there is.
　この構成により、部品点数が削減され、データ伝送ラインの引き回しも非常に簡素になり、通信回路の小型軽量化が図れる。しかも、前記各抵抗素子の抵抗値が全体としてばらついても、すなわち絶対値がばらついても、各抵抗素子間の比率は安定する。そのため、抵抗分圧回路の分圧比は一定であり、可変容量素子に常に所定の安定した制御電圧を印加することができる。 With this configuration, the number of parts is reduced, the routing of the data transmission line becomes very simple, and the communication circuit can be reduced in size and weight. Moreover, even if the resistance values of the respective resistance elements vary as a whole, that is, even if the absolute values thereof vary, the ratio between the resistance elements is stabilized. Therefore, the voltage dividing ratio of the resistance voltage dividing circuit is constant, and a predetermined stable control voltage can always be applied to the variable capacitance element.
（４）前記可変容量素子は、前記強誘電体キャパシタの両端に並列接続された複数のＲＦ抵抗素子を含み、これらのＲＦ抵抗素子は、前記複数の抵抗素子とは異なる層に設けられていることが好ましい。 (4) The variable capacitance element includes a plurality of RF resistance elements connected in parallel to both ends of the ferroelectric capacitor, and these RF resistance elements are provided in a layer different from the plurality of resistance elements. It is preferable.
　この構成により、ＲＦ抵抗素子と抵抗分圧用の抵抗素子とを独立して最適な抵抗値に定めることができる。 With this configuration, the RF resistance element and the resistance-dividing resistance element can be independently set to optimum resistance values.
（５）本発明の高周波デバイスは、（１）～（４）のいずれかに記載の可変容量素子と、この可変容量素子の外部端子に接続されたＲＦＩＣとを１つのチップに設けられたものである。この構成により、通信装置等の電子機器内の回路基板への実装部品数および配線スペースが削減され、小型化が図れる。 (5) A high-frequency device according to the present invention includes a variable capacitance element according to any one of (1) to (4) and an RFIC connected to an external terminal of the variable capacitance element provided in one chip. It is. With this configuration, the number of components mounted on a circuit board and wiring space in an electronic device such as a communication device can be reduced, and the size can be reduced.
（６）本発明の通信装置は、アンテナコイルと、前記アンテナコイルに接続された可変容量素子と、前記可変容量素子に接続されたＲＦＩＣと、を有する通信装置であって、
　前記可変容量素子は（１）～（４）のいずれかに記載の可変容量素子であり、
　前記ＲＦＩＣは、前記複数組の抵抗分圧回路のうち、少なくとも１つの抵抗分圧回路に接続された前記外部端子のすべてが高電位、またはすべてが低電位となる状態をとりうるものである。 (6) The communication device of the present invention is a communication device including an antenna coil, a variable capacitance element connected to the antenna coil, and an RFIC connected to the variable capacitance element,
The variable capacitance element is the variable capacitance element according to any one of (1) to (4),
The RFIC can take a state in which all of the external terminals connected to at least one of the plurality of resistance voltage dividing circuits are at a high potential or all at a low potential.
　この構成により、アクティブ素子であるスイッチを用いないので、歪みの問題がなく、また回路構成の簡素化に伴ってＩＣサイズが小型化され、落下等の衝撃に対する信頼性を確保し易く、さらに、抵抗分圧回路に流れるブリーダー電流が抑制できるかまたは殆ど０にすることができるので低消費電力化が図れる。 With this configuration, the active element switch is not used, so there is no problem of distortion, the IC size is reduced along with the simplification of the circuit configuration, and it is easy to ensure reliability against impacts such as dropping, Since the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
　本発明によれば、アンテナコイルの共振周波数を制御するための可変容量素子として、キャパシタ電極間に強誘電体膜が挟み込まれた強誘電体キャパシタを用い、且つこの強誘電体キャパシタに制御電圧を印加するための制御電圧印加回路として、異なる抵抗値を持った複数の抵抗素子を用いているため、小型であるにもかかわらず、歪みが発生しにくく、周波数特性の安定した信頼性の高い制御電圧印加回路付き可変容量素子および高周波デバイスを実現できる。また、トリマコンデンサのように、機械的な制御を要する可変容量素子を用いる必要が無いため、小型であるにもかかわらず、落下等の衝撃に対する信頼性が高い制御電圧印加回路付き可変容量素子および高周波デバイスを実現できる。更に、抵抗分圧回路に流れるブリーダー電流が抑制できるかまたは殆ど０にすることができるので低消費電力化が図れる。 According to the present invention, a ferroelectric capacitor in which a ferroelectric film is sandwiched between capacitor electrodes is used as a variable capacitance element for controlling the resonance frequency of the antenna coil, and a control voltage is applied to the ferroelectric capacitor. As a control voltage application circuit for applying, a plurality of resistance elements having different resistance values are used. Therefore, although it is small in size, distortion is unlikely to occur and the frequency characteristics are stable and highly reliable control. A variable capacitance element with a voltage application circuit and a high-frequency device can be realized. In addition, since it is not necessary to use a variable capacitance element that requires mechanical control unlike a trimmer capacitor, a variable capacitance element with a control voltage application circuit that is highly reliable against an impact such as a drop despite being small, and A high-frequency device can be realized. Furthermore, since the bleeder current flowing in the resistance voltage dividing circuit can be suppressed or almost reduced to 0, the power consumption can be reduced.
図１は第１の実施形態の可変容量素子１０１の内部の全体の回路図である。FIG. 1 is an overall circuit diagram of the inside of the variable capacitor 101 according to the first embodiment. 図２は、第１の実施形態に係る可変容量素子１０１にブリーダー電流が流れない状態について示す図である。FIG. 2 is a diagram illustrating a state where no bleeder current flows through the variable capacitance element 101 according to the first embodiment. 図３は制御端子Ｐ２１～Ｐ２５に入力される５ビットの２値信号で表される印加電圧ステップと容量可変比との関係を示す図である。FIG. 3 is a diagram showing a relationship between an applied voltage step represented by a 5-bit binary signal inputted to the control terminals P21 to P25 and a capacitance variable ratio. 図４は可変容量素子１０１の主要部の断面図である。FIG. 4 is a cross-sectional view of the main part of the variable capacitance element 101. 図５は第２の実施形態に係る可変容量素子１０２の回路図である。FIG. 5 is a circuit diagram of the variable capacitance element 102 according to the second embodiment. 図６は本発明の制御電圧印加回路付き可変容量素子および高周波デバイスを備える通信装置２０１の回路図である。FIG. 6 is a circuit diagram of a communication apparatus 201 including a variable capacitance element with a control voltage application circuit and a high-frequency device according to the present invention. 図７は可変容量素子内蔵ＲＦＩＣ１１０の三面図である。FIG. 7 is a three-side view of the RFIC 110 with a built-in variable capacitance element. 図８は実装用再配線基板２０に可変容量素子内蔵ＲＦＩＣ１１０を搭載した状態での断面図である。FIG. 8 is a cross-sectional view of the mounting rewiring board 20 with the variable capacitance element built-in RFIC 110 mounted thereon. 図９は第４の実施形態に係る通信装置の回路図である。FIG. 9 is a circuit diagram of a communication apparatus according to the fourth embodiment. 図１０は第１の実施形態に係る可変容量素子の比較例としての可変容量素子の回路図である。FIG. 10 is a circuit diagram of a variable capacitor as a comparative example of the variable capacitor according to the first embodiment. 図１１は、図１０に示した可変容量素子の制御端子Ｐ２１～Ｐ２５の電位と抵抗分圧回路に流れるブリーダー電流について示す図である。FIG. 11 is a diagram showing the potential of the control terminals P21 to P25 of the variable capacitance element shown in FIG. 10 and the bleeder current flowing through the resistance voltage dividing circuit. 図１２は特許文献２に示されている通信回路の例である。FIG. 12 shows an example of a communication circuit disclosed in Patent Document 2.
《第１の実施形態》
　図１は第１の実施形態の可変容量素子１０１の内部の全体の回路図である。可変容量素子１０１は、強誘電体キャパシタＣ１～Ｃ６およびこれらの強誘電体キャパシタＣ１～Ｃ６に制御電圧を印加する制御電圧印加回路を含んでいる。強誘電体キャパシタＣ１～Ｃ６は１つの直列回路が構成されていて、その直列回路の第１端がポートＰ１１に接続されていて、第２端がポートＰ１２に接続されている。この可変容量素子１０１はポートＰ１１およびポートＰ１２間の容量値が変化する素子である。 << First Embodiment >>
FIG. 1 is an overall circuit diagram of the inside of the variable capacitor 101 according to the first embodiment. The variable capacitance element 101 includes ferroelectric capacitors C1 to C6 and a control voltage application circuit that applies a control voltage to these ferroelectric capacitors C1 to C6. The ferroelectric capacitors C1 to C6 constitute one series circuit, and the first end of the series circuit is connected to the port P11, and the second end is connected to the port P12. The variable capacitance element 101 is an element in which the capacitance value between the port P11 and the port P12 changes.
　共通接続点ＣＣ１とグランド端子ＧＮＤとの間に印加される電圧が強誘電体キャパシタＣ１～Ｃ４に対する制御電圧である。また、共通接続点ＣＣ２とグランド端子ＧＮＤとの間に印加される電圧が強誘電体キャパシタＣ５，Ｃ６に対する制御電圧である。 The voltage applied between the common connection point CC1 and the ground terminal GND is a control voltage for the ferroelectric capacitors C1 to C4. The voltage applied between the common connection point CC2 and the ground terminal GND is a control voltage for the ferroelectric capacitors C5 and C6.
　ＲＦ抵抗素子（以下、単に「抵抗」）Ｒ０，Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２３および抵抗分圧用の抵抗素子（以下、単に「抵抗」）Ｒ３１～Ｒ３５は前記制御電圧印加回路を構成している。強誘電体キャパシタＣ１～Ｃ６には、制御電圧印加回路のうち抵抗Ｒ１１，Ｒ１２，Ｒ１３，Ｒ１４および抵抗Ｒ２１，Ｒ２２，Ｒ２３を介して制御電圧が印加される。抵抗Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２３の抵抗値は等しい。これらの抵抗Ｒ０，Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２３は、強誘電体キャパシタＣ１～Ｃ６に制御電圧を印加するとともに、ポートＰ１１－Ｐ１２間に印加されるＲＦ信号が共通接続点ＣＣ１，ＣＣ２およびグランド端子ＧＮＤへ漏れるのを抑制する。 RF resistance elements (hereinafter simply “resistances”) R0, R11 to R14, R21 to R23 and resistance voltage dividing resistance elements (hereinafter simply “resistances”) R31 to R35 constitute the control voltage application circuit. A control voltage is applied to the ferroelectric capacitors C1 to C6 via resistors R11, R12, R13, R14 and resistors R21, R22, R23 in the control voltage application circuit. The resistance values of the resistors R11 to R14 and R21 to R23 are equal. These resistors R0, R11 to R14, R21 to R23 apply a control voltage to the ferroelectric capacitors C1 to C6, and an RF signal applied between the ports P11 and P12 is connected to the common connection points CC1 and CC2 and the ground terminal. Suppresses leakage to GND.
　抵抗Ｒ３１，Ｒ３２，Ｒ３３は第１の抵抗分圧回路ＲＤＶ１を構成していて、抵抗Ｒ３４，Ｒ３５は第２の抵抗分圧回路ＲＤＶ２を構成している。抵抗Ｒ３１，Ｒ３２，Ｒ３３の第１端は制御端子Ｐ２１，Ｐ２２，Ｐ２３にそれぞれ接続されている。これらの抵抗Ｒ３１，Ｒ３２，Ｒ３３の第２端は共通接続点ＣＣ１に接続されている。抵抗Ｒ３４，Ｒ３５の第１端は制御端子Ｐ２４，Ｐ２５にそれぞれ接続されている。また、これらの抵抗Ｒ３４，Ｒ３５の第２端は共通接続点ＣＣ２に接続されている。 The resistors R31, R32, and R33 constitute a first resistance voltage dividing circuit RDV1, and the resistors R34 and R35 constitute a second resistance voltage dividing circuit RDV2. The first ends of the resistors R31, R32, and R33 are connected to the control terminals P21, P22, and P23, respectively. The second ends of these resistors R31, R32, R33 are connected to the common connection point CC1. First ends of the resistors R34 and R35 are connected to control terminals P24 and P25, respectively. The second ends of the resistors R34 and R35 are connected to the common connection point CC2.
　このように、第１の抵抗分圧回路ＲＤＶ１と第２の抵抗分圧回路ＲＤＶ２とは、共通接続点ＣＣ１，ＣＣ２が互いに独立している。すなわち、第１の抵抗分圧回路ＲＤＶ１と第２の抵抗分圧回路ＲＤＶ２とは、複数の強誘電体キャパシタのうち強誘電体キャパシタＣ２～Ｃ５により直流的に絶縁されている。 Thus, the first resistance voltage dividing circuit RDV1 and the second resistance voltage dividing circuit RDV2 have the common connection points CC1 and CC2 independent of each other. That is, the first resistance voltage dividing circuit RDV1 and the second resistance voltage dividing circuit RDV2 are galvanically insulated by the ferroelectric capacitors C2 to C5 among the plurality of ferroelectric capacitors.
　制御端子Ｐ２１～Ｐ２５には外部から高電位（以下、「Ｈレベル」）または低電位（以下、「Ｌレベル」）の電圧（５ビットの２値信号）が印加される。制御端子Ｐ２１，Ｐ２２，Ｐ２３への印加電圧に応じて、第１の抵抗分圧回路ＲＤＶ１による分圧電圧が共通接続点ＣＣ１に生じる。また、制御端子Ｐ２４，Ｐ２５への印加電圧に応じて、第２の抵抗分圧回路ＲＤＶ２による分圧電圧が共通接続点ＣＣ２に生じる。 A high potential (hereinafter “H level”) or low potential (hereinafter “L level”) voltage (5-bit binary signal) is applied to the control terminals P21 to P25 from the outside. In response to the voltages applied to the control terminals P21, P22, and P23, a divided voltage by the first resistance voltage dividing circuit RDV1 is generated at the common connection point CC1. Further, a divided voltage by the second resistance voltage dividing circuit RDV2 is generated at the common connection point CC2 according to the voltage applied to the control terminals P24 and P25.
　第１の抵抗分圧回路ＲＤＶ１および強誘電体キャパシタＣ１，Ｃ２，Ｃ３，Ｃ４は第１グループＧ１に属している。第２の抵抗分圧回路ＲＤＶ２および強誘電体キャパシタＣ５，Ｃ６は第２グループＧ２に属している。 The first resistance voltage dividing circuit RDV1 and the ferroelectric capacitors C1, C2, C3, C4 belong to the first group G1. The second resistance voltage dividing circuit RDV2 and the ferroelectric capacitors C5 and C6 belong to the second group G2.
　制御端子Ｐ２１，Ｐ２２，Ｐ２３への印加電圧に応じて、第１グループＧ１の強誘電体キャパシタＣ１～Ｃ４の容量値が定まり、制御端子Ｐ２４，Ｐ２５への印加電圧に応じて、第２グループＧ２の強誘電体キャパシタＣ４，Ｃ５の容量値が定まる。そして、ポートＰ１１－Ｐ１２間の容量値は強誘電体キャパシタＣ１～Ｃ６の直列合成容量の値となる。 The capacitance values of the ferroelectric capacitors C1 to C4 of the first group G1 are determined according to the applied voltages to the control terminals P21, P22, P23, and the second group G2 is determined according to the applied voltages to the control terminals P24, P25. The capacitance values of the ferroelectric capacitors C4 and C5 are determined. The capacitance value between the ports P11 and P12 is the value of the series combined capacitance of the ferroelectric capacitors C1 to C6.
　図２は、第１の実施形態に係る可変容量素子１０１にブリーダー電流が流れない状態について示す図である。図２（Ａ）（Ｃ）のように、制御端子Ｐ２１，Ｐ２２，Ｐ２３の電位がＨレベルであると、制御端子Ｐ２１，Ｐ２２，Ｐ２３間で電流の出入りは無い。図２（Ｂ）（Ｄ）のように、制御端子Ｐ２１，Ｐ２２，Ｐ２３の電位がＬレベルであるときも、制御端子Ｐ２１，Ｐ２２，Ｐ２３間で電流の出入りは無い。また、図２（Ａ）（Ｄ）のように、制御端子Ｐ２４，Ｐ２５の電位がＨレベルであると、制御端子Ｐ２４，Ｐ２５間で電流の出入りは無い。図２（Ｂ）（Ｃ）のように、制御端子Ｐ２４，Ｐ２５の電位がＬレベルであるときも、制御端子Ｐ２４，Ｐ２５間で電流の出入りは無い。 FIG. 2 is a diagram illustrating a state where no bleeder current flows through the variable capacitance element 101 according to the first embodiment. As shown in FIGS. 2A and 2C, when the potentials of the control terminals P21, P22, and P23 are at the H level, no current flows in and out of the control terminals P21, P22, and P23. As shown in FIGS. 2B and 2D, even when the potentials of the control terminals P21, P22, and P23 are at the L level, no current flows in and out of the control terminals P21, P22, and P23. As shown in FIGS. 2A and 2D, when the potentials of the control terminals P24 and P25 are at the H level, no current flows in and out of the control terminals P24 and P25. As shown in FIGS. 2B and 2C, no current flows in or out between the control terminals P24 and P25 even when the potentials of the control terminals P24 and P25 are at the L level.
　このように、第１グループＧ１に対する２値信号が全てＨレベルまたは全てＬレベルであり、且つ第２グループＧ２に対する２値信号が全てＨレベルまたは全てＬレベルであればブリーダー電流は流れない。 Thus, the bleeder current does not flow if the binary signals for the first group G1 are all at H level or all at L level and the binary signals for the second group G2 are all at H level or all at L level.
　ここで、比較例としての可変容量素子の回路図を図１０に示す。この例では、抵抗Ｒ３１～Ｒ３５による１つの抵抗分圧回路を備え、抵抗Ｒ２１，Ｒ２２，Ｒ２３の一端を抵抗Ｒ４を介して抵抗分圧回路の共通接続点ＣＣに接続している。その他は第１の実施形態の可変容量素子１０１と同様である。 Here, a circuit diagram of a variable capacitance element as a comparative example is shown in FIG. In this example, one resistance voltage dividing circuit including resistors R31 to R35 is provided, and one ends of the resistors R21, R22, and R23 are connected to a common connection point CC of the resistance voltage dividing circuit via a resistor R4. Others are the same as those of the variable capacitor 101 of the first embodiment.
　図１１は、図１０に示した可変容量素子の制御端子Ｐ２１～Ｐ２５の電位と抵抗分圧回路に流れるブリーダー電流について示す図である。このように制御端子Ｐ２１がＨレベル、制御端子Ｐ２２～Ｐ２５がＬレベルであると、抵抗Ｒ３２～Ｒ３５の並列回路と抵抗Ｒ３１との直列回路が構成され、ブリーダー電流が流れ、共通接続点ＣＣに分圧電圧が発生する。 FIG. 11 is a diagram showing the potential of the control terminals P21 to P25 of the variable capacitance element shown in FIG. 10 and the bleeder current flowing through the resistance voltage dividing circuit. As described above, when the control terminal P21 is at the H level and the control terminals P22 to P25 are at the L level, a parallel circuit of the resistors R32 to R35 and a series circuit of the resistor R31 are formed, and a bleeder current flows and flows to the common connection point CC. A divided voltage is generated.
　図３は前記制御端子Ｐ２１～Ｐ２５に入力される５ビットの２値信号で表される印加電圧ステップと容量可変比との関係を示す図である。ここで、抵抗値比率および容量比率の条件(1)(2)(3)(4) は次のとおりである。 FIG. 3 is a diagram showing a relationship between an applied voltage step represented by a 5-bit binary signal inputted to the control terminals P21 to P25 and a capacitance variable ratio. Here, the conditions (1), (2), (3), and (4) for the resistance value ratio and the capacitance ratio are as follows.
［条件(1) ］
　可変容量素子：図１（第１の実施形態）
　Ｒ３１：Ｒ３２：Ｒ３３：Ｒ３４：Ｒ３５＝１：２：４：１：２
　第１グループの容量：第２グループの容量＝１：１
［条件(2) ］
　可変容量素子：図１（第１の実施形態）
　Ｒ３１：Ｒ３２：Ｒ３３：Ｒ３４：Ｒ３５＝１：２：４：１：２
　第１グループの容量：第２グループの容量＝０．８９：１．３３
［条件(3) ］
　可変容量素子：図１（第１の実施形態）
　Ｒ３１：Ｒ３２：Ｒ３３：Ｒ３４：Ｒ３５＝１：１．２：１．４：１：２
　第１グループの容量：第２グループの容量＝０．８９：１．３３
［条件(4) ］
　可変容量素子：図１０（比較例）
　Ｒ３１：Ｒ３２：Ｒ３３：Ｒ３４：Ｒ３５＝１：２：４：８：１６
　第１グループの容量：第２グループの容量＝１：１
　図３において、ステップ１は制御端子Ｐ２１～Ｐ２５の全てがＬレベルであるとき、ステップ３２は制御端子Ｐ２１～Ｐ２５の全てがＨレベルであるときに対応する。「容量可変比」はステップ１のときの容量を基準とする変化割合である。 [Condition 1) ]
Variable capacitor: FIG. 1 (first embodiment)
R31: R32: R33: R34: R35 = 1: 2: 4: 1: 2
Capacity of the first group: Capacity of the second group = 1: 1
[Condition (2)]
Variable capacitor: FIG. 1 (first embodiment)
R31: R32: R33: R34: R35 = 1: 2: 4: 1: 2
Capacity of the first group: Capacity of the second group = 0.89: 1.33
[Condition (3)]
Variable capacitor: FIG. 1 (first embodiment)
R31: R32: R33: R34: R35 = 1: 1.2: 1.4: 1: 2
Capacity of the first group: Capacity of the second group = 0.89: 1.33
[Condition (4)]
Variable capacitance element: FIG. 10 (comparative example)
R31: R32: R33: R34: R35 = 1: 2: 4: 8: 16
Capacity of the first group: Capacity of the second group = 1: 1
In FIG. 3, step 1 corresponds to when all of the control terminals P21 to P25 are at the L level, and step 32 corresponds to when all of the control terminals P21 to P25 are at the H level. The “capacity variable ratio” is a change rate based on the capacity at the time of step 1.
　このように、抵抗Ｒ３１～Ｒ３５の抵抗値は、それらの抵抗値のうち最も低いものを基準として２の累乗またはほぼ２の累乗の比率で定めることにより、前記抵抗分圧比は、制御端子Ｐ２１～Ｐ２５のハイレベルおよびローレベルの組み合わせに応じて２の５乗（＝３２）通りの値をとり得る。 As described above, the resistance values of the resistors R31 to R35 are determined by a power of 2 or a ratio of almost a power of 2 with reference to the lowest one of the resistance values. Depending on the combination of the high level and low level of P25, 2 5 (= 32) values can be taken.
　強誘電体キャパシタＣ１～Ｃ６は印加電圧が大きくなるに従って容量変化比が大きくなる非線形性を備えている。そのため、条件(4) のように、制御電圧の大きさをリニアに切り替えることのできる回路構成の場合、強誘電体キャパシタ自体の容量－電圧特性がそのまま現れる。つまり１ステップごとの容量可変幅（感度）が異なってしまうため、容量値の微調整が困難となる。 The ferroelectric capacitors C1 to C6 have nonlinearity in which the capacitance change ratio increases as the applied voltage increases. Therefore, in the case of a circuit configuration in which the magnitude of the control voltage can be switched linearly as in condition (4) IV, the capacitance-voltage characteristic of the ferroelectric capacitor itself appears as it is. That is, the capacitance variable width (sensitivity) for each step is different, so that it is difficult to finely adjust the capacitance value.
　これに対して、同じ強誘電体キャパシタを用いたとしても、条件(1) のように、第１のグループと第２のグループを設けることによって（抵抗分圧回路を２つに分割することによって）、条件(4) と比較して容量可変比の線形性を高めることができる。但し、ステップ６－７間、ステップ１６－１７間、ステップ２１－２２間で容量変化が他のステップ間に比べて多少大きくなる。 On the other hand, even if the same ferroelectric capacitor is used, by providing the first group and the second group as in condition (1) (by dividing the resistance voltage dividing circuit into two) ), The linearity of the capacity variable ratio can be improved as compared with condition (4) IV. However, the capacity change between steps 6-7, between steps 16-17, and between steps 21-22 is somewhat larger than that between other steps.
　条件(2)(3) のように、各グループでの強誘電体キャパシタの容量比を変えれば、部分的に発生する容量変化の大きいステップを解消できる。また、条件(3) のように、更に抵抗値についても最適化すれば、全ステップに亘って容量変化をほぼ均等にできる。 (Conditions (2) and (3)) If the capacitance ratio of the ferroelectric capacitors in each group is changed, steps with large capacitance changes that occur partially can be eliminated. Further, if the resistance value is further optimized as in condition (3) IV, the capacitance change can be made almost uniform over all steps.
　図４は可変容量素子１０１の主要部の断面図である。図４において基板ＳＩは表面にSiO2膜が形成されたSi基板である。この基板ＳＩ上に強誘電体膜ＦＳ１、キャパシタ電極ＰＴ１、強誘電体膜ＦＳ２、キャパシタ電極ＰＴ２、強誘電体膜ＦＳ３の順に強誘電体膜とPt膜が交互に形成されてキャパシタ部が構成されている。 FIG. 4 is a cross-sectional view of the main part of the variable capacitance element 101. In FIG. 4, the substrate SI is a Si substrate having a SiO 2 film formed on the surface. A ferroelectric film and a Pt film are alternately formed in this order on the substrate SI in the order of the ferroelectric film FS1, the capacitor electrode PT1, the ferroelectric film FS2, the capacitor electrode PT2, and the ferroelectric film FS3 to form a capacitor portion. ing.
　これらの強誘電体膜ＦＳ１，ＦＳ２，ＦＳ３およびキャパシタ電極ＰＴ１，ＰＴ２の積層膜の上部には耐湿保護膜ＰＣ１が被覆されている。この耐湿保護膜ＰＣ１の上部には更に有機保護膜ＰＣ２が形成されている。 A moisture-resistant protective film PC1 is coated on the upper part of the laminated film of these ferroelectric films FS1, FS2, FS3 and capacitor electrodes PT1, PT2. An organic protective film PC2 is further formed on the moisture-resistant protective film PC1.
　有機保護膜ＰＣ２の上部には配線膜ＴＩ１が形成されている。また、この配線膜ＴＩ１はコンタクトホールを介してキャパシタ電極ＰＴ１，ＰＴ２の所定箇所に接続されている。さらに、配線膜ＴＩ１は、耐湿保護膜ＰＣ１および有機保護膜ＰＣ２の周囲を覆うように形成されている。 A wiring film TI1 is formed on the organic protective film PC2. Further, the wiring film TI1 is connected to a predetermined portion of the capacitor electrodes PT1, PT2 through a contact hole. Further, the wiring film TI1 is formed so as to cover the periphery of the moisture-resistant protective film PC1 and the organic protective film PC2.
　配線膜ＴＩ１の表面には層間絶縁膜ＳＲ１が形成されている。この層間絶縁膜ＳＲ１の表面に抵抗膜パターンＲＥ１が形成されている。この抵抗膜パターンＲＥ１の表面は層間絶縁膜ＳＲ２で被覆されていて、この層間絶縁膜ＳＲ２の表面に抵抗膜パターンＲＥ２が形成されている。この抵抗膜パターンＲＥ２の表面は層間絶縁膜ＳＲ３で被覆されている。 An interlayer insulating film SR1 is formed on the surface of the wiring film TI1. A resistance film pattern RE1 is formed on the surface of the interlayer insulating film SR1. The surface of the resistance film pattern RE1 is covered with an interlayer insulating film SR2, and the resistance film pattern RE2 is formed on the surface of the interlayer insulating film SR2. The surface of the resistance film pattern RE2 is covered with an interlayer insulating film SR3.
　これらの抵抗膜パターンＲＥ１，ＲＥ２の抵抗膜は、薄膜プロセス（フォトリソグラフィおよびエッチング技術を利用したプロセス）または厚膜プロセス（スクリーン印刷等の印刷技術を利用したプロセス）で形成されている。各抵抗素子の抵抗値は、抵抗膜パターンの幅、長さおよび厚みによって定められる。 The resistance films of these resistance film patterns RE1 and RE2 are formed by a thin film process (a process using photolithography and etching techniques) or a thick film process (a process using printing techniques such as screen printing). The resistance value of each resistive element is determined by the width, length and thickness of the resistive film pattern.
　層間絶縁膜ＳＲ３の表面には配線膜ＴＩ２が形成されていている。また、この配線膜ＴＩ２は、層間絶縁膜ＳＲ１，ＳＲ２，ＳＲ３に形成されたコンタクトホールを介して配線膜ＴＩ１に接続されている。 A wiring film TI2 is formed on the surface of the interlayer insulating film SR3. The wiring film TI2 is connected to the wiring film TI1 through a contact hole formed in the interlayer insulating films SR1, SR2, SR3.
　層間絶縁膜ＳＲ３の表面にはソルダーレジスト膜ＳＲ４が被覆されている。そして、このソルダーレジスト膜ＳＲ４の開口で且つ配線膜ＴＩ２の表面には外部接続電極ＥＥが形成されている。 The surface of the interlayer insulating film SR3 is covered with a solder resist film SR4. An external connection electrode EE is formed in the opening of the solder resist film SR4 and on the surface of the wiring film TI2.
　前記強誘電体膜ＦＳ１は基板ＳＩおよび耐湿保護膜ＰＣ１に対する密着用・拡散防止用の絶縁膜である。また、強誘電体膜ＦＳ３は耐湿保護膜ＰＣ１に対する密着用の絶縁膜である。前記キャパシタ電極ＰＴ１，ＰＴ２に使用される導電性材料としては、導電性が良好で耐酸化性に優れた高融点の貴金属材料、例えば、Pt，Auを用いることができる。 The ferroelectric film FS1 is an insulating film for adhesion and diffusion prevention with respect to the substrate SI and the moisture-resistant protective film PC1. The ferroelectric film FS3 is an insulating film for adhesion to the moisture resistant protective film PC1. As the conductive material used for the capacitor electrodes PT1 and PT2, a high melting point noble metal material having good conductivity and excellent oxidation resistance, for example, Pt and Au can be used.
　また、前記強誘電体膜ＦＳ１，ＦＳ２，ＦＳ３に使用される薄膜材料としては、高誘電率を有する誘電体材料が使用される。具体的には、(Ba,Sr)TiO3 (BST)、SrTiO3、BaTiO3、Pb(Zr,Ti)O3等のペロブスカイト化合物、SrBi4Ti4O15等のビスマス層状化合物等を使用することができる。 Further, as the thin film material used for the ferroelectric films FS1, FS2, and FS3, a dielectric material having a high dielectric constant is used. Specifically, perovskite compounds such as (Ba, Sr) TiO 3 (BST), SrTiO 3 , BaTiO 3 , Pb (Zr, Ti) O 3 , bismuth layered compounds such as SrBi 4 Ti 4 O 15 , etc. are used. be able to.
　また、配線膜ＴＩ１，ＴＩ２は、Ti／Cu／Tiの三層からなり、Ti層は例えば１００ｎｍに形成され、Cu層は、例えば１０００ｎｍに形成される。 Further, the wiring films TI1 and TI2 are composed of three layers of Ti / Cu / Ti, the Ti layer is formed to 100 nm, for example, and the Cu layer is formed to 1000 nm, for example.
　また、外部接続電極ＥＥは、Au／Niの二層からなり、第１層のNi層は、例えば２０００ｎｍに形成され、第２層のAu層は例えば２００ｎｍに形成される。 The external connection electrode EE includes two layers of Au / Ni. The first Ni layer is formed to 2000 nm, for example, and the second Au layer is formed to 200 nm, for example.
　前記耐湿保護膜ＰＣ１は有機保護膜ＰＣ２から放出される水分がキャパシタ部に浸入するのを防止する。この耐湿保護膜ＰＣ１としては、SiNx、SiO2、Al2O3、TiO2等を使用することができる。また、有機保護膜ＰＣ２は外部からの機械的応力を吸収する。この有機保護膜ＰＣ２としては、PBO（ポリベンゾオキサゾール）樹脂、ポリイミド樹脂、エポキシ樹脂等を使用することができる。 The moisture-resistant protective film PC1 prevents moisture released from the organic protective film PC2 from entering the capacitor portion. As this moisture-resistant protective film PC1, SiNx, SiO 2 , Al 2 O 3 , TiO 2 or the like can be used. The organic protective film PC2 absorbs mechanical stress from the outside. As this organic protective film PC2, PBO (polybenzoxazole) resin, polyimide resin, epoxy resin, or the like can be used.
　前記抵抗膜パターンＲＥ１，ＲＥ２の抵抗材料は例えばニクロムである。 The resistance material of the resistance film patterns RE1 and RE2 is, for example, nichrome.
　図４に示した可変容量素子１０１の製造方法は次のとおりである。 The manufacturing method of the variable capacitance element 101 shown in FIG. 4 is as follows.
　まず、Si基板に熱酸化処理を施し、膜厚７００ｎｍのSiO2からなる酸化物層を形成する。この酸化物層の膜厚は所望の絶縁性を確保できるような膜厚であれば特に限定されるものではないが、好ましくは５００～１０００ｎｍの範囲内に設定される。 First, a thermal oxidation process is performed on the Si substrate to form an oxide layer made of SiO 2 having a thickness of 700 nm. The thickness of the oxide layer is not particularly limited as long as a desired insulating property can be secured, but is preferably set within a range of 500 to 1000 nm.
　次いで、化学溶液堆積（Chemical Solution Deposition；以下「ＣＳＤ」という。）法により前記酸化物層上に膜厚５０ｎｍの密着用・拡散防止用の強誘電体膜ＦＳ１を形成する。この強誘電体膜ＦＳ１の膜厚は所望の密着性・拡散防止性が確保できるような膜厚であれば特に限定されるものではないが、好ましくは１０～１００ｎｍの範囲内に設定される。 Next, a 50 nm-thickness ferroelectric film FS1 for adhesion and diffusion prevention is formed on the oxide layer by a chemical solution deposition (hereinafter referred to as “CSD”) method. The film thickness of the ferroelectric film FS1 is not particularly limited as long as it can ensure desired adhesion and diffusion prevention properties, but is preferably set within a range of 10 to 100 nm.
　強誘電体膜ＦＳ１として使用可能な材料の幾つかは上述のとおりであるが、キャパシタ用の強誘電体膜ＦＳ２と同材料であることが望ましい。例えば、ＢＳＴ膜を形成する場合は、Ｂａ、Ｓｒ、Ｔｉが、モル比で例えばＢａ：Ｓｒ：Ｔｉ＝７：３：１０に配合された成膜原料溶液を用意する。そして、この成膜原料溶液を酸化物層１上に塗布し、４００℃のホットプレ－ト上で乾燥させ、６００℃の温度で３０分間、熱処理を行って結晶化させ、ＢＳＴ膜を形成する。 Some of the materials that can be used as the ferroelectric film FS1 are as described above, but the same material as that of the ferroelectric film FS2 for the capacitor is desirable. For example, when forming a BST film, a film forming raw material solution in which Ba, Sr, and Ti are mixed at a molar ratio of, for example, Ba: Sr: Ti = 7: 3: 10 is prepared. Then, this film forming raw material solution is applied onto the oxide layer 1, dried on a hot plate at 400 ° C., and crystallized by heat treatment at a temperature of 600 ° C. for 30 minutes to form a BST film.
　前記ホットプレートの温度は所望の乾燥特性が得られれば特に限定されるものではないが、好ましくは３００～４００℃の範囲内に設定される。また、前記熱処理の温度は所望の結晶化がなされればよく、特に限定されるものではないが、好ましくは６００～７００℃の範囲内で設定される。また、前記熱処理の時間は所望の結晶化がなされればよく、特に限定されるものではないが、好ましくは１０～６０分間の範囲内で設定される。 The temperature of the hot plate is not particularly limited as long as desired drying characteristics can be obtained, but is preferably set within a range of 300 to 400 ° C. The temperature of the heat treatment is not particularly limited as long as desired crystallization is performed, but is preferably set within a range of 600 to 700 ° C. Further, the heat treatment time is not particularly limited as long as desired crystallization is performed, but it is preferably set within a range of 10 to 60 minutes.
　次に、キャパシタ電極ＰＴ１、強誘電体膜ＦＳ２、キャパシタ電極ＰＴ２、強誘電体膜ＦＳ３を順次成膜する。具体的には、ＲＦマグネトロンスパッタ法により膜厚２５０ｎｍのＰｔやＡｕからなるキャパシタ電極ＰＴ１を形成し、次いで、ＣＳＤ法によりＢＳＴ等からなる膜厚１００ｎｍの強誘電体膜ＦＳ２を形成し、その後、ＲＦマグネトロンスパッタ法により膜厚２５０ｎｍのＰｔやＡｕからなるキャパシタ電極ＰＴ２を形成する。さらに、ＣＳＤ法によりＢＳＴ等からなる膜厚１００ｎｍの強誘電体膜ＦＳ３を形成する。 Next, the capacitor electrode PT1, the ferroelectric film FS2, the capacitor electrode PT2, and the ferroelectric film FS3 are sequentially formed. Specifically, a capacitor electrode PT1 made of Pt or Au with a film thickness of 250 nm is formed by RF magnetron sputtering, then a ferroelectric film FS2 with a film thickness of 100 nm made of BST or the like is formed by CSD, and then A capacitor electrode PT2 made of Pt or Au with a film thickness of 250 nm is formed by RF magnetron sputtering. Further, a 100 nm-thick ferroelectric film FS3 made of BST or the like is formed by the CSD method.
　前記キャパシタ電極ＰＴ１，ＰＴ２の膜厚としては、所望の低抵抗性が確保できる膜厚であれば特に限定されるものではないが、好ましくは１００～５００ｎｍの範囲内に設定される。また、前記強誘電体膜ＦＳ２の膜厚は所望の静電容量を確保できるような膜厚であれば特に限定されるものではないが、好ましくは８０～１５０ｎｍの範囲内に設定される。また、前記強誘電体膜ＦＳ３の膜厚は所望の密着性が確保できるような膜厚であれば特に限定されるものではないが、好ましくは８０～１５０ｎｍの範囲内に設定される。 The film thickness of the capacitor electrodes PT1 and PT2 is not particularly limited as long as a desired low resistance can be ensured, but is preferably set within a range of 100 to 500 nm. Further, the film thickness of the ferroelectric film FS2 is not particularly limited as long as it can secure a desired capacitance, but is preferably set within a range of 80 to 150 nm. Further, the film thickness of the ferroelectric film FS3 is not particularly limited as long as a desired adhesion can be secured, but is preferably set within a range of 80 to 150 nm.
　次に、フォトリソグラフィ技術及びドライエッチング法（反応性イオンエッチング(RIE) 法）により、キャパシタ部の各層のパターンニングを行う。すなわち、フォトレジストを塗布してプリベークした後、フォトマスクを介して紫外光をフォトレジストに照射し、露光、現像、ポストベークを行なってフォトマスクパターンをレジストパターンに転写する。次いで、ArガスやCHF3 ガスを用いて、露出部分をドライエッチングする。 Next, each layer of the capacitor portion is patterned by a photolithography technique and a dry etching method (reactive ion etching (RIE) method). That is, after a photoresist is applied and prebaked, the photoresist is irradiated with ultraviolet light through a photomask, and exposure, development, and postbaking are performed to transfer the photomask pattern to the resist pattern. Next, the exposed portion is dry etched using Ar gas or CHF 3 gas.
　そしてこの後、このキャパシタ部を８００℃の温度で３０分間熱処理する。この熱処理の温度は所望の熱処理特性が得られれば特に限定されるものではないが、好ましくは８００～９００℃の温度の範囲内に設定される。また、この熱処理の時間は所望の熱処理特性が得られれば特に限定されるものではないが、好ましくは１０～６０分間の範囲内で設定される。 Then, this capacitor part is heat-treated at a temperature of 800 ° C. for 30 minutes. The temperature of this heat treatment is not particularly limited as long as desired heat treatment characteristics can be obtained, but it is preferably set within a temperature range of 800 to 900 ° C. The heat treatment time is not particularly limited as long as desired heat treatment characteristics can be obtained, but is preferably set within a range of 10 to 60 minutes.
　次に、キャパシタ部の上面及び側面および強誘電体膜ＦＳ１の側面を覆うように、スパッタリング法により膜厚６００ｎｍの無機材料からなる耐湿保護膜ＰＣ１を形成し、次いで、スピンコ－ト法で感光性樹脂材料であるPBO（ポリベンゾオキサゾール）膜を、前記耐湿保護膜ＰＣ１を覆うように塗布し、その後、１２５℃の温度で５分間加熱し、露光、現像処理を行った後、３５０℃で１時間程度加熱し、膜厚が６０００ｎｍの所定パターンの有機保護膜ＰＣ２を形成する。 Next, a moisture-resistant protective film PC1 made of an inorganic material having a film thickness of 600 nm is formed by a sputtering method so as to cover the upper surface and side surfaces of the capacitor portion and the side surface of the ferroelectric film FS1, and then photosensitive by a spin coating method. A PBO (polybenzoxazole) film, which is a resin material, is applied so as to cover the moisture-resistant protective film PC1, and then heated for 5 minutes at a temperature of 125 ° C., and subjected to exposure and development treatment. By heating for about an hour, the organic protective film PC2 having a predetermined pattern with a film thickness of 6000 nm is formed.
　前記耐湿保護膜ＰＣ１の膜厚は、所望の耐湿保護性が確保できる膜厚であれば特に限定されるものではないが、好ましくは２００～１０００ｎｍの範囲内に設定される。また、前記有機保護膜ＰＣ２の膜厚は、所望の機械的応力吸収性が確保できる膜厚であれば特に限定されるものではないが、好ましくは２０００～１００００ｎｍの範囲内に設定される。 The film thickness of the moisture-resistant protective film PC1 is not particularly limited as long as a desired moisture-resistant protective property can be secured, but is preferably set within a range of 200 to 1000 nm. Further, the thickness of the organic protective film PC2 is not particularly limited as long as the desired mechanical stress absorbability can be secured, but is preferably set within a range of 2000 to 10000 nm.
　次に、有機保護膜ＰＣ２をマスクとし、CHF3ガスを用い、有機保護膜ＰＣ２、耐湿保護膜ＰＣ１および強誘電体膜ＦＳ２をドライエッチングしてパターン形成し、キャパシタ電極ＰＴ１に達するコンタクトホール（図示しない）を形成するとともに、有機保護膜ＰＣ２、耐湿保護膜ＰＣ１および強誘電体膜ＦＳ３をドライエッチングしてパターン形成し、キャパシタ電極ＰＴ２に達するコンタクトホールを形成する。 Next, using the organic protective film PC2 as a mask and using CHF 3 gas, the organic protective film PC2, the moisture-resistant protective film PC1 and the ferroelectric film FS2 are subjected to dry etching to form a pattern, and contact holes (illustrated) reaching the capacitor electrode PT1. The organic protective film PC2, the moisture-resistant protective film PC1 and the ferroelectric film FS3 are dry-etched to form a pattern, thereby forming a contact hole reaching the capacitor electrode PT2.
　次に、ＲＦマグネトロンスパッタ法で、配線膜ＴＩ１となるべき３層の金属層を成膜し、この配線膜ＴＩ１をウェットエッチングによりパターンニングする。 Next, three metal layers to be the wiring film TI1 are formed by RF magnetron sputtering, and the wiring film TI1 is patterned by wet etching.
　次に、層間絶縁膜ＳＲ１をスピンコートし、コンタクトホールを形成する。また、可変容量素子部の抵抗素子１４Ｂとなるべき抵抗膜をスパッタリングや電子ビーム蒸着等の薄膜プロセスにて成膜し、この抵抗膜をリフトオフ法によりパターンニングすることで抵抗膜パターンＲＥ１を形成する。 Next, the interlayer insulating film SR1 is spin-coated to form a contact hole. Further, a resistance film to be the resistance element 14B of the variable capacitance element portion is formed by a thin film process such as sputtering or electron beam evaporation, and the resistance film is patterned by a lift-off method to form the resistance film pattern RE1. .
　次に、層間絶縁膜ＳＲ２をスピンコートし、層間絶縁膜ＳＲ１のコンタクトホールと重なる位置にコンタクトホールを形成する。また、制御電圧印加回路１４Ｒとなるべき抵抗膜をスパッタリングや電子ビーム蒸着等の薄膜プロセスにて成膜し、この抵抗膜をリフトオフ法によりパターンニングすることで抵抗膜パターンＲＥ２を形成する。 Next, the interlayer insulating film SR2 is spin-coated, and a contact hole is formed at a position overlapping the contact hole of the interlayer insulating film SR1. Further, a resistance film to be the control voltage application circuit 14R is formed by a thin film process such as sputtering or electron beam evaporation, and the resistance film pattern RE2 is formed by patterning the resistance film by a lift-off method.
　次に、層間絶縁膜ＳＲ３をスピンコートし、層間絶縁膜ＳＲ２のコンタクトホールと重なる位置にコンタクトホールを形成する。 Next, the interlayer insulating film SR3 is spin-coated, and a contact hole is formed at a position overlapping the contact hole of the interlayer insulating film SR2.
　さらに以下のステップで成膜とパターニングを行う。 Furthermore, film formation and patterning are performed in the following steps.
　ＲＦマグネトロンスパッタ法でコンタクトホールの内部の導体および配線膜ＴＩ２となるべき３層の金属層を成膜する。 The three metal layers to be the conductor inside the contact hole and the wiring film TI2 are formed by RF magnetron sputtering.
　電解めっき法により外部接続電極ＥＥとなるべき金属層を形成する。 A metal layer to be the external connection electrode EE is formed by electrolytic plating.
　前記金属層をフォトリソグラフィ法およびウェットエッチング法でパターニングする。 The metal layer is patterned by a photolithography method and a wet etching method.
　ソルダーレジスト膜ＳＲ４をスピンコート法により形成する。 A solder resist film SR4 is formed by spin coating.
　ソルダーレジスト膜ＳＲ４をフォトリソグラフィ法およびウェットエッチング法でパターニングする。 The solder resist film SR4 is patterned by a photolithography method and a wet etching method.
　このように、可変容量素子として強誘電体キャパシタを用い、制御電圧印加回路として異なる抵抗値を持った複数の抵抗パターンを用いているため、小型で周波数特性に優れたパッシブデバイス（＝制御電圧印加回路付き可変容量素子）を構成できる。 In this way, a ferroelectric capacitor is used as a variable capacitance element, and a plurality of resistance patterns having different resistance values are used as a control voltage application circuit. Therefore, a passive device (= control voltage application) that is small and has excellent frequency characteristics. A variable capacitance element with a circuit) can be configured.
　なお、本発明は上記実施の形態に限定されるものではない。例えば、上記実施の形態で示した各層の膜厚、形成方法、形成条件等は単なる例示であって、薄膜キャパシタとして所期の機能を損なわない範囲で任意に変更可能であるのはいうまでもない。 The present invention is not limited to the above embodiment. For example, the film thickness, formation method, formation conditions, and the like of each layer shown in the above embodiment are merely examples, and it goes without saying that the thin film capacitor can be arbitrarily changed within a range that does not impair the intended function. Absent.
　また、上記実施の形態では、キャパシタ部が、一つの容量発生部を有する単層構造の場合について説明したが、二つ以上の容量発生部を有する多層構造の場合にも同様に適用できるのはいうまでもない。 Further, in the above embodiment, the case where the capacitor portion has a single layer structure having one capacitance generation portion has been described, but the same applies to the case of a multilayer structure having two or more capacitance generation portions. Needless to say.
　図４に示したように、可変容量素子および制御電圧印加回路は、半導体基板上に薄膜プロセスによって形成されている。すなわち、可変容量素子部と制御電圧印加回路部とが共通の基板に一体的に形成されている。特に、制御電圧印加回路を構成する複数の抵抗素子は、それぞれ同一層に同一プロセスにて設けられている。そのため、たとえ各抵抗素子の抵抗値が所望の抵抗値からずれたとしても、各抵抗値の比率そのもののバラツキは抑えることができ、ゆえに、再現性良く出力電圧を制御することができる。他方、可変容量素子は、各強誘電体キャパシタの両端に並列接続された複数のＲＦ抵抗素子を含むが、これらのＲＦ抵抗素子は、制御電圧印加回路を構成する複数の抵抗パターンとは異なる層に設けられており、これらのＲＦ抵抗素子も、同一層に同一プロセスにて設けられている。 As shown in FIG. 4, the variable capacitance element and the control voltage application circuit are formed on a semiconductor substrate by a thin film process. That is, the variable capacitance element part and the control voltage application circuit part are integrally formed on a common substrate. In particular, the plurality of resistance elements constituting the control voltage application circuit are provided in the same layer and in the same process. Therefore, even if the resistance value of each resistance element deviates from a desired resistance value, variation in the ratio of each resistance value itself can be suppressed, and therefore the output voltage can be controlled with good reproducibility. On the other hand, the variable capacitance element includes a plurality of RF resistance elements connected in parallel to both ends of each ferroelectric capacitor. These RF resistance elements are different from the resistance patterns constituting the control voltage application circuit. These RF resistance elements are also provided in the same layer in the same process.
　なお、以上に示した例では、抵抗Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２３について抵抗値が等しいものを用いたが、強誘電体キャパシタＣ１～Ｃ６のインピーダンスに対して十分に大きな抵抗値であれば、抵抗値は特に等しくなくてもよい。 In the example shown above, the resistors R11 to R14 and R21 to R23 having the same resistance value are used. However, if the resistance value is sufficiently large with respect to the impedance of the ferroelectric capacitors C1 to C6, the resistors The values do not have to be particularly equal.
《第２の実施形態》
　図５は第２の実施形態に係る可変容量素子１０２の回路図である。可変容量素子１０２は、強誘電体キャパシタＣ１～Ｃ６およびこれらの強誘電体キャパシタＣ１～Ｃ６に制御電圧を印加する制御電圧印加回路を含んでいる。図１に示した可変容量素子と異なり、強誘電体キャパシタＣ１～Ｃ６の直列回路とポートＰ１１との間にキャパシタＣ０が接続されていて、強誘電体キャパシタＣ１～Ｃ６の直列回路とポートＰ１２との間にキャパシタＣ７が接続されている。また、強誘電体キャパシタＣ１～Ｃ６に対して制御電圧を印加する抵抗Ｒ０，Ｒ１１～Ｒ１３，Ｒ２１～Ｒ２４の接続関係が図１とは異なる。 << Second Embodiment >>
FIG. 5 is a circuit diagram of the variable capacitance element 102 according to the second embodiment. The variable capacitance element 102 includes ferroelectric capacitors C1 to C6 and a control voltage application circuit that applies a control voltage to these ferroelectric capacitors C1 to C6. Unlike the variable capacitance element shown in FIG. 1, a capacitor C0 is connected between a series circuit of ferroelectric capacitors C1 to C6 and a port P11, and a series circuit of ferroelectric capacitors C1 to C6 and a port P12 are connected. A capacitor C7 is connected between the two. Further, the connection relationship of resistors R0, R11 to R13, R21 to R24 for applying a control voltage to the ferroelectric capacitors C1 to C6 is different from that in FIG.
　図５に示した例では、抵抗分圧回路ＲＤＶ１による分圧電圧が強誘電体キャパシタＣ１～Ｃ３に印加され、抵抗分圧回路ＲＤＶ２による分圧電圧が強誘電体キャパシタＣ４～Ｃ６に印加される。その他は第１の実施形態と同様である。 In the example shown in FIG. 5, the divided voltage by the resistance voltage dividing circuit RDV1 is applied to the ferroelectric capacitors C1 to C3, and the divided voltage by the resistance voltage dividing circuit RDV2 is applied to the ferroelectric capacitors C4 to C6. . Others are the same as in the first embodiment.
　図５において、キャパシタＣ０，Ｃ７は直流カット用キャパシタとして作用し、ポートＰ１１，Ｐ１２に接続される素子や回路への影響を抑制できる。ポートＰ１１，Ｐ１２に例えばアンテナコイルが接続される場合、アンテナコイルに対して抵抗Ｒ１１，Ｒ１３の直列回路が並列接続されることが無い。したがって、可変容量素子１０２がアンテナ特性へ悪影響を及ぼすことはない。また、ポートＰ１１，Ｐ１２間の容量とアンテナコイルとでＬＣ共振回路を構成することができる。そして、制御端子Ｐ２１，Ｐ２２，Ｐ２３がいずれもＨレベルまたはＬレベルで且つ制御端子Ｐ２４，Ｐ２５がいずれもＨレベルまたはＬレベルであるとき、すなわちブリーダー電流が流れない状態で、ポートＰ１１，Ｐ１２間の容量を一定に保つことができる。 In FIG. 5, capacitors C0 and C7 act as direct current cut capacitors, and the influence on elements and circuits connected to ports P11 and P12 can be suppressed. For example, when an antenna coil is connected to the ports P11 and P12, a series circuit of resistors R11 and R13 is not connected in parallel to the antenna coil. Therefore, the variable capacitance element 102 does not adversely affect the antenna characteristics. Further, an LC resonance circuit can be configured by the capacitance between the ports P11 and P12 and the antenna coil. When the control terminals P21, P22, P23 are all at the H level or the L level and the control terminals P24, P25 are all at the H level or the L level, that is, when no bleeder current flows, the ports P11, P12 are connected. The capacity of can be kept constant.
　なお、キャパシタＣ０，Ｃ７も強誘電体キャパシタであってもよい。但し、キャパシタＣ０，Ｃ７には制御電圧が印加されないので容量値は一定である。 The capacitors C0 and C7 may also be ferroelectric capacitors. However, since the control voltage is not applied to the capacitors C0 and C7, the capacitance value is constant.
　第１の実施形態で述べたことと同様に、図５の抵抗Ｒ１１～Ｒ１３，Ｒ２１～Ｒ２４の抵抗値は、強誘電体キャパシタＣ１～Ｃ６のインピーダンスに対して十分に大きな抵抗値であれば等しくなくてもよい。 As described in the first embodiment, the resistance values of the resistors R11 to R13 and R21 to R24 in FIG. 5 are equal if the resistance values are sufficiently larger than the impedances of the ferroelectric capacitors C1 to C6. It does not have to be.
《第３の実施形態》
　図６は本発明の制御電圧印加回路付き可変容量素子および高周波デバイスを備える通信装置２０１の回路図である。この通信装置２０１はＮＦＣモジュールの一例である。通信装置２０１は、ＲＦＩＣ１１、制御ＩＣ１２、アンテナコイル１３、および可変容量素子１０２を備えている。可変容量素子１０２とＲＦＩＣ１１とで可変容量素子内蔵ＲＦＩＣ１１０が構成されている。ここで、可変容量素子１０２は第２の実施形態で示した可変容量素子である。可変容量素子内蔵ＲＦＩＣ１１０とアンテナコイル１３とで構成される回路が本発明の「高周波デバイス」に相当する。 << Third Embodiment >>
FIG. 6 is a circuit diagram of a communication apparatus 201 including a variable capacitance element with a control voltage application circuit and a high-frequency device according to the present invention. The communication device 201 is an example of an NFC module. The communication device 201 includes an RFIC 11, a control IC 12, an antenna coil 13, and a variable capacitance element 102. The variable capacitance element 102 and the RFIC 11 constitute a variable capacitance element built-in RFIC 110. Here, the variable capacitor 102 is the variable capacitor shown in the second embodiment. A circuit including the variable capacitance element built-in RFIC 110 and the antenna coil 13 corresponds to the “high frequency device” of the present invention.
　ＲＦＩＣ１１はＧＰＩＯ（General Purpose Input/Output）のＩＯ端子１１Ｐを備えている。同様に、制御ＩＣ１２はＧＰＩＯのＩＯ端子１２Ｐを備えている。 The RFIC 11 includes a GPIO (General Purpose Input / Output) IO terminal 11P. Similarly, the control IC 12 includes a GPIO IO terminal 12P.
　ＲＦＩＣ１１はベースバンド信号と高周波信号との間の変換を行う。この制御ＩＣ１２は、ＲＦＩＣ１１を制御し、通信データを含むデータを入出力する。 RFIC 11 performs conversion between a baseband signal and a high-frequency signal. The control IC 12 controls the RFIC 11 and inputs / outputs data including communication data.
　ＲＦＩＣ１１の二つのＲＸ端子（受信信号端子）に可変容量素子１０２およびアンテナコイル１３の並列回路が接続されている。可変容量素子１０２は図５に示したものである。 The parallel circuit of the variable capacitance element 102 and the antenna coil 13 is connected to the two RX terminals (reception signal terminals) of the RFIC 11. The variable capacitance element 102 is shown in FIG.
　ＲＦＩＣ１１のＩＯ端子１１Ｐおよび制御ＩＣ１２のＩＯ端子１２Ｐは信号ライン１５Ａで接続され、可変容量素子１０２の制御端子Ｐ２１～Ｐ２５は信号ライン１５Ａ，１５Ｂに接続されている。 The IO terminal 11P of the RFIC 11 and the IO terminal 12P of the control IC 12 are connected by a signal line 15A, and the control terminals P21 to P25 of the variable capacitor 102 are connected to signal lines 15A and 15B.
　ＲＦＩＣ１１と制御ＩＣ１２とはデータ伝送ライン１６を介して通信信号の入出力を行い。制御ＩＣ１２は信号ライン１５Ａを介してＲＦＩＣ１１の各種設定などの制御を行う。また、ＲＦＩＣ１１または制御ＩＣ１２は信号ライン１５Ａ，１５Ｂを介して可変容量素子１０２に対して制御データを与える。 The RFIC 11 and the control IC 12 input and output communication signals via the data transmission line 16. The control IC 12 controls various settings of the RFIC 11 via the signal line 15A. Further, the RFIC 11 or the control IC 12 gives control data to the variable capacitance element 102 via the signal lines 15A and 15B.
　可変容量素子１０２はアンテナコイル１３とともにＬＣ並列共振回路であるアンテナ回路を構成し、アンテナ回路の共振周波数を所定周波数に定める。アンテナコイル１３は通信相手のアンテナと電磁界結合して近距離通信のための送受信を行う。 The variable capacitance element 102 constitutes an antenna circuit which is an LC parallel resonance circuit together with the antenna coil 13, and sets the resonance frequency of the antenna circuit to a predetermined frequency. The antenna coil 13 performs electromagnetic wave coupling with an antenna of a communication partner to perform transmission / reception for near field communication.
　図７は可変容量素子内蔵ＲＦＩＣ１１０の三面図である。この可変容量素子内蔵ＲＦＩＣ１１０は、図４に示したように、ウエハーから分断したベアチップである。このＩＣの外部接続電極（パッド）ＥＥには半田ボールＳＢが形成されている。 FIG. 7 is a three-sided view of the RFIC 110 with a built-in variable capacitance element. This variable capacitance element built-in RFIC 110 is a bare chip separated from a wafer as shown in FIG. Solder balls SB are formed on the external connection electrodes (pads) EE of the IC.
　図８は実装用再配線基板２０に可変容量素子内蔵ＲＦＩＣ１１０を搭載した状態での断面図である。実装用再配線基板２０の下面には実装用端子２２が形成されていて、上面には可変容量素子内蔵ＲＦＩＣ１１０を搭載する電極が形成されている。そして、実装用再配線基板２０の内部に再配線用電極２１が形成されている。この基板２０にはアンテナコイル１３（図６参照）が形成されていて、この基板２０に可変容量素子内蔵ＲＦＩＣ１１０を実装することによって高周波デバイスが構成される。 FIG. 8 is a cross-sectional view of the mounting rewiring board 20 with the variable capacitance element built-in RFIC 110 mounted thereon. A mounting terminal 22 is formed on the lower surface of the mounting rewiring board 20, and an electrode for mounting the variable capacitance element built-in RFIC 110 is formed on the upper surface. A rewiring electrode 21 is formed inside the mounting rewiring substrate 20. An antenna coil 13 (see FIG. 6) is formed on the substrate 20, and a high frequency device is configured by mounting the variable capacitance element built-in RFIC 110 on the substrate 20.
　このように、実装用再配線基板２０に可変容量素子内蔵ＲＦＩＣ１１０を搭載した状態のモジュールをプリント配線板に実装するようにしてもよい。 Thus, a module in which the variable capacitance element built-in RFIC 110 is mounted on the mounting rewiring board 20 may be mounted on the printed wiring board.
《第４の実施形態》
　図９は第４の実施形態に係る通信装置の回路図である。この例では、ＲＦＩＣ１１の二つのＴＸ端子（送信信号端子）に接続される回路も表している。図９においてベースバンド回路１８はＲＦＩＣ１１との間でベースバンド信号の通信を行う。アンテナコイル１３は、通信相手側コイルアンテナとの磁界結合によって、通信相手側アンテナと無線信号をやり取りする。このアンテナコイル１３はループ状電極パターンを複数ターンまたは複数層巻回することによって形成されたものである。 << Fourth Embodiment >>
FIG. 9 is a circuit diagram of a communication apparatus according to the fourth embodiment. In this example, a circuit connected to two TX terminals (transmission signal terminals) of the RFIC 11 is also shown. In FIG. 9, the baseband circuit 18 communicates baseband signals with the RFIC 11. The antenna coil 13 exchanges radio signals with the communication partner antenna by magnetic field coupling with the communication partner coil antenna. The antenna coil 13 is formed by winding a loop electrode pattern a plurality of turns or a plurality of layers.
　キャパシタＣ２１，Ｃ２２はＲＦＩＣ１１とアンテナコイル１３との結合度調整用の素子である。また、インダクタＬ１１，Ｌ１２およびキャパシタＣ１１，Ｃ１２，Ｃ２０は送信フィルタを構成している。例えば通信回路がカードモードで動作する場合、ＲＦＩＣ１１はパッシブ動作するので、ＲＸ端子への入力信号から電源電圧を生成するとともに受信信号を読み取り、送信時にはＴＸ端子に接続されている回路（負荷）を負荷変調する。また、例えば通信回路がリーダライタモードで動作する場合には、ＲＦＩＣ１１はアクティブ動作するので、送信時にＲＸ端子を開放してＴＸ端子から送信信号を送信し、受信時にはＴＸ端子を開放してＲＸ端子から受信信号を入力する。このように、通信回路は動作モードに応じて、ＲＦＩＣ１１からアンテナコイル１３側を見たインピーダンスが変化する。この動作モードに応じてアンテナ回路の共振周波数が最適となるように、（ＲＦＩＣ１１からアンテナコイル１３側を見たインピーダンスが整合するように、）可変容量素子１０２が制御される。 Capacitors C21 and C22 are elements for adjusting the degree of coupling between the RFIC 11 and the antenna coil 13. The inductors L11 and L12 and the capacitors C11, C12, and C20 constitute a transmission filter. For example, when the communication circuit operates in the card mode, the RFIC 11 operates passively. Therefore, the power supply voltage is generated from the input signal to the RX terminal, the received signal is read, and a circuit (load) connected to the TX terminal is transmitted during transmission. Modulate the load. For example, when the communication circuit operates in the reader / writer mode, the RFIC 11 operates in an active manner. Therefore, the RX terminal is opened at the time of transmission to transmit a transmission signal from the TX terminal, and the TX terminal is opened at the time of reception to receive the RX terminal. Input the received signal. As described above, the impedance of the communication circuit when the antenna coil 13 is viewed from the RFIC 11 changes according to the operation mode. The variable capacitance element 102 is controlled so that the resonance frequency of the antenna circuit is optimized in accordance with this operation mode (so that the impedance when the antenna coil 13 is viewed from the RFIC 11 is matched).
　なお、アンテナコイル１３の両端には、グランドとの間にそれぞれＥＳＤ保護素子１７Ａ，１７Ｂが接続されている。 Note that ESD protection elements 17A and 17B are connected to both ends of the antenna coil 13 between the antenna coil 13 and the ground.
　ベースバンド回路１８は待ち受け時に（受信待機モードで）可変容量素子１０２内の抵抗分圧回路にブリーダー電流が流れない条件とする。すなわち、その条件となる周波数で待ち受ける。これにより、待ち受け時での電力消費を削減できる。 Suppose that the baseband circuit 18 does not allow the bleeder current to flow through the resistance voltage dividing circuit in the variable capacitance element 102 during standby (in reception standby mode). That is, it waits at the frequency that is the condition. As a result, power consumption during standby can be reduced.
《他の実施形態》
　以上、本発明を具体的な実施の形態について説明したが、本発明はこの例に限定されるものではない。 << Other embodiments >>
While the present invention has been described with respect to specific embodiments, the present invention is not limited to this example.
　例えば、共通接続点が互いに独立した抵抗分圧回路は２つに限らず、３つ以上備えていてもよい。 For example, the number of resistance voltage dividing circuits whose common connection points are independent from each other is not limited to two, and may be three or more.
　また、複数の抵抗分圧回路の共通接続点が強誘電体キャパシタまたは他のキャパシタにより直流的に非導通状態であればよく、直列接続された複数のキャパシタには強誘電体キャパシタとその他のキャパシタとが混在していてもよい。 Further, the common connection point of the plurality of resistance voltage dividing circuits only needs to be in a DC non-conductive state by a ferroelectric capacitor or another capacitor, and the ferroelectric capacitor and other capacitors are connected to the plurality of capacitors connected in series. May be mixed.
　また、可変容量素子は、アンテナコイルに単独で並列接続されていてもよいが、可変容量素子に対して直列にコンデンサが挿入されていてもよい。また、アンテナコイルに対して直列に接続されていてもよい。 In addition, the variable capacitance element may be independently connected in parallel to the antenna coil, but a capacitor may be inserted in series with the variable capacitance element. Moreover, you may connect in series with respect to the antenna coil.
　また、本発明の高周波デバイスは、ＲＦＩＤのリーダライタに限定されるものではなく、ＲＦＩＤタグとして構成されていてもよい。 The high-frequency device of the present invention is not limited to the RFID reader / writer, and may be configured as an RFID tag.
Ｃ１～Ｃ６…強誘電体キャパシタ
Ｃ０，Ｃ７…キャパシタ
Ｃ１１，Ｃ１２，Ｃ２０，Ｃ２１，Ｃ２２…キャパシタ
ＣＣ１，ＣＣ２…共通接続点
ＥＥ…外部接続電極
ＦＳ１，ＦＳ２，ＦＳ３…強誘電体膜
Ｇ１…第１グループ
Ｇ２…第２グループ
ＧＮＤ…グランド端子
Ｌ１１，Ｌ１２…インダクタ
Ｐ１１，Ｐ１２…ポート
Ｐ２１～Ｐ２５…制御端子
ＰＣ１…耐湿保護膜
ＰＣ２…有機保護膜
ＰＴ１，ＰＴ２…キャパシタ電極
Ｒ０，Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２４，Ｒ３１～Ｒ３５…ＲＦ抵抗素子
ＲＤＶ１…第１の抵抗分圧回路
ＲＤＶ２…第２の抵抗分圧回路
ＲＥ１，ＲＥ２…抵抗膜パターン
ＳＢ…半田ボール
ＳＩ…基板
ＳＲ１，ＳＲ２，ＳＲ３…層間絶縁膜
ＳＲ４…ソルダーレジスト膜
ＴＩ１，ＴＩ２…配線膜
１１…ＲＦＩＣ
１１Ｐ…ＩＯ端子
１２…制御ＩＣ
１２Ｐ…ＩＯ端子
１３…アンテナコイル
１４Ｂ…可変容量素子部の抵抗素子
１４Ｒ…制御電圧印加回路
１５Ａ，１５Ｂ…信号ライン
１６…データ伝送ライン
１７Ａ，１７Ｂ…ＥＳＤ保護素子
１８…ベースバンド回路
２０…実装用再配線基板
２１…再配線用電極
２２…実装用端子
１０１，１０２…可変容量素子
１１０…可変容量素子内蔵ＲＦＩＣ
２０１…通信装置 C1-C6: Ferroelectric capacitors C0, C7: Capacitors C11, C12, C20, C21, C22 ... Capacitors CC1, CC2 ... Common connection point EE ... External connection electrodes FS1, FS2, FS3 ... Ferroelectric film G1 ... First Group G2 ... Second group GND ... Ground terminals L11, L12 ... Inductors P11, P12 ... Ports P21-P25 ... Control terminals PC1 ... Moisture-resistant protective film PC2 ... Organic protective films PT1, PT2 ... Capacitor electrodes R0, R11-R14, R21- R24, R31 to R35... RF resistor element RDV1... First resistor voltage divider circuit RDV2... Second resistor voltage divider circuit RE1, RE2... Resistive film pattern SB... Solder ball SI ... Substrate SR1, SR2, SR3. SR4 ... Solder resist film TI1, TI2 ... Wiring film 11 ... RFIC
11P ... IO terminal 12 ... Control IC
12P ... IO terminal 13 ... antenna coil 14B ... resistance element 14R of variable capacitance element section ... control voltage application circuit 15A, 15B ... signal line 16 ... data transmission line 17A, 17B ... ESD protection element 18 ... baseband circuit 20 ... for mounting Rewiring board 21 ... Rewiring electrode 22 ... Mounting terminals 101, 102 ... Variable capacitance element 110 ... RFIC with built-in variable capacitance element
201: Communication device

Claims (6)

  1. 　強誘電体膜およびこの強誘電体膜を挟み込むキャパシタ電極を有し、前記キャパシタ電極間に印加される制御電圧値に応じて容量値が変化する強誘電体キャパシタと、
    　複数の制御端子に第１端がそれぞれ接続され、第２端が共通接続点に接続された複数の抵抗素子による抵抗分圧回路を有し、前記共通接続点の電圧を前記強誘電体キャパシタに印加する制御電圧印加回路と、を備え、
    　前記抵抗分圧回路は、共通接続点が互いに独立した複数組の抵抗分圧回路で構成され、且つ前記強誘電体キャパシタまたは他のキャパシタにより直流的に非導通状態であることを特徴とする可変容量素子。     A ferroelectric film having a ferroelectric film and a capacitor electrode sandwiching the ferroelectric film, the capacitance value of which varies according to a control voltage value applied between the capacitor electrodes;
    A plurality of resistance elements each having a first end connected to a plurality of control terminals and a second end connected to a common connection point; and a voltage at the common connection point to the ferroelectric capacitor. A control voltage application circuit for applying,
    The resistance voltage dividing circuit is composed of a plurality of sets of resistance voltage dividing circuits whose common connection points are independent from each other, and is variable in direct current by the ferroelectric capacitor or another capacitor. Capacitance element.
  2. 　前記複数の抵抗素子は基板上に設けられた抵抗パターンであり、前記抵抗パターンは、前記複数の抵抗素子の抵抗値が、それらの抵抗値のうち最も低いものを基準として２の累乗の比率となるように形成されている、請求項１に記載の可変容量素子。 The plurality of resistance elements are resistance patterns provided on a substrate, and the resistance pattern has a ratio of a power of 2 with respect to a resistance value of the plurality of resistance elements based on the lowest one of the resistance values. The variable capacitance element according to claim 1, wherein the variable capacitance element is formed as follows.
  3. 　前記可変容量素子と前記制御電圧印加回路は、前記基板上に薄膜プロセスによって形成されたものであり、前記複数の抵抗素子は前記基板上の同一層に同一プロセスで形成されたものである、請求項１または２に記載の可変容量素子。 The variable capacitance element and the control voltage application circuit are formed on the substrate by a thin film process, and the plurality of resistance elements are formed on the same layer on the substrate by the same process. Item 3. The variable capacitor according to Item 1 or 2.
  4. 　前記可変容量素子は、前記強誘電体キャパシタの両端に並列接続された複数のＲＦ抵抗素子を含み、これらのＲＦ抵抗素子は、前記複数の抵抗素子とは異なる層に設けられている、請求項３に記載の可変容量素子。 The variable capacitance element includes a plurality of RF resistance elements connected in parallel to both ends of the ferroelectric capacitor, and these RF resistance elements are provided in a layer different from the plurality of resistance elements. 4. The variable capacitance element according to 3.
  5. 　請求項１～４のいずれかに記載の可変容量素子と、前記可変容量素子の前記制御端子に接続されたＲＦＩＣとが１つのチップに設けられて構成されたことを特徴とする高周波デバイス。 5. A high-frequency device comprising: the variable capacitance element according to claim 1; and an RFIC connected to the control terminal of the variable capacitance element provided on one chip.
  6. 　アンテナコイルと、前記アンテナコイルに接続された可変容量素子と、前記可変容量素子に接続されたＲＦＩＣと、を有する通信装置であって、
    　前記可変容量素子は請求項１～４のいずれかに記載の可変容量素子であり、
    　前記ＲＦＩＣは、前記複数組の抵抗分圧回路のうち、少なくとも１つの抵抗分圧回路に接続された前記制御端子のすべてがＨレベル、またはすべてがＬレベルとなる状態をとり得るものである通信装置。     A communication device comprising an antenna coil, a variable capacitance element connected to the antenna coil, and an RFIC connected to the variable capacitance element,
    The variable capacitor is the variable capacitor according to any one of claims 1 to 4,
    The RFIC is a communication that can take a state in which all of the control terminals connected to at least one of the plurality of resistance voltage dividing circuits are at an H level or all at an L level. apparatus.
PCT/JP2013/064578 2012-06-08 2013-05-27 Variable capacitance element, high-frequency device, and communication device WO2013183472A1 (en)

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