WO2013176203A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2013176203A1
WO2013176203A1 PCT/JP2013/064305 JP2013064305W WO2013176203A1 WO 2013176203 A1 WO2013176203 A1 WO 2013176203A1 JP 2013064305 W JP2013064305 W JP 2013064305W WO 2013176203 A1 WO2013176203 A1 WO 2013176203A1
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bonding
bonding pad
layer
semiconductor device
substrate
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PCT/JP2013/064305
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French (fr)
Japanese (ja)
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松良幸
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株式会社村田製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device characterized by a bonding pad portion.
  • Patent Document 1 discloses a structure that reduces an impact on an element structure below a bonding pad during wire bonding.
  • FIG. 4 is a cross-sectional view of the wire bonding portion of the semiconductor device disclosed in Patent Document 1.
  • the semiconductor device includes a semiconductor substrate 10 on which a semiconductor element is formed, conductive layers 12 and 16 electrically conducting to the semiconductor element, an insulating layer 14 provided between the conductive layers, and a protective film 18.
  • the body 22 is formed, a liquid conductive resin material is dropped from above the laminated body 22 to form a conductive resin layer on the laminated body, and the conductive resin layer is cured by heating to form a bonding pad.
  • the shock buffer layer 28 is formed, and a bonding wire is bonded to the upper side of the shock buffer layer.
  • the thickness of the conductive resin layer, which is the shock buffer layer 28 varies due to a process problem. As a result, there is a possibility that a portion of many bonding pads that cannot absorb shock during bonding may be generated.
  • An object of the present invention is to provide a highly reliable semiconductor device in which variation in shock absorbing effect during bonding is reduced and element destruction during bonding is suppressed.
  • the semiconductor device of the present invention has a semiconductor substrate on which an element is formed, and a bonding pad forming layer in which a bonding pad is formed on the surface, In the lower part of the bonding pad, a cavity is formed in the bonding pad forming layer or the semiconductor substrate or across the bonding pad forming layer and the semiconductor substrate.
  • the cavity is wider than the formation area of the bump formed on the bonding pad. This enhances the impact absorbing effect of the bonding pad during bonding. In addition, it is possible to reduce variations in the impact absorbing effect of the bonding pads during bonding due to variations in bonding positions.
  • the element formed on the semiconductor substrate is, for example, a MEMS (Micro Electro Mechanical System) element.
  • MEMS Micro Electro Mechanical System
  • the ultrasonic shock is not directly applied to the semiconductor substrate on which the element is formed, and the microfabricated element on the semiconductor substrate or the semiconductor device itself Destruction can be prevented.
  • FIG. 1 is a cross-sectional view of the main part of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 3 is a sectional view of the main part of a semiconductor device according to the third embodiment of the present invention.
  • 4A and 4B are cross-sectional views of a wire bonding portion of the semiconductor device of Patent Document 1.
  • FIG. 1 is a cross-sectional view of the main part of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 3 is a sectional view of the main part of a semiconductor device according to the third embodiment of the present invention.
  • 4A and 4B are cross-sectional views of a wire bonding portion of the semiconductor device of Patent Document 1.
  • FIG. 1 is a cross-sectional view of the main
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor device 101 according to the first embodiment of the present invention.
  • the semiconductor device 101 includes a silicon semiconductor substrate 1, an SOI substrate formed of an oxide insulating film 2 and a semiconductor layer 3 formed on the semiconductor substrate 1.
  • a wiring element 4 and the like are formed on the SOI substrate to constitute a MEMS element.
  • a glass substrate 8 is bonded to the upper portion of the SOI substrate through a bonding layer 5. Bonding pads 9 are formed on the surface of the glass substrate 8.
  • a cavity 6 is formed at the position of the bonding layer 5 below the bonding pad 9 of the glass substrate 8.
  • via conductors 7 a and 7 b are formed in the bonding layer 5 and the glass substrate 8 to conduct between the bonding pad 9 and the wiring conductor 4. Then, as shown in FIG. 1, a bonding wire 50 is wire bonded to the bonding pad 9. That is, the bump 50 ⁇ / b> B is formed on the bonding pad 9 above the cavity 6.
  • the bonding layer 5 is a polyimide film, and a cavity 6 is formed by photolithography. Specifically, it is formed by the following process.
  • a polyimide precursor is applied on an SOI substrate and then pre-baked to form a polyimide precursor film.
  • An opening to be a cavity 6 is formed in the polyimide precursor film by photolithography.
  • C The patterned polyimide precursor film is heat-treated. In this way, the bonding layer 5 made of polyimide having a cavity at a predetermined position is formed.
  • the via conductors 7a and 7b are formed by a film forming method such as a plating method, a sputtering method, or a vapor deposition method.
  • the vibration part of the MEMS element does not vibrate excessively due to ultrasonic vibration during bonding or excessive acceleration is not applied, and the MEMS element can be prevented from being broken.
  • the cavity 6 is formed wider than the formation area of the bump 50B. Therefore, the impact absorption effect of the bonding pad at the time of bonding is high. Further, the variation in the impact absorbing effect of the bonding pad during bonding due to the variation in bonding position is small.
  • Second Embodiment In the first embodiment, an example in which the glass substrate 8 is bonded to the upper portion of the SOI substrate via the bonding layer 5 and a cavity is formed in the bonding layer 5 has been described. However, the present invention is not limited to this structure. Absent. In the first embodiment, an example using an SOI substrate is shown, but the present invention is not limited to this. In addition, the element formed on the semiconductor substrate is not limited to the MEMS element, but can be applied to a semiconductor device including other semiconductor elements, and deterioration and damage of the semiconductor device itself due to an impact during bonding can be suppressed. In the second embodiment, a semiconductor device having a bonding pad formation layer on the surface of a semiconductor substrate and having no bonding layer will be described.
  • FIG. 2 is a cross-sectional view of the main part of the semiconductor device 102 according to the second embodiment.
  • the semiconductor device 102 includes a silicon semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 having bonding pads 9 formed on the surface.
  • a cavity 6 is formed in the bonding pad forming layer 10.
  • the bonding pad forming layer 10 is a silicon layer or a glass layer.
  • the bonding pad forming layer 10 is formed on the silicon semiconductor substrate 1 by sputtering or the like.
  • the bonding pad forming layer 10 may be provided by bonding a silicon layer or a glass layer formed in a separate process to the silicon semiconductor substrate 1.
  • the bonding layer may or may not be interposed.
  • the bonding pad forming layer 10 can be bonded to the silicon semiconductor substrate 1 through a polyimide film or a glass frit layer.
  • bonding can be performed by an anodic bonding method or a fusion bonding method.
  • the cavity can be formed by bonding a layer in which a cavity has been previously formed by etching, or by forming a sacrificial layer and etching the sacrificial layer.
  • the concave portion on the bonding pad forming layer 10 side is formed as the cavity 6 at the bonding portion between the bonding pad forming layer 10 and the semiconductor substrate 1.
  • 10 and the semiconductor substrate 1 may be recessed toward the semiconductor substrate 1 side.
  • a cavity may be formed across both the bonding pad formation layer 10 and the semiconductor substrate 1.
  • the third embodiment shows a semiconductor device in which a cavity is formed inside a bonding pad formation layer.
  • FIG. 3 is a cross-sectional view of the main part of the semiconductor device 103 according to the third embodiment.
  • the semiconductor device 103 includes a silicon semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 having bonding pads 9 formed on the surface.
  • a cavity 6 is formed inside the bonding pad forming layer 10.
  • the bonding pad forming layer 10 is a silicon layer or a glass layer.
  • the bonding pad forming layer 10 is formed on the silicon semiconductor substrate 1 by sputtering or the like.
  • the cavity can be formed by a method in which layers having cavities formed in advance by etching or a method in which a sacrificial layer is formed and the sacrificial layer is etched. .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device (101) comprises a silicon semiconductor substrate (1) and an SOI substrate constituted by an oxide insulating film (2) and a semiconductor layer (3) formed on this semiconductor substrate (1). A MEMS element is constituted by forming a wiring conductor (4) or the like on this SOI substrate. A glass substrate (8) is joined, by means of a junction layer (5), to the top of the SOI substrate. A bonding pad (9) is formed on the surface of the glass substrate (8). A cavity (6) is formed in a position of this junction layer (5) below the bonding pad (9) of the glass substrate (8). In this way, variability of the impact absorption effect of the bonding pad when bonding is reduced, so that a semiconductor device of high reliability is constituted, in which element damage when bonding is suppressed.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関し、特に、ボンディングパッド部に特徴を有する半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device characterized by a bonding pad portion.
　ワイヤーボンディング時におけるボンディングパッドの下部にある素子構造に対する衝撃を低減させる構造が特許文献１に開示されている。 Patent Document 1 discloses a structure that reduces an impact on an element structure below a bonding pad during wire bonding.
　図４は特許文献１に示されている半導体装置のワイヤーボンディング部分の断面図である。この半導体装置は、半導体素子が形成された半導体基板１０と、半導体素子に対し電気的に導通する導電層１２，１６と、導電層間に設けられた絶縁層１４と、保護膜１８とを備える積層体２２を形成し、この積層体２２の上方から液状の導電性樹脂材を滴下して、積層体上に導電性樹脂層を形成し、導電性樹脂層を加熱によって硬化させることで、ボンディングパッドの衝撃緩衝層２８を形成し、衝撃緩衝層の上側にボンディングワイヤーをボンディングするようにしている。 FIG. 4 is a cross-sectional view of the wire bonding portion of the semiconductor device disclosed in Patent Document 1. The semiconductor device includes a semiconductor substrate 10 on which a semiconductor element is formed, conductive layers 12 and 16 electrically conducting to the semiconductor element, an insulating layer 14 provided between the conductive layers, and a protective film 18. The body 22 is formed, a liquid conductive resin material is dropped from above the laminated body 22 to form a conductive resin layer on the laminated body, and the conductive resin layer is cured by heating to form a bonding pad. The shock buffer layer 28 is formed, and a bonding wire is bonded to the upper side of the shock buffer layer.
特開２００３－９２３０６号公報JP 2003-92306 A
　特許文献１に示されている半導体装置においては、そのプロセス上の問題に起因して、衝撃緩衝層２８である導電性樹脂層の厚みにばらつきが生じる。その結果、多数のボンディングパッドのうち、ボンディング時の衝撃吸収ができない部分が生じるおそれがある。 In the semiconductor device disclosed in Patent Document 1, the thickness of the conductive resin layer, which is the shock buffer layer 28, varies due to a process problem. As a result, there is a possibility that a portion of many bonding pads that cannot absorb shock during bonding may be generated.
　本発明は、ボンディング時の衝撃吸収効果のばらつきを低減して、ボンディング時の素子破壊を抑制した、信頼性の高い半導体装置を提供することを目的としている。 An object of the present invention is to provide a highly reliable semiconductor device in which variation in shock absorbing effect during bonding is reduced and element destruction during bonding is suppressed.
　本発明の半導体装置は、素子が形成された半導体基板、および表面にボンディングパッドが形成されたボンディングパッド形成層を有し、
　前記ボンディングパッドの下部において、前記ボンディングパッド形成層もしくは前記半導体基板に、または前記ボンディングパッド形成層と前記半導体基板とにまたがって、空洞が形成されていることを特徴としている。 The semiconductor device of the present invention has a semiconductor substrate on which an element is formed, and a bonding pad forming layer in which a bonding pad is formed on the surface,
In the lower part of the bonding pad, a cavity is formed in the bonding pad forming layer or the semiconductor substrate or across the bonding pad forming layer and the semiconductor substrate.
　前記空洞は前記ボンディングパッドに形成されるバンプの形成域より広がっていることが好ましい。このことで、ボンディング時のボンディングパッドの衝撃吸収効果が高まる。また、ボンディング位置のばらつきによるボンディング時のボンディングパッドの衝撃吸収効果のばらつきも低減できる。 It is preferable that the cavity is wider than the formation area of the bump formed on the bonding pad. This enhances the impact absorbing effect of the bonding pad during bonding. In addition, it is possible to reduce variations in the impact absorbing effect of the bonding pads during bonding due to variations in bonding positions.
　前記半導体基板に形成された素子は、例えばMEMS（Micro Electro Mechanical System）素子である。 The element formed on the semiconductor substrate is, for example, a MEMS (Micro Electro Mechanical System) element.
　本発明によれば、ボンディングパッドの下部に空洞が形成されているので、素子が形成された半導体基板に直接的に超音波衝撃が加わらず、半導体基板に微細加工された素子あるいは半導体装置自体の破壊を防ぐことができる。 According to the present invention, since the cavity is formed under the bonding pad, the ultrasonic shock is not directly applied to the semiconductor substrate on which the element is formed, and the microfabricated element on the semiconductor substrate or the semiconductor device itself Destruction can be prevented.
図１は本発明の第１の実施形態である半導体装置の主要部の断面図である。FIG. 1 is a cross-sectional view of the main part of the semiconductor device according to the first embodiment of the present invention. 図２は本発明の第２の実施形態である半導体装置の主要部の断面図である。FIG. 2 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. 図３は本発明の第３の実施形態である半導体装置の主要部の断面図である。FIG. 3 is a sectional view of the main part of a semiconductor device according to the third embodiment of the present invention. 図４（Ａ）、図４（Ｂ）は特許文献１の半導体装置のワイヤーボンディング部分の断面図である。4A and 4B are cross-sectional views of a wire bonding portion of the semiconductor device of Patent Document 1. FIG.
《第１の実施形態》
　図１は本発明の第１の実施形態である半導体装置１０１の主要部の断面図である。この半導体装置１０１は、シリコン半導体基板１、この半導体基板１上に形成された酸化絶縁膜２および半導体層３によるＳＯＩ基板を備えている。このＳＯＩ基板上に配線導体４等が形成されてMEMS素子が構成されている。ＳＯＩ基板の上部には接合層５を介してガラス基板８が接合されている。ガラス基板８の表面にはボンディングパッド９が形成されている。 << First Embodiment >>
FIG. 1 is a cross-sectional view of a main part of a semiconductor device 101 according to the first embodiment of the present invention. The semiconductor device 101 includes a silicon semiconductor substrate 1, an SOI substrate formed of an oxide insulating film 2 and a semiconductor layer 3 formed on the semiconductor substrate 1. A wiring element 4 and the like are formed on the SOI substrate to constitute a MEMS element. A glass substrate 8 is bonded to the upper portion of the SOI substrate through a bonding layer 5. Bonding pads 9 are formed on the surface of the glass substrate 8.
　ガラス基板８のボンディングパッド９の下部の接合層５の位置には空洞６が形成されている。また、接合層５およびガラス基板８には、ボンディングパッド９と配線導体４との間を導通させるビア導体７ａ，７ｂが形成されている。そして、図１に示すように、ボンディングパッド９にボンディングワイヤー５０がワイヤーボンディングされる。すなわち、バンプ５０Ｂが空洞６の上部でボンディングパッド９に形成される。 A cavity 6 is formed at the position of the bonding layer 5 below the bonding pad 9 of the glass substrate 8. In addition, via conductors 7 a and 7 b are formed in the bonding layer 5 and the glass substrate 8 to conduct between the bonding pad 9 and the wiring conductor 4. Then, as shown in FIG. 1, a bonding wire 50 is wire bonded to the bonding pad 9. That is, the bump 50 </ b> B is formed on the bonding pad 9 above the cavity 6.
　前記接合層５はポリイミド膜であり、フォトリソグラフィによって空洞６が形成される。具体的には、つぎの工程で形成される。 The bonding layer 5 is a polyimide film, and a cavity 6 is formed by photolithography. Specifically, it is formed by the following process.
（Ａ）ＳＯＩ基板上にポリイミド前駆体を塗布した後、プリベークし、ポリイミド前駆体被膜を形成する。
（Ｂ）フォトリソグラフィにより、ポリイミド前駆体被膜に空洞６となる開口を形成する。
（Ｃ）パターン化されたポリイミド前駆体被膜を熱処理する。
　このようにして、所定位置に空洞を有するポリイミドによる接合層５を形成する。なお、ビア導体７ａ，７ｂは例えばメッキ工法、スパッタ工法、蒸着工法といった成膜工法で形成される。 (A) A polyimide precursor is applied on an SOI substrate and then pre-baked to form a polyimide precursor film.
(B) An opening to be a cavity 6 is formed in the polyimide precursor film by photolithography.
(C) The patterned polyimide precursor film is heat-treated.
In this way, the bonding layer 5 made of polyimide having a cavity at a predetermined position is formed. The via conductors 7a and 7b are formed by a film forming method such as a plating method, a sputtering method, or a vapor deposition method.
　本発明によれば、ボンディングパッド（ボンディング可能な電極膜）の下部に空洞が形成されているので、下部の半導体基板に微細加工された素子にバンプ５０Ｂの超音波衝撃が直接伝達されない。そのため、MEMS素子の振動部がボンディング時の超音波振動によって過度に振動したり、過度の加速度が加わったりすることがなく、MEMS素子の破壊を防ぐことができる。 According to the present invention, since the cavity is formed below the bonding pad (bondable electrode film), the ultrasonic impact of the bump 50B is not directly transmitted to the element microfabricated on the lower semiconductor substrate. Therefore, the vibration part of the MEMS element does not vibrate excessively due to ultrasonic vibration during bonding or excessive acceleration is not applied, and the MEMS element can be prevented from being broken.
　また、空洞６はバンプ５０Ｂの形成域より広く形成されている。そのため、ボンディング時のボンディングパッドの衝撃吸収効果が高い。また、ボンディング位置のばらつきによるボンディング時のボンディングパッドの衝撃吸収効果のばらつきも小さい。 Further, the cavity 6 is formed wider than the formation area of the bump 50B. Therefore, the impact absorption effect of the bonding pad at the time of bonding is high. Further, the variation in the impact absorbing effect of the bonding pad during bonding due to the variation in bonding position is small.
《第２の実施形態》
　第１の実施形態ではＳＯＩ基板の上部には接合層５を介してガラス基板８を接合し、接合層５に空洞を形成した例を示したが、本発明はこの構造に限定されるものではない。また、第１の実施形態ではＳＯＩ基板を用いた例を示したが、本発明はこれに限定されるものではない。また、半導体基板に形成される素子はMEMS素子に限らず、その他の半導体素子を備えた半導体装置にも適用でき、ボンディング時の衝撃による半導体装置自体の劣化や破損を抑制することができる。第２の実施形態では、半導体基板表面にボンディングパッド形成層が設けられ、接合層をもたない半導体装置について示す。 << Second Embodiment >>
In the first embodiment, an example in which the glass substrate 8 is bonded to the upper portion of the SOI substrate via the bonding layer 5 and a cavity is formed in the bonding layer 5 has been described. However, the present invention is not limited to this structure. Absent. In the first embodiment, an example using an SOI substrate is shown, but the present invention is not limited to this. In addition, the element formed on the semiconductor substrate is not limited to the MEMS element, but can be applied to a semiconductor device including other semiconductor elements, and deterioration and damage of the semiconductor device itself due to an impact during bonding can be suppressed. In the second embodiment, a semiconductor device having a bonding pad formation layer on the surface of a semiconductor substrate and having no bonding layer will be described.
　図２は第２の実施形態である半導体装置１０２の主要部の断面図である。この半導体装置１０２は、素子が形成されたシリコン半導体基板１、および表面にボンディングパッド９が形成されたボンディングパッド形成層１０を有する。ボンディングパッド形成層１０の内部には空洞６が形成されている。 FIG. 2 is a cross-sectional view of the main part of the semiconductor device 102 according to the second embodiment. The semiconductor device 102 includes a silicon semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 having bonding pads 9 formed on the surface. A cavity 6 is formed in the bonding pad forming layer 10.
　ボンディングパッド形成層１０はシリコン層やガラス層などである。このボンディングパッド形成層１０はシリコン半導体基板１上にスパッタリング等で成膜されたものである。 The bonding pad forming layer 10 is a silicon layer or a glass layer. The bonding pad forming layer 10 is formed on the silicon semiconductor substrate 1 by sputtering or the like.
　前記ボンディングパッド形成層１０は、別工程で形成したシリコン層やガラス層などをシリコン半導体基板１へ接合することによって設けてもよい。シリコン半導体基板１へボンディングパッド形成層１０を接合する場合には、接合層を介してもよいし、介さなくてもよい。接合層を設ける場合にはポリイミド膜やガラスフリットの層を介してボンディングパッド形成層１０をシリコン半導体基板１へ接合することができる。接合層を設けない場合には陽極接合法やフュージョン接合法で接合することができる。 The bonding pad forming layer 10 may be provided by bonding a silicon layer or a glass layer formed in a separate process to the silicon semiconductor substrate 1. When bonding the bonding pad forming layer 10 to the silicon semiconductor substrate 1, the bonding layer may or may not be interposed. When the bonding layer is provided, the bonding pad forming layer 10 can be bonded to the silicon semiconductor substrate 1 through a polyimide film or a glass frit layer. When the bonding layer is not provided, bonding can be performed by an anodic bonding method or a fusion bonding method.
　前記空洞は、あらかじめエッチングにより空洞を形成した層を接合する方法や、犠牲層を形成し、犠牲層をエッチングすることで形成する方法が可能である。 The cavity can be formed by bonding a layer in which a cavity has been previously formed by etching, or by forming a sacrificial layer and etching the sacrificial layer.
　なお、図２に示した例では、ボンディングパッド形成層１０と半導体基板１との接合部でボンディングパッド形成層１０側に凹んだ箇所を空洞６として形成したが、この空洞６はボンディングパッド形成層１０と半導体基板１との接合部で半導体基板１側に凹んでいてもよい。また、ボンディングパッド形成層１０と半導体基板１の両方にまたがって空洞が形成されていてもよい。 In the example shown in FIG. 2, the concave portion on the bonding pad forming layer 10 side is formed as the cavity 6 at the bonding portion between the bonding pad forming layer 10 and the semiconductor substrate 1. 10 and the semiconductor substrate 1 may be recessed toward the semiconductor substrate 1 side. A cavity may be formed across both the bonding pad formation layer 10 and the semiconductor substrate 1.
《第３の実施形態》
　第３の実施形態では、ボンディングパッド形成層の内部に空洞が形成された半導体装置について示す。 << Third Embodiment >>
The third embodiment shows a semiconductor device in which a cavity is formed inside a bonding pad formation layer.
　図３は第３の実施形態である半導体装置１０３の主要部の断面図である。この半導体装置１０３は、素子が形成されたシリコン半導体基板１、および表面にボンディングパッド９が形成されたボンディングパッド形成層１０を有する。ボンディングパッド形成層１０の内部に空洞６が形成されている。 FIG. 3 is a cross-sectional view of the main part of the semiconductor device 103 according to the third embodiment. The semiconductor device 103 includes a silicon semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 having bonding pads 9 formed on the surface. A cavity 6 is formed inside the bonding pad forming layer 10.
　ボンディングパッド形成層１０はシリコン層やガラス層などである。このボンディングパッド形成層１０はシリコン半導体基板１上にスパッタリング等で成膜されたものである。 The bonding pad forming layer 10 is a silicon layer or a glass layer. The bonding pad forming layer 10 is formed on the silicon semiconductor substrate 1 by sputtering or the like.
　この例では、ボンディングパッド形成層１０を３層で形成し、第２層に空洞６を形成する工程を設けている。このような構造の場合も、第２の実施形態の場合と同様に、あらかじめエッチングにより空洞を形成した層を接合する方法や、犠牲層を形成し、犠牲層をエッチングする方法で空洞が形成できる。 In this example, a step of forming the bonding pad forming layer 10 in three layers and forming the cavity 6 in the second layer is provided. In the case of such a structure, as in the case of the second embodiment, the cavity can be formed by a method in which layers having cavities formed in advance by etching or a method in which a sacrificial layer is formed and the sacrificial layer is etched. .
１…半導体基板
２…酸化絶縁膜
３…半導体層
４…配線導体
５…接合層
６…空洞
７ａ，７ｂ…ビア導体
８…ガラス基板
９…ボンディングパッド
１０…ボンディングパッド形成層
５０…ボンディングワイヤー
５０Ｂ…バンプ
１０１，１０２，１０３…半導体装置 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Oxide insulating film 3 ... Semiconductor layer 4 ... Wiring conductor 5 ... Bonding layer 6 ... Cavity 7a, 7b ... Via conductor 8 ... Glass substrate 9 ... Bonding pad 10 ... Bonding pad formation layer 50 ... Bonding wire 50B ... Bump 101, 102, 103 ... Semiconductor device

Claims (3)

  1. 　素子が形成された半導体基板、および表面にボンディングパッドが形成されたボンディングパッド形成層を有し、
    　前記ボンディングパッドの下部において、前記ボンディングパッド形成層もしくは前記半導体基板に、または前記ボンディングパッド形成層と前記半導体基板とにまたがって、空洞が形成されていることを特徴とする半導体装置。     A semiconductor substrate having an element formed thereon, and a bonding pad forming layer having a bonding pad formed on the surface;
    A semiconductor device, wherein a cavity is formed below the bonding pad in the bonding pad forming layer or the semiconductor substrate or across the bonding pad forming layer and the semiconductor substrate.
  2. 　前記空洞は前記ボンディングパッドに形成されるバンプの形成域より広がっている、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the cavity extends from a bump formation area formed on the bonding pad.
  3. 　前記半導体基板に形成された素子はMEMS素子である、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the element formed on the semiconductor substrate is a MEMS element.
PCT/JP2013/064305 2012-05-25 2013-05-23 Semiconductor device WO2013176203A1 (en)

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Cited By (1)

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CN111868916A (en) * 2018-03-15 2020-10-30 微芯片技术股份有限公司 Integrated Circuit (IC) device including force mitigation system for reducing under-pad damage caused by wire bonding

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JP2009515348A (en) * 2005-11-09 2009-04-09 フラウンホーファー・ゲゼルシャフト・ツール・フェルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ Method for fabricating a conductive bushing on a nonconductive or semiconductive substrate
JP2009105160A (en) * 2007-10-22 2009-05-14 Renesas Technology Corp Semiconductor device

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JP2009515348A (en) * 2005-11-09 2009-04-09 フラウンホーファー・ゲゼルシャフト・ツール・フェルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ Method for fabricating a conductive bushing on a nonconductive or semiconductive substrate
JP2009105160A (en) * 2007-10-22 2009-05-14 Renesas Technology Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111868916A (en) * 2018-03-15 2020-10-30 微芯片技术股份有限公司 Integrated Circuit (IC) device including force mitigation system for reducing under-pad damage caused by wire bonding

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