TW201401396A - Semiconductor device - Google Patents
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- TW201401396A TW201401396A TW102113665A TW102113665A TW201401396A TW 201401396 A TW201401396 A TW 201401396A TW 102113665 A TW102113665 A TW 102113665A TW 102113665 A TW102113665 A TW 102113665A TW 201401396 A TW201401396 A TW 201401396A
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/05556—Shape in side view
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/1461—MEMS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Abstract
Description
本發明係關於一種半導體裝置，特別是關於一種於接合墊部具有特徵之半導體裝置。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a semiconductor device having features in a bonding pad portion.
於專利文獻1中，揭示有如下之構造：減少線接合時之相對於處於接合墊之下部之元件構造之衝擊。 Patent Document 1 discloses a configuration in which the impact of the element structure at the lower portion of the bonding pad at the time of wire bonding is reduced.
圖4係專利文獻1所示之半導體裝置之線接合部分之剖面圖。該半導體裝置係設為如下：形成包括形成有半導體元件之半導體基板10、相對於半導體元件電性導通之導電層12、16、設置於導電層間之絕緣層14、及保護膜18之積層體22，自該積層體22之上方滴下液狀之導電性樹脂材而於積層體上形成導電性樹脂層，藉由加熱而使導電性樹脂層硬化，藉此形成接合墊之衝擊緩衝層28，從而於衝擊緩衝層之上側，接合(bonding)接合線。 4 is a cross-sectional view showing a wire joint portion of the semiconductor device shown in Patent Document 1. The semiconductor device is formed by forming a semiconductor substrate 10 including a semiconductor element, conductive layers 12 and 16 electrically connected to the semiconductor element, an insulating layer 14 provided between the conductive layers, and a laminate 22 of the protective film 18. A liquid conductive resin material is dropped from above the laminated body 22 to form a conductive resin layer on the laminated body, and the conductive resin layer is cured by heating to form the impact buffer layer 28 of the bonding pad. Bonding the bonding wires on the upper side of the impact buffer layer.
[專利文獻1]日本專利特開2003-92306號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2003-92306
於專利文獻1所示之半導體裝置中，因其製程上之問題，而於衝擊緩衝層28即導電性樹脂層之厚度中產生不均。其結果，存在如下之虞：於多個接合墊中，產生無法實現接合時之衝擊吸收之部分。 In the semiconductor device shown in Patent Document 1, unevenness occurs in the thickness of the impact buffer layer 28, that is, the conductive resin layer, due to a problem in the process. As a result, there is a problem in that a part of the plurality of bonding pads is incapable of achieving impact absorption at the time of bonding.
本發明之目的在於提供一種減少接合時之衝擊吸收效果之不均而抑制接合時的元件損壞之可靠性較高之半導體裝置。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which is highly reliable in suppressing unevenness in impact absorption at the time of bonding and suppressing damage of components during bonding.
本發明之半導體裝置之特徵在於，其具有形成有元件之半導體基板、及於表面形成有接合墊之接合墊形成層，且 A semiconductor device according to the present invention is characterized in that it has a semiconductor substrate on which an element is formed, and a bonding pad forming layer on which a bonding pad is formed on the surface, and
於上述接合墊之下部，在上述接合墊形成層或者上述半導體基板上、或跨及上述接合墊形成層與上述半導體基板形成有空腔。 A cavity is formed in the bonding pad forming layer or the semiconductor substrate or across the bonding pad forming layer and the semiconductor substrate in the lower portion of the bonding pad.
較佳為，上述空腔廣於形成於上述接合墊之凸塊之形成區域。藉由該情形，接合時之接合墊之衝擊吸收效果提高。又，亦可減少因接合位置之不均引起之接合時之接合墊的衝擊吸收效果之不均。 Preferably, the cavity is wider than a formation region of the bump formed on the bonding pad. In this case, the impact absorption effect of the bonding pad at the time of joining is improved. Further, it is possible to reduce the unevenness of the impact absorbing effect of the bonding pad at the time of bonding due to the unevenness of the bonding position.
形成於上述半導體基板之元件係例如為MEMS(Micro Electro Mechanical System，微機電系統)元件。 The element formed on the semiconductor substrate is, for example, a MEMS (Micro Electro Mechanical System) element.
根據本發明，於接合墊之下部形成有空腔，因此不會對形成有元件之半導體基板直接施加超音波衝擊，從而可防止微細加工於半導體基板之元件、或者半導體裝置本身之損壞。 According to the present invention, since a cavity is formed in the lower portion of the bonding pad, ultrasonic interference is not directly applied to the semiconductor substrate on which the element is formed, and damage to the element which is finely processed on the semiconductor substrate or the semiconductor device itself can be prevented.
1‧‧‧半導體基板 1‧‧‧Semiconductor substrate
2‧‧‧氧化絕緣膜 2‧‧‧Oxidation insulating film
3‧‧‧半導體層 3‧‧‧Semiconductor layer
4‧‧‧配線導體 4‧‧‧Wiring conductor
5‧‧‧接合層 5‧‧‧ bonding layer
6‧‧‧空腔 6‧‧‧ Cavity
7a、7b‧‧‧通孔導體 7a, 7b‧‧‧ through-hole conductor
8‧‧‧玻璃基板 8‧‧‧ glass substrate
9‧‧‧接合墊 9‧‧‧Join pad
10‧‧‧接合墊形成層 10‧‧‧ Bonding pad formation
12‧‧‧導電層 12‧‧‧ Conductive layer
14‧‧‧絕緣層 14‧‧‧Insulation
16‧‧‧導電層 16‧‧‧ Conductive layer
18‧‧‧保護膜 18‧‧‧Protective film
22‧‧‧積層體 22‧‧‧Layered body
28‧‧‧衝擊緩衝層 28‧‧‧ Shock buffer layer
50‧‧‧接合線 50‧‧‧bonding line
50B‧‧‧凸塊 50B‧‧‧Bumps
101、102、103‧‧‧半導體裝置 101, 102, 103‧‧‧ semiconductor devices
圖1係作為本發明之第1實施形態之半導體裝置之主要部分的剖面圖。 Fig. 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention.
圖2係作為本發明之第2實施形態之半導體裝置之主要部分的剖面圖。 Fig. 2 is a cross-sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention.
圖3係作為本發明之第3實施形態之半導體裝置之主要部分的剖面圖。 Fig. 3 is a cross-sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention.
圖4(A)、圖4(B)係專利文獻1之半導體裝置之線接合部分之剖面圖。 4(A) and 4(B) are cross-sectional views showing a wire joint portion of the semiconductor device of Patent Document 1.
圖1係作為本發明之第1實施形態之半導體裝置101之主要部分的剖面圖。該半導體裝置101包括由矽半導體基板1、形成於該半導體基板1上之氧化絕緣膜2、及半導體層3形成之SOI基板。於該SOI基板上形成配線導體4等而構成MEMS元件。於SOI基板之上部，介隔接合層5而接合有玻璃基板8。於玻璃基板8之表面，形成有接合墊9。 Fig. 1 is a cross-sectional view showing a main part of a semiconductor device 101 according to a first embodiment of the present invention. The semiconductor device 101 includes an SOI substrate formed of a germanium semiconductor substrate 1, an oxide insulating film 2 formed on the semiconductor substrate 1, and a semiconductor layer 3. A wiring conductor 4 or the like is formed on the SOI substrate to form a MEMS element. The glass substrate 8 is bonded to the upper portion of the SOI substrate via the bonding layer 5. On the surface of the glass substrate 8, a bonding pad 9 is formed.
於玻璃基板8之接合墊9之下部之接合層5的位置，形成有空腔6。又，於接合層5及玻璃基板8，形成有使接合墊9與配線導體4之間導通之通孔導體7a、7b。而且，如圖1所示，接合線50線接合於接合墊9。即，凸塊50B係於空腔6之上部，形成於接合墊9。 A cavity 6 is formed at a position of the bonding layer 5 at the lower portion of the bonding pad 9 of the glass substrate 8. Further, through-hole conductors 7a and 7b that electrically connect the bonding pad 9 and the wiring conductor 4 are formed on the bonding layer 5 and the glass substrate 8. Further, as shown in FIG. 1, the bonding wires 50 are wire-bonded to the bonding pads 9. That is, the bump 50B is attached to the upper portion of the cavity 6 and formed on the bonding pad 9.
上述接合層5為聚醯亞胺膜，且藉由光微影法而形成空腔6。具體而言，藉由以下之步驟而形成。 The bonding layer 5 is a polyimide film, and the cavity 6 is formed by photolithography. Specifically, it is formed by the following steps.
(A)於在SOI基板上，塗佈聚醯亞胺前驅物後，進行預烘烤，從而形成聚醯亞胺前驅物被膜。 (A) After coating the polyimide precursor on the SOI substrate, prebaking is performed to form a polyimide film of the polyimide precursor.
(B)藉由光微影法，於聚醯亞胺前驅物被膜，形成變為空腔6之開口。 (B) An opening which becomes the cavity 6 is formed by the photolithography method on the polyimide film of the polyimide precursor.
(C)對經圖案化之聚醯亞胺前驅物被膜進行熱處理。 (C) heat treating the patterned polyimide precursor film.
以此方式，形成於特定位置具有空腔之聚醯亞胺之接合層5。再者，通孔導體7a、7b係例如藉由鍍敷方法、濺鍍方法、蒸鍍方法等成膜方法而形成。 In this way, the bonding layer 5 of the polyimide having a cavity at a specific position is formed. Further, the via hole conductors 7a and 7b are formed by, for example, a film formation method such as a plating method, a sputtering method, or a vapor deposition method.
根據本發明，於接合墊(可接合之電極膜)之下部，形成有空腔，因此凸塊50B之超音波衝擊不會直接傳達至微細加工於下部之半導體基板之元件。因此，MEMS元件之振動部不會因接合時之超音波振動而過度地振動、或施加過度之加速度，從而可防止MEMS元件之損壞。 According to the present invention, a cavity is formed under the bonding pad (the electrode film that can be bonded), so that the ultrasonic shock of the bump 50B is not directly transmitted to the element of the semiconductor substrate finely processed to the lower portion. Therefore, the vibrating portion of the MEMS element does not excessively vibrate due to ultrasonic vibration at the time of joining, or excessive acceleration is applied, thereby preventing damage of the MEMS element.
又，空腔6係較凸塊50B之形成區域更廣地形成。因此，接合時 之接合墊之衝擊吸收效果較高。又，因接合位置之不均引起之接合時之接合墊的衝擊吸收效果之不均亦較小。 Further, the cavity 6 is formed wider than the formation region of the bump 50B. Therefore, when joining The impact pad has a higher impact absorption effect. Further, the unevenness of the impact absorbing effect of the bonding pad at the time of joining due to the unevenness of the joining position is also small.
第1實施形態係表示於SOI基板之上部，介隔接合層5而接合玻璃基板8，且於接合層5形成有空腔之例，但本發明並不限定於該構造。又，第1實施形態係表示使用有SOI基板之例，但本發明並不限定於此。又，形成於半導體基板之元件並不限定於MEMS元件，亦可適用包括其他半導體元件之半導體裝置，且可抑制因接合時之衝擊引起之半導體裝置本身之劣化或破損。第2實施形態係表示如下之半導體裝置：於半導體基板表面，設置接合墊形成層，且不具有接合層。 The first embodiment is an example in which the glass substrate 8 is bonded to the upper portion of the SOI substrate by interposing the bonding layer 5, and a cavity is formed in the bonding layer 5. However, the present invention is not limited to this structure. Further, the first embodiment shows an example in which an SOI substrate is used, but the present invention is not limited thereto. Moreover, the element formed on the semiconductor substrate is not limited to the MEMS element, and a semiconductor device including another semiconductor element can be applied, and deterioration or breakage of the semiconductor device itself due to an impact at the time of bonding can be suppressed. The second embodiment shows a semiconductor device in which a bonding pad forming layer is provided on the surface of a semiconductor substrate without a bonding layer.
圖2係作為第2實施形態之半導體裝置102之主要部分之剖面圖。該半導體裝置102具有形成有元件之矽半導體基板1、及於表面形成有接合墊9之接合墊形成層10。於接合墊形成層10之內部，形成有空腔6。 Fig. 2 is a cross-sectional view showing a main part of a semiconductor device 102 as a second embodiment. The semiconductor device 102 has a germanium semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 on which a bonding pad 9 is formed. Inside the bonding pad forming layer 10, a cavity 6 is formed.
接合墊形成層10為矽層或玻璃層等。該接合墊形成層10係藉由濺鍍等而成膜於矽半導體基板1上者。 The bonding pad forming layer 10 is a ruthenium layer, a glass layer or the like. The bonding pad forming layer 10 is formed on the germanium semiconductor substrate 1 by sputtering or the like.
上述接合墊形成層10亦可藉由如下方式設置：將於另一步驟中所形成之矽層或玻璃層等接合至矽半導體基板1。於將接合墊形成層10接合至矽半導體基板1之情形時，可介隔接合層，亦可不介隔接合層。於設置接合層之情形時，可介隔聚醯亞胺膜或玻璃料之層而將接合墊形成層10接合至矽半導體基板1。於不設置接合層之情形時，可藉由陽極接合法或熔融接合法而接合。 The bonding pad forming layer 10 may be provided by bonding a germanium layer or a glass layer or the like formed in another step to the germanium semiconductor substrate 1. In the case where the bonding pad forming layer 10 is bonded to the germanium semiconductor substrate 1, the bonding layer may be interposed or may not be interposed. In the case where the bonding layer is provided, the bonding pad forming layer 10 may be bonded to the germanium semiconductor substrate 1 via a layer of a polyimide film or a frit. When the bonding layer is not provided, it can be joined by an anodic bonding method or a fusion bonding method.
上述空腔可藉由如下方法形成：接合預先藉由蝕刻而形成有空腔之層；或形成犧牲層，對犧牲層進行蝕刻。 The cavity may be formed by bonding a layer in which a cavity is previously formed by etching, or forming a sacrificial layer to etch the sacrificial layer.
再者，於圖2所示之例中，將於接合墊形成層10與半導體基板1之接合部，向接合墊形成層10側凹陷之部位形成為空腔6，但該空腔6 亦可於接合墊形成層10與半導體基板1之接合部，向半導體基板1側凹陷。又，亦可跨及接合墊形成層10與半導體基板1之兩者而形成有空腔。 Further, in the example shown in FIG. 2, a portion where the bonding pad forming layer 10 and the semiconductor substrate 1 are recessed toward the bonding pad forming layer 10 side is formed as a cavity 6, but the cavity 6 is formed. The junction between the bonding pad forming layer 10 and the semiconductor substrate 1 may be recessed toward the semiconductor substrate 1 side. Further, a cavity may be formed across the bonding pad forming layer 10 and the semiconductor substrate 1.
第3實施形態係表示於接合墊形成層之內部，形成有空腔之半導體裝置。 The third embodiment is a semiconductor device in which a cavity is formed inside a bonding pad forming layer.
圖3係作為第3實施形態之半導體裝置103之主要部分之剖面圖。該半導體裝置103具有形成有元件之矽半導體基板1、及於表面形成有接合墊9之接合墊形成層10。於接合墊形成層10之內部，形成有空腔6。 Fig. 3 is a cross-sectional view showing a main part of a semiconductor device 103 as a third embodiment. The semiconductor device 103 has a germanium semiconductor substrate 1 on which elements are formed, and a bonding pad forming layer 10 on which a bonding pad 9 is formed. Inside the bonding pad forming layer 10, a cavity 6 is formed.
接合墊形成層10為矽層或玻璃層等。該接合墊形成層10係藉由濺鍍等而成膜於矽半導體基板1上者。 The bonding pad forming layer 10 is a ruthenium layer, a glass layer or the like. The bonding pad forming layer 10 is formed on the germanium semiconductor substrate 1 by sputtering or the like.
於該例中，設置有如下步驟：將接合墊形成層10形成為3層，且於第2層形成空腔6。於此種構造之情形時，與第2實施形態之情形相同地，亦可藉由如下方法形成空腔：接合預先藉由蝕刻而形成有空腔之層；或形成犧牲層，對犧牲層進行蝕刻。 In this example, the following steps are provided: the bonding pad forming layer 10 is formed into three layers, and the cavity 6 is formed in the second layer. In the case of such a structure, as in the case of the second embodiment, the cavity may be formed by bonding a layer in which a cavity is previously formed by etching, or forming a sacrificial layer to perform the sacrificial layer. Etching.
1‧‧‧半導體基板 1‧‧‧Semiconductor substrate
2‧‧‧氧化絕緣膜 2‧‧‧Oxidation insulating film
3‧‧‧半導體層 3‧‧‧Semiconductor layer
4‧‧‧配線導體 4‧‧‧Wiring conductor
5‧‧‧接合層 5‧‧‧ bonding layer
6‧‧‧空腔 6‧‧‧ Cavity
7a、7b‧‧‧通孔導體 7a, 7b‧‧‧ through-hole conductor
8‧‧‧玻璃基板 8‧‧‧ glass substrate
9‧‧‧接合墊 9‧‧‧Join pad
50‧‧‧接合線 50‧‧‧bonding line
50B‧‧‧凸塊 50B‧‧‧Bumps
101‧‧‧半導體裝置 101‧‧‧Semiconductor device
Claims (3)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012119277 | 2012-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201401396A true TW201401396A (en) | 2014-01-01 |
Family
ID=49623884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102113665A TW201401396A (en) | 2012-05-25 | 2013-04-17 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| TW (1) | TW201401396A (en) |
| WO (1) | WO2013176203A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10896888B2 (en) * | 2018-03-15 | 2021-01-19 | Microchip Technology Incorporated | Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005053494A1 (en) * | 2005-11-09 | 2007-05-16 | Fraunhofer Ges Forschung | Process for producing electrically conductive feedthroughs through non-conductive or semiconductive substrates |
| JP5329068B2 (en) * | 2007-10-22 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2013
- 2013-04-17 TW TW102113665A patent/TW201401396A/en unknown
- 2013-05-23 WO PCT/JP2013/064305 patent/WO2013176203A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013176203A1 (en) | 2013-11-28 |
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