WO2013172238A1

WO2013172238A1 - Method for producing thin-film transistor

Info

Publication number: WO2013172238A1
Application number: PCT/JP2013/062961
Authority: WO
Inventors: 雅司小野; 真宏高田; 田中　淳; 鈴木　真之
Original assignee: 富士フイルム株式会社
Priority date: 2012-05-14
Filing date: 2013-05-08
Publication date: 2013-11-21
Also published as: KR101717336B1; TWI585986B; JP5901420B2; JP2013239532A; KR20140143844A; TW201349512A

Abstract

Provided is a method for producing a thin-film transistor, the method involving an oxide semiconductor layer formation step in which an oxide semiconductor layer is formed from: a first region having a composition represented by In_(a)Ga_(b)Zn_(c)O_(d) (wherein a, b, c, d>0); and a second region which is disposed farther away from the gate electrode than the first region and which has a composition that is different from the first region and that is represented by In_(e)Ga_(f)Zn_(g)O_(h) (wherein e, f, g, h>0) in which f/(e+f)≤0.875. The method also involves a heat treatment step in which the oxide semiconductor layer is subjected to heat treatment at 300°C or higher in a moist atmosphere having an absolute humidity of 4.8 g/m³ or higher.

Description

Thin film transistor manufacturing method

The present invention relates to a method for manufacturing a thin film transistor.

In recent years, research and development of thin film transistors (TFTs) using an In—Ga—Zn—O-based (hereinafter referred to as IGZO) oxide semiconductor thin film as an active layer (channel layer) have been actively conducted. An oxide semiconductor thin film can be formed at a low temperature, has higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible thin film transistor is formed on a substrate such as a plastic plate or a film. Is possible.

Here, Table 1 shows a comparison of field effect mobility and process temperature of various transistor characteristics.

As shown in Table 1, a thin film transistor whose active layer is polysilicon can obtain a mobility of about 100 cm ² / Vs. However, since the process temperature is as high as 450 ° C. or higher, it can be applied only to a substrate having high heat resistance. It cannot be formed and is not suitable for low cost, large area, and flexibility. In addition, since the thin film transistor whose active layer is amorphous silicon can be formed at a relatively low temperature of about 300 ° C., the selectivity of the substrate is wider than that of polysilicon, but only a mobility of about 1 cm ² / Vs can be obtained at most. Not suitable for fine display applications.
On the other hand, from the viewpoint of low-temperature film formation, thin film transistors whose organic active layer is organic can be formed at 100 ° C. or lower, and therefore are expected to be applied to flexible display applications using plastic film substrates with low heat resistance. The mobility is only as high as that of amorphous silicon.

For example, in Japanese Patent Application Laid-Open No. 2010-21555, as an active layer, a high mobility layer containing an oxide of IZO, ITO, GZO, or AZO is disposed on the side close to the gate electrode, and on the side far from the gate electrode. A thin film transistor having an oxide layer containing Zn is disclosed.
A thin film transistor using an oxide semiconductor, in particular an oxide semiconductor containing In, Ga, and Zn, as an active layer has a property that a threshold voltage is negatively shifted when irradiated with light having a wavelength shorter than 460 nm. Has been reported (see CS Chuang et al., SID 08 DIGEST, P-13).

The blue light-emitting layer used in organic EL and liquid crystals shows broad light emission with a peak of about λ = 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to 420 nm, blue color In consideration of passing about 70% of 400 nm light, the filter is required to have low characteristic deterioration with respect to light irradiation in a wavelength region smaller than 450 nm. If the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, a threshold shift of the transistor occurs.

On the other hand, with the increase in size and definition of displays, there is a demand for higher mobility of thin film transistors for driving the display. Covering with amorphous silicon and conventional IGZO elements (mobility of about 10 cmA ² / Vs) High-function displays that cannot be performed are being proposed.
As one of the methods for realizing high mobility, there is a TFT having a structure in which a plurality of active layers made of oxide semiconductors are stacked. In such a stacked TFT, in order to reduce deterioration in characteristics due to light irradiation. No attempt has been made to improve the light irradiation stability essentially without providing a protective layer or the like or a blocking layer on the active layer.

Here, for example, when a threshold shift amount (ΔVth) for 420 nm light irradiation is set to 1 V or less as an index of stability to light irradiation, a stacked TFT satisfying ΔVth ≦ 1V for 420 nm light irradiation is formed. It is difficult to realize.
In Japanese Patent Laid-Open No. 2010-21555, an IZO system or the like is used as a current path layer, and a high mobility TFT can be realized, but the light irradiation characteristics are not mentioned.
In addition, CS Chuang et al., SID 08 DIGEST, P-13 evaluated the deterioration of characteristics of conventional IGZO single-film TFT elements with respect to light irradiation. Insufficient characteristics regarding irradiation stability.

In addition, when the stacked TFT structure is adopted, it is assumed that a large number of defect levels that contribute to deterioration of light stability are likely to be formed at the stacked interface due to damage during film formation. In general, in the laminated structure, carriers move due to the lamination of the active layer, so that a hamp effect that causes an increase in off-current is likely to occur, and the light stability and on / off characteristics of the TFT are deteriorated.
Under such circumstances, it is difficult to suppress the hamp effect while realizing high light stability in the stacked TFT.

The present invention manufactures a stacked thin film transistor that realizes high light stability (ΔVth ≦ 1V with respect to light irradiation at λ = 420 nm) and suppresses the hump effect in the Vg-Id characteristic by a relatively simple manufacturing process. It is an object to provide a method for manufacturing a thin film transistor.

Examples of embodiments of the present invention are described below.
<1> As the oxide semiconductor layer of a thin film transistor including an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, In _(a) Ga _(b) Zn _(c) O _{( d)} a first region having a composition represented by (a> 0, b> 0, c> 0, d> 0), and a region farther from the gate electrode than the first region; _(E) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0), satisfying f / (e + f) ≦ 0.875, An oxide semiconductor layer forming step of forming a second region having a composition different from that of the first region;
A heat treatment step of performing heat treatment at 300 ° C. or higher in a humid atmosphere with an absolute humidity of 4.8 g / m ³ or higher on the oxide semiconductor layer;
A method of manufacturing a thin film transistor including:
<2> The method for producing a thin film transistor according to <1>, wherein the composition of the first region is in a range satisfying b ≦ 91a / 74−17 / 40 (provided that a + b + c = 1).
<3> The method for producing a thin film transistor according to <1> or <2>, wherein the heat treatment step is performed at an absolute humidity of 9.5 g / m ³ or more.
<4> The composition of the first region is
c ≦ 3/5,
b> 0,
b ≧ 3a / 7-3 / 14,
b ≧ 9a / 5−53 / 50,
b ≦ −8a / 5 + 33/25, and
b ≦ 91a / 74-17 / 40
The method for producing a thin film transistor according to <2> or <3>, wherein the thin film transistor is in a range satisfying the above (provided that a + b + c = 1).
<5> The composition of the first region is
b ≦ 17a / 23-28 / 115,
b ≧ 3a / 37,
b ≧ 9a / 5−53 / 50, and
b ≦ 1/5
The manufacturing method of the thin-film transistor as described in <4> in the range which satisfy | fills.
<6> The method for manufacturing a thin film transistor according to any one of <1> to <5>, wherein the composition of the second region satisfies f / (e + f)> 0.25.
<7> The method for manufacturing a thin film transistor according to any one of <1> to <6>, wherein the film thickness of the second region is larger than 10 nm and smaller than 70 nm.
<8> The method for manufacturing a thin film transistor according to any one of <1> to <7>, wherein the film thickness of the first region is 5 nm or more and less than 10 nm.
<9> The method for manufacturing a thin film transistor according to any one of <1> to <8>, wherein the oxide semiconductor layer is amorphous.
<10> The method for producing a thin film transistor according to <1> to <9>, wherein a heat treatment temperature in the heat treatment step is 400 ° C. or higher.
<11> The method for producing a thin film transistor according to <1> to <10>, wherein a heat treatment temperature in the heat treatment step is 450 ° C. or higher.

According to the present invention, a stacked thin film transistor that achieves high light stability (ΔVth ≦ 1V with respect to light irradiation at λ = 420 nm) and suppresses the hump effect in the Vg-Id characteristic can be obtained by a relatively simple manufacturing process. A method of manufacturing a thin film transistor that can be manufactured is provided.

FIG. 1 is a schematic diagram showing a configuration of an example (bottom gate-top contact type) of a thin film transistor according to the present invention. FIG. 2 is a schematic diagram showing the configuration of an example (top gate-bottom contact type) thin film transistor according to the present invention. FIG. 3A is a cross-sectional STEM image showing immediately after the IGZO laminated film is laminated, and FIG. 3B is a cross-sectional STEM image showing the IGZO laminated film after 600 ° C. annealing. FIG. 4 is a schematic diagram of the light irradiation characteristic evaluation method. FIG. 5 is a diagram showing the moisture content dependency of the Vg-Id characteristics in the annealing atmosphere. FIG. 6 is a graph showing changes in Vg-Id characteristics under light irradiation in Example 1. FIG. FIG. 7 is a diagram illustrating the threshold shift amount ΔVth with respect to the irradiation wavelength in the first embodiment. FIG. 8 is a schematic cross-sectional view showing a part of the liquid crystal display device of the embodiment. FIG. 9 is a schematic configuration diagram of electrical wiring of the liquid crystal display device of FIG. FIG. 10 is a schematic cross-sectional view showing a part of the organic EL display device of the embodiment. FIG. 11 is a schematic configuration diagram of electrical wiring of the organic EL display device of FIG. FIG. 12 is a schematic cross-sectional view showing a part of the X-ray sensor array of the embodiment. FIG. 13 is a schematic configuration diagram of electrical wiring of the X-ray sensor array of FIG. FIG. 14 shows the composition range of the first region in the oxide semiconductor layer of the thin film transistor of the present invention and the composition and mobility of the first region in the oxide semiconductor layer of Example and Comparative Example in a ternary phase diagram method. FIG.

Hereinafter, a method for manufacturing a thin film transistor of the present invention, and a display device, a sensor, and an X-ray sensor (digital imaging device) including the thin film transistor manufactured according to the present invention will be specifically described with reference to the drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals and description thereof is omitted as appropriate.

In the thin film transistor manufacturing method of the present invention, an In _(a) Ga _{(b) is used} as the oxide semiconductor layer of a thin film transistor including an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. A first region having a composition represented by Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0), and farther from the gate electrode than the first region In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0), f / (e + f) ≦ 0. Forming a second region satisfying 875 and having a composition different from that of the first region (oxide semiconductor layer forming step);
Heat-treating the oxide semiconductor layer at a temperature of 300 ° C. or higher (heat treatment step) in a humid atmosphere with an absolute humidity of 4.8 g / m ³ or higher.

In general, in the case of a stacked thin film transistor having an active layer stacked structure, carriers flow into a region having a high electron affinity from a region having a low electron affinity due to the magnitude relationship of the electron affinity of each region. When carrier inflow into the first region relatively close to the gate electrode occurs, a parasitic conduction path may be formed in addition to the main channel path generated at the interface between the first region and the gate insulating film. . The presence of such parasitic conduction causes a hump effect in the Vg-Id characteristic and deteriorates the On / Off ratio. In addition, if the number of carriers in the parasitic conduction path increases due to light irradiation, or the photo-excited carriers in another layer are trapped in the trap level near the parasitic conduction path, the off-current increases and the current rises in the transistor. It causes a voltage shift and leads to light instability.

In the stacked thin film transistor, since the first region and the second region are semiconductor layers having different compositions, a situation in which a large number of defect levels exist at the interface between the first and second regions is easy. I can imagine. In particular, in the case of an oxide semiconductor, a defect level due to oxygen defects exists, and such a defect level is an in-gap level formed in a band gap. Such an in-gap level causes photocurrent generation and the accompanying threshold shift, even if light irradiation with energy smaller than the band gap is caused, which also causes photoinstability.

When forming an IGZO layer as an oxide semiconductor layer, the present inventors have a first region and a second region having a specific composition range (f / (e + f) ≦ 0.875) from the side close to the gate electrode. However, the effect of effectively suppressing the hump effect can be obtained by annealing in a specific moist atmosphere, and the threshold shift amount ΔVth for light irradiation with a wavelength of 420 nm is 1V. I found that it would be less.
The thin film transistor manufacturing method of the present invention reduces the defects at the interface between the first region and the second region inside the active layer by annealing in a specific wet atmosphere, thereby increasing the high mobility of the stacked thin film transistor. It is possible to impart high light stability while maintaining. This is because moisture contained in a humid atmosphere is taken into the active layer in the form of OH groups and H, contributing to the reduction of dangling bonds at the interface existing inside the active layer and the reduction of parasitic conduction paths. It is believed that there is.

First, a thin film transistor (referred to as “TFT” as appropriate) manufactured according to the present invention will be described with reference to the drawings. Note that the TFT shown in FIGS. 1 and 2 will be specifically described as a representative example, but the present invention can also be applied to the manufacture of TFTs of other forms (structures).

The element structure of the TFT of the present invention may be either a so-called bottom gate type structure (also called an inverted staggered structure) or a top gate type structure (also called a staggered structure) based on the position of the gate electrode. The top gate structure is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an active layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer. . The bottom-gate structure is a form in which a gate electrode is disposed below the gate insulating film and an active layer is formed above the gate insulating film when the substrate on which the TFT is formed is the lowest layer. .
The element structure of the TFT of the present invention is based on a contact portion between an oxide semiconductor layer and a source electrode and a drain electrode (referred to as “source / drain electrodes” as appropriate), which is a so-called top contact type or bottom contact type. The aspect of this may be sufficient. The bottom contact type structure is a form in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type structure is a form in which the active layer is formed before the source / drain electrodes and the upper surface of the active layer is in contact with the source / drain electrodes.
In addition to the above, the TFT according to the present invention can have various configurations, and may appropriately have a configuration including a protective layer on the active layer and an insulating layer on the substrate.

FIG. 1 is a sectional view schematically showing the configuration of a thin film transistor 1 according to the first embodiment of the present invention, and FIG. 2 is a schematic view showing the configuration of the thin film transistor 2 according to the second embodiment of the present invention. In each thin-

film transistor

1 and 2 of FIG. 1 and FIG. 2, the same code | symbol is attached | subjected to the common element.
The thin film transistor 1 of the first embodiment shown in FIG. 1 is a bottom gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 2 is a top gate-bottom contact type transistor. In the embodiment shown in FIGS. 1 and 2, the arrangement of the gate electrode 16, the source electrode 13, and the drain electrode 14 with respect to the oxide semiconductor layer 12 is different, but the function of each element given the same reference numeral is the same. Similar materials can be applied.

The

thin film transistors

1 and 2 according to the embodiment of the present invention include a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12, a source electrode 13, and a drain electrode 14, and the oxide semiconductor layer 12 includes The first region A1 and the second region A2 are provided from the side closer to the gate electrode 16 in the film thickness direction. The first region A1 and the second region A2 constituting the oxide semiconductor layer 12 are continuously formed, and an insulating layer, an electrode layer, or the like is provided between the first region A1 and the second region A2. Layers other than the oxide semiconductor layer are not interposed, and are formed of an oxide semiconductor film.
Hereinafter, each component including the substrate on which the

TFTs

1 and 2 of the present invention are formed will be described in detail.

(substrate)
The substrate 11 for forming the thin film transistor according to the present invention is not particularly limited as long as it has heat resistance of 300 ° C. or higher, and can be appropriately selected according to the purpose. it can. The structure of the substrate 11 may be a single layer structure or a laminated structure.
For example, a substrate made of an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin having high heat resistance such as polyimide, a resin composite material, or the like can be used.

Also, a silicon substrate, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate, or an aluminum with an oxide film whose surface insulation is improved by subjecting the surface to an oxidation treatment (for example, anodization treatment). A substrate or the like can be used.

Oxide Semiconductor Layer The oxide semiconductor layer 12 is referred to as a first region A1 (appropriately referred to as “A1 layer”) and a second region A2 (appropriately referred to as “A2 layer”) from the order close to the gate electrode 16. ), And is disposed to face the gate electrode 16 with the gate insulating film 15 in between. The first region A1 is an IGZO layer having a composition represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0). is there. On the other hand, the second region A2 located on the side farther than the first region A1 with respect to the gate electrode 16, that is, on the side opposite to the surface in contact with the gate insulating film 15 of the first region A1, is In _{(e )} Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0), satisfying f / (e + f) ≦ 0.875, the first region It is an IGZO layer having a composition different from A1.

First Region The first region A1 preferably satisfies b ≦ 91a / 74−17 / 40 (where a + b + c = 1), c ≦ 3/5, b> 0, b ≧ 3a / 7-3 / 14, b ≧ 9a / 5−53 / 50, b ≦ −8a / 5 + 33/25, and b ≦ 91a / 74−17 / 40 (where a + b + c = 1) are more desirable. In such a composition region, since the first region A1 has a higher electron affinity than the second region A2, the conduction channel is formed in the first region A1. Since the carrier mobility is also high in the composition region, a high mobility exceeding 20 cm ² / Vs is also realized.

Since the film of the first region A1 having the above composition also has a high carrier concentration, it is difficult to obtain sufficiently low off-state current and switching characteristics when the film of the first region A1 is used alone as an active layer. is there.

The first region A1 is b ≦ 17a / 23−28 / 115, b ≧ 3a / 37, b ≧ 9a / 5−53 / 50, and b ≦ 1/5 (where a + b + c = 1). It is desirable. If the composition of the first region A1 is within the composition range, a field-effect mobility of more than 30 cm ² / Vs can be realized.

The thickness of the first region A1 is desirably less than 10 nm. In the first region A1, it is preferable to use an extremely in-rich IGZO film that can easily achieve high mobility. However, since such a high mobility film has a high carrier concentration, the threshold value is greatly shifted to the negative side. there is a possibility. If the thickness of the first region A1 is 10 nm or more, the total carrier concentration in the active layer is in an excessive state, and pinch-off becomes relatively difficult.
On the other hand, the thickness of the first region A1 is preferably 5 nm or more from the viewpoint of obtaining uniformity and high mobility of the oxide semiconductor layer 12.

Second Region The second region A2 of the oxide semiconductor layer 12 is on the side farther than the first region A1 with respect to the gate electrode 16, that is, the surface in contact with the gate insulating film 15 in the first region A1. Located on the opposite side. The second region A2 is represented by In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0), and f / (e + f) ≦ The IGZO layer satisfies 0.875 and has a composition different from that of the first region A1.

It is desirable that the composition of the second region A2 is f / (e + f)> 0.25. If f / (e + f) ≦ 0.25 in the second region A2, the carrier concentration in the second region A2 increases, and the effect of carrier movement to the first region A1 becomes significant. There is a possibility that the carrier concentration in the first region A1 becomes excessively high, the off-current increases, and the threshold value is large and takes a negative value.

The thickness of the second region A2 is desirably 30 nm or more. If the thickness of the second region A2 is 30 nm or more, a reduction in off-current can be expected more reliably. On the other hand, if the thickness of the second region A2 is 10 nm or less, there is a risk of increasing the off-current or degrading the S value. The thickness of the second region A2 is preferably less than 70 nm. If the thickness of the second region is 70 nm or more, a reduction in off-current can be expected, but the resistance between the source / drain electrode layer and the first region A1 increases, resulting in a decrease in mobility. There is a risk of inviting. Therefore, the thickness of the second region A2 is desirably larger than 10 nm and smaller than 70 nm.

Overall thickness of oxide semiconductor layer The total thickness (total thickness) of the oxide semiconductor layer 12 is preferably about 10 to 200 nm, from the viewpoint of film uniformity and patterning property, and is 35 nm or more and less than 80 nm. Is more preferable.

The oxide semiconductor layer 12 (the first region A1 and the second region A2) is preferably amorphous. If the first and second regions A1 and A2 are amorphous films, there is no crystal grain boundary and a highly uniform film can be obtained.
Note that whether or not the laminated film composed of the first and second regions A1 and A2 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, it can be determined that the laminated film is amorphous.

The carrier concentration of the oxide semiconductor layer 12 can be controlled not only by the composition modulation of the regions A1 and A2, but also by the oxygen partial pressure control during film formation.
Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first and second regions A1 and A2. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and accordingly, the field effect mobility can be expected to increase. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the first region A1, it is possible to promote the oxidation of the film and reduce the amount of oxygen vacancies in the first region A1. .

Further, by doping a part of Zn of the oxide semiconductor layer 12 composed of the first and second regions A1 and A2 with element ions having a wider band gap, the light irradiation stability accompanying the increase of the optical band gap can be improved. Can be granted. Specifically, the band gap of the film can be increased by doping Mg. For example, by doping Mg in each region of the A1 layer and A2 layer, the band gap can be increased while maintaining the band profile of the laminated film, compared to a system in which the composition ratio of only In, Ga, and Zn is controlled. It is.

Since the blue light-emitting layer used in organic EL exhibits broad light emission having a peak at about λ = 450 nm, if the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, A threshold shift occurs. Therefore, it is preferable that the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.

Also, the carrier density in each of the first and second regions A1 and A2 can be arbitrarily controlled by cation doping. In order to increase the carrier density, a material that tends to be a cation having a relatively large valence (eg, Ti, Zr, Hf, Ta, etc.) may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. ) To control the carrier density.

Source / Drain Electrode The source electrode 13 and the drain electrode 14 are not particularly limited in terms of material and structure as long as both have high conductivity. For example, metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, metal oxide such as Al—Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), etc. The source /

drain electrodes

13 and 14 can be formed of a conductive film or the like as a single layer or a laminated structure of two or more layers.

In the case where the source electrode 13 and the drain electrode 14 are made of the above metal or metal oxide, the film thickness, the patterning property by etching or lift-off method, the conductivity, and the like are each independently 10 nm or more. , 1000 nm or less, preferably 50 nm or more and 100 nm or less.

Gate Insulating Film The gate insulating film 15 is a layer that separates the gate electrode 16, the oxide semiconductor 12, and the source /

drain electrodes

13, 14, and preferably has high insulating properties. For example, the gate insulating film 15 is composed of an insulating film such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO _2, or an insulating film containing two or more of these compounds. be able to.

Note that the gate insulating film 15 needs to have a sufficient thickness to reduce leakage current and improve voltage resistance. On the other hand, if the thickness is too large, the drive voltage increases. Although depending on the material, the thickness of the gate insulating film 15 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

Gate electrode The gate electrode 16 is not particularly limited as long as it has high conductivity. For example, metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, metal oxide such as Al—Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), etc. A gate electrode can be formed using a conductive film or the like as a single layer or a stacked structure of two or more layers.

When the gate electrode 16 is composed of the metal or metal oxide, the thickness is preferably 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by etching or lift-off method, and the conductivity. 50 nm or more and 200 nm or less is more preferable.

Manufacturing Method of Thin Film Transistor Next, a manufacturing method of the bottom gate-top contact type thin film transistor 1 shown in FIG. 1 will be described. In addition, the constituent material of each part, thickness, etc. are as above-mentioned, and in order to avoid duplication description, it abbreviate | omits in the following description.

Formation of Gate Electrode First, a substrate 11 is prepared, and a layer other than the thin film transistor 1 is formed on the substrate 11 as necessary, and then a gate electrode 16 is formed.
The gate electrode 16 is used, for example, from a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with the material. For example, after the electrode film is formed, the gate electrode 16 is formed by patterning into a predetermined shape by etching or a lift-off method. At this time, it is preferable to pattern the gate electrode 16 and the gate wiring simultaneously.

Formation of Gate Insulating Film After forming the gate electrode 16, the gate insulating film 15 is formed.
The gate insulating film 15 is used from a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with the material. For example, the gate insulating film 15 may be patterned into a predetermined shape by photolithography and etching.

Formation of Oxide Semiconductor Layer Next, the oxide semiconductor layer 12 is formed in the order of the first region A1 and the second region A2 at a position facing the gate electrode 16 on the gate insulating film 15.

Film Formation of First Region As a first region of the oxide semiconductor layer 12, In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b> 0, c> 0, d > 0), preferably c ≦ 3/5, b> 0, b ≧ 3a / 7-3 / 14, b ≧ 9a / 5−53 / 50, b ≦ −8a / 5 + 33/25, and , B ≦ 91a / 74−17 / 40 (where a + b + c = 1), more preferably b ≦ 17a / 23−28 / 115, b ≧ 3a / 37, b ≧ 9a / 5−53 / 50 An IGZO layer having a composition in a range satisfying b ≦ 1/5 is formed.

A method for forming the first and second regions A1 and A2 constituting the oxide semiconductor layer 12 is not particularly limited, but it is preferable to form the film by a sputtering method. Since the sputtering method has a high deposition rate and can form a highly uniform film, an oxide semiconductor film with a large area can be formed at low cost. When the first region is formed by sputtering, a complex oxide target adjusted in advance to have a desired cation composition may be used, or ternary co-sputtering of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO. May be used.
The substrate temperature during film formation may be arbitrarily selected according to the substrate, but when a resin flexible substrate is used, the substrate temperature is preferably closer to room temperature in order to prevent deformation of the substrate.

Deposition of the second region Following the formation of the first region A1, In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0 The second region A2 having a composition satisfying f / (e + f) ≦ 0.875 and preferably satisfying f / (e + f)> 0.25 is formed.
The film formation in the second region A2 is a method of once stopping the film formation after the film formation in the first region A1, changing the oxygen partial pressure in the film formation chamber and the power applied to the target, and then restarting the film formation. Alternatively, the oxygen partial pressure in the deposition chamber and the power applied to the target may be changed quickly or slowly without stopping the deposition.
Further, the target may be a method of changing the input power by using the target used at the time of film formation in the first area A1, or switching the film formation from the first area A1 to the second area A2. At this time, a method may be used in which power supply to the target used for film formation in the first region A1 is stopped and power is applied to different targets including In, Ga, and Zn, or the first region A1. In addition to the target used for the film formation, a method of additionally applying power to a plurality of targets may be used.
The substrate temperature at the time of forming the second region A2 may be arbitrarily selected according to the substrate, but when a resin flexible substrate is used, as in the case of forming the first region A1, The substrate temperature is preferably closer to room temperature.

When the regions A1 and A2 are formed by sputtering, the oxide semiconductor layer 12 is preferably formed continuously without being exposed to the atmosphere. When the oxide semiconductor layer 12 is formed without being exposed to the air, impurities can be prevented from being mixed between the regions A1 and A2, and as a result, more excellent transistor characteristics can be obtained. In addition, since the number of film forming steps can be reduced, the manufacturing cost can also be reduced.
Note that in this embodiment, when the bottom-gate thin film transistor 1 is manufactured, the oxide semiconductor layer 12 is formed in the order of the first region A1 and the second region A2, and the top-gate type thin film transistor 1 shown in FIG. When the thin film transistor 2 is manufactured, the second region A2 and the first region A1 may be formed in this order.

Heat treatment step After forming the first region A1 and the second region A2 as the oxide semiconductor layer 12, the heat treatment step is performed at 300 ° C. in a humid atmosphere with an absolute humidity of 4.8 g / m ³ or more (dew point temperature of 0.8 ° C. or more). The above heat treatment (post-annealing treatment) is performed.
By performing heat treatment in such a humid atmosphere, the Hump effect can be suppressed as compared with the case where annealing is performed in a dry atmosphere with an absolute humidity of less than 4.8 g / m ^3. Instability to the generated light irradiation can be suppressed. From the viewpoint of enhancing light stability, the wet atmosphere in the heat treatment step is preferably performed at an absolute humidity of 9.5 g / m ³ or more (dew point temperature of 10.7 ° C. or more).

Further, the heat treatment temperature is preferably 400 ° C. or higher, and more preferably 450 ° C. or higher. When the heat treatment temperature is 400 ° C. or higher, the light irradiation stability can be extremely increased (for example, | ΔVth | ≦ 0.1 V for light irradiation of 420 nm).
Moreover, it is preferable that the heat processing time is 5 minutes or more and 120 minutes or less from a viewpoint of improving light irradiation stability reliably.
On the other hand, when the heat treatment is performed at a temperature of 600 ° C. or more, cation mutual diffusion occurs between the first region A1 and the second region A2, and the two regions are mixed. In this case, it is difficult to concentrate conductive carriers only in the first region. Therefore, the heat treatment temperature in the heat treatment step is desirably less than 600 ° C. Whether or not cation mutual diffusion occurs in the first region and the second region can be confirmed, for example, by performing analysis by cross-sectional TEM.

FIG. 3 is a cross-sectional STEM (scanning transmission electron microscope) image of a laminated film in which a total of five IGZO films of Ga / (In + Ga) = 0.75 and IGZO films of Ga / (In + Ga) = 0.25 are laminated. FIG. 3 (left; FIG. 3 (A)) shows a state immediately after stacking (before annealing) and FIG. 3 (right; FIG. 3 (B)) shows a case where the annealing temperature is 600 ° C. 3A and 3B, it can be confirmed that the laminated structure of the IGZO film maintains the laminated structure to some extent even when annealed at 600 ° C., but the contrast is blurred at the interface of different cation compositions. You can see the situation. This suggests that heterogeneous interdiffusion has begun to occur, and the upper limit temperature in the heat treatment step is desirably 600 ° C. or lower.

After the heat treatment, the oxide semiconductor layer 12 is patterned. Patterning can be performed by photolithography and etching. Specifically, a pattern of the oxide semiconductor layer 12 is formed by forming a resist pattern on the remaining portion by photolithography and etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid. Form.
Note that after the oxide semiconductor layer 12 is patterned, the heat treatment step, that is, heat treatment at 300 ° C. or higher may be performed in a humid atmosphere with an absolute humidity of 4.8 g / m ³ or higher.

Formation of Source / Drain Electrode Next, a metal film for forming the source /

drain electrodes

13 and 14 is formed on the oxide semiconductor layer 12.
Each of the source electrode 13 and the drain electrode 14 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as CVD or a plasma CVD method, or the like. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.
For example, the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 13 and the drain electrode 14 are formed. At this time, it is preferable to pattern the source /

drain electrodes

13 and 14 and the wiring (not shown) connected to these

electrodes

13 and 14 simultaneously.
Through the above procedure, the thin film transistor 1 illustrated in FIG. 1 can be manufactured.

By using the method of manufacturing a thin film transistor of the present invention, high mobility and high light irradiation stability can be obtained without using a protective layer or the like on the active layer for reducing characteristic deterioration against light irradiation. A protective layer as described above may be provided on the active layer. For example, by providing a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less), the stability against light irradiation can be further improved.

The thin film transistor manufactured according to the present invention has high light irradiation stability while suppressing the hamp effect, and can be applied to various devices. The display device and the sensor using the thin film transistor manufactured according to the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

FIG. 8 shows a schematic sectional view of a part of a liquid crystal display device which is an embodiment of a display device including a thin film transistor manufactured according to the present invention, and FIG. 9 shows a schematic configuration diagram of its electric wiring. Show.

As shown in FIG. 8, the liquid crystal display device 5 of the present embodiment includes a top gate-bottom contact type thin film transistor 2 shown in FIG. 2 and a pixel lower portion on the gate electrode 16 protected by the passivation layer 54 of the thin film transistor 2. A liquid crystal layer 57 sandwiched between the electrode 55 and the opposed upper electrode 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, respectively on the substrate 11 side and the color filter 58 of the TFT 2. It has a configuration including

polarizing plates

59a and 59b.

Further, as shown in FIG. 9, the liquid crystal display device 5 of this embodiment includes a plurality of gate wirings 51 that are parallel to each other and data wirings 52 that are parallel to each other and intersect the gate wirings 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 2 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 2 is electrically connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.

In the liquid crystal device of this embodiment shown in FIG. 8, the top gate type thin film transistor is provided. However, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type, A bottom-gate thin film transistor may be used.

Since the thin film transistor manufactured according to the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen. In particular, when the active layer (oxide semiconductor layer) 12 is amorphous, variations in device characteristics can be suppressed, and an excellent display quality with a large screen and no unevenness can be realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and thus the power consumption of the display device can be reduced.
Further, according to the present invention, the first region A1 and the second region A2 constituting the active layer can be formed using an amorphous film that can be formed at a low temperature (for example, 200 ° C. or less). Therefore, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible liquid crystal display device having excellent display quality.

Organic EL Display Device As an embodiment of a display device including a TFT manufactured according to the present invention, FIG. 10 shows a schematic sectional view of a part of an active matrix organic EL display device, and FIG. A schematic block diagram is shown.
There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

In the active matrix type organic EL display device 6 of the present embodiment, a top gate-top contact type thin film transistor is provided as a driving TFT 2a and a switching TFT 2b on a substrate 60 provided with a passivation layer 61a. On the

thin film transistors

2a and 2b, an organic light emitting element 65 comprising an organic light emitting layer 64 sandwiched between a lower electrode 62 and an upper electrode 63 is provided, and the upper surface is also protected by a passivation layer 61b.

As shown in FIG. 11, the organic EL display device 6 according to the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a data wiring 67 and a driving wiring 68 that are parallel to each other and intersect the gate wiring 66. I have. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16 b of the switching thin film transistor 2 b is connected to the gate line 66, and the source electrode 13 b of the switching thin film transistor 2 b is connected to the data line 67. The drain electrode 14b of the switching thin film transistor 2b is connected to the gate electrode 16a of the driving thin film transistor 2a, and the driving thin film transistor 2a is kept on by using the capacitor 69. The source electrode 13 a of the driving thin film transistor 2 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.

The organic EL device of this embodiment shown in FIG. 10 is also provided with the top gate type

thin film transistors

2a and 2b. However, the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type. Without limitation, a bottom-gate thin film transistor may be used.

Since the thin film transistor manufactured according to the present invention has high mobility, low power consumption and high quality display can be achieved. Further, according to the present invention, the first region A1 and the second region A2 constituting the active layer can be formed using an amorphous film that can be formed at a low temperature (for example, 200 ° C. or less). Therefore, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, a flexible organic EL display device having excellent display quality can be provided.

In the organic EL display device shown in FIG. 10, the top electrode 63 may be a top emission type with a transparent electrode, or the bottom electrode 62 and the

TFTs

2a and 2b may be a transparent electrode by using a transparent electrode. Good.

X-Ray Sensor FIG. 12 shows a schematic cross-sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 13 shows a schematic configuration diagram of its electrical wiring.
The X-ray sensor 7 of this embodiment includes a thin film transistor 2 and a capacitor 70 formed on a substrate 11, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. . A passivation film 75 is provided on the thin film transistor 2.

The capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 12) of the thin film transistor 2 through a contact hole 79 provided in the insulating film 78.

The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is provided so as to cover the thin film transistor 2 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

As shown in FIG. 13, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that are parallel to each other and intersect the gate wiring 81. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 2 is provided in the vicinity of the intersection between the gate line 81 and the data line 82.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 2 is connected to the charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with the grounded counter electrode 76.

In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper part (upper electrode 73 side) in FIG. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 2.

Since the X-ray sensor of the present invention includes the thin film transistor 2 having a high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. A range image is obtained.
In particular, the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the first region A1 and the second region A2 constituting the active layer in the thin film transistor 2 are amorphous, an image with excellent uniformity can be obtained.

In the X-ray sensor of this embodiment shown in FIG. 12, the top gate type thin film transistor is provided. However, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, but the bottom gate type. A thin film transistor may be used.

Experimental examples are described below, but the present invention is not limited to these examples.
The inventors of the present invention have a high light irradiation stability (| ΔVth | ≦ 1 V (with respect to light irradiation at 420 nm) while suppressing the hump effect by stacking an oxide semiconductor having a specific composition and a specific heat treatment. ) Was verified by the following experiment.

Dependence of moisture content in annealing atmosphere on TFT characteristics High oxide mobility and high light stability can be obtained by laminating an oxide semiconductor film with a specific composition as the active layer of a thin film transistor and annealing it in a humid atmosphere. It was verified that
First, as Examples 1 to 8 and Comparative Examples 1 to 5, the following bottom gate-top contact type thin film transistors were manufactured.

As the substrate, a p-type silicon substrate (manufactured by Mitsubishi Materials Corporation) on which a SiO ₂ oxide film (thickness: 100 nm) was formed on the surface and highly doped was used.

Next, an oxide semiconductor layer was formed over the p-type silicon substrate.
As the first region A1 included in the oxide semiconductor layer, In _(a) Ga _(b) Zn _(c) O _(d) (a = 37/60, b = 3/60, c = 20/60, d > 0) was sputtered with a thickness of 5 nm.
In the state where the A1 layer is fixed to the above composition, as the A2 layer, In _(e) Ga _(f) Zn _(g) O _(h) (f / (e + f) = 0.75, e> 0, f> 0, g > 0, h> 0), an IGZO layer having a thickness of 50 nm was formed by sputtering.
The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by ternary co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target in the regions A1 and A2. The film thickness in each region was adjusted by adjusting the film formation time.
The film formation conditions in the first region A1 and the second region are as follows, and sputtering conditions other than the composition of each region are common in the experiments described later.

Sputtering conditions for the first region A1 Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature: Room temperature Oxygen partial pressure / Argon partial pressure: 0.067

Sputtering conditions for the second region A2 Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature: room temperature Oxygen partial pressure / Argon partial pressure: 0.033

After stacking the oxide semiconductor layer by sputtering, an electrode layer made of Ti (10 nm) / Au (40 nm) was formed on the stacked film (oxide semiconductor layer) by vacuum vapor deposition through a metal mask.

After forming the electrode layer, a wet atmosphere was injected into the annealing chamber with the annealing temperature set to 400 ° C. (except for Comparative Example 5) and the oxygen partial pressure fixed (20%). The annealing time was 1 hour. A shunt-type humidity generator (SRG-1M-10L (trade name) manufactured by Shinei Technology Co., Ltd.) was used to generate a humid atmosphere. In Comparative Example 5, the annealing temperature was 200 ° C.

Thus, bottom gate type thin film transistors in Examples 1 to 8 and Comparative Examples 1 to 5 having a channel length of 180 μm and a channel width of 1 mm were obtained.

Mobility With respect to the TFTs of Examples 1 to 8 and Comparative Examples 1 to 5 thus manufactured, a semiconductor parameter analyzer 4156C (trade name; manufactured by Agilent Technologies) was used, and transistor characteristics (Vg-Id characteristics) and mobility μ were measured. Measurements were made.
Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10V, sweeping the gate voltage (Vg) within the range of -30V to + 30V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it. The off-current was defined as a current value at Vg = 0 V in the Vg-Id characteristic.
The mobility is linear mobility from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 1V. Was calculated.

Light Irradiation Stability After evaluating the Vg-Id characteristics of the fabricated TFT, the stability of the TFT characteristics against light irradiation was evaluated by irradiating monochromatic light with a variable wavelength. FIG. 4 shows an outline of TFT characteristic measurement under monochromatic light irradiation. As shown in FIG. 4, each TFT was placed on the probe stage stage 200, and after flowing dry air for 2 hours or more, TFT characteristics were measured under the dry air atmosphere. The irradiation intensity of the monochrome light source is 10 μW / cm ² , the wavelength λ is 360 to 700 nm, and the Vg-Id characteristics when the monochrome light is not irradiated are compared with the Vg-Id characteristics when the monochrome light is irradiated. Stability (ΔVth) was evaluated. The measurement conditions of the TFT characteristics under monochrome light irradiation were fixed by Vds = 10 V and measured by sweeping the gate voltage in the range of Vg = −15 to 15V. Unless otherwise specified below, all measurements are performed after irradiating with monochromatic light for 10 minutes. The threshold shift amount ΔVth for light irradiation of 420 nm was used as an indicator of the light stability of the TFT. In addition, the said evaluation method is common in subsequent experiment.

Table 2 shows a list of absolute humidity (dew point temperature) during annealing, composition of the A2 layer, and TFT characteristics.
FIG. 5 shows Vg-Id characteristics in the TFTs of Examples 1 to 4 and Comparative Examples 1 to 4.
In addition, FIG. 6 shows the IV characteristics during the monochrome light irradiation in the TFT of Example 1, and FIG. 7 shows the threshold shift amount ΔVth with respect to the irradiation wavelength.

In Examples 1 to 8, when the composition of the A2 layer is f / (e + f) ≦ 0.875, and the annealing step is 4.8 g / m ³ or more in absolute humidity (dew point temperature: 0.8 ° C. or more) It can be seen that both high mobility and high light stability can be achieved.

On the other hand, in the case of Comparative Example 1, the composition of the A2 layer is f / (e + f) ≦ 0.875, but the annealing process is less than 4.8 g / m ^{3 in} absolute humidity, and Vg as shown in FIG. A hum characteristic in the −Id characteristic (a bump appears in the IV characteristic) is remarkable, and the current value in the hump region increases during light irradiation, and detailed evaluation cannot be performed.
In Comparative Examples 2 and 3, the annealing conditions are the same as in Examples 4, 7, and 8, but the composition of the A2 layer does not satisfy f / (e + f) ≦ 0.875, and the hump is included in the Vg-Id curve. The effect appeared and the photostability could not be evaluated. Further, it can be seen that the threshold value is greatly shifted minus, and the off-current value (Id value at Vg = 0 V) is worse than that in the example.
From the above results, it is understood that the A2 layer has f / (e + f) ≦ 0.875, and high light stability can be realized while suppressing the hump effect by annealing (400 ° C.) at an absolute humidity of 4.8 g / m ³ or more. . In Comparative Example 5, the annealing temperature is 200 ° C. In this case, it can be seen that the composition conditions are satisfied but sufficient light stability is not obtained.

As shown in Table 2, in Examples 1 to 3 where the humidity was increased in the annealing atmosphere (corresponding to relative humidity of 88%, 70% and 55%, respectively), 420 nm (light irradiation energy hν = 2.95 eV). The results in are almost the same as those in the other examples, but the light stability is improved in the case of 400 nm (light irradiation energy hν = 3.10 eV) compared to the other examples. From this, it can be seen that when the humidity is increased, the deep gap level can be more effectively reduced in the oxide semiconductor.

A1 layer composition dependency of TFT characteristics TFT characteristics when the second region A2 is fixed to the IGZO layer (f / (e + f) = 0.75), and the first region A1 is composition-modulated and annealed. Are summarized in Table 3. The thickness of the first region A1 was 5 nm, and the thickness of the second region was 50 nm.
The annealing conditions are an absolute humidity of 15.3 g / m ³ , 400 ° C., and 1 hour.

As shown in Table 3 above, in Examples 9 to 20, although the composition of the A1 layer is different, the difference in light stability is small, and it is understood that the dependency of the composition of the A1 layer on the TFT characteristics, particularly light stability, is small.
Regarding the TFTs manufactured in Examples and Comparative Examples, the composition range of the first region A1 is shown in FIG. 14 by the ternary phase diagram method.

Annealing temperature dependence of TFT characteristics in a humid atmosphere The A1 layer composition was In: Ga: Zn = 37/60: 3/60: 20/60, and the A2 layer composition was f / (e + f) = 0.75. The thickness of the first region A1 was 5 nm, and the thickness of the second region was 50 nm.
The annealing conditions were such that the absolute humidity was 15.3 g / m ³ and only the annealing temperature was modulated. The mobility and light stability of the TFT were evaluated. The evaluation results are shown in Table 4 below.

From Table 4, it is possible to suppress ΔVth with light irradiation of 420 nm to be smaller than −0.1 V even when annealing in the same wet atmosphere is performed at 400 ° C. or higher, which is extremely light stable. A TFT element can be realized.

Although the use of the thin film transistor manufactured by the present invention described above is not particularly limited, for example, a display device as an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro-Luminescence) display device, an inorganic EL display device) Etc.) as a driving element.

Furthermore, the thin film transistor manufactured according to the present invention is a device such as a flexible display that can be manufactured by a low temperature process using a resin substrate, an image sensor such as a CCD (Charge-Coupled Device), a CMOS (Complementary Metal-Oxide Semiconductor), or an X-ray sensor. It is suitably used as a driving element (driving circuit) in various electronic devices such as various sensors such as MEMS (Micro Electro Mechanical System).

The display device and sensor of the present invention using the thin film transistor manufactured according to the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

The disclosure of Japanese Patent Application No. 2012-110773 is incorporated herein by reference in its entirety.
All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually stated to be incorporated by reference, Incorporated herein by reference.

Claims

As the oxide semiconductor layer of a thin film transistor including an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, In (a) Ga (b) Zn (c) O (d) ( a first region having a composition represented by a> 0, b> 0, c> 0, d> 0), a region farther from the gate electrode than the first region, and In (e) Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0), f / (e + f) ≦ 0.875, An oxide semiconductor layer forming step of forming a second region having a composition different from
A heat treatment step of performing heat treatment at 300 ° C. or higher in a humid atmosphere with an absolute humidity of 4.8 g / m 3 or higher on the oxide semiconductor layer;
A method of manufacturing a thin film transistor including:
2. The method of manufacturing a thin film transistor according to claim 1, wherein the composition of the first region is in a range satisfying b ≦ 91a / 74−17 / 40 (where a + b + c = 1).
The method of manufacturing a thin film transistor according to claim 1 or 2, wherein the heat treatment step is performed at an absolute humidity of 9.5 g / m 3 or more.
The composition of the first region is:
c ≦ 3/5,
b> 0,
b ≧ 3a / 7-3 / 14,
b ≧ 9a / 5−53 / 50,
b ≦ −8a / 5 + 33/25, and
b ≦ 91a / 74-17 / 40
4. The method for manufacturing a thin film transistor according to claim 2, wherein the method is in a range satisfying (where a + b + c = 1). 5.
The composition of the first region is:
b ≦ 17a / 23-28 / 115,
b ≧ 3a / 37,
b ≧ 9a / 5−53 / 50, and
b ≦ 1/5
The manufacturing method of the thin-film transistor of Claim 4 which exists in the range which satisfy | fills.
6. The method of manufacturing a thin film transistor according to claim 1, wherein the composition of the second region satisfies f / (e + f)> 0.25.
The method for manufacturing a thin film transistor according to any one of claims 1 to 6, wherein the film thickness of the second region is larger than 10 nm and smaller than 70 nm.
The method of manufacturing a thin film transistor according to any one of claims 1 to 7, wherein the film thickness of the first region is not less than 5 nm and less than 10 nm.
The method for manufacturing a thin film transistor according to any one of claims 1 to 8, wherein the oxide semiconductor layer is amorphous.
10. The method of manufacturing a thin film transistor according to claim 1, wherein a heat treatment temperature in the heat treatment step is 400 ° C. or higher.
11. The method of manufacturing a thin film transistor according to claim 1, wherein a heat treatment temperature in the heat treatment step is 450 ° C. or higher.