KR20140143844A - Method for producing thin-film transistor - Google Patents

Abstract

A first region having a composition represented by In _(a) Ga _(b) Zn _(c) O _(d) (a, b, c, d> 0) is _{disposed, in (e) Ga (f} ) Zn (g) O (h) (e, f, g, h> 0) as is and represents, f / (e + f) satisfies ≤ 0.875, and the first region A step of forming an oxide semiconductor layer for forming a second region having a different composition and a heat treatment step of performing heat treatment at 300 DEG C or more in a wet atmosphere having an absolute humidity of 4.8 g / And a manufacturing method thereof.

Description

METHOD FOR PRODUCING THIN-FILM TRANSISTOR [0002]

The present invention relates to a method of manufacturing a thin film transistor.

Recently, research and development of a thin film transistor (TFT) using an oxide semiconductor thin film of an In-Ga-Zn-O system (hereinafter referred to as IGZO) as an active layer (channel layer) is in full swing. Since the oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light, it is possible to form a flexible thin film transistor on a substrate such as a plastic plate or a film.

Table 1 shows the comparison of the field effect mobility and the process temperature of various transistor characteristics.

As shown in Table 1, although the thin film transistor whose active layer is polysilicon can obtain a mobility of about 100 cm 2 / Vs, since the process temperature is as high as 450 ° C or more, only a substrate with high heat resistance can not be formed, It is not suitable for inexpensive, large area, and flexible. Since the thin film transistor in which the active layer is amorphous silicon can be formed at a relatively low temperature of about 300 캜, the selectivity of the substrate is wider than that of polysilicon, but only a mobility of about 1 cm 2 / Vs is obtained, Not suitable for use.

On the other hand, from the viewpoint of low-temperature film formation, thin film transistors in which the active layer is an organic material can be formed at 100 DEG C or lower. Therefore, application to flexible display using low heat resistance plastic film substrates is expected. Only results equivalent to those of Perth silicon were obtained.

For example, in JP-A-2010-21555, a high mobility layer containing an oxide of IZO, ITO, GZO, or AZO is disposed on the side closer to the gate electrode as an active layer, A thin film transistor in which an oxide layer containing Zn is disposed is disclosed.

In addition, a thin film transistor using an oxide semiconductor, particularly an oxide semiconductor containing In, Ga and Zn as an active layer, has a property that a threshold voltage shifts to a negative value when light having a wavelength smaller than 460 nm is irradiated (CS Chuang et al., SID 08 DIGEST, see P-13).

The blue light emitting layer used for organic EL or liquid crystal exhibits broad light emission having a peak at about? = 450 nm, but the lower part of the light emission spectrum of blue light of the organic EL device continues to 420 nm, The color filter is required to have a low characteristic deterioration for light irradiation in a wavelength region smaller than 450 nm in consideration of passing light of 400 nm through about 70%. If the optical bandgap of the IGZO film is relatively narrow and the region has optical absorption, the threshold shift of the transistor will occur.

On the other hand, with the increase in size and high definition of the display, there is a demand for a higher degree of mobility of the thin film transistor for driving the display, and the use of amorphous silicon or a conventional IGZO element (mobility of about 10 cm ² / Vs) High-performance displays can not be offered.

As one of the methods for achieving high mobility, there is a TFT having a structure in which a plurality of active layers made of oxide semiconductors are laminated. In such a multilayer TFT, a protective layer for reducing characteristic deterioration upon light irradiation, There has been no attempt to improve the light irradiation stability without forming a layer on the active layer.

Here, for example, when a criterion that the threshold shift amount (? Vth) with respect to light irradiation at 420 nm is set to 1 V or less is provided as an index of stability against light irradiation,? Vth? 1 V Is difficult to realize.

Japanese Laid-Open Patent Publication No. 2010-21555 discloses a high mobility TFT using an IZO system or the like as a current path layer, but does not mention light irradiation characteristics.

CS Chuang et al., SID 08 DIGEST, and P-13 evaluated the deterioration of the characteristics of the conventional IGZO monolayer TFT with respect to light irradiation. From the above numerical values, however, Characteristics are insufficient.

Further, when a multilayer TFT structure is employed, it is assumed that a large number of defect levels, which contribute to deterioration in optical stability, are likely to be formed in the laminated interface due to damage during film formation or the like. In addition, in general, in the laminated structure, the carrier moves due to the lamination of the active layers, so that a hump (hump) effect that causes an increase in the off current is likely to occur, resulting in deterioration of the light stability and on / off characteristics of the TFT .

In such a situation, it is difficult to suppress the hump effect while realizing high light stability in a multi-layer TFT.

INDUSTRIAL APPLICABILITY The present invention relates to a laminate type thin film transistor in which a high light stability (DELTA Vth ≤ 1 V with respect to light irradiation of? = 420 nm) is realized and a hump effect in Vg- And a method for manufacturing the thin film transistor.

Examples of embodiments of the present invention are described below.

_(A) Ga _(b) Zn _(c) O _(d) ( _(a)) as the oxide semiconductor layer of the thin film transistor having the oxide semiconductor layer, the source electrode, the drain electrode, the gate insulating film, _(e) Ga _(f) Zn _{( f)} , which is disposed on a side farther from the gate electrode than the first region, and a second region having a composition represented by In (0), b> 0, c> to _{g) O (h) (e} > 0, f> 0, g> 0, h> 0) as shown, f / (e + f) ≤ satisfies 0.875, and with the first area is different composition second region having A step of forming an oxide semiconductor layer to be formed,

And a heat treatment step of subjecting the oxide semiconductor layer to a heat treatment at 300 DEG C or higher in a wet atmosphere having an absolute humidity of 4.8 g / m < 3 > or more.

<2> The method of manufacturing a thin film transistor according to <1>, wherein the composition of the first region is in a range satisfying b ≦ 91a / 74-17 / 40 (provided that a + b + c = 1).

<3> The method for manufacturing a thin film transistor according to <1> or <2>, wherein the heat treatment is performed at an absolute humidity of 9.5 g / m 3 or more.

&Lt; 4 &gt; The composition of claim 1,

c? 3/5,

b> 0,

b? 3a / 7 - 3/14,

b? 9a / 5 - 53/50,

b? -8a / 5 + 33/25,

b &lt; / = 91a / 74-17 / 40 wherein a + b + c = 1.

&Lt; 5 &gt; The composition of claim 1,

b? 17a / 23 - 28/115,

b? 3a / 37,

b? 9a / 5 - 53/50,

b &lt; / = 5. &lt; 4 &gt;

<6> The method of manufacturing a thin film transistor according to any one of <1> to <5>, wherein the composition of the second region satisfies f / (e + f)> 0.25.

<7> The method of manufacturing a thin film transistor according to any one of <1> to <6>, wherein the film thickness of the second region is larger than 10 nm and smaller than 70 nm.

<8> The method of manufacturing a thin film transistor according to any one of <1> to <7>, wherein the film thickness of the first region is 5 nm or more and less than 10 nm.

<9> The method of manufacturing a thin film transistor according to any one of <1> to <8>, wherein the oxide semiconductor layer is amorphous.

<10> The method for manufacturing a thin film transistor according to any one of <1> to <9>, wherein the heat treatment temperature in the heat treatment step is 400 ° C. or higher.

<11> The method for manufacturing a thin film transistor according to any one of <1> to <10>, wherein the heat treatment temperature in the heat treatment step is 450 ° C. or higher.

INDUSTRIAL APPLICABILITY According to the present invention, a laminate-type thin film transistor which realizes high light stability (DELTA Vth &amp;le; 1 V with respect to light irradiation of? = 420 nm) and suppresses hump effect in Vg- A method of manufacturing a thin film transistor is provided.

1 is a schematic view showing the structure of an example of a thin film transistor (bottom gate-top contact type) related to the present invention.
2 is a schematic diagram showing the configuration of an example of a thin film transistor (top gate-bottom contact type) related to the present invention.
Fig. 3 (A) is a cross-sectional STEM image immediately after lamination of the IGZO laminated film, and Fig. 3 (B) is a cross-sectional STEM image after annealing at 600 ° C of the IGZO laminated film.
4 is a schematic view of a method for evaluating light irradiation characteristics.
Fig. 5 is a graph showing the dependence of the Vg-Id characteristic on the moisture content in the annealing atmosphere. Fig.
Fig. 6 is a graph showing the change in Vg-Id characteristics under light irradiation in Example 1. Fig.
7 is a diagram showing the threshold shift amount? Vth with respect to the irradiation wavelength in the first embodiment.
8 is a schematic cross-sectional view showing a part of the liquid crystal display device of the embodiment.
9 is a schematic configuration diagram of the electric wiring of the liquid crystal display device of Fig.
10 is a schematic cross-sectional view showing a part of the organic EL display device according to the embodiment.
11 is a schematic configuration diagram of the electric wiring of the organic EL display device of Fig.
12 is a schematic cross-sectional view showing a part of the X-ray sensor array of the embodiment.
13 is a schematic configuration diagram of the electric wiring of the X-ray sensor array of Fig.
14 is a graph showing the composition range of the first region in the oxide semiconductor layer of the thin film transistor of the present invention and the composition and the mobility of the first region in the oxide semiconductor layers of Examples and Comparative Examples by a three- to be.

Hereinafter, a method of manufacturing a thin film transistor of the present invention and a display device, a sensor and an X-ray sensor (digital photographing apparatus) provided with the thin film transistor manufactured by the present invention will be described in detail with reference to the drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and a description thereof will be omitted as appropriate.

Method of manufacturing a TFT of the present invention, the oxide as a semiconductor layer, a source electrode and a drain electrode, a gate insulating film, the oxide semiconductor layer of the thin-film transistor having a gate _{electrode, In (a) Ga (b} ) Zn ( _{c) O (d) (a} > 0, b> 0, c> 0, d> and the first zone having a composition represented by 0), is arranged on the first long side from the gate electrode than the first region, in _{(e ) Ga (f) Zn (g} ) O (h) (e> 0, f> 0, g> 0, h> 0) as shown, f / (e + f) ≤ satisfies 0.875, and is from the first region Forming a second region having a different composition (an oxide semiconductor layer forming step)

(Heat treatment step) is performed on the oxide semiconductor layer at 300 DEG C or higher in a wet atmosphere having an absolute humidity of 4.8 g / m &lt; 3 &gt; or more.

In general, in the case of a stacked-layer thin film transistor in which the active layers are stacked, the influx of carriers from the region having a small electron affinity to the region having a large electron affinity occurs due to the magnitude of the electron affinity of each region. When carrier injection into the first region relatively close to the gate electrode occurs, a parasitic conduction path may be formed in addition to the main channel path occurring at the interface between the first region and the gate insulating film. The presence of such a parasitic conduction results in a hump effect in the Vg-Id characteristic, which deteriorates the On / Off ratio. Further, if the carriers in the parasitic conduction path are increased by light irradiation, or carriers optically excited in other layers are trapped at the trap level near the parasitic conduction path, an increase in the off current, a shift in the rising voltage of the current in the transistor Resulting in optical instability.

In addition, in the stacked-layer thin film transistor, since the first region and the second region are semiconductor layers having different compositions, it is easy to imagine that a plurality of defect levels exist at the interface between the first region and the second region. In particular, in the case of an oxide semiconductor, there is a defect level caused by an oxygen defect, and such a defect level is an in-gap level formed in the band gap. Such a level in the gap causes optical instability even though light irradiation with energy smaller than the band gap causes the generation of the photocurrent and the shift of the threshold value accompanied therewith.

The present inventors have found that when the IGZO layer is formed as an oxide semiconductor layer, a hump effect is obtained when a first region and a second region having a specific composition range (f / (e + f)? 0.875) However, by performing annealing in a specific wetting atmosphere, an effect of effectively suppressing the hump effect can be obtained, and it has been found that the threshold shift amount? Vth with respect to light irradiation at 420 nm is less than 1 V.

The method for manufacturing a thin film transistor of the present invention reduces the defects in the first region and the second region inside the active layer by annealing under a specific wetting atmosphere to thereby provide high light stability while maintaining high mobility of the stacked thin film transistor It is possible. This is believed to be due to the fact that moisture contained in the wet atmosphere is introduced into the active layer in the form of OH or H to reduce the dangling bonds at the interfaces present in the active layer and reduce the parasitic conduction paths.

Thin film transistor

First, a thin film transistor (appropriately referred to as &quot; TFT &quot;) manufactured by the present invention will be described with reference to the drawings. Although the TFTs shown in Figs. 1 and 2 will be specifically described as a representative example, the present invention can also be applied to the manufacture of TFTs of other types (structures).

The element structure of the TFT of the present invention may be any of a so-called bottom gate type structure (also referred to as a reverse stagger structure) and a top gate type structure (also referred to as a stagger structure) based on the position of the gate electrode. The top gate structure is a structure in which a gate electrode is disposed on an upper side of a gate insulating film and an active layer is formed on a lower side of a gate insulating film when a substrate on which TFTs are formed is the lowest layer. The bottom gate type structure is a structure in which the gate electrode is disposed below the gate insulating film and the active layer is formed above the gate insulating film when the substrate on which the TFT is formed is the lowest layer.

The element structure of the TFT of the present invention is based on the contact portion of the oxide semiconductor layer and the source electrode and the drain electrode (appropriately referred to as &quot; source / drain electrode &quot;), It may be. In the bottom contact type structure, source / drain electrodes are formed before the active layer, and the lower surface of the active layer is in contact with the source / drain electrodes. In the top contact type structure, the active layer is formed earlier than the source / drain electrodes, and the upper surface of the active layer is in contact with the source / drain electrodes.

Further, the TFT related to the present invention may have various configurations other than the above, and may be configured to include a protective layer and an insulating layer on the active layer appropriately.

Fig. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor 1 according to a first embodiment of the present invention, and Fig. 2 is a configuration of a thin film transistor 2 according to a second embodiment of the present invention. In each of the thin film transistors 1 and 2 shown in Figs. 1 and 2, common elements are denoted by the same reference numerals.

The thin film transistor 1 of the first embodiment shown in Fig. 1 is a bottom gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in Fig. 2 is a top gate-bottom contact type transistor to be. The embodiment shown in Figs. 1 and 2 differs in the arrangement of the gate electrode 16, the source electrode 13 and the drain electrode 14 with respect to the oxide semiconductor layer 12, And the same material can be applied.

The thin film transistors 1 and 2 according to the embodiment of the present invention are provided with a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12, a source electrode 13, and a drain electrode 14, And the oxide semiconductor layer 12 has a first region A1 and a second region A2 from the side closer to the gate electrode 16 in the film thickness direction. The first region A1 and the second region A2 constituting the oxide semiconductor layer 12 are continuously formed and the insulating layer and the electrode layer are formed between the first region A1 and the second region A2 The layer other than the oxide semiconductor layer is not interposed but is composed of an oxide semiconductor film.

Hereinafter, each component will be described in detail, including the substrate on which the TFTs 1 and 2 of the present invention are formed.

(Board)

The substrate 11 for forming the thin film transistor according to the present invention is not particularly limited in shape, structure and size as long as it has heat resistance of 300 占 폚 or higher, and can be appropriately selected depending on the purpose. The substrate 11 may have a single-layer structure or a stacked-layer structure.

For example, an inorganic material such as glass or YSZ (yttrium stabilized zirconium), or a substrate made of resin or resin composite material having high heat resistance such as polyimide can be used.

In addition, a silicon substrate, a stainless steel substrate, a metal multilayer substrate formed by laminating stainless and dissimilar metals, an aluminum substrate or an aluminum substrate having an oxide film improved in surface insulating property by performing oxidation treatment (for example, anodizing treatment) Can be used.

The oxide semiconductor layer

The oxide semiconductor layer 12 is formed so as to cover the first region A1 (appropriately referred to as "A1 layer") and the second region A2 (appropriately referred to as "A2 layer" And is disposed to face the gate electrode 16 with the gate insulating film 15 interposed therebetween. The first region A1 is an IGZO layer having a composition represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0). On the other hand, the second region A2, which is located on the side farther from the first region A1 with respect to the gate electrode 16, that is, on the side opposite to the side in contact with the gate insulating film 15 of the first region A1, F / (e + f)? 0.875, where In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0) Is an IGZO layer having a composition different from that of (A1).

The first region

The first region A1 preferably satisfies b? 91a / 74-17 / 40 (where a + b + c = 1), c? 3/5, b? 0, b? 3a / 7-3 / 14, b? 9a / 5? 53/50, b? -8a / 5 + 33/25 and b? 91a / 74-17 / 40 (a + b + c = 1). In such a composition region, the conduction channel is formed in the first region A1 because the first region A1 has a larger electron affinity than the second region A2. Since the carrier mobility is also high in the composition region, a high mobility of more than 20 cm 2 / Vs is realized.

Further, since the film of the first region A1 having the above composition has a high carrier concentration, it is difficult to obtain sufficiently low off current and switching characteristics when the film of the first region A1 alone is used as the active layer.

B? 17a / 23-28/115, b? 3a / 37, b? 9a / 5-53 / 50 and b? 1/5 (where a + b + c = 1) in the first region A1 . When the composition of the first region (A1) is within the composition range, field effect mobility exceeding 30 cm2 / Vs can be realized.

The thickness of the first region A1 is preferably less than 10 nm. The first region A1 is preferably a very In-rich IGZO film which is easy to realize high mobility. However, since such a high mobility film has a high carrier concentration, there is a possibility that the threshold value is shifted to the minus side. If the thickness of the first region A1 is 10 nm or more, the total carrier concentration in the active layer becomes excessive, and pinch-off becomes relatively difficult.

On the other hand, the thickness of the first region A1 is preferably 5 nm or more from the viewpoint of obtaining uniformity of the oxide semiconductor layer 12 and high mobility.

The second region

The second region A2 of the oxide semiconductor layer 12 is formed on the side farther from the first region A1 with respect to the gate electrode 16, that is, the side contacting the gate insulating film 15 in the first region A1 Is located on the opposite side. The second region A2 is represented by In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0) 0.875, and is an IGZO layer having a composition different from that of the first region (A1).

The composition of the second region A2 is preferably f / (e + f) &gt; 0.25. When f / (e + f)? 0.25 in the second region A2, the carrier concentration in the second region A2 is high and the effect of carrier transfer to the first region A1 becomes significant, The carrier concentration in the region A1 excessively increases, and there is a fear that the increase of the off current and the threshold value take a negative value.

The thickness of the second region A2 is preferably 30 nm or more. When the thickness of the second region A2 is 30 nm or more, it is possible to more reliably reduce the off current. On the other hand, if the thickness of the second region A2 is 10 nm or less, the off current may increase and the S value may deteriorate. It is preferable that the thickness of the second region A2 is less than 70 nm. If the thickness of the second region is 70 nm or more, the reduction of the off current can be expected, but the resistance between the source / drain electrode layer and the first region A1 is increased, resulting in a decrease in mobility . Therefore, the thickness of the second region A2 is preferably larger than 10 nm and smaller than 70 nm.

The entire oxide semiconductor layer

The total thickness (total film thickness) of the oxide semiconductor layer 12 is preferably about 10 to 200 nm, more preferably 35 to less than 80 nm from the viewpoints of film uniformity and patterning properties.

It is preferable that the oxide semiconductor layer 12 (first region A1, second region A2) is amorphous. If the first and second regions A1 and A2 are amorphous films, no grain boundaries exist and a film with high uniformity can be obtained.

Whether or not the laminated film composed of the first and second regions A1 and A2 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, it can be judged that the laminated film is amorphous.

The control of the carrier concentration of the oxide semiconductor layer 12 can be performed not only by modulating the composition of the regions A1 and A2 but also by controlling the oxygen partial pressure at the time of film formation.

Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressures at the time of film formation in the first and second regions A1 and A2, respectively. By increasing the oxygen partial pressure at the time of film formation, the carrier concentration can be reduced, and the off current can be expected to be reduced accordingly. On the other hand, if the oxygen partial pressure at the time of film formation is lowered, the carrier concentration can be increased, and accordingly, the field effect mobility can be expected to increase. It is also possible to promote the oxidation of the film to reduce the amount of oxygen deficiency in the first region A1, for example, by performing a treatment for irradiating oxygen radicals or ozone after film formation in the first region A1.

In addition, by doping a part of Zn of the oxide semiconductor layer 12 made of the first and second regions A1 and A2 with element ions having a wider bandgap, the light irradiation stability accompanying the increase of the optical band gap can be improved . Specifically, it is possible to increase the bandgap of the film by doping Mg. For example, by doping Mg to each region of the A1 layer and the A2 layer, it is possible to increase the band gap while maintaining the band profile of the laminated film, as compared with a system in which the composition ratio of only In, Ga, and Zn is controlled.

Since the blue light emitting layer used for the organic EL shows broad light emission having a peak at about? = 450 nm, if the optical band gap of the IGZO film is relatively narrow and optical absorption is present in the region, I wake up. Therefore, it is particularly preferable that the band gap of the material used for the channel layer is larger in the thin film transistor used for driving the organic EL.

The carrier density of the first and second angular regions A1 and A2 can be arbitrarily controlled by cation doping. In order to increase the carrier density, a material (for example, Ti, Zr, Hf, Ta, or the like) that is liable to become a relatively large valence cation may be doped. However, in the case of doping a large cation with cations, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplification of the film formation process and cost reduction. Therefore, the carrier density is controlled according to the oxygen concentration .

Source / drain electrodes

The material and the structure of the source electrode 13 and the drain electrode 14 are not particularly limited as long as they have high conductivity. A metal oxide such as Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide indium (IZO) or the like such as Al, Mo, Cr, Ta, Ti, The source / drain electrodes 13 and 14 can be formed by using a single layer or a laminated structure of two or more layers.

In the case where the source electrode 13 and the drain electrode 14 are formed of the metal or metal oxide, the thickness of each of the source electrode 13 and the drain electrode 14 is 10 nm or less in consideration of the film forming property, the patterning property by the etching or lift- Or more and 1000 nm or less, and more preferably 50 nm or more and 100 nm or less.

Gate insulating film

The gate insulating film 15 is preferably a layer that separates the gate electrode 16 and the oxide semiconductor 12 and the source and drain electrodes 13 and 14 in a state insulated from each other and has a high insulating property. For example, _{SiO 2, SiNx, SiON, Al} 2 O 3, Y 2 O 3, Ta 2 O 5, HfO 2 , such as an insulating film of, or constituting the gate insulating film 15 of an insulating film such as containing two or more of these compounds can do.

In addition, the gate insulating film 15 needs to have a sufficient thickness to reduce the leak current and improve the voltage resistance, while if the thickness is too large, the driving voltage is increased. The thickness of the gate insulating film 15 may vary depending on the material, but is preferably 10 nm to 10 mu m, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

Gate electrode

The gate electrode 16 is not particularly limited as long as it has high conductivity. A metal oxide such as Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide indium (IZO) or the like such as Al, Mo, Cr, Ta, Ti, Of a conductive film or the like may be formed as a single layer or a laminated structure of two or more layers to form a gate electrode.

When the gate electrode 16 is formed of the metal or the metal oxide, it is preferable that the thickness is 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by the etching or the lift-off method, , And more preferably 50 nm or more and 200 nm or less.

Manufacturing method of thin film transistor

Next, a method of manufacturing the bottom gate-top contact type thin film transistor 1 shown in Fig. 1 will be described. The constituent material, thickness, etc. of each part are as described above, and the description thereof is omitted in the following description to avoid duplicate description.

Formation of gate electrode

First, a substrate 11 is prepared, and if necessary, a layer other than the thin film transistor 1 is formed on the substrate 11, and then the gate electrode 16 is formed.

The gate electrode 16 can be formed by a known method such as a physical method such as a wet method such as a printing method or a coating method, a vacuum evaporation method, a sputtering method and an ion plating method, a chemical method such as a CVD method or a plasma CVD method, The film may be formed according to a method appropriately selected in consideration of suitability of the film. For example, the electrode film is formed and patterned into a predetermined shape by etching or lift-off method to form the gate electrode 16. At this time, it is preferable to simultaneously pattern the gate electrode 16 and the gate wiring.

Formation of gate insulating film

After the gate electrode 16 is formed, a gate insulating film 15 is formed.

The gate insulating film 15 may be formed by a chemical method such as a physical method such as a wet method such as a printing method or a coating method, a vacuum evaporation method, a sputtering method, and an ion plating method, or a chemical method such as a CVD method or a plasma CVD method, The film may be formed according to a method selected appropriately. For example, the gate insulating film 15 may be patterned into a predetermined shape by photolithography and etching.

Formation of oxide semiconductor layer

Subsequently, the first region A1 and the second region A2 are formed in this order as the oxide semiconductor layer 12 at a position facing the gate electrode 16 on the gate insulating film 15. Next,

The tent of the first area

The first region of the oxide semiconductor layer 12 is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0) B? 9a / 5? 53/50, b? -8a / 5 + 33/25, and b? 91a / B? 17a / 23-28/115, b? 3a / 37, b? 9a / 5-53 / 50, and more preferably, b &lt; / = 1/5.

The method of forming the first and second regions A1 and A2 constituting the oxide semiconductor layer 12 is not particularly limited, but it is preferable to form the film by the sputtering method. Since the sputtering method can form a film having a high deposition rate and a high uniformity, it is possible to form a large-area oxide semiconductor film at a low cost. When forming the first region by sputtering, a composite oxide target that has been adjusted in advance so as to have a desired cation composition may be used, or a ternary sputter of In ₂ O ₃ , Ga ₂ O ₃ , or ZnO may be used do.

The substrate temperature during film formation may be arbitrarily selected depending on the substrate. However, in the case of using a resin-made flexible substrate, it is preferable that the substrate temperature is closer to room temperature in order to prevent deformation of the substrate.

The tent of the second zone

The subsequent to film formation, In _(e) of the first area _{(A1) Ga (f) Zn} (g) O (h) (e> 0, f> 0, g> 0, h> 0) represents a, f / ( (e + f)? 0.875, preferably satisfying f / (e + f) &gt; 0.25.

The film formation in the second region A2 may be a method in which film formation is temporarily stopped after the film formation in the first region A1 and the oxygen partial pressure in the film formation chamber and the electric power applied to the target are changed, The oxygen partial pressure in the deposition chamber and the power applied to the target may be changed quickly or gently without stopping the deposition.

Alternatively, the target may be a method of using the target used at the time of film formation of the first region A1 as it is and changing the applied power. In switching the film from the first region A1 to the second region A2 , The application of electric power to the target used for film formation of the first region A1 is stopped and electric power is applied to a different target containing In, Ga, and Zn. Alternatively, the first region A1 may be used for film formation of the first region A1 In addition to the target, it is also possible to apply a power application to a plurality of targets.

The substrate temperature at the time of forming the second region A2 may be arbitrarily selected depending on the substrate. However, in the case of using the resin-made flexible substrate, the substrate temperature is lowered to room temperature Close to each other.

When the regions A1 and A2 are formed by the sputtering method, the oxide semiconductor layer 12 is preferably formed continuously without being exposed to the atmosphere. By forming the oxide semiconductor layer 12 without exposing it to the atmosphere, it is possible to prevent the impurities from being mixed between the regions A1 and A2, and as a result, more excellent transistor characteristics can be obtained. In addition, since the number of film forming steps can be reduced, the manufacturing cost can be reduced.

In the present embodiment, at the time of manufacturing the bottom gate type thin film transistor 1, the oxide semiconductor layer 12 is formed in the order of the first region A1 and the second region A2, In manufacturing the top gate type thin film transistor 2 shown in Fig. 2, the second region A2 and the first region A1 may be formed in this order.

Heat treatment process

After the first region A1 and the second region A2 are formed as the oxide semiconductor layer 12, heat treatment at 300 deg. C or higher in a wet atmosphere of an absolute humidity of 4.8 g / m3 or more (dew point temperature of 0.8 deg. Post annealing) is performed.

By performing the heat treatment in the wet atmosphere as described above, the hump effect can be suppressed as compared with the case where annealing is performed in a dry atmosphere of less than 4.8 g / m &lt; 3 &gt;, and consequently, Can be suppressed. From the viewpoint of enhancing the light stability, it is preferable that the wetting atmosphere of the heat treatment process is performed at an absolute humidity of 9.5 g / m 3 or more (dew point temperature of 10.7 ° C or more).

The heat treatment temperature is preferably 400 占 폚 or higher, and more preferably 450 占 폚 or higher. If the heat treatment temperature is 400 占 폚 or higher, the light irradiation stability can be made very high (for example, |? Vth |? 0.1 V for light irradiation at 420 nm).

The heat treatment time is preferably 5 minutes or more and 120 minutes or less from the viewpoint of reliably increasing the light irradiation stability.

On the other hand, in the case of treatment at a temperature of 600 占 폚 or more in the heat treatment step, mutual diffusion of cation occurs between the first region A1 and the second region A2, and the two regions are mixed with each other. In this case, it becomes difficult to concentrate the conducting carrier only in the first region. Therefore, it is preferable that the heat treatment temperature in the heat treatment process is less than 600 ° C. Whether or not the mutual diffusion of cation in the first region and the second region is occurring can be confirmed by, for example, performing analysis by a cross-sectional TEM.

Fig. 3 is a sectional STEM (scanning transmission electron microscope) image of a laminated film in which a total of five layers of an IGZO film of Ga / (In + Ga) = 0.75 and an IGZO film of Ga / (In + Ga) (Before the annealing) and FIG. 3 (right: FIG. 3 (B)) shows that the annealing temperature was 600 ° C. It can be seen from Figs. 3 (A) and 3 (B) that the laminated structure of the IGZO film maintains the laminated structure to some extent even after annealing at 600 ° C., but the contrast at the interface of the different cation composition You can see what you are like. This suggests that mutual diffusion of different phases is beginning to occur, and the upper limit temperature in the heat treatment step is preferably 600 ° C or less.

After the heat treatment, the oxide semiconductor layer 12 is patterned. The patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed by photolithography at the remaining portion, and a pattern of the oxide semiconductor layer 12 is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixture of phosphoric acid, nitric acid and acetic acid do.

After the patterning of the oxide semiconductor layer 12, the heat treatment may be performed at a temperature of 300 占 폚 or higher in the above-described heat treatment step, that is, in a wet atmosphere having an absolute humidity of 4.8 g / m3 or more.

Formation of source / drain electrodes

Next, a metal film for forming the source / drain electrodes 13 and 14 is formed on the oxide semiconductor layer 12.

The source electrode 13 and the drain electrode 14 are all formed by a physical method such as a wet method such as a printing method or a coating method, a vacuum deposition method, a sputtering method or an ion plating method, a chemical method such as CVD or plasma CVD Or the like may be appropriately selected in consideration of the suitability of the material to be used.

For example, the metal film is patterned into a predetermined shape by an etching or a lift-off method to form the source electrode 13 and the drain electrode 14. At this time, it is preferable to simultaneously pattern the source / drain electrodes 13 and 14 and the wirings (not shown) connected to the electrodes 13 and 14 at the same time.

Through the above procedure, the thin film transistor 1 shown in Fig. 1 can be manufactured.

By using the manufacturing method of the thin film transistor of the present invention, high mobility and high light irradiation stability can be obtained without using a protective layer or the like for reducing characteristic deterioration upon light irradiation on the active layer. Of course, The same protective layer may be formed. For example, by forming a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less), it is possible to further improve stability against light irradiation.

The thin film transistor manufactured by the present invention has high light irradiation stability while suppressing the hump effect, and can be applied to various devices. Both the display device and the sensor using the thin film transistor manufactured by the present invention exhibit good characteristics due to low power consumption. Here, the &quot; characteristic &quot; is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

Liquid crystal display

Fig. 8 shows a schematic sectional view of a part of a liquid crystal display device according to an embodiment of a display device having a thin film transistor manufactured by the present invention, and Fig. 9 shows a schematic configuration diagram of the electric wiring.

8, the liquid crystal display device 5 according to the present embodiment includes a top gate-bottom contact type thin film transistor 2 shown in Fig. 2 and a passivation layer 54 of the thin film transistor 2 A liquid crystal layer 57 sandwiched between the pixel lower electrode 55 and the opposing upper electrode 56 on the gate electrode 16 formed on the gate electrode 16 and an RGB color filter 58 for coloring different colors And the polarizing plates 59a and 59b are provided on the substrate 11 side of the TFT 2 and on the color filter 58, respectively.

9, the liquid crystal display device 5 of the present embodiment includes a plurality of gate wirings 51 that are parallel to each other and a plurality of data wirings 52 . Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 2 is provided in the vicinity of the intersection of the gate wiring 51 and the data wiring 52.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 51 and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 52. [ The drain electrode 14 of the thin film transistor 2 is electrically connected to the pixel lower electrode 55 through a contact hole 19 formed in the gate insulating film 15 (a conductor is buried in the contact hole 19) . The pixel lower electrode 55 constitutes a capacitor 53 together with the grounded counter electrode 56.

Although the liquid crystal device of this embodiment shown in Fig. 8 is provided with the top gate type thin film transistor, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type, Gate type thin film transistor.

Since the thin film transistor manufactured by the present invention has high mobility, high-quality display such as high-precision, high-speed response, and high contrast can be performed in a liquid crystal display device, and is also suitable for large-screen display. In particular, when the active layer (oxide semiconductor layer) 12 is amorphous, variation in device characteristics can be suppressed, and excellent display quality without unevenness on a large surface can be realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and further, the power consumption of the display device can be reduced.

According to the present invention, the first region A1 and the second region A2 constituting the active layer can be formed using an amorphous film which can be formed at a low temperature (for example, 200 DEG C or lower) As the substrate, a resin substrate (plastic substrate) can be used. Therefore, according to the present invention, a flexible liquid crystal display device having excellent display quality can be provided.

Organic EL display device

Fig. 10 is a schematic cross-sectional view of an active matrix type organic EL display device as one embodiment of a display device having TFTs manufactured by the present invention, and Fig. 11 is a schematic configuration diagram of electric wiring .

There are two types of driving methods of the organic EL display device, that is, a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at a low cost, but since the scanning lines are selected one by one to emit light to the pixels, the number of scanning lines and the light emission time per scanning line are inversely proportional to each other. As a result, it is difficult to obtain a high definition and a large screen. In the active matrix method, since transistors and capacitors are formed for each pixel, the manufacturing cost is increased. However, since there is no problem that the number of scanning lines can not be increased like a simple matrix method, it is suitable for high definition and large screen.

In the active matrix type organic EL display device 6 of the present embodiment, a top gate-top contact type thin film transistor is formed on a substrate 60 provided with a passivation layer 61a, And a switching TFT 2b. An organic light emitting element 65 composed of an organic light emitting layer 64 sandwiched by the lower electrode 62 and the upper electrode 63 is provided on the thin film transistors 2a and 2b and the upper surface of the organic light emitting element 65 is covered with the passivation layer 61b Respectively.

11, the organic EL display device 6 of the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a plurality of data wirings 66 that cross the gate wirings 66 67 and a drive wiring 68. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16b of the switching thin film transistor 2b is connected to the gate wiring 66 and the source electrode 13b of the switching thin film transistor 2b is connected to the data wiring 67. [ The drain electrode 14b of the switching thin film transistor 2b is connected to the gate electrode 16a of the driving thin film transistor 2a and the capacitor 69 is used to turn on the driving thin film transistor 2a State. The source electrode 13a of the driving thin film transistor 2a is connected to the driving wiring 68 and the drain electrode 14a is connected to the organic EL light emitting element 65. [

Although the organic EL device of this embodiment shown in Fig. 10 is also provided with the top gate type thin film transistors 2a and 2b, the thin film transistor used in the organic EL device which is the display device of the present invention, Type, but may be a bottom gate type thin film transistor.

Since the thin film transistor manufactured by the present invention has high mobility, high-quality display with low power consumption becomes possible. According to the present invention, the first region A1 and the second region A2 constituting the active layer can be formed using an amorphous film which can be formed at a low temperature (for example, 200 DEG C or lower) A resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible organic EL display device having excellent display quality.

In the organic EL display device shown in Fig. 10, the upper electrode 63 may be formed as a transparent electrode in the top emission type, and each electrode of the lower electrode 62 and the TFTs 2a and 2b may be a transparent electrode Bottom emissive type.

X-ray sensor

Fig. 12 shows a schematic sectional view of a part of the X-ray sensor which is one embodiment of the sensor of the present invention, and Fig. 13 shows a schematic configuration diagram of the electric wiring.

The X-ray sensor 7 of the present embodiment includes a thin film transistor 2 and a capacitor 70 formed on a substrate 11, a charge collecting electrode 71 formed on the capacitor 70, (72), and an upper electrode (73). On the thin film transistor 2, a passivation film 75 is formed.

The capacitor 70 has a structure in which the insulating film 78 is sandwiched between the capacitor lower electrode 76 and the capacitor upper electrode 77. The capacitor upper electrode 77 is connected to either one of the source electrode 13 and the drain electrode 14 of the thin film transistor 2 through the contact hole 79 formed in the insulating film 78 14).

The charge collecting electrode 71 is formed on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is formed so as to cover the thin film transistor 2 and the capacitor 70. The upper electrode 73 is formed on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

13, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that are parallel to each other and cross the gate wirings 81. [ . Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 2 is provided near the intersection of the gate wiring 81 and the data wiring 82.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 81 and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 82. [ The drain electrode 14 of the thin film transistor 2 is connected to the charge collecting electrode 71 and the charge collecting electrode 71 is connected to the grounded opposing electrode 76 together with the capacitor 70 Respectively.

In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper portion (on the side of the upper electrode 73) in FIG. 11 to generate electron-hole pairs in the X- By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated electric charge is accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 2.

Since the X-ray sensor of the present invention is provided with the thin film transistor 2 having high on-current and excellent reliability, it has high S / N ratio and excellent sensitivity characteristics. Therefore, when used in an X- An image of the range is obtained.

Particularly, the X-ray digital photographing apparatus of the present invention is suitable for use in an X-ray digital photographing apparatus which can perform not only a still image photographing but also a photographing of a moving image and a photographing of a still image in one operation. Further, when the first region A1 and the second region A2 constituting the active layer in the thin film transistor 2 are amorphous, an image excellent in uniformity is obtained.

Although the X-ray sensor of this embodiment shown in Fig. 12 is provided with a top gate type thin film transistor, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, Type thin film transistor.

Example

Hereinafter, experimental examples will be described, but the present invention is not limited at all by these examples.

The inventors of the present invention have found that it is possible to achieve a high light irradiation stability (|? Vth |? 1 V (with respect to light irradiation at 420 nm)) while laminating an oxide semiconductor of a specific composition and suppressing the hump effect by a specific heat treatment Was verified by the following experiment.

Dependence of moisture content in annealing atmosphere of TFT characteristics

It has been verified that high mobility and high optical stability can be obtained by laminating an oxide semiconductor film having a specific composition as an active layer of a thin film transistor and performing an annealing treatment in a wet atmosphere.

First, the following bottom gate-top contact type thin film transistors were manufactured as Examples 1 to 8 and Comparative Examples 1 to 5.

As the substrate, a highly doped p-type silicon substrate (manufactured by Mitsubishi Materials Corporation) was used, in which an oxide film of SiO ₂ (thickness: 100 nm) was formed on the surface.

Then, an oxide semiconductor layer was formed on the p-type silicon substrate.

A first area (A1) constituting the oxide semiconductor _{layer, In (a) Ga (b} ) Zn (c) O (d) (a = 37/60, b = 3/60, c = 20/60, d > 0) was sputter deposited to a thickness of 5 nm.

_(E) Ga _(f) Zn _(g) O _(h) (f / (e + f) = 0.75, e> 0, f> 0, g> 0, h &gt; 0) was formed by sputtering to a thickness of 50 nm.

The oxide semiconductor layer was continuously formed between the regions without exposure to the atmosphere. Sputtering of each region was performed using a ternary sputter using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target in the regions A1 and A2. The film thickness of each region was adjusted by adjusting the film formation time.

The film forming conditions in the first region A1 and the second region are as follows, and the sputtering conditions other than the composition of each region are common in experiments to be described later.

The sputtering conditions of the first region A1

Reached vacuum degree: 6 × 10 ^-6 Pa

Film forming pressure: 4.4 x 10 &lt; ^-1 &gt; Pa

Film forming temperature: room temperature

Oxygen partial pressure / argon partial pressure: 0.067

The sputtering conditions of the second region A2

Reached vacuum degree: 6 × 10 ^-6 Pa

Film forming pressure: 4.4 x 10 &lt; ^-1 &gt; Pa

Film forming temperature: room temperature

Oxygen partial pressure / argon partial pressure: 0.033

After stacking the oxide semiconductor layers by sputtering, an electrode layer made of Ti (10 nm) / Au (40 nm) was formed on the laminated film (oxide semiconductor layer) by a vacuum evaporation method via a metal mask.

After the formation of the electrode layer, the annealing temperature was 400 占 폚 (except for Comparative Example 5), and the oxygen partial pressure was fixed (20%). The annealing time was 1 hour. A shrunken type humidity generator (SRG-1M-10L (trade name) manufactured by Shin Ai Technology Co., Ltd.) was used to generate a humid atmosphere. In Comparative Example 5, the annealing temperature was 200 占 폚.

Thus, a bottom gate type thin film transistor in each of Examples 1 to 8 and Comparative Examples 1 to 5 having a channel length of 180 占 퐉 and a channel width of 1 mm was obtained.

Mobility

The transistor characteristics (Vg-Id characteristics) and the mobility μ were measured using the semiconductor parameter analyzer 4156C (trade name, manufactured by Agilent Technologies) for the TFTs of the above-described Examples 1 to 8 and Comparative Examples 1 to 5 Respectively.

The Vg-Id characteristics were measured by fixing the drain voltage Vd to 10 V and sweeping the gate voltage Vg within the range of -30 V to +30 V to determine the drain current (Id). The off current was defined as the current value at Vg = 0 V in the Vg-Id characteristic.

The mobility was calculated from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) within the range of -30 V to +30 V with the drain voltage (Vd) fixed at 1 V, Respectively.

Light irradiation stability

The prepared TFT was evaluated for stability of TFT characteristics for light irradiation by evaluating Vg-Id characteristics and then irradiating monochromatic light with variable wavelength. The outline of the measurement of the TFT characteristics under monochrome light irradiation is shown in Fig. As shown in Fig. 4, each TFT was placed on the probe stage 200 and the drying atmosphere was allowed to flow for 2 hours or more, and then the TFT characteristics were measured in the drying atmosphere. By comparing the Vg-Id characteristic at the time of monochrome light irradiation and the Vg-Id characteristic at the time of monochrome light irradiation by setting the irradiation intensity of the monochrome light source to 10 μW / cm 2 and the wavelength λ to 360 to 700 nm, (? Vth) was evaluated. The measurement conditions of the TFT characteristics under monochrome light irradiation were determined by sweeping the gate voltage in the range of Vg = -15 to 15 V with Vds fixed at 10 V. In addition, all measurements are carried out after monochrome light is irradiated for 10 minutes, unless otherwise specified below. The shift amount? Vth of the threshold value for the 420 nm light irradiation was regarded as an index of the optical stability of the TFT. In addition, the evaluation method is common in the subsequent experiments.

Table 2 shows the absolute humidity (dew point temperature) at annealing, the composition of the A2 layer, and the TFT characteristics.

Vg-Id characteristics of the TFTs of Examples 1 to 4 and Comparative Examples 1 to 4 are shown in Fig.

The I-V characteristic at the time of monochrome light irradiation in the TFT of Example 1 is shown in Fig. 6, and the threshold shift amount? Vth with respect to the irradiation wavelength is shown in Fig.

In Examples 1 to 8, when the composition of the A2 layer is f / (e + f)? 0.875 and the annealing process has an absolute humidity of 4.8 g / m 3 or more (dew point temperature: 0.8 ° C or more) It can be seen that both can be compatible.

On the other hand, in the case of Comparative Example 1, the composition of the A2 layer is f / (e + f)? 0.875, but the annealing process has an absolute humidity of less than 4.8 g / (Bumps appear in the IV characteristic), and the current value of the hump region increases at the time of light irradiation, and detailed evaluation can not be made.

In Comparative Examples 2 and 3, the annealing conditions were the same as those in Examples 4, 7 and 8, but the composition of the A2 layer did not satisfy f / (e + f)? 0.875 and a hump effect appeared in the Vg- It was not possible to evaluate the light stability. It is also seen that the threshold value is shifted by a large amount and the off current value (Id value at Vg = 0 V) is deteriorated as compared with the embodiment.

From the above results, it can be seen that high optical stability can be realized while the hump effect is suppressed by annealing (400 ° C) at an absolute humidity of 4.8 g / m 3 or more with the f / (e + f)? 0.875 of the A2 layer. In Comparative Example 5, the annealing temperature is 200 ° C. In this case, it is understood that satisfactory optical stability is not obtained although the composition is satisfied.

As shown in Table 2, in the cases of Embodiments 1 to 3 (corresponding to relative humidity of 88%, 70% and 55%, respectively) and 420 nm (light irradiation energy hν = 2.95 eV) , The light stability was improved in comparison with the other embodiments in the case of 400 nm (light irradiation energy hν = 3.10 eV). From this, it can be seen that when the humidity is raised, the deep-gap level can be more effectively reduced in the oxide semiconductor.

Al layer composition dependence of TFT characteristics

Table 3 shows the TFT characteristics when the second region A2 is fixed to the IGZO layer (f / (e + f) = 0.75) and the first region A1 is subjected to composition modulation and annealing. The thickness of the first region A1 was 5 nm and the thickness of the second region was 50 nm.

The annealing condition is an absolute humidity of 15.3 g / m3, 400 DEG C, 1 hour.

As shown in Table 3, in Examples 9 to 20, although the composition of the A1 layer is different, the difference in light stability is small, and it is found that the composition dependence of the A1 layer on the TFT characteristics, particularly the light stability, is small.

With respect to the TFTs manufactured in Examples and Comparative Examples, the composition range of the first region (A1) is shown in FIG. 14 by a three-phase diagram technique.

Annealing temperature dependence of TFT characteristics under wet atmosphere

The composition of the Al layer was In: Ga: Zn = 37/60: 3/60:20/60, and the composition of the A2 layer was f / (e + f) = 0.75. The thickness of the first region A1 was 5 nm and the thickness of the second region was 50 nm.

The annealing conditions were such that the absolute humidity was 15.3 g / m &lt; 3 &gt; and only the annealing temperature was modulated. The mobility and the light stability of the TFT were evaluated. The evaluation results are shown in Table 4 below.

From Table 4, it is possible to suppress the? Vth at the light irradiation of 420 nm to less than -0.1 V, and realize a highly light-stable TFT device even when the annealing is performed under the same wet atmosphere.

The use of the thin film transistor manufactured according to the present invention described above is not particularly limited. For example, a display device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) Device or the like).

The thin film transistor manufactured by the present invention can be applied to a device such as a flexible display which can be manufactured by a low temperature process using a resin substrate, an image sensor such as a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor) (Drive circuit) in various electronic devices such as various types of sensors, MEMS (Micro Electro Mechanical System), and the like.

The display device and the sensor of the present invention using the thin film transistor manufactured by the present invention all exhibit good characteristics with low power consumption. Here, the &quot; characteristic &quot; is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

The disclosure of Japanese Patent Application No. 2012-110773 is hereby incorporated by reference in its entirety.

All publications, patent applications, and technical specifications described in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, and technical specification were specifically and individually disclaimed Accepted.

Claims (11)

_(A) Ga _(b) Zn _(c) O _(d) (a> 0 ₎ as the oxide semiconductor layer of the thin film transistor having the oxide semiconductor layer, the source electrode, the drain electrode, the gate insulating film, _(e) Ga _(f) Zn _(g) O ₍ 0), b> 0, c> 0, d> 0) ₍ e + f) &lt; / = 0.875 and represented by the following expression _(h) (e &gt; 0, f &gt; 0, g &gt; A semiconductor layer forming step,
And a heat treatment step of subjecting the oxide semiconductor layer to a heat treatment at 300 DEG C or higher in a wet atmosphere having an absolute humidity of 4.8 g / m &lt; 3 &gt; or more. The method according to claim 1,
Wherein the composition of the first region is in the range of b? 91a / 74-17 / 40 (where a + b + c = 1). 3. The method according to claim 1 or 2,
Wherein the heat treatment step is performed at an absolute humidity of 9.5 g / m 3 or more. The method according to claim 2 or 3,
The composition of the first region may be,
c? 3/5,
b> 0,
b? 3a / 7 - 3/14,
b? 9a / 5 - 53/50,
b? -8a / 5 + 33/25,
b &lt; / = 91a / 74-17 / 40 (note that a + b + c = 1). 5. The method of claim 4,
The composition of the first region may be,
b? 17a / 23 - 28/115,
b? 3a / 37,
b? 9a / 5 - 53/50,
b &lt; / = 5. &lt; / RTI &gt; 6. The method according to any one of claims 1 to 5,
And the composition of the second region satisfies f / (e + f) &gt; 0.25. 7. The method according to any one of claims 1 to 6,
Wherein the film thickness of the second region is larger than 10 nm and smaller than 70 nm. 8. The method according to any one of claims 1 to 7,
Wherein the film thickness of the first region is 5 nm or more and less than 10 nm. 9. The method according to any one of claims 1 to 8,
Wherein the oxide semiconductor layer is amorphous. 10. The method according to any one of claims 1 to 9,
Wherein the heat treatment temperature in the heat treatment step is 400 占 폚 or higher. 11. The method according to any one of claims 1 to 10,
Wherein the heat treatment temperature in the heat treatment step is 450 DEG C or higher.

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