WO2013161438A1 - Dispositif de traitement d'informations, procédé de traitement d'informations, et programme - Google Patents

Dispositif de traitement d'informations, procédé de traitement d'informations, et programme Download PDF

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Publication number
WO2013161438A1
WO2013161438A1 PCT/JP2013/057457 JP2013057457W WO2013161438A1 WO 2013161438 A1 WO2013161438 A1 WO 2013161438A1 JP 2013057457 W JP2013057457 W JP 2013057457W WO 2013161438 A1 WO2013161438 A1 WO 2013161438A1
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Prior art keywords
power
information processing
processing apparatus
power supply
state
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PCT/JP2013/057457
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English (en)
Japanese (ja)
Inventor
増田　健
清隆 赤坂
敏正 土田
今井　隆浩
義幸 田中
健一 大西
徳文 吉田
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ソニー株式会社
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Publication of WO2013161438A1 publication Critical patent/WO2013161438A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to an information processing apparatus, an information processing method, and a program.
  • Patent Document 1 describes a technique that enables a timer Wake when EC is turned off at S4 / S5.
  • Patent Document 2 describes a method for reducing the amount of read / write data in hibernation performed by BIOS.
  • Patent Document 1 has a problem that the accuracy of the start time by the timer is lowered because EC is used as an alternative to the RTC of the chipset.
  • EC is used as an alternative to the RTC of the chipset.
  • it is difficult to start at the correct time. For this reason, for example, when a TV program is scheduled to be recorded, it is assumed that recording cannot be started or stopped at a desired time.
  • a processor that controls a system of an information processing device, a chipset that manages data transfer of the processor, a power supply control unit that performs control of power supply to the system, and the chipset
  • an information processing apparatus including a BIOS that sets a start time in a clock, and a start unit that starts the power supply control unit a predetermined time before the start time.
  • the activation unit may be constituted by a timer included in the power supply control unit.
  • the activation unit may be constituted by a timer provided separately from the power control unit.
  • the activation unit may be constituted by a hardware switch.
  • the activation time is set to the clock of the chipset that manages the data transfer of the processor that controls the system of the information processing apparatus, and the system is connected to the system a predetermined time before the activation time.
  • a control method for the information processing apparatus is provided, including starting a power supply control unit that executes control of power supply.
  • a processor that controls a system of an information processing device, a chip set that manages data transfer of the processor, a power supply control unit that performs control of power supply to the system, and the processor And an activation unit that activates the power supply control unit according to the timing at which the power supply control unit controls the power supply in a state where the power of the chipset is turned off.
  • the activation unit may be constituted by a timer included in the power supply control unit.
  • the activation unit may be constituted by a timer provided separately from the power control unit.
  • the activation unit may be constituted by a hardware switch.
  • the power control unit may control power supply of a memory that stores information in a state where the power of the processor and the chipset is turned off.
  • 17 is a schematic diagram illustrating an example in which a hardware (HW) switch 150 is provided instead of the dedicated circuit in FIG. 16.
  • 15 is a schematic diagram showing an example in which another device (Any Devices) 160 is provided instead of the memory 109 in FIG.
  • It is a schematic diagram which shows the structure applied to applications other than power supply control. It is a schematic diagram which shows the mounting specification of each state in 3rd Embodiment. It is a schematic diagram which shows the discharge characteristic at the time of S3 and S0. It is a characteristic view which shows the threshold value of LBH. It is a characteristic view which shows timer hibernation. It is a flowchart which shows the process of LBH. It is a flowchart which shows a process of Timer
  • FIG. 11 is a characteristic diagram illustrating load-capacity characteristics of an information processing apparatus having a low capacity and a high performance. It is a flowchart which shows the process of a hybrid sleep function. It is a flowchart which shows a process of a battery sleep disable. It is a block diagram which shows the process of 3rd Embodiment. It is a block diagram which shows the process of 3rd Embodiment. It is a block diagram which shows the process of 3rd Embodiment. It is a block diagram which shows the process of 3rd Embodiment. It is a block diagram which shows the process of 3rd Embodiment. It is a block diagram which shows the process of 3rd Embodiment.
  • the mobile device is set in a standby state when the user does not use it, and is configured to immediately return from the standby state when the user wants to use the device.
  • FIG. 1 is a schematic diagram showing a configuration of a general PC 100.
  • a PC 200 includes a processor (CPU (Central Processing Unit)) 202, a chip set 204, an EC (Embedded Controller) 206, a memory (DRAM) 209, an LCD (Liquid Crystal Display), a liquid crystal display device, 1, a storage device 220 such as an HDD (Hard Disk Drive), and a battery 222.
  • CPU Central Processing Unit
  • EC embedded Controller
  • DRAM Memory
  • LCD Liquid Crystal Display
  • HDD Hard Disk Drive
  • the chip set 204 is a chip that manages the exchange of data between the CPU 202 and various devices such as the storage device 220 and the LCD within the information processing apparatus 200.
  • the chipset 204 includes a north bridge 208 and a south bridge 210.
  • the north bridge 208 includes a memory controller 212 that controls the memory 209.
  • the south bridge 210 includes an RTC (Real Time Clock) 214 that is a chip dedicated to timekeeping. Unlike the chips on other motherboards, the RTC 214 operates by receiving power from the built-in battery while the power is turned off (received from an external power source while the power is on).
  • the OS (operating system) obtains the date and time from the RTC 214 at the time of startup, and thereafter, the OS measures the time independently.
  • the EC 206 executes power supply control of the PC 200, and is configured by, for example, an LSI (Large Scale Integration Circuit).
  • Suspend is also referred to as S3 (state) in the ACPI (Advanced Configuration and Power Interface) standard. Suspend is also referred to as standby or sleep. Suspend holds the data in memory 209 while This is a standby state in which the power consumption of the entire system can be reduced and the operating state can be quickly restored by turning off or stopping devices such as the processor 202, the storage device 220, and the LCD. In the suspend mode, the memory 209 holds data in a state where the OS is activated. Therefore, when the OS is restored, the OS is not restarted and returns to the state before the suspension.
  • S3 state
  • ACPI Advanced Configuration and Power Interface
  • Self refresh is a mode in which the clock is deactivated to reduce the power consumption of the device and the refresh operation is automatically executed using an internal refresh counter. Self-refreshing is effective when data must be retained but the device is not accessed for a long time.
  • the power consumption is relatively large compared to the state where the entire system is turned off (S5 of the ACPI standard). Further, in the suspend mode, when the power supply is cut off, such as when a power failure occurs or when the remaining battery level is exhausted, the data in the memory 209 is lost and the data cannot be restored.
  • Hibernation (S4, also called hibernation)>
  • the hibernation function saves (saves) the contents of the memory 209 in the storage device 220 such as an HDD immediately before turning off the power of the system, restores the contents of the memory 209 with the contents saved in the storage device 220 at the next startup, and returns. It is. Hibernation is also referred to as S4 in the ACPI standard.
  • Hibernation has the advantage that it consumes less power than suspend because the system power can be completely turned off.
  • hibernation since the contents of the memory 209 are saved and restored in the storage device 220, a relatively long time is required for transition and restoration.
  • Patent Document 2 describes a method for reducing the amount of read / write data in hibernation performed by the BIOS.
  • InstantOn is an OS that is prepared separately from a normal OS that can use all the functions of the system and that starts up in a short time with limited functions.
  • a normal OS or InstantOn is selected as an OS to be started according to a user instruction.
  • the EC 206 is responsible for managing the power state of the system.
  • the state where the EC 206 is turned off (OFF) corresponds to the ACPI standard S5 and is a state where the entire system is turned off.
  • suspend (S3, standby) is different from power off (S5), and it is necessary to maintain power supply to the memory 209 of the system. For this reason, in the case of the general PC 200 shown in FIG. 1, the EC 206 cannot be turned off during the suspension.
  • Hybrid Sleep A combination of S3 (standby) and hibernation, and a hibernation image (Hib Image) is created on the storage device 220 simultaneously with the transition to standby. Although the transition time for creating a hibernation image is longer than that for the standby mode, the transition to the standby mode is fast, so the return to S0 is quick. Further, unlike standby, even if the power is lost, it is possible to recover from the hibernation image on the storage device 220. In addition, Hybrid Sleep is introduced as a function of Windows (registered trademark) Vista.
  • the PC 200 realizes the return from the standby state by using solutions such as suspend, hibernation, and InstantOn.
  • solutions such as suspend, hibernation, and InstantOn.
  • the EC 206 cannot be turned off in the suspend state, there is a problem that power consumption increases.
  • hibernation there is a problem that a relatively long time is required for transition / return time.
  • each embodiment will be described focusing on an embodiment related to reducing power consumption of the entire system during suspension and an embodiment related to reducing transition time in hibernation.
  • the first embodiment relates to a technique for turning off an EC power supply in order to reduce power during suspend (standby). By turning off the EC power supply, power during standby can be greatly reduced. Power supply to the memory is controlled by GPIO Use the Expander. It is possible to maintain the output level of the suspended memory by collecting the signals that need to be controlled in the GPIO Expander and supplying only the power of the GPIO Expander.
  • FIG. 2 is a schematic diagram illustrating the overall configuration of the information processing apparatus 100 according to each embodiment described below.
  • An example of the information processing apparatus 100 is a notebook personal computer (PC), but is not limited to this.
  • the information processing apparatus 100 includes a processor 102, a chip set (PCH: platform controller hub) 104, an EC 106, a memory 109, a GPIO expander IC (GPIO Expander) 110, a charge control IC 112, and a USB port. 114, a storage device (SSD or HDD or the like) 116, an access LED 118, and a BIOS ROM 119.
  • the information processing apparatus 100 includes a keyboard 120, a battery 122, a power button 124, and a power LED 126.
  • the chipset 104 is not composed of the north bridge 208 and the south bridge 210, and the processor 102 includes the function of the north bridge 208. Yes. That is, the north bridge 208 in FIG. 1 is integrated with the processor 102. For this reason, the processor 102 includes a memory controller 110 that controls the memory 109.
  • the chip set 104 is mainly composed of the south bridge 210 of FIG.
  • the chip set 104 includes an RTC (Real Time Clock) 114 that is a chip dedicated to timing.
  • the EC 106 includes an alarm timer 107.
  • FIG. 3 is a schematic diagram illustrating a specific configuration of the information processing apparatus 100 according to the first embodiment.
  • FIG. 3 mainly shows the memory 109 and the components that supply power to the memory 109.
  • the EC 106 is operated by two power supply systems (VCC1 / VCC2).
  • the GPIO Expander 110 uses a power supply corresponding to the power supply VCC1 of the EC 106.
  • the output levels of the two signals (MEMORY_ON / RST_ON) supplied to the memory 109 are kept.
  • MEMORY_ON is a signal for controlling the power source of the memory 109
  • RST_ON / EC_ON is a signal for controlling a reset signal of the memory 109.
  • These signals are the VCC1 operating part of EC106 or GPIO. Supplied from the Expander 110.
  • the power supply VCC2 of the EC 106 is turned off in the suspend (S3). As a result, most of the functions of the EC 106 are turned off. On the other hand, the power supply VCC1 of the EC 106 is not turned off even in the suspend state, and the power is supplied to the GPIO Expander 110 even in the suspend state.
  • the GPIO Expander 110 is turned on, and a signal to the memory 109 can be continuously sent.
  • power consumption can be significantly reduced.
  • the power supply VCC1 is provided in the EC 106, but the power supply VCC1 may be provided separately from the EC 106. As a result, the EC 106 can be completely turned off during the suspend.
  • the power supply of the EC 106 that executes control of power supply to the system is turned off during standby when the power of the processor 102 that controls the system is turned off, and separately from the EC 106 during standby.
  • the provided GPIO Expander 110 executes power supply to the memory 109 that stores information.
  • the configuration for realizing this processing can be configured by hardware (circuit) or a central processing unit such as a CPU and a program for causing this to function.
  • FIG. 4 is a schematic diagram illustrating another example of a specific configuration of the information processing apparatus 100 according to the first embodiment.
  • an external latch circuit 130 is provided instead of the GPIO Expander 110.
  • the external latch circuit 130 uses a power supply corresponding to the power supply VCC1 of the EC 106 in the suspend state.
  • the power supply VCC2 of the EC 106 can be turned off during the suspend similarly to the configuration shown in FIG. 3, so that the power consumption in the suspend can be greatly reduced.
  • FIG. 5 is a schematic diagram for explaining an example of the effect of the first embodiment.
  • the power consumption of the EC 206 at the time of suspend is 200 [mW]
  • the EC 106 at the time of suspend is The power consumption can be reduced to 0 [mW]. Therefore, the power consumption of the entire information processing apparatus 100 ((Total)) can be reduced to 200 [mW], and 100 [mW] with respect to the total power consumption (300 [mW]) of the PC 200 in FIG.
  • the usable period of the battery 122 after charging can be set to 15 days, which is 1.5 times longer than the 10 days of the PC 200 in FIG. Become.
  • the signals for maintaining the memory 109 at the time of suspend are collected in the GPIO Expander 110, and the power of the EC 106 is turned off at the time of suspend. Can be greatly reduced. Thereby, the holding period of the battery 122 can be extended significantly.
  • Second Embodiment 3.1 Operation of Second Embodiment
  • the second embodiment relates to a technology that realizes the startup time with high accuracy when the EC and the chipset are powered off during suspension.
  • the chipset 104 includes an RTC (Real Time Clock) 114.
  • RTC Real Time Clock
  • PCH chipset
  • Resume power supply the function of the RTC 114 provided in the chipset 104 cannot be used. That is, power consumption can be reduced by turning off the power of the chipset 104, but there is a demerit that sacrifices the function of the RTC 214.
  • the EC 106 needs to be turned on (ON). If the EC 106 is turned off, power management cannot be performed. However, if the EC 106 is turned on, the power consumption increases.
  • the information processing apparatus 100 has an RTC Wake function.
  • the RTC Wake is a function that the chipset 104 starts itself at a predetermined time.
  • the RTC Wake function is set by a user instruction or OS and enabled by the BIOS.
  • the processor 102 can be turned on only for a necessary period.
  • the power of the chipset 104 needs to be turned on.
  • the BIOS is a group of programs for controlling peripheral devices such as the EC 106 and the storage device 116 connected to the processor 102 and the chipset 104.
  • the basic input / output unit for these devices is used for the OS and application software. To provide.
  • the BIOS is stored in the BIOS ROM 119.
  • the same setting is made on the EC 106 by the BIOS.
  • the EC 106 turns on the power of the chipset 104 a predetermined time before the date and time set by the RTC wake (for example, several seconds before).
  • the RTC A wake interrupt occurs and the system starts up. According to such a configuration, the EC 106 and the chip set 104 can be turned on only when necessary, and the power consumption can be significantly reduced.
  • FIG. 6 is a schematic diagram showing signals exchanged between the processor (CPU) 102, the chipset 104, and the EC 106, and the power on / off state.
  • a region with a dot indicates a state where the power is off (OFF)
  • a region without a dot indicates a state where the power is on (ON).
  • the chip set 104 has the RTC 114.
  • the EC 106 also has a unique timer 107.
  • RTC Wake When RTC Wake is set in the chipset 104, the RTC wake interrupt occurs at the set date and time in the chipset 104, the processor 102 is powered on, and the system is activated.
  • the BIOS 103 operating on the processor 102 acquires information on the date and time of activation (Wake) by the RTC Wake from the chipset 104.
  • the BIOS 103 activates the EC 106 based on the information acquired from the chipset 104 (RTC). (date and time similar to wake) is set.
  • the EC 106 sets its own timer 107 (Alarm Timer) so as to start up a predetermined time before the set date and time.
  • the predetermined time depends on the accuracy of the timer 107 of the EC 106, and the RTC Depending on the margin until the wake is activated, the EC 106 is set to a time when the activation of the EC 106 can surely precede the RTC Wake.
  • the predetermined time is set to an arbitrary value such as 1 second, 5 seconds, 1 minute, and 5 minutes.
  • the EC 106 is activated based on the time set in the timer 107 several seconds before the date and time when the chip set 104 should be restored by the RTC Wake. This is because, as mentioned above, RTC This is because when the Wake date and time is set, the timer 107 of the EC 106 is set so as to start slightly before the set date and time.
  • the restored EC 106 supplies power to the chip set 104.
  • the RTC Wake time set in the RTC 114 has not been reached, and the timer of the RTC 114 has not expired.
  • the RTC is electrically The environment where wake is possible is prepared.
  • the EC 106 operates only to create an environment in which the RTC wake can be realized. After the power is supplied to the chipset 104, the system is automatically activated by the RTC wake and reaches S0. For this reason, in this embodiment, the actual RTC The system transitions to S0 by the wake mechanism and starts up (Wake). Therefore, compared with the case where the EC 106 as described in Patent Document 1 is used as a substitute for the RTC 114, it is possible to start up accurately with respect to the time of the RTC 114 (system time).
  • the EC 106 is started sufficiently early so that the system is accurately started according to the time of the RTC 114. can do. Therefore, for example, even when performing TV recording, recording can be performed accurately in accordance with the time of the TV program based on the time of the RTC 114. In addition, it becomes easy to notify that the RTC 114 has returned (Resume) in terms of OS or BIOS. Therefore, an operation intended at the time intended by the user is possible.
  • RTC wake by RTC 114 can be supported, and it is not necessary to emulate RTC wake using a device other than RTC 114, such as EC 106, so that the accuracy of the startup time of the system can be further improved.
  • startup is performed by RTC wake compared to emulation using an external device, an error in startup time when viewed from the OS can be suppressed.
  • the OS is RTC It is possible to easily detect that a wake has occurred.
  • the power source of the main memory 109 is managed by the EC 106.
  • the EC 106 sets the date and time when the power of the memory 109 is turned off in its own alarm timer (AlarmAlTimer). At this time, it is recorded that the memory power is turned off at the next startup.
  • the power of the processor 102 and the EC 106 is turned off while the power of the memory 109 is on.
  • the EC 106 performs the power management operation of the main memory. Since the date and time when the power of the memory 109 is turned off is set in the own alarm timer (Alarm
  • FIG. 15 is a schematic diagram showing the configuration of the processor 102, the chip set (PCH) 104, the EC 106, and the memory 109. Power is supplied to each of the chip set 104 and the RTC 114. PCH Power is supplied to the chipset 104, and RTC Power is supplied to the RTC 114. Further, power is supplied to each of the EC 106 and the timer 107. EC power is supplied to the EC 106, and BAT Power is supplied to the timer 107. The processor 102 is supplied with power (CPU power).
  • the power sources of the timer 107, the RTC 114, the chipset 104, the processor 102, the EC 106, and the memory 109 are separated so that they can be controlled.
  • the power supply other than the RTC 114 and the timer 107 is configured to be capable of ON / OFF control by the EC 106. According to the configuration shown in FIG. 15, the timer 107 can be operated even when the EC 106 is not activated. Further, the RTC 114 can be operated even when the chipset 104 is not activated.
  • FIG. 16 is a schematic diagram showing a modification of the configuration of FIG.
  • the timer 107 is built in the EC 106.
  • a dedicated circuit 140 having the same function as the timer 107 may be provided outside.
  • the dedicated circuit 140 generates an interrupt signal for a startup request (Wake UP Request) to the EC 106.
  • FIG. 17 shows an example in which a hardware (HW) switch 150 is provided instead of the dedicated circuit 140 shown in FIG.
  • the EC 106 can be activated by a trigger other than the timer 107.
  • the HW switch 150 when the HW switch 150 generates an activation request interrupt signal, the EC 106 is turned on, and the power management of the device can be performed.
  • FIG. 18 is a schematic diagram illustrating an example in which another device (Any Devices) 160 is provided in place of the memory 109 in FIG.
  • any device capable of controlling power in the EC 106 can control power with the same configuration.
  • FIG. 19 is a schematic diagram showing a configuration applied to applications other than power supply control.
  • the device 170 is controlled by the EC 106 other than the power control.
  • the EC 106 can be powered off (OFF) while the device 170 is not controlled. In this way, even when performing control other than power control, it is possible to reduce power consumption by turning on the EC 106 only when necessary.
  • Third Embodiment 4.1 Overview of USB Charging Next, a third embodiment of the present disclosure will be described.
  • the third embodiment relates to a technology for connecting the information processing apparatus 100 and another apparatus and charging the other apparatus.
  • USB charging will be described as an example.
  • USB Charge is specified in Battery Charging Specification (hereinafter referred to as BCS), which is a quick charging standard using BUS Power formulated by USB-IF.
  • BCS Battery Charging Specification
  • the latest version of BCS is Ver.:Revision 1.2 (2010/12/7 release).
  • the conventional USB BUS power can only supply power up to 500 [mA] (900 [mA] for USB 3.0) at a voltage of 5 [V] ⁇ 5%. ] Power can be supplied up to 1.5 [A] at a voltage of ⁇ 5%.
  • USB Charge port The definition of the USB Charge port will be described.
  • the BCS defines the following three types of ports. 1. SDP: Standard Downstream Port It is a normal USB port, can communicate with other devices, and can supply up to VBUS 500 [mA]. 2. DCP: Dedicated Charging Port MAX 1.5 [A] can be supplied from VBUS. Communication is not possible. 3. CDP: Charging Downstream Port MAX 1.5 [A] can be supplied from VBUS and communication is possible.
  • the device connected to the information processing apparatus 100 and charged by USB is a device such as a smartphone or a digital camera. Some devices automatically pull VBUS even during S3.
  • FIG. 20 is a schematic diagram illustrating an example of mounting specifications of each state in the information processing apparatus 100 according to the present embodiment.
  • default Default
  • two types of Charge A mode is assumed.
  • Default is a setting at the time of shipment, which is the same setting as a normal USB Port, and S0 and S3 are SDP.
  • S0 is CDP and DCP is a state other than S0 with respect to the default. Therefore, rapid charging is possible in all states.
  • the remaining amount of the battery 122 may be empty when the information processing apparatus 100 is not connected to an AC power source. In particular, if the remaining amount of the battery 122 becomes empty while data is being written to the storage device 116 by hibernation, the data may be lost.
  • the occurrence of data lost (Data) Lost) is suppressed by temporarily stopping the USB charge under a predetermined condition.
  • LBH low battery hibernation
  • Timer timer hibernation
  • FIG. 21 is a schematic diagram showing the discharge characteristics at S3 and S0.
  • FIG. 22 is a characteristic diagram showing the threshold value of LBH. As shown in FIG. 21, since the discharge characteristic at S3 and the discharge characteristic at S0 are different, different threshold values are set at S3 and S0 in consideration of this.
  • the S0 LBH threshold is 5% of the remaining battery power. If the LBH threshold value of S3 is set to 30% and the transition is made to S3 in the state where the remaining battery level is 25% in S0, LBH is executed, so the transition is made to S4.
  • the amount of power consumed during USB charging is larger than that of normal USB communication, and in LBH, the battery 122 may become empty during the creation of the Hib Image. In this case, data loss occurs.
  • FIG. 23 is a characteristic diagram showing timer hibernation, where the vertical axis indicates the remaining battery level and the horizontal axis indicates time.
  • the process starts (wakes) at S0, writes an image to the storage device 116, and then transitions to S4.
  • timer hibernation there is a possibility that the remaining amount of the battery 122 may be emptied during the timer period of 1 hour. Also, in timer hibernation, it must be started once at S0 in order to create a Hib Image. For this reason, it takes much more time for image creation than for low battery hibernation, and the possibility that the battery will be emptied becomes higher.
  • FIG. 24 is a flowchart showing LBH processing.
  • FIG. 24 shows an example in which LBH is activated during S0.
  • step S12 if the remaining battery level is 5% or less, the process proceeds to step S14 and Hib Image is created and the process proceeds from S0 to S4.
  • the power consumption of USB Char is large, and during USB charging, power is consumed even at steps S12 and S14.
  • the battery 116 may be emptied during image creation.
  • FIG. 25 is a flowchart showing the processing of Timer Hib.
  • Timer Hib is activated only during S3.
  • step S22 a transition is made from S0 to S3, and the timer of the RTC 114 starts.
  • step S24 it is determined whether or not the timer has exceeded 1 hour. If the timer has exceeded 1 hour, the process proceeds from S3 to S0 in step S26. If the timer is less than 1 hour, the process returns to step S24.
  • step S28 Hib Image is created and the process proceeds from S0 to S4.
  • it is necessary to start (wake) once in S0 in order to create the Hib Image it takes more time than the LBH to create the Image, and the battery 122 is more likely to be emptied.
  • FIG. 26 is a characteristic diagram showing the temporary stop mechanism, in which the vertical axis indicates the remaining capacity of the battery 122 and the horizontal axis indicates time.
  • the temporary stop mechanism temporarily stops the power supply by USB charging when the remaining battery level becomes 30% during USB charging in S3 (characteristic 1).
  • time t2 When a predetermined time elapses after the power supply is stopped, at time t2, Timer Hib is activated.
  • characteristic 2 in FIG. 26 shows a case where Timer Hib is activated at time t2 after one hour has elapsed after the transition to S3 when USB charging is not performed in S0.
  • Characteristic 3 shows a case where the capacity of the battery 122 becomes 5% or less during USB charging at S0. In this case, LBH is activated at time t1.
  • the temporary stop condition is when DC driving, during S3, and when the remaining battery capacity falls below 30 %%. Therefore, in the characteristics 2 and 3 in FIG.
  • FIG. 27 is a flowchart showing the temporary stop mechanism.
  • the configuration for realizing this processing can be configured by hardware (circuit) or a central processing unit such as a CPU and a program for causing this to function.
  • step S30 USB charging is enabled in the S0 state.
  • step S32 it is determined whether the drive is AC drive or DC drive. If the drive is AC drive, the process proceeds to step S34, and a transition from S0 to S3 / S4 / S5 is possible in a state where USB charging is possible. . In this case, USB charging is possible in S3 / S4 / S5.
  • step S36 the process proceeds to step S36, and the state change is determined.
  • step S38 transition is made from S0 to S4 / S5 in a state where USB charging is possible.
  • step S40 it is determined whether or not the remaining battery capacity exceeds 30%. If the remaining battery capacity exceeds 30%, the process waits in step S40. On the other hand, when the remaining battery level is 30% or less, the process proceeds to step S42, and the suspension condition is satisfied, so that the USB chargeable state is changed to the USB charge impossible state. As a result, USB charging to the device connected to the information processing apparatus 100 is stopped.
  • step S44 the process proceeds to step S46, and the state changes from the USB charge disable state to the USB charge enable state.
  • step S44 the process proceeds to the subsequent processes, and the LBH process (steps S12 to S16 in FIG. 24) or Timer Hib processing (steps S24 to S29 in FIG. 25) is performed.
  • the grounds for setting the remaining battery level 30% (threshold value that does not cause Data Lost) as the triggering condition of the suspension mechanism will be described below.
  • the activation condition can be set to a uniform value for all models of the information processing apparatus 100.
  • the trouble of setting the threshold value for each model can be saved.
  • the load is under an environment of a temperature of 20 ° C. -Calculate the threshold value from the capacity characteristics.
  • Timer at S3 The electric power required until S0 is activated (waked) by Hib is about 10% of the capacity of the battery 122.
  • the load (the power applied during the transition from S0 to S4) when the hibernation is turned on (ON) is about 15% of the battery capacity.
  • FIG. 28 is a schematic diagram showing the load when the hibernation is turned on (the amount of decrease in the capacity of the battery 122 during hibernation) in each of a plurality of different USB loads.
  • the margin considering the temperature characteristics is set to 5% of the battery capacity. Accordingly, it is desirable to set the remaining capacity of about 30% of the battery capacity as a threshold in total of 10% + 15% + 5%.
  • the threshold value is specified in units of [mWh], a relatively high threshold value is obtained in a model having a small battery capacity.
  • a battery with a capacity that can handle the PC performance (load power) is selected, so in order to set a uniform threshold for all models, the threshold unit is set to [%]. It is preferable to decide.
  • the USB charge is temporarily stopped when the DC drive is in progress and during S3 and the remaining battery capacity falls below 30 %%. , It is possible to reliably prevent the data from being lost.
  • Hybrid Sleep Function Next, an outline of the hybrid sleep function will be described as another data loss countermeasure.
  • an image is stored by hibernation by hybrid sleep or BIOS, and power supply other than the memory 109 is turned off in the S3 state, thereby promoting battery capacity retention during DC driving.
  • Hybrid Sleep is the S3 state in which the Hib Image is created as described above, and the hibernation image is created on the storage device 220 simultaneously with the transition to the standby.
  • FIG. 30 is a flowchart showing the process of the hybrid sleep function. As shown in FIG. 30, in the state where AC driving is not performed in the S0 state (step S50), when the transition to S3 is instructed (step S52), the state transits to Hybrid Sleep, and Hib Image is created (step S60).
  • step S52 If it is determined in step S52 that the transition to S3 is not instructed, the process proceeds to step S54 to determine whether the remaining battery capacity exceeds 5%. If the remaining battery capacity is 5% or less, the process starts from S0. Transition to S4 and Hib Image is created (step 56, S58).
  • Hib Image is created at the timing of entering S3, so that it is possible to reliably prevent data loss.
  • Battery sleep disable About Disable Battery 122 sleeps when Battery Sleep is enabled and the battery charge / discharge current is below a certain current value and is not communicating with EC 106 for a certain period of time. Enter the mode.
  • the CPU 123 of the battery 122 that detects the amount of current enters a sleep state.
  • the release condition is when the EC 106 starts up the processor.
  • FIG. 31 is a flowchart showing battery sleep disable processing.
  • FIG. 31 shows both the case where measures against battery sleep disable are taken (step S96 and later) and the case where measures are not taken (step S106 and later).
  • Battery sleep disable is set regardless of whether or not connected to AC power (step S96) when power other than the memory is turned off in step S3 (step S92).
  • step S100 the battery is not in the sleep state, and the CPU 123 of the battery 122 is also activated. Therefore, when USB charging is performed (step S102), the occurrence of abnormal heat generation is reliably suppressed (step S104).
  • the disable condition is that both the 1st / 2nd battery is disabled when the USB charging is on. To turn off USB charging, only the 2nd battery is disabled and the 1st battery is enabled.
  • step S108 the battery 122 is in the sleep state and the CPU 123 is not activated. For this reason, when USB charging is performed in step S110, abnormal heat generation occurs.
  • FIGS. 32 to 37 show a state in which a device to be charged 300 to be USB charged is connected to the information processing device 100.
  • FIG. The charged device 300 includes a chip set 302, a battery 304, a power switch 306, and a USB connection unit 308.
  • the configuration of the information processing apparatus 100 is the same as that of FIG. 2, but the CPU 123 of the battery 122 (not shown in FIG. 2) and a power switch (Power) for USB charging are not shown.
  • SW) 130 and USB connection unit 132 are shown. 32 to 37, it is shown that the power is not turned on to the components with dots.
  • FIG. 32 shows a state in which the USB charge is off at S0. In this state, all the components including the processor 102 and the chip set 104 are turned on. An image on the display screen (Image) exists on the processor 102, and the EC 106 monitors (monitors) the remaining amount of the battery 122. The EC 106 controls the port mode (port mode) of the power switch 130 for charging. In FIG. 32, the port mode is SDP, and the charged device 300 can be supplied up to 0.5 [A].
  • FIG. 33 shows a state where the state transitions from S0 to S3 and the USB charge is off.
  • the power of the processor 102 is turned off, and the image is written in the memory 109.
  • the power is not supplied to the memory 109, and thus the Image disappears.
  • the EC 106 monitors the remaining amount of the battery 122.
  • the SDP state is maintained, and the device can supply up to 0.5 [A].
  • FIG. 34 shows a state in which the transition from S0 to S4 / S5 and the USB charging is off (OFF). In this state, almost all the components are turned off. At S4, the image is stored in the HDD 116. In this case, even if the power is turned off, the image is stored in the HDD 116, so the image is not lost. Since the EC 106 is powered off, the remaining amount of the battery 122 cannot be monitored. Further, the CPU 123 of the battery 122 enters a sleep state, and the port mode is turned off (OFF). Therefore, the charged device 300 is not charged.
  • FIG. 35 shows a state where USB Charge is on in S0. In this state, all the components including the processor 102 and the chip set 104 are turned on. Image exists on the processor 102, and the EC 106 monitors (monitors) the remaining amount of the battery 122. The EC 106 controls the port mode (Port mode) of the power switch (Power SW) 130 for charging.
  • the port mode is CDP and can supply up to 1.5 [A] to the charged device 300 to be charged. In addition, when the to-be-charged apparatus 300 does not support CDP, the supply is up to 0.5 [A].
  • FIG. 36 shows a state in which the state transitions from S0 to S3, and USB Charge is (ON).
  • the power of the processor 102 is turned off, and the image is written in the memory 109.
  • the image disappears.
  • the EC 106 monitors the remaining amount of the battery 122.
  • the port mode is DCP and can supply up to 1.5 [A] to the device.
  • FIG. 37 shows a state in which the transition from S0 to S4 / S5 is performed and the USB charge is on.
  • the power supply of the EC 106 is maintained.
  • the image is stored in the HDD. In this case, even if the power is turned off, the image is stored in the HDD 116, so the image is not lost.
  • the EC 106 monitors the remaining amount of the battery 122.
  • the CPU 123 of the battery 122 is not in the sleep state, and the port mode is DCP.
  • the fourth embodiment improves user convenience during BIOS hibernation.
  • ⁇ Cancellation of hibernation> As described above, in hibernation, the contents of the memory 109 are saved (saved) in the storage device 116 such as an HDD immediately before the system is turned off. At this time, depending on the usage amount of the system memory 109 and the performance of the storage device 116, it may take time to write out the BIOS hibernation data, and the process cannot be interrupted. It may take a minute or more to write the data.
  • an interrupt handler for the power button 124 is prepared in the BIOS, and hibernation is canceled when the power button 124 is pressed. If hibernation is canceled, hibernation data writing is interrupted and the system is returned to S0. The EC 106 detects that the power button 124 has been pressed and raises an interrupt to the system.
  • Cancel is a function that, when the power button is pressed during BIOS hibernation data export, stops the export and returns immediately. This function eliminates the need to wait until the BIOS hibernation data writing is completed when it is desired to return during the BIOS hibernation data writing operation, thereby improving the usability of the user.
  • the access lamp is turned off while the BIOS hibernation data is being written out, the user who wants to return is naturally guided to the power button 124 and can use the cancel function without being aware of it.
  • a command I / F for overriding and controlling the lighting state of the power LED 126 and the access LED 118 between the BIOS 103 and the EC 106 is prepared.
  • the BIOS 103 instructs the EC 106 to turn off the lamp before writing out the BIOS hibernation data.
  • the lamp is turned off in order not to make the user aware of the time taken to write out the BIOS hibernation data.
  • the BIOS hibernation data is written a little longer, the user will not mistakenly assume that the system is frozen.
  • the user can be made aware that the user can return to S0 by pressing the power button 124 without making the user aware of the cancel function. That is, when the power LED 126 is turned off, it looks like an off state, and the user is naturally guided by pressing the power button 124 in order to turn on the power.
  • the EC 106 implements a function of ignoring the turn-off instruction by the BIOS so that the process of intentionally turning off the lamp is not performed. If it is frozen, the lamp is lit without the system returning, so it is possible to inform the user of some abnormal state.
  • FIG. 38 is a flowchart showing the processing of this embodiment.
  • the BIOS 103 issues a command for instructing the EC 106 to turn off the lamp.
  • the EC 106 overrides the lamp and turns off.
  • writing processing to the storage device 116 is performed by hibernation.
  • the EC 106 stops the lamp override.
  • FIG. 39 is a flowchart showing the writing process.
  • the BIOS 103 writes part of the hibernation data.
  • the EC 106 stops the lamp override, and in the next step S136, the system is returned.
  • step S132 If the power button 124 is not pressed in step S132, the process proceeds to step S138, where it is determined whether or not writing of all data has been completed. If the writing has been completed, the process is terminated (RETURN). If the writing has not been completed, the process returns to step S130.
  • the fourth embodiment when the power button 124 is pressed, hibernation is canceled, so that user convenience can be improved.
  • the lamp is turned off before the BIOS hibernation data is written, even if the BIOS hibernation data is written a little longer, the user will not mistakenly assume that the system is frozen. Further, the user can recognize that it is in a state where the user can cancel with the power button 124 and return to S0.
  • a processor for controlling the system of the information processing apparatus A chipset for managing the data transfer of the processor; A power supply control unit for controlling power supply to the system; A BIOS for setting a startup time to the clock of the chipset; An activation unit that activates the power control unit a predetermined time before the activation time;
  • An information processing apparatus comprising: (2) The information processing apparatus according to (1), wherein the activation unit includes a timer included in the power control unit. (3) The information processing apparatus according to (1), wherein the activation unit includes a timer provided separately from the power control unit. (4) The information processing apparatus according to (1), wherein the activation unit includes a hardware switch.
  • a processor for controlling the system of the information processing apparatus for controlling the system of the information processing apparatus; A chipset for managing the data transfer of the processor; A power supply control unit for controlling power supply to the system; In a state where the power of the processor and the chipset is turned off, an activation unit that activates the power control unit according to the timing at which the power control unit controls the power supply;
  • An information processing apparatus comprising: (7) The information processing apparatus according to (6), wherein the activation unit includes a timer included in the power control unit. (8) The information processing apparatus according to (6), wherein the activation unit includes a timer provided separately from the power control unit. (9) The information processing apparatus according to (6), wherein the activation unit includes a hardware switch. (10) The information processing apparatus according to (6), wherein the power control unit controls power supply of a memory that stores information in a state where the power of the processor and the chipset is turned off.

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Abstract

Le présent dispositif de traitement d'informations comprend : un processeur commandant un système; un jeu de puces qui gère le traitement/la réception de données du processeur; une unité de commande de source d'alimentation commandant l'alimentation en courant électrique du système; un BIOS qui règle un temps d'activation dans une horloge du jeu de puces; et une unité d'activation activant l'unité de commande de source d'alimentation un temps prédéterminé avant le temps d'activation.
PCT/JP2013/057457 2012-04-27 2013-03-15 Dispositif de traitement d'informations, procédé de traitement d'informations, et programme WO2013161438A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003271263A (ja) * 2002-03-15 2003-09-26 Toshiba Corp 情報処理装置、時刻情報制御方法
JP2007122566A (ja) * 2005-10-31 2007-05-17 Toshiba Corp 情報処理装置およびレジューム制御方法
JP2010152721A (ja) * 2008-12-25 2010-07-08 Toshiba Corp 情報処理装置および情報処理装置の起動プログラム
JP2011204167A (ja) * 2010-03-26 2011-10-13 Sony Corp 情報処理装置
JP2011248788A (ja) * 2010-05-30 2011-12-08 Lenovo Singapore Pte Ltd パワー・オフ状態での消費電力の低減が可能な電子機器および消費電力の低減方法
JP2012226677A (ja) * 2011-04-22 2012-11-15 Lenovo Singapore Pte Ltd コンピュータがウエイク・アップする方法およびコンピュータ

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003271263A (ja) * 2002-03-15 2003-09-26 Toshiba Corp 情報処理装置、時刻情報制御方法
JP2007122566A (ja) * 2005-10-31 2007-05-17 Toshiba Corp 情報処理装置およびレジューム制御方法
JP2010152721A (ja) * 2008-12-25 2010-07-08 Toshiba Corp 情報処理装置および情報処理装置の起動プログラム
JP2011204167A (ja) * 2010-03-26 2011-10-13 Sony Corp 情報処理装置
JP2011248788A (ja) * 2010-05-30 2011-12-08 Lenovo Singapore Pte Ltd パワー・オフ状態での消費電力の低減が可能な電子機器および消費電力の低減方法
JP2012226677A (ja) * 2011-04-22 2012-11-15 Lenovo Singapore Pte Ltd コンピュータがウエイク・アップする方法およびコンピュータ

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