WO2013160994A1 - Structure plaquée de trou traversant - Google Patents

Structure plaquée de trou traversant Download PDF

Info

Publication number
WO2013160994A1
WO2013160994A1 PCT/JP2012/060906 JP2012060906W WO2013160994A1 WO 2013160994 A1 WO2013160994 A1 WO 2013160994A1 JP 2012060906 W JP2012060906 W JP 2012060906W WO 2013160994 A1 WO2013160994 A1 WO 2013160994A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
insulating substrate
layer
electroplating
conductive
Prior art date
Application number
PCT/JP2012/060906
Other languages
English (en)
Japanese (ja)
Inventor
哲男 湯本
Original Assignee
三共化成株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三共化成株式会社 filed Critical 三共化成株式会社
Priority to JP2014512051A priority Critical patent/JP5753628B2/ja
Priority to PCT/JP2012/060906 priority patent/WO2013160994A1/fr
Publication of WO2013160994A1 publication Critical patent/WO2013160994A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/185—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method by making a catalytic pattern by photo-imaging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate

Definitions

  • the present invention relates to a through hole plating structure in which one end of a through hole formed in an insulating substrate is closed with an electroplating layer.
  • the conductive circuit formed on each printed wiring board normally passes through these printed wiring boards in the stacking direction and has a conductive through hole (also referred to as “via hole”). Are connected to each other.
  • a conductive through hole also referred to as “via hole”.
  • the electroplating solution becomes difficult to enter and circulate inside the through-hole, not only does it take a long time to fill the through-hole with electroplating, but also the surface of the printed wiring board during that long time.
  • the plating thickness of the conductive circuit or the like formed at the same time is enlarged, and not only the thickness when laminated in a multilayer is increased, but also a short circuit between adjacent conductive circuits is likely to occur.
  • an electroplating layer is formed only in the vicinity of the inlet and outlet of the through hole, and the opening diameter near the inlet and outlet becomes small, Within the vicinity of the outlet, it takes a long time to form the electroplating layer.
  • the surface of the electroplating layer that closes the entrance / exit portion of the through hole is usually formed as a concave surface that is not flat.
  • the surface of the electroplating layer is not flat but concave in the part that closes the entrance / exit of the through hole in this way, if a through hole is provided directly above the through hole, or an electronic component is mounted directly above the through hole by wire bonding And the degree of freedom in the construction of the multilayer printed wiring board is greatly reduced.
  • a conductive base layer is formed on the surface of the insulating base and the inner side surface of the via hole, a special electroplating accelerator is applied, and then this accelerator is removed except for the inner side surface of the via hole.
  • a means for filling a via hole by performing electroplating on a conductive base layer has been proposed (see Patent Document 1). According to this means, since the formation of electroplating is promoted on the inner surface of the via hole where the promoter remains, it is described that the via hole can be filled by electroplating in a relatively short time.
  • a conductive base layer is formed on the surface of the insulating substrate and the inner surface of the via hole, a special electroplating accelerator and an inhibitor are added, and then electroplating is performed on the conductive base layer.
  • a means for filling a via hole and then flattening the electroplating of the surface of the substrate with an etching solution has been proposed (see Patent Document 2, etc.).
  • the electroplating accelerator and the suppressant promote the formation of electroplating on the inner surface of the via hole, so that the via hole can be filled by electroplating in a relatively short time, and the surface of the substrate can be filled with an etching solution. It is described that the surface of the electroplating layer in the portion closing the via hole entrance can be flattened by dissolving the surface of the electroplating formed in (1).
  • a conductive layer is provided on one surface of the insulating base, a via hole reaching the conductive layer from the other side of the base is formed, and a conductive base layer is formed on the surface of the insulating base and the inner side surface of the via hole.
  • a means for forming an electroplating in the via hole by forming a needle-like electrode into the via hole see Patent Document 3 and the like.
  • the electroplating can be quickly and uniformly formed in the via hole by the needle-shaped electrode that has entered the via hole, the electroplating of the portion that can quickly and uniformly fill the via hole and close the via hole entrance It is described that the surface of the layer can be flattened.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2001-291955 Patent Document 2 Japanese Patent Application Laid-Open No. 2005-31245 Patent Document 3 Japanese Patent Application Laid-Open No. 2006-032476
  • the means described in Patent Document 1 described above requires a special accelerator that promotes the formation of electroplating, and the problem that the surface of the electroplating layer that closes the via hole entrance becomes concave.
  • the means described in Patent Document 2 requires a special accelerator and inhibitor that promotes or suppresses the formation of electroplating, and further, the surface of the electroplating layer that closes the via hole entrance with the etching solution is used. A flattening process is required.
  • the means described in Patent Document 3 requires a needle-like electrode that enters into a minute via hole.
  • an object of the present invention is to provide a through-hole plating structure in which one end of a through-hole can be closed in a short state by a commonly used electroplating method in a short time.
  • the present inventors have conducted extensive research.
  • the pointed part of the object to be plated has a higher current density, compared with other flat parts.
  • the through hole is made into a specific shape, inspired by the phenomenon that the surface of the through hole is formed thick, one end of the through hole is flattened in a short time by a commonly used electroplating method.
  • the present invention was completed by finding that it can be occluded.
  • the present inventors made the through hole into the following shape, by a normal electroplating method and in a short time, It has been found that one end of the through hole can be closed with a flat surface.
  • One end portion of the through hole is formed in a spindle shape having an apex angle of 60 to 30 degrees, and the tip portion of the spindle shape is opened on the surface of the insulating substrate.
  • the periphery of the opening where the through hole opens in the insulating substrate has an acute angle of 60 to 30 degrees in the cross-sectional shape, the current density at the tip of the periphery increases, and an electroplating layer is formed on the tip of the periphery. Can be formed quickly.
  • the through hole has a weight-like shape, the diameter of the opening that opens in the insulating substrate is reduced, and the opening of the plating solution is facilitated by facilitating circulation from the rear end portion that widens toward the end.
  • An electroplating layer can be formed more rapidly at the tip of the periphery of the part.
  • the surface of the insulating substrate where the through hole is opened is formed flat, that is, the periphery of the opening is formed into a knife edge of a one-edged blade having a flat upper end in the cross-sectional shape.
  • the surface of the electroplating layer which is the surface of the insulating substrate and closes the portion where the through hole is opened, can be formed on a flat surface.
  • the opening diameter at which the through hole opens on the surface of the insulating substrate is set in the range of 10 to 100 ⁇ m. Thereby, the opening part of a through hole can be obstruct
  • the opening portion of the through hole can be closed with the surface of the electroplating layer being flat during the time for forming the electroplating layer having a predetermined thickness on the inner surface of the through hole. Therefore, the time can be greatly shortened as compared with the case where the through hole is filled with electroplating as in the prior art described above.
  • the other end portion of the through hole is not clogged by the electroplating layer because the bottom end of the weight-like shape is wide and has a large diameter. Therefore, according to the present invention, a through hole can be laminated directly on a through hole or an electronic component can be mounted by wire bonding only on one surface of an insulating substrate. On the other side of the insulating substrate, there is no problem in stacking through-holes or mounting electronic components by wire bonding, except directly above the through-holes. There is no significant decrease.
  • the present invention provides a through-hole plating structure in which one end portion of a through hole formed in an insulating substrate is closed by an electroplating layer, and the one end portion of the through hole is formed in a conical space. And the tip of the cone-shaped space penetrates the surface of the insulating base and opens to the surface of the insulating base, and the surface of the insulating base has the through hole open.
  • the portion to be formed is formed on a flat surface.
  • the apex angle of the cone-shaped space is 60 to 120 degrees, and the opening diameter opened to the surface of the insulating substrate is 10 to 100 ⁇ m.
  • a conductive layer is provided on each of the inner surface of the through hole, the surface of the insulating substrate, and the back surface of the insulating substrate, and the conductive layer provided on the inner surface of the through hole has the insulating property.
  • the conductive layer provided on the surface of the substrate is connected to the conductive layer provided on the back surface of the insulating substrate.
  • Each of the conductive layers is formed by laminating an electroplating layer on a conductive base layer, and the portion where the through hole opens on the surface of the edge base is flattened by the electroplating layer. It is closed so that it may become.
  • the opening area on the bottom surface side of the conical space can be avoided to be larger than necessary, and the influence on the arrangement of the conductive circuit on the surface of the insulating substrate located on the bottom surface side can be reduced. desirable. Therefore, it is desirable to form the through hole in a shape in which a cylindrical space communicates with the bottom surface of the conical space.
  • a conductive base layer can be easily and precisely formed on a specific portion on the front and back surfaces of the insulating substrate where a conductive circuit or the like is formed and the inner surface of the through hole. Therefore, it is more desirable that the conductive base layer is an electroless plating layer.
  • the insulating substrate is a product obtained by injection molding a thermoplastic resin.
  • the material of the “insulating base” is preferably a thermoplastic or thermosetting synthetic resin, but other insulating materials such as ceramic and glass can also be used.
  • the thermoplastic resin include polyethylene, polypropylene, polystyrene, ABS, polycarbonate, polyethylene terephthalate, polybutylene terephthalate, polysulfone, polyether polysulfone, polyarylsulfone, polyetherimide, polyamide, modified polyphenylene oxide resin, and aromatic liquid crystal. Polymers and norbornene resins are applicable.
  • the “insulating substrate” is not limited to injection molding, and may be molded by mechanical processing such as compression molding or grinding.
  • the “cone shape” means a shape in which the cross-sectional area gradually decreases toward the tip, and the cross-sectional shape is not limited to a circular cone, and includes, for example, an ellipse and a polygon.
  • the portion of the insulating substrate on which the through hole is opened is formed on a flat surface.” This is because the portion where the through hole is opened is closed with an electroplating layer. This is because the surface of the closed electroplating layer can be flattened.
  • the opening portion of the through hole is X-shaped with a gap in the axial center, that is, the portion where the through hole opens on the surface of the insulating base is recessed in a V shape.
  • “formed on a flat surface” means that no depression, protrusion, step, or the like is formed on the surface of the insulating substrate where the through hole opens.
  • the apex angle of the cone shape is 60 to 120 degrees”.
  • the tip angle (in the cross-sectional shape including the axis) of the opening where the through hole opens in the insulating substrate is 60 degrees or more. This is because the current density at the tip of the periphery cannot be sufficiently increased, and the time for forming the electroplating layer at the tip of the periphery becomes long. Further, if it exceeds 120 degrees, the tip angle of the peripheral edge becomes 30 degrees or less and becomes too thin, and when the through hole is injection-molded, the resin does not easily flow to the peripheral tip.
  • the apex angle is more preferably 80 to 100 degrees.
  • the opening diameter opening on the surface of the insulating base is 10 to 100 ⁇ m” is that when the opening diameter is less than 10 ⁇ m, the electroplating solution may recirculate in the vicinity of the opening of the through hole. This is because it becomes difficult and the electroplating layer is poorly attached in the opening, and the formation of the electroplating layer becomes uneven. Moreover, when it exceeds 100 micrometers, it is because the time for obstruct
  • the opening diameter is more preferably 30 to 60 ⁇ m.
  • the conductive layer is provided on the surface of the insulating substrate and the back surface of the insulating substrate, respectively.”
  • the conductive layer means a conductive circuit or a conductive circuit provided on the front and back surfaces of the insulating substrate. It means a connection terminal.
  • the conductive layer provided on the inner surface of the through hole is connected to the conductive layer provided on the surface of the insulating substrate and the conductive layer provided on the back surface of the insulating substrate.” The reason is that the conductive layers provided on the front and back surfaces of the insulating substrate are made conductive through the conductive layers provided on the inner side surfaces of the through holes. Thereby, it is possible to make the stacked printed boards conductive with each other through the conductive layers provided on the front and back surfaces of the insulating substrate, not limited to the position directly above the through hole.
  • the “electroconductive underlayer” is preferably an electroless plating layer, but also includes physical vapor deposition such as vacuum vapor deposition, sputtering, and ion plating.
  • the “electroplating layer” is one in which a current is passed through an electrolyte solution containing metal ions, and the metal ions in the electrolyte solution are deposited on an object charged on the cathode, and is commonly used. It means what is formed by a general procedure using a plating solution and a plating apparatus. That is, no special plating solution, plating apparatus, and procedure are required.
  • copper, nickel, a noble metal, an alloy, etc. correspond to the plating metal of electroplating, and the thing which laminated
  • a through-hole plating structure in which one end of a through-hole is closed in a flat state in a short time by a commonly used electroplating method.
  • FIG. 1 shows an insulating substrate 1 in which a through hole 2 is formed, and shows a state before an electroplating layer is formed. That is, the block-like insulating substrate 1 is obtained by injection-molding an aromatic liquid crystal polyester, and the through hole 2 is also injection-molded at the same time.
  • One end portion of the through hole 2, that is, the upper end portion in FIG. 1, is formed in a conical space 21, and the tip portion of the conical space penetrates the surface of the insulating base 1 to provide this insulating property.
  • a circular opening 22 is opened on the surface of the substrate.
  • a portion 11 of the surface of the insulating substrate 1 where the through hole 2 opens is formed on a flat surface.
  • a cylindrical space 23 is formed in communication with the bottom surface of the conical space 21 of the through hole 2.
  • the apex angle B of the conical space 21 of the through hole 2 is 90 degrees. Therefore, in the cross-sectional shape including the axis of the through hole 2 shown in FIG. 1, the inner inclined surface 24 of the conical space 21 of the through hole and the portion 11 on the surface of the insulating substrate 1 where the through hole 2 opens. Is an acute angle of 45 degrees.
  • the opening diameter B of the opening 22 of the through hole 2 is 40 ⁇ m.
  • FIG. 2 shows conductive layers 3, 4, and 4 on the inner surface of the through hole 2, the surface 11 of the insulating substrate 1, the back surface 13 of the insulating substrate, and the side surface 14 of the insulating substrate, respectively.
  • the case where 5 and 6 are provided is shown.
  • the conductive layer 4 provided on the inner surface of the through hole 2 is connected to the conductive layer 3 provided on the surface 11 of the insulating substrate and the conductive layer 5 provided on the back surface 13 of the insulating substrate. .
  • the conductive layer 5 provided on the back surface 13 of the rim base 1 and the conductive layer 6 provided on the side surface 14 are connected to each other.
  • Each of the conductive layers 3 to 6 is obtained by laminating electrolytic copper plating layers 32, 42, 52 and 62 on the surfaces of the electroless copper plating layers 31, 41, 51 and 61.
  • the opening 22 through which the through hole 2 opens on the surface 11 of the insulating substrate 1 is closed by the electroplating layer 32 so that the surface becomes flat.
  • the entire surface of the insulating substrate 1 and the inner surface of the through hole 2 are roughened. This is because the anchor effect improves the adhesion of electroless plating in the subsequent process and imparts hydrophilicity.
  • the roughening means known chemical etching can be used.
  • the insulating substrate 1 provided with the through holes 2 is degreased and immersed in an etching solution such as an aqueous solution of caustic potash.
  • the insulating substrate 1 whose surface has been roughened is neutralized by immersing it in an acidic aqueous solution.
  • the catalyst for electroless plating is applied to the entire surface of the insulating substrate and the inner surface of the through-hole 2.
  • a known means can also be used for applying the catalyst.
  • the insulating substrate 1 is immersed in a mixed catalyst solution of tin and palladium, and then activated with an acid such as hydrochloric acid or sulfuric acid to deposit palladium on the surface.
  • a relatively strong reducing agent such as stannous chloride is adsorbed on the surface and immersed in a catalyst solution containing noble metal ions such as gold to deposit gold on the surface.
  • the surface of the insulating substrate 1 provided with the catalyst is dried in preparation for the irradiation of the laser beam for dry processing in a subsequent step, and the catalyst is fixed on the surface of the insulating substrate.
  • an electroless copper plating layer is formed on the entire surface of the insulating substrate 1 on which the catalyst is fixed and on the inner surface of the through hole 2. This is because a conductive underlayer is formed as an electrode for electroplating in a subsequent process. Therefore, about 0.6 ⁇ m is sufficient for the thickness of the electroless copper plating layer.
  • a well-known means can be used also for formation of an electroless copper plating layer. For example, in the case of electroless copper plating, 5-15 g / liter of copper sulfate as a metal salt, 8-12 ml / liter of a 37% by volume solution of formalin as a reducing agent, and Rochelle as a complexing material A solution with a temperature of 20 ° C. mixed with 20 to 25 g / l of salt and 5 to 12 g / l of sodium hydroxide as alkaline agent is used. Electroless nickel plating can be performed instead of electroless copper plating.
  • the electroless copper plating layer formed on the entire surface of the insulating substrate 1 is laminated with an electroplating layer in a later process, so that a laser is formed along the contour of a portion where a conductive circuit, a connection terminal, and the like are formed.
  • Light is irradiated to remove the electroless plating layer on the contour.
  • this laser beam for example, a YAG laser having an output of 0.5 W is used.
  • the contour of the laser light irradiation is the surface 11 of the insulating substrate 1 where the opening 22 of the through hole 2 is opened, that is, the periphery surrounding the opening 22, and the insulating substrate. 1 includes the outline of a portion 13 where the lower end of the through hole is opened, that is, the periphery surrounding the opening, and the side surface of the insulating base and forming a conductive circuit, a connection terminal, and the like. It is.
  • the electroless plating layers 31, 41, 51 and 61 inside the contour are outside the contour. It becomes electrically insulated from the electroless plating layer. Therefore, only the electroless plating layers 31, 41, 51 and 61 inside the contour are energized, and the electrolytic copper plating layers 32, 42, 52 and 62 are laminated on the surface of the electroless plating layer inside the contour. .
  • the thickness of these electrolytic copper plating layers 32 etc. shall be 30 micrometers.
  • the formation of the electrolytic copper plating layer can be performed by a commonly used general means.
  • the bath composition is, for example, CuSO 4 .5H 2 O (75 g) / lH 2 SO 4 (190 g) / lCl (60 ppm) / additive (appropriate amount).
  • the anode material is phosphorous copper
  • the bath temperature is set to 25 ° C.
  • the cathode current density is 2.5 A / dm 2.
  • the anode electrode may be a flat plate placed at a position 20 to 30 Cm away from the surface of the insulating substrate 1.
  • the opening 22 of the through hole 2 can be closed in a short state with a flat surface without using a special plating accelerator or inhibitor, or an electrode having a special structure. . That is, the tip portion of the through hole 2 is formed in a conical shape 21, and the lower end of the conical shape is formed in a cylindrical shape and has a large cross-sectional area. Therefore, in accordance with the miniaturization of the conductive circuit, the diameter of the opening 22 of the through hole 2 opening on the surface of the insulating substrate 1 is reduced, and the penetration and circulation of the plating solution into the through hole are promoted. Can do.
  • the periphery of the opening 22 of the through hole 2 that opens on the surface of the insulating substrate 1 has an acute angle with a flat upper surface, so that the current density at the periphery increases, and an electrolytic copper plating layer is rapidly formed on the periphery. Is done.
  • the electrolytic copper plating layer is formed by reducing the opening diameter of the opening 22 of the through hole 2 and flattening the surface of the insulating substrate 1 where the through hole is opened. If formed to a thickness of about 30 ⁇ m, the opening 22 of the through hole can be closed so that the surface is flat as shown in FIG. When the opening diameter of the opening 22 of the through hole 2 is 10 to 100 ⁇ m, an electrolytic copper plating layer is formed to a thickness of about 25 to 40 ⁇ m in order to close the surface so as to be flat.
  • the insulating substrate 1 on which the electrolytic copper plating layers 32, 42, 52 and 62 are laminated is immersed in, for example, an aqueous iron chloride solution, and the electroless plating outside the contours where these electrolytic copper plating layers are not laminated.
  • the copper plating layer is dissolved and removed.
  • the surfaces of the electroless copper plating layers 31 to 61 are respectively formed on the surface of the insulating substrate 1, the inner surface of the through hole 2, the back surface of the insulating substrate, and the side surfaces of the insulating substrate.
  • the conductive layers 3 to 6 can be formed by laminating the copper electroplating layers 32 to 62 on the substrate.
  • another printed circuit board can be laminated by superimposing the through hole directly on the through hole 2 on the surface of the insulating substrate 1, or the flat surface of the electrolytic copper plating layer 32 closing the opening 22 of the through hole.
  • Electronic components and the like can be mounted on the surface.
  • the back surface of the insulating substrate 1 has a conductive layer 5 communicating with the conductive layer 4 formed on the inner surface of the through hole 2, another printed circuit board or the like can be laminated on the back surface of the insulating substrate. .
  • one end of the through hole can be closed with a flat surface in a short time by a commonly used electroplating method, it can be widely used in industries related to electronic devices such as multilayer printed boards.
  • Electroless copper plating layer (electroless plating layer) 32 Copper electroplating layer (electroplating layer) 4 Conductive layer 41 Electroless copper plating layer (electroless plating layer) 42 Electro copper plating layer (electro plating layer) 5 Conductive layer 51 Electroless copper plating layer (electroless plating layer) 52 Electro copper plating layer (electro plating layer) 6 Conductive layer 61 Electroless copper plating layer (electroless plating layer) 62 Copper electroplating layer (electroplating layer)

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Selon la présente invention, un substrat isolant (1) présentant un trou traversant (2) est moulé par injection. La partie supérieure du trou traversant (2) prend la forme d'un espace conique (21), et la partie inférieure prend la forme d'un espace cylindrique (23). L'angle au sommet de la forme conique vaut de 60 à 120 degrés, et le diamètre d'ouverture dans l'extrémité supérieure du trou traversant (2) vaut de 10 à 100 µm. Sur les surfaces avant et arrière du substrat isolant (1) et sur les surfaces intérieures du trou traversant, des couches de cuivrage électrolytique (32 à 52) sont empilées respectivement sur des couches de dépôt autocatalytique (31 à 51), formant ainsi des couches électroconductrices (3 à 6). Le bord périphérique d'une ouverture (22) dans l'extrémité supérieure du trou traversant (2) présente une densité de courant électrique élevée en raison d'un angle aigu, et une solution de cuivrage électrolytique entre et circule facilement depuis l'extrémité inférieure du trou traversant. En conséquence, une couche de cuivrage électrolytique peut être formée rapidement sur le bord périphérique de ladite ouverture, et l'extrémité supérieure du trou traversant peut être refermée sur le dessus en peu de temps, pour ainsi rendre la surface plane.
PCT/JP2012/060906 2012-04-24 2012-04-24 Structure plaquée de trou traversant WO2013160994A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014512051A JP5753628B2 (ja) 2012-04-24 2012-04-24 スルーホールのめっき構造
PCT/JP2012/060906 WO2013160994A1 (fr) 2012-04-24 2012-04-24 Structure plaquée de trou traversant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/060906 WO2013160994A1 (fr) 2012-04-24 2012-04-24 Structure plaquée de trou traversant

Publications (1)

Publication Number Publication Date
WO2013160994A1 true WO2013160994A1 (fr) 2013-10-31

Family

ID=49482365

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/060906 WO2013160994A1 (fr) 2012-04-24 2012-04-24 Structure plaquée de trou traversant

Country Status (2)

Country Link
JP (1) JP5753628B2 (fr)
WO (1) WO2013160994A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017033998A (ja) * 2015-07-29 2017-02-09 ローム株式会社 半導体装置およびその製造方法
US20210269357A1 (en) * 2017-05-25 2021-09-02 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53100468A (en) * 1977-02-14 1978-09-01 Tokyo Shibaura Electric Co Method of producing circuit board
JPH01135092A (ja) * 1987-11-20 1989-05-26 Nec Corp 印刷配線板の製造方法
JPH02133988A (ja) * 1988-11-15 1990-05-23 Shindo Denshi Kogyo Kk 両面プラスチックフィルム回路基板のスルーホール形成方法
JPH04250695A (ja) * 1991-01-28 1992-09-07 Matsushita Electric Works Ltd 多層回路板のバイアホール加工方法
JP2001007468A (ja) * 1999-06-24 2001-01-12 Nec Kansai Ltd 配線基板，多層配線基板およびその製造方法
JP2001135750A (ja) * 1999-11-01 2001-05-18 Nippon Circuit Kogyo Kk 半導体パッケージ用基板の製造方法
JP2006313790A (ja) * 2005-05-06 2006-11-16 Matsushita Electric Works Ltd 基板のスルーホール構造
JP2006332582A (ja) * 2005-04-28 2006-12-07 Matsushita Electric Works Ltd スルーホール構造、及びマイクロリレー、並びに加速度センサ
JP2010532562A (ja) * 2007-07-05 2010-10-07 オー・アー・セー・マイクロテック・アクチボラゲット 低抵抗のウエハ貫通ビア

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004095690A (ja) * 2002-08-29 2004-03-25 Kyocera Corp セラミック基板の製造方法
JP3894213B2 (ja) * 2004-12-24 2007-03-14 株式会社デンソー スルーホール両面基板の製造方法
JP2009295850A (ja) * 2008-06-06 2009-12-17 Hitachi Chem Co Ltd 多層回路基板の製造方法及びこれから得られる多層回路基板、半導体チップ搭載基板並びにこの基板を用いた半導体パッケージ

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53100468A (en) * 1977-02-14 1978-09-01 Tokyo Shibaura Electric Co Method of producing circuit board
JPH01135092A (ja) * 1987-11-20 1989-05-26 Nec Corp 印刷配線板の製造方法
JPH02133988A (ja) * 1988-11-15 1990-05-23 Shindo Denshi Kogyo Kk 両面プラスチックフィルム回路基板のスルーホール形成方法
JPH04250695A (ja) * 1991-01-28 1992-09-07 Matsushita Electric Works Ltd 多層回路板のバイアホール加工方法
JP2001007468A (ja) * 1999-06-24 2001-01-12 Nec Kansai Ltd 配線基板，多層配線基板およびその製造方法
JP2001135750A (ja) * 1999-11-01 2001-05-18 Nippon Circuit Kogyo Kk 半導体パッケージ用基板の製造方法
JP2006332582A (ja) * 2005-04-28 2006-12-07 Matsushita Electric Works Ltd スルーホール構造、及びマイクロリレー、並びに加速度センサ
JP2006313790A (ja) * 2005-05-06 2006-11-16 Matsushita Electric Works Ltd 基板のスルーホール構造
JP2010532562A (ja) * 2007-07-05 2010-10-07 オー・アー・セー・マイクロテック・アクチボラゲット 低抵抗のウエハ貫通ビア

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017033998A (ja) * 2015-07-29 2017-02-09 ローム株式会社 半導体装置およびその製造方法
US20210269357A1 (en) * 2017-05-25 2021-09-02 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US11972993B2 (en) * 2017-05-25 2024-04-30 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same

Also Published As

Publication number Publication date
JP5753628B2 (ja) 2015-07-22
JPWO2013160994A1 (ja) 2015-12-21

Similar Documents

Publication Publication Date Title
JP4996653B2 (ja) 成形回路部品の製造方法
WO2011062037A1 (fr) Carte à circuit imprimé et son procédé de fabrication
KR101553499B1 (ko) 회로 기판, 도전막 형성 방법 및 밀착 향상제
WO2020219354A1 (fr) Condensateur multicouche ayant une configuration d'électrode en mode ouvert et des terminaisons flexibles
CN202610367U (zh) 超声波振动电镀装置
EP3284849A1 (fr) Élément de contact électrique multicouche
JP5753628B2 (ja) スルーホールのめっき構造
CN111508924A (zh) 部件承载件的通孔中的悬伸部补偿式环形镀层
TWM600477U (zh) 具有用額外鍍覆結構和橋結構填充的通孔的部件承載件
JP5628496B2 (ja) 三次元成形回路部品の製造方法
JP6696988B2 (ja) プリント配線板及び電子部品
JP5302810B2 (ja) 三次元成形回路部品の製造方法
JPH1143797A (ja) ビアフィリング方法
JP4875595B2 (ja) 導電回路を有する合成樹脂製のばね
JP2019121740A (ja) プリント配線板製造方法
JP2014138033A (ja) フレキシブルプリント配線板及びその製造方法
JP5426325B2 (ja) 成形回路部品
JP5102643B2 (ja) 導電回路を有する合成樹脂製のばね
JPH118469A (ja) ビアフィリング方法
WO2021049624A1 (fr) Composant de circuit moulé et dispositif électronique
JP4803420B2 (ja) 射出成形回路部品とその製造方法
KR100911204B1 (ko) 빌드업 고집적 회로기판의 제조방법
JP4989666B2 (ja) 成形回路部品の製造方法
JP4328195B2 (ja) 配線基板及びその製造方法並びに電気装置
JP2009062609A (ja) 成形回路部品の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12875451

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014512051

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12875451

Country of ref document: EP

Kind code of ref document: A1