WO2013157206A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
WO2013157206A1
WO2013157206A1 PCT/JP2013/002240 JP2013002240W WO2013157206A1 WO 2013157206 A1 WO2013157206 A1 WO 2013157206A1 JP 2013002240 W JP2013002240 W JP 2013002240W WO 2013157206 A1 WO2013157206 A1 WO 2013157206A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
well
ground
conductivity type
semiconductor integrated
Prior art date
Application number
PCT/JP2013/002240
Other languages
French (fr)
Japanese (ja)
Inventor
靖之 石川
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Publication of WO2013157206A1 publication Critical patent/WO2013157206A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Definitions

  • the present disclosure relates to a semiconductor integrated circuit in which an internal circuit composed of a plurality of transistors and a clock generation circuit are formed on the same semiconductor substrate.
  • a clock signal output circuit that generates and outputs a multiplied clock signal obtained by multiplying the frequency of a reference clock signal by a digital PLL operation, and the multiplied clock signal is supplied to operate.
  • an integrated circuit device having an internal circuit and an internal power supply generation circuit that generates an internal power supply and supplies the clock signal output circuit and the internal circuit.
  • the clock signal processing circuit described above includes a ring oscillator that generates a reference clock signal.
  • the ring oscillator is formed by connecting a plurality of delay gates (for example, NOT gates) in a ring shape.
  • the NOT gate has a property that the gate delay time changes according to the supplied power supply voltage. Therefore, when the power supply voltage fluctuates or the ground potential fluctuates, the frequency of the reference clock signal may fluctuate (clock jitter may occur).
  • the NOT gate is composed of a plurality of MOSFETs.
  • a MOSFET for example, a first well of a first conductivity type formed in a first conductivity type semiconductor substrate, two second wells of a second conductivity type formed in the first well, and A configuration having a third well of the first conductivity type is employed.
  • the two second wells correspond to the source and drain of the MOSFET, and the third well corresponds to a back gate for applying a reverse bias to the PN junction formed between the first well and the second well.
  • the first wiring connected to the source and the second wiring connected to the back gate are electrically connected to each other through the common wiring, and the common wiring is connected to the ground wiring.
  • the fluctuation current caused by the change in the consumption current of the internal circuit flows into the source through the semiconductor substrate, the first well, the third well, the second wiring, and the first wiring, and the source potential (ground potential) fluctuates. There is a risk of doing.
  • the source potential fluctuates, the above-described clock jitter may occur.
  • An object of the present disclosure is to provide a semiconductor integrated circuit in which generation of clock jitter is suppressed.
  • an internal circuit including a plurality of transistors and a clock generation circuit are formed on the same semiconductor substrate.
  • the clock generation circuit includes a ring oscillator and outputs a clock signal based on a signal output from the ring oscillator.
  • the semiconductor substrate is of a first conductivity type.
  • the transistor includes a first well of a first conductivity type formed in the semiconductor substrate, a second well of a second conductivity type different from the first conductivity type, and the first well formed in the first well. A third well of conductivity type. Two of the second wells formed in one of the first wells function as a terminal of the transistor.
  • a first wiring is connected to one of the two second wells, and a second wiring is connected to the third well.
  • the first wiring and the second wiring are each independently connected to a ground member connected to the ground.
  • the potential of the second well is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator due to the fluctuating current is suppressed.
  • FIG. 1 is a top view showing a schematic configuration of the semiconductor integrated circuit according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing the main part of the semiconductor integrated circuit.
  • FIG. 3 is a circuit diagram showing a schematic configuration of the ring oscillator.
  • FIG. 4 is a cross-sectional view showing a modification of the semiconductor integrated circuit.
  • FIG. 5 is a cross-sectional view showing a modification of the semiconductor integrated circuit.
  • the semiconductor integrated circuit 100 includes a semiconductor substrate 10, an internal circuit 30, a clock generation circuit 50, a capacitor 70, and an external terminal 90 as main parts.
  • the internal circuit 30 operates based on the clock signal output from the clock generation circuit 50, and the capacitor 70 functions to remove noise included in the signal input to the clock generation circuit 50.
  • Each of the internal circuit 30, the clock generation circuit 50, and the capacitor 70 is connected to the power supply terminal 91 and the ground terminal 92 of the external terminal 90.
  • the ground terminal 92 corresponds to a ground member.
  • each of the internal circuit 30, the clock generation circuit 50, and the capacitor 70 includes a plurality of transistors formed on the semiconductor substrate 10.
  • the semiconductor substrate 10 according to the present embodiment is a P-channel type, and each of the internal circuit 30 and the clock generation circuit 50 is mainly configured by an N-channel type MOSFET 11, and the capacitor 70 is configured by a P-channel type MOSFET 12. Yes.
  • the N-channel MOSFET 11 includes a P-type first well 13 formed in the surface layer of the semiconductor substrate 10, two N-type second wells 14 and 15 formed in the first well 13, and a P-type third well.
  • a well 16 and a first gate electrode 17 provided on the first well 13 between the second wells 14 and 15 are provided.
  • the second well 14 corresponds to a drain terminal
  • the second well 15 corresponds to a source terminal
  • the third well 16 corresponds to a back gate terminal.
  • the second well 14 is referred to as a drain terminal 14
  • the second well 15 is referred to as a source terminal
  • the third well 16 is referred to as a back gate terminal 16.
  • the P-channel MOSFET 12 includes an N-type fourth well 18 formed in the surface layer of the semiconductor substrate 10, two P-type fifth wells 19 and 20 formed in the fourth well 18, and an N-type sixth well 18.
  • a well 21 and a second gate electrode 22 provided on the fourth well 18 between the fifth wells 19 and 20 are provided.
  • the fifth well 19 corresponds to a drain terminal
  • the fifth well 20 corresponds to a source terminal
  • the sixth well 21 corresponds to a back gate terminal.
  • the fifth well 19 is referred to as a drain terminal 19
  • the fifth well 20 is referred to as a source terminal
  • the sixth well 21 is referred to as a back gate terminal 21.
  • the drain terminal 14 is electrically connected to the power supply terminal 91, and the source terminal 15 and the back gate terminal 16 are electrically connected to the ground terminal 92. . More specifically, the drain terminal 14 is connected to the power supply terminal 91 via a P-channel MOSFET (not shown) that constitutes a CMOS together with the N-channel MOSFET 11, and is connected to the source terminal 15 as shown in FIG.
  • the wiring connected to the back gate terminal 16 is connected to one end of the third wiring 95, and the other end of the third wiring 95 is connected to the ground terminal 92.
  • the drain terminal 14 is electrically connected to the power supply terminal 91, and the source terminal 15 and the back gate terminal 16 are electrically connected independently to the ground terminal 92. ing. More specifically, the drain terminal 14 is connected to the power supply terminal 91 via a P-channel MOSFET (not shown) that constitutes a CMOS together with the N-channel MOSFET 11, and is connected to the source terminal 15 as shown in FIG.
  • the first wiring 93 and the second wiring 94 connected to the back gate terminal 16 are electrically connected independently to the ground terminal 92.
  • Each of the wirings 93 and 94 is electrically connected to the ground terminal 92 independently of the third wiring 95.
  • the drain terminal 19 the source terminal 20, and the back gate terminal 21 are electrically connected to each other and connected to the power supply wiring (96).
  • the second gate electrode 22 is connected to the wirings 93 and 94.
  • the clock generation circuit 50 has a ring oscillator 51 shown in FIG.
  • the clock generation circuit 50 functions to output a clock signal based on the reference clock signal output from the ring oscillator 51 to the internal circuit 30. More specifically, the clock generation circuit 50 outputs to the internal circuit 30 a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by a digital PLL (Phase Locked Loop) operation based on the reference clock signal of the ring oscillator 51. Fulfills the function.
  • PLL Phase Locked Loop
  • the ring oscillator 51 is formed by connecting a plurality of logic gates (NAND gate 52, NOT gate 53) in a ring shape, and each of the logic gates 52, 53 is configured by an N-channel MOSFET 11 or the like. Since the NOT gate 53 has the property that the gate delay time changes according to the supplied voltage, the reference clock signal to be output when the power supply voltage changes or the ground potential (the potential of the source terminal 15) changes. May fluctuate (clock jitter may occur). Since the ring oscillator 51 shown in FIG. 3 is well known as shown in Japanese Patent No. 4576862, a detailed description is omitted in this embodiment.
  • the first wiring 93 connected to the source terminal 15 and the second wiring 94 connected to the back gate terminal 16 are electrically connected to the ground terminal 92 independently.
  • the first wiring and the second wiring are caused by the change in the consumption current of the internal circuit 30.
  • the fluctuating current (broken arrow shown in FIG. 2) flows into the clock generation circuit 50 via the semiconductor substrate 10, it passes to the ground terminal 92 (ground) via the back gate terminal 16 and the second wiring 94. Since it flows, it is difficult to flow through the first wiring 93. Therefore, the potential of the source terminal 15 is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator 51 due to the fluctuating current is suppressed.
  • the first wiring 93 and the second wiring 94 are electrically connected to the ground terminal 92 independently. According to this, unlike the configuration in which the ground wiring is connected to the ground terminal and the first wiring and the second wiring are connected to the ground wiring, the fluctuation current is supplied to the clock generation circuit 50 via the semiconductor substrate 10. Even if it flows in, the voltage generated by the voltage drop of the resistance of the ground wiring is suppressed from being applied to the first wiring 93 (source terminal 15). Therefore, the potential of the source terminal 15 is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator 51 due to the fluctuating current is suppressed.
  • the structure which forms the 1st well 13 in a larger well of an N channel type is also considered.
  • the configuration shown in the present embodiment is desirable as a configuration for suppressing the above-described variation in the potential of the source terminal 15 due to the variation current.
  • the source terminal 15 of the N-channel MOSFET 11 constituting the internal circuit 30 is connected to the ground terminal 92 via the third wiring 95.
  • the clock generation circuit 50 is controlled by increasing or decreasing the fluctuation current flowing through the ground wiring. Fluctuations in the potential of the source terminal 15 of the N-channel MOSFET 11 to be configured are suppressed. Therefore, the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed.
  • the capacitor 70 includes an N-type fourth well 18 formed in the surface layer of the semiconductor substrate 10, two P-type fifth wells 19 and 20, and an N-type sixth well 21 formed in the fourth well 18. And a P-channel type MOSFET 12 having a second gate electrode 22 provided on the fourth well 18 between the fifth wells 19 and 20.
  • a PN junction is formed between the semiconductor substrate 10 and the fourth well 18, so that the fluctuation current hardly flows to the fourth well 18.
  • the fluctuation current is suppressed from flowing to the clock generation circuit 50 via the capacitor 70, and the fluctuation of the potential of the first wiring 93 (source terminal 15) is suppressed.
  • the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed.
  • the semiconductor substrate 10 is a P-channel type.
  • the semiconductor substrate 10 can adopt an N-channel type configuration.
  • the conductivity types of the wells 13 to 16 and 18 to 21 are inverted, the main elements 30 and 50 are each composed mainly of a P-channel MOSFET, and the capacitor 70 is composed of an N-channel MOSFET.
  • each of the wirings 93 and 94 is connected to one ground terminal 92 in common.
  • a configuration in which the first wiring 93 is connected to the ground terminal 92a and the second wiring 94 is connected to the ground terminal 92b may be employed.
  • the wirings 93 and 94 are electrically connected to the ground terminal 92 .
  • a configuration in which the wirings 93 and 94 are connected to the ground wiring 98 connected to the ground terminal 92 may be employed.
  • the fluctuation current is generated via the semiconductor substrate 10 and the clock generation circuit. Even if it flows into the voltage 50, the voltage generated by the voltage drop of the resistance of the common wiring is suppressed from being applied to the first wiring 93 (source terminal 15).
  • the ground wiring 98 and the ground terminal 92 constitute the ground member described in the claims.
  • the second gate electrode 22 is connected to the wirings 93 and 94 via the ground wiring 98.
  • a configuration in which the resistance of the second wiring 94 is larger than the resistance of the first wiring 93 is preferable. This makes it difficult for the variable current to flow through the second wiring 94 as compared with the configuration in which the resistance of the second wiring is the same as the resistance of the first wiring. Therefore, the voltage generated by the voltage drop of the resistance is reduced by the resistance of the ground wiring 98, and the potential of the first wiring 93 (source terminal 15) is hardly changed. As a result, the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed.
  • a resistance element may be arranged in the second wiring 94.

Abstract

In this semiconductor integrated circuit, a clock generating circuit (50) and an internal circuit (30) comprising a transistor (11) are formed on a semiconductor substrate (10) of a first conductivity type. The clock generating circuit (50) has a ring oscillator (51). The transistor (11) has a first well (13) of a first conductivity type, and, formed in the first well (13), second wells (14, 15) of a second conductivity type and a third well (16) of the first conductivity type. A first interconnect (93) connected to the second well (16), and a second interconnect (94) connected to the third well (16), in the transistor (11) constituting the clock generating circuit (50) are respectively connected independently to ground members (92, 98).

Description

半導体集積回路Semiconductor integrated circuit 関連出願の相互参照Cross-reference of related applications
　本開示は、２０１２年４月１７日に出願された日本出願番号２０１２－９４０４３号に基づくもので、ここにその記載内容を援用する。 This disclosure is based on Japanese Patent Application No. 2012-94043 filed on April 17, 2012, the contents of which are incorporated herein by reference.
　本開示は、複数のトランジスタから成る内部回路及びクロック生成回路が、同一の半導体基板に形成された半導体集積回路に関するものである。 The present disclosure relates to a semiconductor integrated circuit in which an internal circuit composed of a plurality of transistors and a clock generation circuit are formed on the same semiconductor substrate.
　従来、例えば特許文献１に示されるように、基準クロック信号の周波数をデジタル的なＰＬＬ動作により逓倍した逓倍クロック信号を生成して出力するクロック信号出力回路と、逓倍クロック信号が供給されて動作する内部回路と、内部電源を生成し、クロック信号出力回路及び内部回路に供給する内部電源生成回路と、を有する集積回路装置が提案されている。上記したクロック信号処理回路は、基準クロック信号を生成するリングオシレータを備えている。 Conventionally, for example, as shown in Patent Document 1, a clock signal output circuit that generates and outputs a multiplied clock signal obtained by multiplying the frequency of a reference clock signal by a digital PLL operation, and the multiplied clock signal is supplied to operate. There has been proposed an integrated circuit device having an internal circuit and an internal power supply generation circuit that generates an internal power supply and supplies the clock signal output circuit and the internal circuit. The clock signal processing circuit described above includes a ring oscillator that generates a reference clock signal.
特許第４５７６８６２号公報Japanese Patent No. 4576862
　ところで、特許文献１に示される集積回路装置では、クロック信号出力回路と内部回路が同一の半導体基板に形成されている。そのため、内部回路にて消費電流が変化すると、その変化に起因する変動電流が、半導体基板を介して、クロック信号出力回路のリングオシレータに流れ込む虞がある。 By the way, in the integrated circuit device disclosed in Patent Document 1, the clock signal output circuit and the internal circuit are formed on the same semiconductor substrate. For this reason, when the consumption current changes in the internal circuit, there is a possibility that the fluctuation current resulting from the change flows into the ring oscillator of the clock signal output circuit via the semiconductor substrate.
　リングオシレータは、複数個の遅延ゲート（例えばＮＯＴゲート）がリング状に接続されて成るものである。ＮＯＴゲートは、供給される電源電圧に応じてゲート遅延時間が変化する性質を有する。そのため、電源電圧が変動したり、グランド電位が変動したりすると、基準クロック信号の周波数も変動する（クロックジッタが発生する）虞がある。 The ring oscillator is formed by connecting a plurality of delay gates (for example, NOT gates) in a ring shape. The NOT gate has a property that the gate delay time changes according to the supplied power supply voltage. Therefore, when the power supply voltage fluctuates or the ground potential fluctuates, the frequency of the reference clock signal may fluctuate (clock jitter may occur).
　通常、ＮＯＴゲートは、複数個のＭＯＳＦＥＴから構成される。このようなＭＯＳＦＥＴとしては、例えば、第１導電型の半導体基板に形成された第１導電型の第１ウェルと、前記第１ウェルに形成された、第２導電型の２つの第２ウェル及び第１導電型の第３ウェルと、を有する構成が採用される。２つの第２ウェルがＭＯＳＦＥＴのソースとドレインとに相当し、第３ウェルは、第１ウェルと第２ウェルとの間に形成されるＰＮ接合に逆バイアスを印加するためのバックゲートに相当する。このようなＭＯＳＦＥＴにおいて、ソースに接続された第１配線とバックゲートに接続された第２配線とが共通配線を介して互いに電気的に接続され、共通配線がグランド配線に接続された構成の場合、内部回路の消費電流変化に起因する変動電流が、半導体基板、第１ウェル、第３ウェル、第２配線、及び、第１配線を介してソースに流れ込み、ソースの電位（グランド電位）が変動する虞がある。ソースの電位が変動すると、上記したクロックジッタが発生する虞がある。 Usually, the NOT gate is composed of a plurality of MOSFETs. As such a MOSFET, for example, a first well of a first conductivity type formed in a first conductivity type semiconductor substrate, two second wells of a second conductivity type formed in the first well, and A configuration having a third well of the first conductivity type is employed. The two second wells correspond to the source and drain of the MOSFET, and the third well corresponds to a back gate for applying a reverse bias to the PN junction formed between the first well and the second well. . In such a MOSFET, the first wiring connected to the source and the second wiring connected to the back gate are electrically connected to each other through the common wiring, and the common wiring is connected to the ground wiring. The fluctuation current caused by the change in the consumption current of the internal circuit flows into the source through the semiconductor substrate, the first well, the third well, the second wiring, and the first wiring, and the source potential (ground potential) fluctuates. There is a risk of doing. When the source potential fluctuates, the above-described clock jitter may occur.
　本開示は、クロックジッタの発生が抑制された半導体集積回路を提供することを目的とする。 An object of the present disclosure is to provide a semiconductor integrated circuit in which generation of clock jitter is suppressed.
　本開示の一態様に係る半導体集積回路は、複数のトランジスタから成る内部回路及びクロック生成回路が、同一の半導体基板に形成されている。前記クロック生成回路は、リングオシレータを有し、前記リングオシレータから出力される信号に基づいたクロック信号を出力する。前記半導体基板は、第１導電型である。前記トランジスタは、前記半導体基板に形成された第１導電型の第１ウェルと、前記第１ウェルに形成された、前記第１導電型とは異なる第２導電型の第２ウェル及び前記第１導電型の第３ウェルと、を有する。１つの前記第１ウェルに形成された２つの前記第２ウェルが、前記トランジスタの端子として機能する。前記クロック生成回路を構成する前記トランジスタにおいて、２つの前記第２ウェルの内の一方に第１配線が接続され、前記第３ウェルに第２配線が接続される。前記第１配線と前記第２配線とがそれぞれ独立して、グランドに接続されるグランド部材に接続されている。 In a semiconductor integrated circuit according to one embodiment of the present disclosure, an internal circuit including a plurality of transistors and a clock generation circuit are formed on the same semiconductor substrate. The clock generation circuit includes a ring oscillator and outputs a clock signal based on a signal output from the ring oscillator. The semiconductor substrate is of a first conductivity type. The transistor includes a first well of a first conductivity type formed in the semiconductor substrate, a second well of a second conductivity type different from the first conductivity type, and the first well formed in the first well. A third well of conductivity type. Two of the second wells formed in one of the first wells function as a terminal of the transistor. In the transistor constituting the clock generation circuit, a first wiring is connected to one of the two second wells, and a second wiring is connected to the third well. The first wiring and the second wiring are each independently connected to a ground member connected to the ground.
　前記半導体集積回路によれば、前記第２ウェルの電位が変動し難く、変動電流によるリングオシレータのクロックジッタの発生が抑制される。 According to the semiconductor integrated circuit, the potential of the second well is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator due to the fluctuating current is suppressed.
　本開示における上記あるいは他の目的、構成、利点は、下記の図面を参照しながら、以下の詳細説明から、より明白となる。図面において、
図１は、第１実施形態に係る半導体集積回路の概略構成を示す上面図である。 図２は、半導体集積回路の要部を示す断面図である。 図３は、リングオシレータの概略構成を示す回路図である。 図４は、半導体集積回路の変形例を示す断面図である。 図５は、半導体集積回路の変形例を示す断面図である。 The above and other objects, configurations, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the following drawings. In the drawing
FIG. 1 is a top view showing a schematic configuration of the semiconductor integrated circuit according to the first embodiment. FIG. 2 is a cross-sectional view showing the main part of the semiconductor integrated circuit. FIG. 3 is a circuit diagram showing a schematic configuration of the ring oscillator. FIG. 4 is a cross-sectional view showing a modification of the semiconductor integrated circuit. FIG. 5 is a cross-sectional view showing a modification of the semiconductor integrated circuit.
（第１実施形態）
　図１～図３に基づいて、本実施形態に係る半導体集積回路を説明する。図１に示すように、半導体集積回路１００は、要部として、半導体基板１０と、内部回路３０と、クロック生成回路５０と、コンデンサ７０と、外部端子９０と、を有する。内部回路３０はクロック生成回路５０から出力されるクロック信号に基づいて動作し、コンデンサ７０は、クロック生成回路５０に入力される信号に含まれるノイズを除去する機能を果たす。内部回路３０と、クロック生成回路５０と、コンデンサ７０のそれぞれは、外部端子９０の電源端子９１とグランド端子９２に接続されている。グランド端子９２は、グランド部材に相当する。 (First embodiment)
The semiconductor integrated circuit according to the present embodiment will be described with reference to FIGS. As shown in FIG. 1, the semiconductor integrated circuit 100 includes a semiconductor substrate 10, an internal circuit 30, a clock generation circuit 50, a capacitor 70, and an external terminal 90 as main parts. The internal circuit 30 operates based on the clock signal output from the clock generation circuit 50, and the capacitor 70 functions to remove noise included in the signal input to the clock generation circuit 50. Each of the internal circuit 30, the clock generation circuit 50, and the capacitor 70 is connected to the power supply terminal 91 and the ground terminal 92 of the external terminal 90. The ground terminal 92 corresponds to a ground member.
　図２に示すように、内部回路３０と、クロック生成回路５０と、コンデンサ７０のそれぞれは、半導体基板１０に形成された複数のトランジスタから成る。本実施形態に係る半導体基板１０は、Ｐチャネル型であり、内部回路３０と、クロック生成回路５０のそれぞれは、主としてＮチャネル型ＭＯＳＦＥＴ１１によって構成され、コンデンサ７０は、Ｐチャネル型ＭＯＳＦＥＴ１２によって構成されている。 As shown in FIG. 2, each of the internal circuit 30, the clock generation circuit 50, and the capacitor 70 includes a plurality of transistors formed on the semiconductor substrate 10. The semiconductor substrate 10 according to the present embodiment is a P-channel type, and each of the internal circuit 30 and the clock generation circuit 50 is mainly configured by an N-channel type MOSFET 11, and the capacitor 70 is configured by a P-channel type MOSFET 12. Yes.
　Ｎチャネル型ＭＯＳＦＥＴ１１は、半導体基板１０の表層に形成されたＰ型の第１ウェル１３と、第１ウェル１３に形成された、Ｎ型の２つの第２ウェル１４，１５及びＰ型の第３ウェル１６と、第２ウェル１４，１５の間の第１ウェル１３上に設けられた第１ゲート電極１７と、を有する。第２ウェル１４がドレイン端子、第２ウェル１５がソース端子、第３ウェル１６がバックゲート端子に相当する。以下においては、説明を明瞭とするために、第２ウェル１４をドレイン端子１４、第２ウェル１５をソース端子１５、第３ウェル１６をバックゲート端子１６と示す。 The N-channel MOSFET 11 includes a P-type first well 13 formed in the surface layer of the semiconductor substrate 10, two N-type second wells 14 and 15 formed in the first well 13, and a P-type third well. A well 16 and a first gate electrode 17 provided on the first well 13 between the second wells 14 and 15 are provided. The second well 14 corresponds to a drain terminal, the second well 15 corresponds to a source terminal, and the third well 16 corresponds to a back gate terminal. In the following, for clarity of explanation, the second well 14 is referred to as a drain terminal 14, the second well 15 is referred to as a source terminal 15, and the third well 16 is referred to as a back gate terminal 16.
　Ｐチャネル型ＭＯＳＦＥＴ１２は、半導体基板１０の表層に形成されたＮ型の第４ウェル１８と、第４ウェル１８に形成された、Ｐ型の２つの第５ウェル１９，２０及びＮ型の第６ウェル２１と、第５ウェル１９，２０の間の第４ウェル１８上に設けられた第２ゲート電極２２と、を有する。第５ウェル１９がドレイン端子、第５ウェル２０がソース端子、第６ウェル２１がバックゲート端子に相当する。以下においては、説明を明瞭とするために、第５ウェル１９をドレイン端子１９、第５ウェル２０をソース端子２０、第６ウェル２１をバックゲート端子２１と示す。 The P-channel MOSFET 12 includes an N-type fourth well 18 formed in the surface layer of the semiconductor substrate 10, two P-type fifth wells 19 and 20 formed in the fourth well 18, and an N-type sixth well 18. A well 21 and a second gate electrode 22 provided on the fourth well 18 between the fifth wells 19 and 20 are provided. The fifth well 19 corresponds to a drain terminal, the fifth well 20 corresponds to a source terminal, and the sixth well 21 corresponds to a back gate terminal. Hereinafter, for the sake of clarity, the fifth well 19 is referred to as a drain terminal 19, the fifth well 20 is referred to as a source terminal 20, and the sixth well 21 is referred to as a back gate terminal 21.
　内部回路３０を構成するＮチャネル型ＭＯＳＦＥＴ１１では、ドレイン端子１４が電源端子９１に電気的に接続され、ソース端子１５とバックゲート端子１６それぞれが電気的に接続されてグランド端子９２に接続されている。より詳しく言えば、ドレイン端子１４は、Ｎチャネル型ＭＯＳＦＥＴ１１と共にＣＭＯＳを構成するＰチャネル型ＭＯＳＦＥＴ（図示略）を介して電源端子９１に接続され、図２に示すように、ソース端子１５に接続された配線とバックゲート端子１６に接続された配線とが第３配線９５の一端に接続され、第３配線９５の他端がグランド端子９２に接続されている。 In the N-channel MOSFET 11 constituting the internal circuit 30, the drain terminal 14 is electrically connected to the power supply terminal 91, and the source terminal 15 and the back gate terminal 16 are electrically connected to the ground terminal 92. . More specifically, the drain terminal 14 is connected to the power supply terminal 91 via a P-channel MOSFET (not shown) that constitutes a CMOS together with the N-channel MOSFET 11, and is connected to the source terminal 15 as shown in FIG. The wiring connected to the back gate terminal 16 is connected to one end of the third wiring 95, and the other end of the third wiring 95 is connected to the ground terminal 92.
　クロック生成回路５０を構成するＮチャネル型ＭＯＳＦＥＴ１１では、ドレイン端子１４が電源端子９１に電気的に接続され、ソース端子１５とバックゲート端子１６それぞれが電気的に独立して、グランド端子９２に接続されている。より詳しく言えば、ドレイン端子１４は、Ｎチャネル型ＭＯＳＦＥＴ１１と共にＣＭＯＳを構成するＰチャネル型ＭＯＳＦＥＴ（図示略）を介して電源端子９１に接続され、図２に示すように、ソース端子１５に接続された第１配線９３と、バックゲート端子１６に接続された第２配線９４とが、電気的に独立してグランド端子９２に接続されている。なお、配線９３，９４それぞれは、第３配線９５とは電気的に独立してグランド端子９２に接続されている。 In the N-channel MOSFET 11 constituting the clock generation circuit 50, the drain terminal 14 is electrically connected to the power supply terminal 91, and the source terminal 15 and the back gate terminal 16 are electrically connected independently to the ground terminal 92. ing. More specifically, the drain terminal 14 is connected to the power supply terminal 91 via a P-channel MOSFET (not shown) that constitutes a CMOS together with the N-channel MOSFET 11, and is connected to the source terminal 15 as shown in FIG. The first wiring 93 and the second wiring 94 connected to the back gate terminal 16 are electrically connected independently to the ground terminal 92. Each of the wirings 93 and 94 is electrically connected to the ground terminal 92 independently of the third wiring 95.
　コンデンサ７０を構成するＰチャネル型ＭＯＳＦＥＴ１２では、ドレイン端子１９とソース端子２０とバックゲート端子２１とが互いに電気的に接続され、電源配線（９６）に接続されている。また、第２ゲート電極２２が配線９３，９４に接続されている。 In the P-channel MOSFET 12 constituting the capacitor 70, the drain terminal 19, the source terminal 20, and the back gate terminal 21 are electrically connected to each other and connected to the power supply wiring (96). The second gate electrode 22 is connected to the wirings 93 and 94.
　ところで、クロック生成回路５０は、図３に示すリングオシレータ５１を有している。クロック生成回路５０は、リングオシレータ５１から出力される基準クロック信号に基づいたクロック信号を内部回路３０に出力する機能を果たす。より詳しく言えば、クロック生成回路５０は、リングオシレータ５１の基準クロック信号に基づき、基準クロック信号の周波数をデジタル的なＰＬＬ（Ｐｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ）動作により逓倍した逓倍クロック信号を内部回路３０に出力する機能を果たす。 Incidentally, the clock generation circuit 50 has a ring oscillator 51 shown in FIG. The clock generation circuit 50 functions to output a clock signal based on the reference clock signal output from the ring oscillator 51 to the internal circuit 30. More specifically, the clock generation circuit 50 outputs to the internal circuit 30 a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by a digital PLL (Phase Locked Loop) operation based on the reference clock signal of the ring oscillator 51. Fulfills the function.
　リングオシレータ５１は、複数個の論理ゲート（ＮＡＮＤゲート５２、ＮＯＴゲート５３）がリング状に接続されて成り、論理ゲート５２，５３それぞれが、Ｎチャネル型ＭＯＳＦＥＴ１１などによって構成されている。ＮＯＴゲート５３は、供給される電圧に応じてゲート遅延時間が変化する性質を有するため、電源電圧が変動したり、グランド電位（ソース端子１５の電位）が変動したりすると、出力する基準クロック信号の周波数が変動する（クロックジッタが発生する）虞がある。なお、図３に示すリングオシレータ５１は、特許第４５７６８６２号公報に示されるように周知なので、本実施形態では詳細な説明を割愛する。 The ring oscillator 51 is formed by connecting a plurality of logic gates (NAND gate 52, NOT gate 53) in a ring shape, and each of the logic gates 52, 53 is configured by an N-channel MOSFET 11 or the like. Since the NOT gate 53 has the property that the gate delay time changes according to the supplied voltage, the reference clock signal to be output when the power supply voltage changes or the ground potential (the potential of the source terminal 15) changes. May fluctuate (clock jitter may occur). Since the ring oscillator 51 shown in FIG. 3 is well known as shown in Japanese Patent No. 4576862, a detailed description is omitted in this embodiment.
　次に、本実施形態に係る半導体集積回路１００の作用効果を説明する。上記したように、ソース端子１５に接続された第１配線９３と、バックゲート端子１６に接続された第２配線９４とが、電気的に独立してグランド端子９２に接続されている。これによれば、第１配線と第２配線とが共通配線を介して互いに電気的に接続され、共通配線がグランド端子に接続された構成とは異なり、内部回路３０の消費電流変化に起因する変動電流（図２に示す破線矢印）が、半導体基板１０を介して、クロック生成回路５０に流れ込んだとしても、バックゲート端子１６と第２配線９４とを介してグランド端子９２（グランド）へと流れるため、第１配線９３には流れ難い。そのため、ソース端子１５の電位が変動し難く、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。 Next, functions and effects of the semiconductor integrated circuit 100 according to this embodiment will be described. As described above, the first wiring 93 connected to the source terminal 15 and the second wiring 94 connected to the back gate terminal 16 are electrically connected to the ground terminal 92 independently. According to this, unlike the configuration in which the first wiring and the second wiring are electrically connected to each other through the common wiring, and the common wiring is connected to the ground terminal, the first wiring and the second wiring are caused by the change in the consumption current of the internal circuit 30. Even if the fluctuating current (broken arrow shown in FIG. 2) flows into the clock generation circuit 50 via the semiconductor substrate 10, it passes to the ground terminal 92 (ground) via the back gate terminal 16 and the second wiring 94. Since it flows, it is difficult to flow through the first wiring 93. Therefore, the potential of the source terminal 15 is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator 51 due to the fluctuating current is suppressed.
　また、上記したように、第１配線９３と第２配線９４とが電気的に独立してグランド端子９２に接続されている。これによれば、グランド端子にグランド配線が接続され、このグランド配線に第１配線と第２配線とが接続された構成とは異なり、変動電流が、半導体基板１０を介してクロック生成回路５０に流れ込んだとしても、グランド配線の抵抗の電圧降下によって生じる電圧が、第１配線９３（ソース端子１５）に印加されることが抑制される。そのため、ソース端子１５の電位が変動し難く、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。 Further, as described above, the first wiring 93 and the second wiring 94 are electrically connected to the ground terminal 92 independently. According to this, unlike the configuration in which the ground wiring is connected to the ground terminal and the first wiring and the second wiring are connected to the ground wiring, the fluctuation current is supplied to the clock generation circuit 50 via the semiconductor substrate 10. Even if it flows in, the voltage generated by the voltage drop of the resistance of the ground wiring is suppressed from being applied to the first wiring 93 (source terminal 15). Therefore, the potential of the source terminal 15 is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator 51 due to the fluctuating current is suppressed.
　なお、変動電流によるソース端子１５の電位の変動を抑制するために、第１ウェル１３を、Ｎチャネル型のより大きなウェルに形成する構成も考えられる。しかしながら、この構成の場合、トランジスタ１１の形成領域が増大するという問題が生じる。そのため、変動電流による上記したソース端子１５の電位の変動を抑制する構成としては、本実施形態で示した構成が望ましい。 In addition, in order to suppress the fluctuation | variation of the electric potential of the source terminal 15 by fluctuation | variation electric current, the structure which forms the 1st well 13 in a larger well of an N channel type is also considered. However, in this configuration, there is a problem that the formation region of the transistor 11 increases. Therefore, the configuration shown in the present embodiment is desirable as a configuration for suppressing the above-described variation in the potential of the source terminal 15 due to the variation current.
　内部回路３０を構成するＮチャネル型ＭＯＳＦＥＴ１１のソース端子１５が第３配線９５を介してグランド端子９２に接続されている。これによれば、グランド端子にグランド配線が接続され、このグランド配線に第１配線と第３配線とが接続された構成とは異なり、グランド配線を流れる変動電流の増減によって、クロック生成回路５０を構成するＮチャネル型ＭＯＳＦＥＴ１１のソース端子１５の電位が変動することが抑制される。そのため、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。 The source terminal 15 of the N-channel MOSFET 11 constituting the internal circuit 30 is connected to the ground terminal 92 via the third wiring 95. According to this, unlike the configuration in which the ground wiring is connected to the ground terminal, and the first wiring and the third wiring are connected to the ground wiring, the clock generation circuit 50 is controlled by increasing or decreasing the fluctuation current flowing through the ground wiring. Fluctuations in the potential of the source terminal 15 of the N-channel MOSFET 11 to be configured are suppressed. Therefore, the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed.
　コンデンサ７０は、半導体基板１０の表層に形成されたＮ型の第４ウェル１８と、第４ウェル１８に形成された、Ｐ型の２つの第５ウェル１９，２０及びＮ型の第６ウェル２１と、第５ウェル１９，２０の間の第４ウェル１８上に設けられた第２ゲート電極２２と、を有するＰチャネル型ＭＯＳＦＥＴ１２から成る。 The capacitor 70 includes an N-type fourth well 18 formed in the surface layer of the semiconductor substrate 10, two P-type fifth wells 19 and 20, and an N-type sixth well 21 formed in the fourth well 18. And a P-channel type MOSFET 12 having a second gate electrode 22 provided on the fourth well 18 between the fifth wells 19 and 20.
　これによれば、コンデンサがＮチャネル型ＭＯＳＦＥＴから成る構成とは異なり、半導体基板１０と第４ウェル１８との間にＰＮ接合が形成されるので、変動電流が第４ウェル１８に流れ難くなる。これにより、コンデンサ７０を介して、変動電流がクロック生成回路５０に流れることが抑制され、第１配線９３（ソース端子１５）の電位の変動が抑制される。この結果、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。 According to this, unlike the configuration in which the capacitor is formed of an N-channel MOSFET, a PN junction is formed between the semiconductor substrate 10 and the fourth well 18, so that the fluctuation current hardly flows to the fourth well 18. Thereby, the fluctuation current is suppressed from flowing to the clock generation circuit 50 via the capacitor 70, and the fluctuation of the potential of the first wiring 93 (source terminal 15) is suppressed. As a result, the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed.
　以上、本開示の実施形態について説明したが、本開示は上記した実施形態になんら制限されることなく、本開示の主旨を逸脱しない範囲において、種々変形して実施することが可能である。 The embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.
　本実施形態では、半導体基板１０が、Ｐチャネル型である例を示した。しかしながら、半導体基板１０が、Ｎチャネル型の構成を採用することもできる。この場合、ウェル１３～１６、１８～２１それぞれの導電型が反転し、主要素３０，５０それぞれは、主としてＰチャネル型ＭＯＳＦＥＴによって構成され、コンデンサ７０は、Ｎチャネル型ＭＯＳＦＥＴによって構成される。 In the present embodiment, an example in which the semiconductor substrate 10 is a P-channel type is shown. However, the semiconductor substrate 10 can adopt an N-channel type configuration. In this case, the conductivity types of the wells 13 to 16 and 18 to 21 are inverted, the main elements 30 and 50 are each composed mainly of a P-channel MOSFET, and the capacitor 70 is composed of an N-channel MOSFET.
　本実施形態では、図２に示すように、配線９３，９４それぞれが、共通して１つのグランド端子９２に接続された例を示した。しかしながら、図４に示すように、第１配線９３がグランド端子９２ａに接続され、第２配線９４がグランド端子９２ｂに接続された構成を採用することもできる。 In the present embodiment, as shown in FIG. 2, each of the wirings 93 and 94 is connected to one ground terminal 92 in common. However, as shown in FIG. 4, a configuration in which the first wiring 93 is connected to the ground terminal 92a and the second wiring 94 is connected to the ground terminal 92b may be employed.
　本実施形態では、配線９３，９４それぞれが電気的に独立してグランド端子９２に接続された例を示した。しかしながら、図５に示すように、グランド端子９２に接続されたグランド配線９８に、配線９３，９４それぞれが接続された構成を採用することもできる。この場合、第１配線と第２配線とが共通配線を介して互いに電気的に接続され、共通配線がグランド配線に接続された構成とは異なり、変動電流が半導体基板１０を介してクロック生成回路５０に流れ込んだとしても、共通配線の抵抗の電圧降下によって生じる電圧が、第１配線９３（ソース端子１５）に印加されることが抑制される。そのため、ソース端子１５の電位が変動し難く、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。この変形例においては、グランド配線９８と、グランド端子９２とによって、特許請求の範囲に記載のグランド部材が構成される。また、第２ゲート電極２２は、グランド配線９８を介して配線９３，９４に接続されている。 In the present embodiment, an example in which the wirings 93 and 94 are electrically connected to the ground terminal 92 is shown. However, as shown in FIG. 5, a configuration in which the wirings 93 and 94 are connected to the ground wiring 98 connected to the ground terminal 92 may be employed. In this case, unlike the configuration in which the first wiring and the second wiring are electrically connected to each other via the common wiring, and the common wiring is connected to the ground wiring, the fluctuation current is generated via the semiconductor substrate 10 and the clock generation circuit. Even if it flows into the voltage 50, the voltage generated by the voltage drop of the resistance of the common wiring is suppressed from being applied to the first wiring 93 (source terminal 15). Therefore, the potential of the source terminal 15 is unlikely to fluctuate, and the occurrence of clock jitter of the ring oscillator 51 due to the fluctuating current is suppressed. In this modification, the ground wiring 98 and the ground terminal 92 constitute the ground member described in the claims. The second gate electrode 22 is connected to the wirings 93 and 94 via the ground wiring 98.
　なお、上記変形例の場合、第２配線９４の抵抗が、第１配線９３の抵抗よりも大きい構成が好ましい。これによれば、第２配線の抵抗が、第１配線の抵抗と同一である構成と比べて、変動電流が第２配線９４に流れ難くなる。そのため、グランド配線９８の抵抗の分、抵抗の電圧降下によって生じる電圧が低くなり、第１配線９３（ソース端子１５）の電位が変動し難くなる。この結果、変動電流によるリングオシレータ５１のクロックジッタの発生が抑制される。なお、第２配線９４の抵抗が、第１配線９３の抵抗よりも大きくするために、第２配線９４に抵抗要素を配置しても良い。 In the case of the above modification, a configuration in which the resistance of the second wiring 94 is larger than the resistance of the first wiring 93 is preferable. This makes it difficult for the variable current to flow through the second wiring 94 as compared with the configuration in which the resistance of the second wiring is the same as the resistance of the first wiring. Therefore, the voltage generated by the voltage drop of the resistance is reduced by the resistance of the ground wiring 98, and the potential of the first wiring 93 (source terminal 15) is hardly changed. As a result, the occurrence of clock jitter in the ring oscillator 51 due to the fluctuation current is suppressed. In order to make the resistance of the second wiring 94 larger than the resistance of the first wiring 93, a resistance element may be arranged in the second wiring 94.

Claims (6)

  1. 　複数のトランジスタ（１１）から成る内部回路（３０）及びクロック生成回路（５０）が、同一の半導体基板（１０）に形成された半導体集積回路であって、
    　前記クロック生成回路（５０）は、リングオシレータ（５１）を有し、前記リングオシレータ（５１）から出力される信号に基づいたクロック信号を出力し、
    　前記半導体基板（１０）は、第１導電型であり、
    　前記各トランジスタ（１１）は、前記半導体基板（１０）に形成された第１導電型の第１ウェル（１３）と、前記第１ウェル（１３）に形成された、前記第１導電型とは異なる第２導電型の第２ウェル（１４，１５）及び前記第１導電型の第３ウェル（１６）と、を有し、
    　１つの前記第１ウェル（１３）に形成された２つの前記第２ウェル（１４，１５）が、前記トランジスタ（１１）の端子として機能し、
    　前記クロック生成回路（５０）を構成する前記トランジスタ（１１）において、２つの前記第２ウェル（１４，１５）の内の一方（１５）に第１配線（９３）が接続され、前記第３ウェル（１６）に第２配線（９４）が接続され、
    　前記第１配線（９３）と前記第２配線（９４）とがそれぞれ独立して、グランドに接続されるグランド部材（９２，９８）に接続されていることを特徴とする半導体集積回路。     An internal circuit (30) composed of a plurality of transistors (11) and a clock generation circuit (50) are semiconductor integrated circuits formed on the same semiconductor substrate (10),
    The clock generation circuit (50) includes a ring oscillator (51), and outputs a clock signal based on a signal output from the ring oscillator (51).
    The semiconductor substrate (10) is of a first conductivity type,
    Each of the transistors (11) includes a first conductivity type first well (13) formed in the semiconductor substrate (10) and the first conductivity type formed in the first well (13). A second well (14, 15) of a different second conductivity type and a third well (16) of the first conductivity type,
    Two second wells (14, 15) formed in one first well (13) function as terminals of the transistor (11),
    In the transistor (11) constituting the clock generation circuit (50), a first wiring (93) is connected to one (15) of the two second wells (14, 15), and the third well The second wiring (94) is connected to (16),
    The semiconductor integrated circuit according to claim 1, wherein the first wiring (93) and the second wiring (94) are independently connected to ground members (92, 98) connected to the ground.
  2. 　前記グランド部材（９２，９８）は、グランド端子（９２）であることを特徴とする請求項１に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 1, wherein the ground member (92, 98) is a ground terminal (92).
  3. 　前記グランド部材（９２，９８）は、グランド配線（９８）と、グランド端子（９２）とを有し、
    　前記第１配線（９３）と前記第２配線（９４）とが前記グランド配線（９８）に接続されていることを特徴とする請求項１に記載の半導体集積回路。     The ground member (92, 98) has a ground wiring (98) and a ground terminal (92),
    The semiconductor integrated circuit according to claim 1, wherein the first wiring (93) and the second wiring (94) are connected to the ground wiring (98).
  4. 　前記第２配線（９４）の抵抗が、前記第１配線（９３）の抵抗よりも大きいことを特徴とする請求項３に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 3, wherein the resistance of the second wiring (94) is larger than the resistance of the first wiring (93).
  5. 　前記内部回路（３０）を構成する前記トランジスタ（１１）において、２つの第２ウェル（１４，１５）の内の一方に接続された第３配線（９５）が、前記グランド端子（９２）に接続されていることを特徴とする請求項２～４のいずれか１項に記載の半導体集積回路。 In the transistor (11) constituting the internal circuit (30), a third wiring (95) connected to one of the two second wells (14, 15) is connected to the ground terminal (92). The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is formed.
  6. 　前記クロック生成回路（５０）に入力される信号に含まれるノイズを除去するためのコンデンサ（７０）をさらに有しており、
    　前記コンデンサ（７０）は、前記半導体基板（１０）に形成された第２導電型の第４ウェル（１８）と、前記第４ウェル（１８）に形成された第１導電型の第５ウェル（１９，２０）及び第２導電型の第６ウェル（２１）と、複数の前記第５ウェル（１９，２０）の間の第４ウェル（１８）上に設けられたゲート（２２）と、を有し、
    　複数の前記第５ウェル（１９，２０）と前記第６ウェル（２１）それぞれが、前記クロック生成回路（５０）と電源端子とを接続する電源配線（９６）に接続され、前記ゲート（２２）が、前記第１配線（９３）と前記第２配線（９４）それぞれと電気的に接続されていることを特徴とする請求項１～５いずれか１項に記載の半導体集積回路。     A capacitor (70) for removing noise included in a signal input to the clock generation circuit (50);
    The capacitor (70) includes a second conductivity type fourth well (18) formed in the semiconductor substrate (10) and a first conductivity type fifth well (18) formed in the fourth well (18). 19, 20) and a second conductivity type sixth well (21), and a gate (22) provided on the fourth well (18) between the plurality of fifth wells (19, 20). Have
    A plurality of the fifth wells (19, 20) and the sixth well (21) are connected to a power supply wiring (96) connecting the clock generation circuit (50) and a power supply terminal, and the gate (22). 6. The semiconductor integrated circuit according to claim 1, wherein the first wiring (93) and the second wiring (94) are electrically connected to each other.
PCT/JP2013/002240 2012-04-17 2013-04-01 Semiconductor integrated circuit WO2013157206A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-094043 2012-04-17
JP2012094043A JP2013222851A (en) 2012-04-17 2012-04-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
WO2013157206A1 true WO2013157206A1 (en) 2013-10-24

Family

ID=49383180

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/002240 WO2013157206A1 (en) 2012-04-17 2013-04-01 Semiconductor integrated circuit

Country Status (2)

Country Link
JP (1) JP2013222851A (en)
WO (1) WO2013157206A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185364A (en) * 1986-02-10 1987-08-13 Hitachi Ltd Semiconductor integrated circuit device
JPH0223663A (en) * 1988-07-12 1990-01-25 Sanyo Electric Co Ltd Semiconductor integrated circuit
WO1997032399A1 (en) * 1996-02-29 1997-09-04 Seiko Epson Corporation Semiconductor integrated circuit device
JPH1117111A (en) * 1997-06-23 1999-01-22 Seiko Epson Corp Semiconductor integrated device
JP2005269516A (en) * 2004-03-22 2005-09-29 Denso Corp Integrated circuit device
JP2006245551A (en) * 2005-02-02 2006-09-14 Ricoh Co Ltd Semiconductor integrated device and method of shield-wiring the device
JP2009117858A (en) * 1997-08-21 2009-05-28 Renesas Technology Corp Semiconductor integrated circuit device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185364A (en) * 1986-02-10 1987-08-13 Hitachi Ltd Semiconductor integrated circuit device
JPH0223663A (en) * 1988-07-12 1990-01-25 Sanyo Electric Co Ltd Semiconductor integrated circuit
WO1997032399A1 (en) * 1996-02-29 1997-09-04 Seiko Epson Corporation Semiconductor integrated circuit device
JPH1117111A (en) * 1997-06-23 1999-01-22 Seiko Epson Corp Semiconductor integrated device
JP2009117858A (en) * 1997-08-21 2009-05-28 Renesas Technology Corp Semiconductor integrated circuit device
JP2005269516A (en) * 2004-03-22 2005-09-29 Denso Corp Integrated circuit device
JP2006245551A (en) * 2005-02-02 2006-09-14 Ricoh Co Ltd Semiconductor integrated device and method of shield-wiring the device

Also Published As

Publication number Publication date
JP2013222851A (en) 2013-10-28

Similar Documents

Publication Publication Date Title
US7746147B2 (en) Semiconductor device
JP5952035B2 (en) Low pass filter circuit and voltage regulator
WO2010103931A1 (en) Power-on reset circuit
JP6328909B2 (en) Semiconductor integrated circuit device
US8456225B1 (en) Negative charge pump
JP2011211444A (en) Internal power supply voltage generation circuit
JP2011151719A (en) Level shift circuit
TWI520486B (en) Level shift circuit set in semiconductor apparatus
TWI643055B (en) Reference voltage circuit
JP5421075B2 (en) Input circuit
WO2013157206A1 (en) Semiconductor integrated circuit
JP5599993B2 (en) Semiconductor device
US9991882B2 (en) Semiconductor apparatus
JP5805380B2 (en) Delay circuit and inverter in semiconductor integrated device
JP2008177755A (en) Level shift circuit and semiconductor device using the same
JP5606345B2 (en) Output circuit
JP6543485B2 (en) Output buffer circuit
JP2017153095A (en) Semiconductor circuit and semiconductor device
JP3917985B2 (en) Semiconductor integrated circuit device and microcomputer
JP6113489B2 (en) Semiconductor circuit and semiconductor device
TWI542149B (en) Rail-to-rail input buffer
KR101919555B1 (en) Reference current source
TWI545417B (en) Control Method of Bulk and Its Control Circuit
TW201348915A (en) Circuit and method for power supply
US20090189643A1 (en) Constant voltage generating device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13777974

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13777974

Country of ref document: EP

Kind code of ref document: A1