JPH1117111A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive to prevent the capacity of a low-path filter from being subjected to the effect of noise from a substrate current which is generated from other cell, to which the capacity cell of the low-path filter belongs, by a method wherein a gate film capacity is formed of a transistor formed in a well of a semiconductor type opposite to that of a water substrate. SOLUTION: An N-type well 101 and a P-type well 102 are provided in the surface of a P-type wafer substrate 100. A GND potential is given to the well 102 from a CND terminal 110 via a P<+> stopper 109 and a VDD potential is given to the well 101 from a VDD pin 106 via an N<+> stopper 112. In such a way, as the VDD potential is given to the well 101 to which a capacity cell of a low-path filter(LPF) belongs, and the GND potential is given to the substrate 100, the junction between the well 101 and the substrate 110 becomes an inverse P-N junction. For that, even if there are N-type well to which other circuit belongs, those fellow N-type wells are not electrically jointed with each other. As a result, a capacity 108 of the LPE can be protected from noise due to a substrate current which is generated from the well 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a PLL (Phase Locked Loop) having a built-in filter.

[0002]

2. Description of the Related Art Conventionally, the gate film capacitance of a PLL filter has been configured as shown in FIG.

FIG. 2 shows a wafer 200 in this example.
Is a P substrate, and N well 202 and P well 201
Are formed. Normally, the P well is supplied with the GND potential, and the N well is supplied with the VDD potential. The source and the drain of the transistor are N + diffusion 20 respectively.
3 and the N + diffusion 204, both of which are also supplied with the GND potential. Then, a capacitor 208 is formed between the gate terminal 207 and the P well 201 having the GND potential via the insulating film 211.

[0004]

However, in the conventional configuration, some closed P-wells are electrically connected to each other by the resistance component of the P-type conductor through the P substrate 200, and the other P-wells are connected to each other. There is a disadvantage that the circuit formed in the well is susceptible to noise due to the substrate current generated. That is, no matter how much measures are taken in the shield of the wiring layer and the circuit layout, the noise coming from the substrate cannot be prevented. In particular, the higher the accuracy of the PLL, the higher the sensitivity of the control system to minute potential fluctuations of the low-pass filter (hereinafter referred to as LPF), which causes deterioration of the PLL characteristics.

FIG. 3 shows this state. P wafer substrate 3
00 via the resistance component 305 of the P-type semiconductor
The two P wells 301 and 303 are electrically connected. Depending on the chip area, this resistance is typically a few kilograms to a few ohms. Now, the capacity of the LPF is in the P well 301, and another circuit (for example, a digital circuit) is in the P well 30.
3, the substrate current (noise component) 30 due to switching noise or the like generated in the P well 303.
6 fluctuates the LPF capacitance of the P well 301 via the resistor 305. Each P-well is statically GND
Although it is supposed to be equal in potential, inrush current leaks from the source or drain of the transistor into the P well at the time of switching of the circuit, and the potential of the P well instantaneously becomes GND.
This is because the potential difference is generated between the P well and the other P wells. FIG. 3 shows an example of a twin well.
The essential problem that the P-type area 1 and the P-type area 303 are connected via the P-substrate resistance is the same.

[0006]

According to the present invention, there is provided a semiconductor integrated device comprising: (1) a semiconductor having a so-called twin-well (twin-tub) structure formed of P-type and N-type wells on the surface of a wafer substrate; There is a phase-locked loop (PLL) with a built-in low-pass filter.
F is a circuit having a capacitance in at least a part thereof, and the capacitance is a so-called gate film capacitance formed by a vertical structure of a CMOS gate film and a transistor channel, and the capacitance is a semiconductor type opposite to the wafer substrate. It is formed by a transistor formed in a well.

(2) Among semiconductors having a so-called single tab structure having a well formed of a semiconductor opposite to the wafer substrate on the surface of the wafer substrate, there is a PLL (Phase Locked Loop) incorporating a LPF (Low Pass Filter). The LPF is a circuit having a capacitance in at least a part of the LPF. The capacitance is a so-called gate film capacitance formed by a vertical structure of a CMOS gate film and a transistor channel, and the capacitance is a semiconductor film opposite to a wafer substrate. It is formed by a transistor formed in a mold well.

[0008]

When there are a plurality of semiconductor type wells opposite to the wafer substrate, the wells and the wafer substrate form a P / N type reverse junction, so that the respective wells are not electrically connected. Therefore, there is no influence of noise from the substrate current generated by another well to which the capacity cell of the LPF belongs.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first example of a capacitance structure of an LPF constructed according to the present invention. Here, a case where the wafer is a P substrate and has a twin well structure is taken as an example. P-type wafer substrate 1
There is an N-type well 101 and a P-well 102 on the surface of 00. The P well 102 is supplied with a GND potential from a GND terminal 110 via a P + stopper 109. In addition, V is applied to the N well 101 via an N + stopper 112.
A VDD potential is supplied from the DD pin 106. Then, in the N well 101 area, source 1 by P + diffusion
03 and a drain 104, and a gate 105 made of polysilicon thereon further form a PMOS transistor structure. However, the source 103 and the drain 1
04 is supplied with a VDD potential. Gate electrode 10
The end of 5 is the LPF-C terminal 107), which is the capacitor terminal of the LPF. That is, the LPF is passed through the oxide gate film 111.
-N well 10 connected to C terminal (107) and VDD
The capacitor 108 of the LPF is formed between the capacitor 108 and the capacitor 1.

This is the most characteristic point of the present invention.
Since the N well 101 to which the capacitance of the LPF belongs is provided with VDD and the P substrate 100 of the wafer is provided with GND, the N well 101 and the P substrate 100 are P / N reverse junctions. No matter how many N wells exist, the N wells are not electrically connected to each other. Therefore, the capacitance 108 of the LPF is protected from substrate noise. This is L
This is because the N well to which the capacitance of the PF belongs can be constituted by the semiconductor type opposite to that of the wafer substrate.

FIG. 4 is a block diagram of a PLL having a capacitor having the structure shown in FIG. Fin terminal 411 is a reference clock input, PFD 400 is a phase comparator, CP 403
Is a charge pump, VCO 408 is a voltage controlled oscillation circuit,
N409 is an N frequency dividing circuit, and Fout terminal 409 is the output of this PLL. In this case, the output frequency is Fout
= Fin * N. The LPF composed of the resistor 405 (R) and the capacitor 406 (C) is composed of the CP 403 and the VCO 40.
Between eight. (The primary filter is simply used here, but the gist of the present invention is not limited to a secondary filter or an active filter.) The resistor-side terminal 407 of the capacitor 406 corresponds to the 107 (LPF-C) terminal in FIG. I do. A VDD power supply side terminal 415 of the capacitor 406 corresponds to the N well 101 in FIG.

FIG. 5 shows a second example of the capacitance structure of the LPF constructed according to the present invention. Here, a case where the wafer is a P substrate and has a single tab structure is taken as an example. This time there is no P-well, but there are two N-type wells 501 and N-wells 502 on the surface of the P-type wafer substrate 500. P-type wafer substrate 50
To 0, the GND potential is GN via the P + stopper 509.
It is provided from a D terminal 510. N-well 501
Is supplied with a VDD potential from a VDD pin 506 via an N + stopper 512. And N-well 501
In the area, the source 503 and the drain 5 are formed by P + diffusion.
04 and polysilicon have gate 505 and PM
Create an OS transistor structure. However, this source 5
03 and the drain 504 are supplied with the VDD potential.
The end of the gate electrode 505 is 507 (LPF-C) with LPF
Capacitor terminals. That is, the LPF capacitor 508 is formed between the LPF-C terminal (507) and the N well 501 connected to VDD via the oxide gate film 511. Here, even if another N well 502 generates a substrate current, it does not affect the N well 501 through the P wafer substrate 500. Therefore, the stability of the LPF capacitor 508 is maintained.

As described above, the present invention can be applied to a wafer having a single tub structure without losing its essence.

In the examples of FIGS. 1 and 5, the VDD semiconductor terminal (pad) for supplying the N-well VDD potential to which the LPF capacitor belongs is connected to the VD of another circuit which easily generates noise.
If separated from the semiconductor terminal (pad) of D, L
The effect of the stability of the PF capacity increases.

FIG. 6 shows a third example of the capacitance structure of the LPF constructed according to the present invention. Here, a case where the wafer is an N substrate and has a twin well structure is taken as an example. N-type wafer substrate 6
On the surface of 00, there are a P-type well 601 and an N-well 602. The VDD potential is applied to the N well 602 from the VDD terminal 610 via the N + stopper 609. Also, the P well 601 is connected to the G via a P + stopper 612.
A GND potential is supplied from the ND pin 606. The source 6 is formed in the P well 601 area by N + diffusion.
03, a drain 604 and polysilicon have a gate 605 to form an NMOS transistor structure. However, the source 603 and the drain 604 are supplied with the GND potential. The tip of the gate electrode 605 is 607 (LP
FC terminal) and a capacitor terminal of the LPF. That is, the LPF-C terminal (607) via the oxide gate film 611
An LPF capacitor 608 is formed between the capacitor and the P well 601 connected to GND.

In the N-type wafer substrate of this embodiment, LP
GND is given to the P well 601 to which the capacity of F belongs, and VDD is given to the N substrate 600 of the wafer.
Since the well 601 and the N substrate 600 are P / N reverse junctions, the P wells are not electrically connected to each other no matter how many P wells are present. Therefore, the capacity of LPF 6
08 is protected from substrate noise. This is LPF
This is because the P well to which the capacitance of the above belongs belongs to the semiconductor type opposite to that of the wafer substrate.

FIG. 7 is a PLL block diagram in the case of having a capacitor having the structure of FIG.

A Fin terminal 711 has a reference clock input, P
FD700 is a phase comparison circuit, CP703 is a charge pump, VCO708 is a voltage controlled oscillator, N709 is N
The divider circuit and the Fout terminal 709 are the output of this PLL. In this case, the output frequency is Fout = Fin * N
Becomes Then, a resistor 705 (R) and a capacitor 706 (C)
Is between CP 703 and VCO 708. (The primary filter is simply used here, but the gist of the present invention is not limited to a secondary filter or an active filter.) The resistor-side terminal 707 of the capacitor 706 corresponds to the 607 (LPF-C) terminal in FIG. I do. The GND power supply side terminal 708 of the capacitor 706 is connected to the P well 60 of FIG.
Equivalent to 1. In the example of FIG. 4 and the example of FIG. 7, the power supplies of the capacity of the LPF are VDD and GND, respectively, but they function similarly in terms of PLL characteristics.

Although the details are omitted because the structure is easily guessed, as a fourth example of the present invention, even when the wafer has an N-type substrate and a single tab structure, it can be applied without changing the gist of the present invention at all. Needless to say.

[0021]

As described above, according to the semiconductor integrated device of the present invention, it is possible to prevent noise injected from another circuit through a wafer substrate and to constitute a high-precision PLL LPF. can do.

Generally, as a method of forming a capacitance,
There are a capacitance between the polysilicon layers, a capacitance between the metal wiring layers, a capacitance between the polysilicon layer and the metal wiring layer, and the like. All of these have a thick insulating layer of several thousand angstroms, so that The capacitance value is small.
However, the thickness of the insulating film of the gate film capacitance of the present invention is several tens.
Since the thickness is as small as 0 Å, there is also an effect that a large capacitance value can be obtained with a small area.

[Brief description of the drawings]

FIG. 1 shows a first example (P substrate, twin well) according to the present invention.
FIG.

FIG. 2 is a structural diagram of a (P substrate, twin well) capacitor according to a conventional configuration.

FIG. 3 is an explanatory diagram of a (P substrate, twin well) substrate current according to a conventional configuration.

FIG. 4 shows a first example (P substrate, twin well) according to the present invention.
FIG.

FIG. 5 is a second example (P substrate, single tab) according to the present invention.
FIG.

FIG. 6 shows a third example (N substrate, twin well) according to the present invention.
FIG.

FIG. 7 shows a third example (N substrate, twin well) according to the present invention.
FIG.

[Explanation of symbols]

 100 ·· P-type wafer substrate 101 ··· N-type well 102 ··· P-type well 105 ··· Polysilicon gate 106 ··· VDD power supply terminal 107 ··· Capacitance terminal of LPF 108 ··· Capacity of LPF 109 ··· P + stopper 110 ··· GND power supply terminal 111 ··· Gate oxide film 112 ··· N + stopper 400 ··· PFD (phase comparison circuit) 402 ··· CP (charge pump circuit) 405 ··· Resistance of LPF 406 ··· Capacity of LPF 408 ··· VCO (Voltage control oscillation circuit) 409 N division circuit

Claims (2)

[Claims] 1. A semiconductor device comprising a P-type and N-type well formed on the surface of a wafer substrate and having a PLL with a built-in low-pass filter. The LPF is a circuit having a capacitance in at least a part thereof. Is a gate film capacitance formed by a vertical structure of a CMOS gate film and a transistor channel, wherein the capacitance is formed by a transistor formed in a semiconductor type well opposite to a wafer substrate. . 2. A semiconductor having a well formed on a surface of a wafer substrate with a semiconductor opposite to the wafer substrate,
There is a PLL with a built-in low-pass filter.
Is a circuit having a capacitance in at least a part of the circuit. The capacitance is a so-called gate film capacitance formed by a vertical structure of a gate film of a CMOC and a transistor channel. The capacitance is a semiconductor well opposite to a wafer substrate. A semiconductor integrated device formed by the transistor formed in the semiconductor device.