JPH09199608A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the delay time of a logic circuit from increasing or an erroneous operation from occurring by suppressing the fluctuation of the voltage value of a power line and a ground line on switching. SOLUTION: In an integrated circuit, a number of cells 1 consisting of a PMOS 2 made of an N well 21, P-type diffusion layers 24, 25, and 26, and gates 22 and 23 and an NMOS 3 made of a P well 31, N-type diffusion layers 34, 35, and 36, and gates 32 and 33 are regularly arranged. A partial cell out of a number of cells 1 is wired and connected and becomes an actually used cell 1 for constituting a logic circuit and a power supply line 14 and a ground line 15 are wired and connected to the actually used cell. In this case, a power supply connection line 141 is used to make connection to the gate 32 of at least one NMOS 3 out of the power supply line 14 and the non-used cell 1 and a ground connection line 151 is used to make connection to the gate 23 of at least one PMOS 2 out of the ground line 15 and the non-used cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a gate array structure.

[0002]

2. Description of the Related Art In recent years, in the field of manufacturing semiconductor integrated circuits,
A gate array LSI having a sea-of-gate (hereinafter referred to as SOG) structure, which has no wiring area and in which basic gates generally called cells are regularly arranged on the entire surface of the chip, has been manufactured and put into practical use. There is. In the SOG structure, generally, all the arranged cells are not used, and some cells are connected by wiring to provide a logic circuit. Therefore, for example, a cell used as a wiring area or a cell not used in the logic circuit configuration is formed on the chip as an empty cell (unused cell), but is not subjected to wiring processing.

[0003]

On the other hand, in recent years, SOG has been highly integrated due to the miniaturization of semiconductor integrated circuits, and along with this, a power supply line for supplying power to cells,
The width of the ground line is also narrowed. As a result, the wiring resistance of the power supply line and the ground line increases, and the voltage value of the power supply line and the ground line greatly drops due to the switching current of the logic circuit. There is a problem that fluctuation causes increase of delay time of logic circuit and malfunction. Therefore, it is expected to develop a semiconductor integrated circuit that can suppress fluctuations in the voltage values of the power supply line and the ground line during switching, thereby suppressing increase in delay time of the logic circuit and occurrence of malfunction.

[0004]

In order to solve the above-mentioned problems, the present invention provides a P-channel MOS transistor (hereinafter referred to as PMOS) including an N-well, a P-type diffusion layer and a gate, and a P-well and an N-type. A large number of cells, which are N-channel MOS transistors (hereinafter, referred to as NMOS) each including a diffusion layer and a gate, are regularly arranged, and some of the cells are connected by wiring to form a logic circuit. This is done in a semiconductor integrated circuit in which a logic circuit using cell is configured and the rest is a logic circuit unused cell not used in a logic circuit, and a power supply line and a ground line are connected to the logic circuit using cell by wiring. That is,
In the semiconductor integrated circuit according to the invention of claim 1, a power supply line,
At least one NMOS of the logic circuit unused cells
Connected to the gate of the power supply line by the power supply line, and the PM of at least one of the ground line and the logic circuit unused cell.
The gate of the OS was connected by a ground connection line.

In the semiconductor integrated circuit according to the second aspect of the present invention, the power supply line and at least one N type diffusion layer of the logic circuit unused cells are connected by a power supply connection line, and the ground line and the logic circuit At least one of the used cells was connected to the P-type diffusion layer by a ground connection line.

According to the first aspect of the present invention, since the power supply line is connected to the gate of at least one NMOS of the logic circuit unused cells, when the logic circuit is switched,
The gate capacitance formed between the NMOS gate and the P well immediately below the NMOS is the decoupling between the power supply and the ground.
Acts as a capacitor. As a result, the voltage value of the power supply line is stabilized with respect to the ground voltage value. In addition, the PM of at least one of the ground line and the logic circuit unused cell
Since the gate of the OS is connected, the gate capacitance formed between the gate and the N well immediately below the gate functions as a decoupling capacitor between the power supply and the ground when the logic circuit is switched. As a result, the voltage value of the ground line is stabilized with respect to the power supply voltage value.

According to the second aspect of the invention, since the power supply line and the N-type diffusion layer of at least one of the cells not used in the logic circuit are connected, the N-type diffusion layer and the portion directly under the N-type diffusion layer at the time of switching the logic circuit. The P-N junction capacitance due to the junction with the P well functions as a decoupling capacitor between the power supply and the ground. Further, since the ground line and at least one P-type diffusion layer of the logic circuit unused cell are connected, when the logic circuit is switched, the P-type diffusion layer and the N well immediately below the P-type diffusion layer are joined together. The N-junction capacitance acts as a power-ground decoupling capacitor. Therefore, the voltage fluctuation at the time of switching the power supply line and the ground line can be suppressed low.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor integrated circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a layout diagram of essential parts showing a first embodiment of the present invention.
Particularly, an example of wiring connection of unused cells of the logic circuit, which is a feature of the present invention, is shown for one cell. FIG. 2
FIG. 2 is a sectional view taken along the line AA in FIG. In this semiconductor integrated circuit, as shown in FIGS. 1 and 2, one basic cell 1 is composed of two PMOSs 2 and two NMOSs 3, and a large number of the basic cells 1 are formed on a substrate (chip).
It has a regularly arranged gate array structure.

That is, the substrate 11 in one cell 1
An N well 21 and a P well 31 are formed side by side. The gates 22 and 23 of the two PMOSs 2 are formed substantially parallel to each other on the base 11 at the position where the N well 21 is formed.
Three P-type diffusion layers 2 separated by the two gates 22 and 23
4, 25, 26 are formed. And gate 2
The two PMOSs 2 and 23 and the P-type diffusion layers 24, 25 and 26 form two PMOSs 2. Similarly, the gates 3 of the two NMOSs 3 are formed on the substrate 11 where the P well 31 is formed.
Reference numerals 2 and 33 are provided so as to be substantially parallel to each other and are provided such that their longitudinal directions substantially coincide with the longitudinal directions of the gates 22 and 23 of the PMOS 2, respectively. Also P well 3
Three N-type diffusion layers 34, 35, and 36 are formed on the surface side of the base 11 from the position 1 with the two gates 32 and 33 as boundaries. Then, the gates 32 and 33 and the N-type diffusion layer 34,
Two NMOSs 3 are formed by 35 and 36.

Both ends of the gates 22 and 23 are N wells 21 outside the P type diffusion layers 24, 25 and 26, respectively.
Both ends of the gates 32 and 33 are formed so as to extend upward and the P well 31 outside the N type diffusion layers 34, 35 and 36, respectively.
It is formed so as to extend upward. Also, as shown in FIG.
A gate insulating film 12 is interposed between the gates 22, 23, 32, 33 and the base 11.

As described above, a large number of cells 1 having the above-described structure are regularly arranged on the base 11, and some of the cells 1 are connected by wiring to form a logic circuit. Has been done. Cell 1 used in the logic circuit here
Is a logic circuit used cell (hereinafter referred to as an actually used cell) 1 and the rest is a logic circuit unused cell (hereinafter referred to as an unused cell) 1 that is not used in the logic circuit.

On the other hand, a power supply line 14 made of aluminum (Al) is continuously provided on the PMOS 2 of each cell 1 which is regularly arranged on the base 11 through an insulating film 13 (see FIG. 2). , An insulating film 1 on the NMOS 3 of each cell 1.
A ground wire 15 made of Al is continuously provided through the wiring 3. Normally, the potential of the N well 21 is the power source potential VD.
The potentials of the D and P wells 31 are set to the ground potential GND. Therefore, for example, the power line 14 and the ground line 15 provided in the unused cell 1 shown in FIG. The wiring is connected to the N well 21 and the P well 31 of the actually used cell provided around the cell 1.

By the way, in the present embodiment, the power supply line 14 is connected to the gate 32 of the NMOS 3 of the unused cell 1 by the power supply connection line 141, and the ground line 15 is connected to the gate 23 of the PMOS 2 of the unused cell 1. And the ground connection line 151. Specifically, the power supply connection line 141 is formed to extend from the power supply line 14 toward the gate 32 of the NMOS 3 of the unused cell 1, and the tip end side of the power supply connection line 141 is the insulating film 13 as shown in FIG.
Through the contact hole 16 formed in the gate 32
Is connected to the tip of. Further, a ground connection line 151 is formed to extend from the ground line 15 toward the gate 23 of the PMOS 2 of the unused cell 1, and the ground connection line 151 is formed.
Of the contact hole 1 whose tip side is formed in the insulating film 13
It is connected to the tip of the gate 23 via 7.

Power connection line 141, ground connection line 151
Is preferably formed so that the length thereof is as short as possible in terms of wiring resistance. Therefore, in the present embodiment, the power supply connection line 141 is formed to extend from the position near the gate 32 of the NMOS 3 in the power supply line 14. Is
In the ground line 15, the ground connection line 151 extends from a position close to the gate 23 of the PMOS 2 and is formed. The power supply connection line 141 and the ground connection line 151 are formed at the same time when the patterns of the power supply line 14 and the ground line 15 are formed, and are made of Al like the power supply line 14 and the ground line 15.

In the semiconductor integrated circuit configured as described above, the power supply line 14 is connected to the gate 32 of the NMOS 3 of the unused cell 1 by the power supply connection line 141.
The gate capacitance of the MOS capacitor structure formed between the gate 32 and the P well 31 functions as a decoupling capacitor between the power supply and the ground. Therefore, the voltage value of the power supply line 14 is stabilized with respect to the ground voltage value. In addition, the ground line 15 is the PMO of the unused cell 1.
Since the gate 23 of S2 is connected to the ground connection line 151, the gate capacitance formed between the gate 23 and the N well 21 also acts as a decoupling capacitor between the power supply and the ground. The voltage value of 15 is stabilized with respect to the power supply voltage value. As a result, fluctuations in the voltage values of the power supply line 14 and the ground line 15 at the time of switching of the logic circuit provided in this semiconductor integrated circuit are suppressed, and the power supply voltage values of the actually used cells around the unused cell 1 are stabilized. It

FIG. 3 is a waveform diagram of the power supply line 14 and the ground line 15 in the semiconductor integrated circuit of the above embodiment,
In the figure, (a) is the waveform of the power supply line 14, (b) is the ground line 1
5, waveform (c) shows the output waveform of the logic circuit in this semiconductor integrated circuit. The broken line in the figure is a comparative example, and shows the waveform (d) of the power supply line 14 and the output waveform (e) of the logic circuit when not connected to the gate 32, respectively. As shown in FIG. 3, when the logic circuit switches from the "Low" output to the "High" output, the power supply line 14
Since a switching current flows in the
A large voltage drop occurs as shown in FIG. On the other hand, in the case of the above embodiment,
As shown in (a), the amount of voltage drop of the power supply line 14 is small, and as shown in (e), the output of the logic circuit is steep.

Although not shown, if the ground line 15 is not connected to the gate 23, a voltage drop similar to that of the power supply line 14 shown in FIG. It is confirmed that the connection reduces the amount of voltage drop of the ground line 15. From these facts, the decoupling due to the gate capacitance formed between the gate 32 and the P well 31 and the gate capacitance formed between the gate 23 and the N well 21 is performed.
It can be seen that the voltage values of the power supply line 14 and the ground line 15 during switching are stabilized by the capacitor effect.

As described above, according to the first embodiment, the voltage values of the power supply line 14 and the ground line 15 can be stabilized, so that the delay time of the logic circuit and the malfunction of the logic circuit due to the power supply voltage drop are increased. Occurrence can be suppressed. Further, since the power supply connection line 141 and the ground connection line 151 can be formed simultaneously with the formation of the power supply line 14 and the ground line 15, the above effect can be obtained without increasing the number of steps.

In the above embodiment, the case where the power supply line is connected to the gate of one NMOS of the unused cells and the ground line is connected to the gate of one PMOS of the unused cells has been described. , The power line is not limited to this, and two or more NMOs of the unused cells are connected to each other.
Of course, it may be connected to the gate of S, and the ground line may be connected to the gates of two or more PMOSs of the unused cells.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. Note that, like FIG. 1, FIG. 4 is a layout diagram showing the wiring connection of unused cells for one cell, and FIG. 5 is a sectional view taken along the line BB in FIG. This embodiment is different from the first embodiment in that the power supply line 14 is connected to the N-type diffusion layer 34 instead of the gate 32 of the NMOS 3 of the unused cell 1, and the ground line 1 is connected.
5 is connected to the P-type diffusion layer 26 instead of the gate 23 of the PMOS 2 of the unused cell 1.

That is, from the power supply line 14 to the N of the NMOS3.
A power supply connection line 141 is formed so as to extend toward the mold diffusion layer 34, and the tip side of the power supply connection line 141 is N through a contact hole 18 formed in the insulating film 13 as shown in FIG.
It is connected to the mold diffusion layer 34. Further, a ground connection line 151 is formed to extend from the ground line 15 toward the P-type diffusion layer 26 of the PMOS 2, and the tip side of the ground connection line 151 is formed through the contact hole 19 formed in the insulating film 13 into the P-type diffusion layer 26. It is connected to the.

In the semiconductor integrated circuit thus configured, since the power supply line 14 is connected to the N-type diffusion layer 34, the N-type diffusion layer 34 and the P-well 31 which is at the ground potential are joined together. , The so-called P-N junction capacitance is the power source-
It will act as a decoupling capacitor between grounds. Further, since the ground line 15 is connected to the P-type diffusion layer 26, the P-N junction capacitance due to the junction between the P-type diffusion layer 26 and the N well 21 which is at the power supply potential is decoupled between the power supply and the ground. -It will work as a capacitor. Therefore, the semiconductor integrated circuit of the second embodiment can stabilize the voltage values of the power supply line 14 and the ground line 15 at the time of switching of the logic circuit and can suppress the power supply voltage drop. It is possible to suppress the increase of the delay time of the logic circuit and the occurrence of malfunction.

In this embodiment, the case where the power supply line is connected to one N type diffusion layer of the unused cells and the ground line is connected to one P type diffusion layer of the unused cells will be described. However, the power supply line may be connected to two or more N-type diffusion layers of the unused cells, and similarly, the ground line may be connected to two or more P-type diffusion layers of the unused cells. Of course it is okay.

Next, a third embodiment of the present invention will be described with reference to FIG. Note that FIG. 6 is a layout diagram showing the wiring connection of unused cells for one cell, as in FIG. As shown in FIG. 6, this embodiment is a combination of the first embodiment and the second embodiment.
The gate 32 of the MOS3 and the N-type diffusion layer 34 are connected by the power supply connection line 141, and the ground line 15 and PM
The gate 23 of the OS 2 and the P-type diffusion layer 26 are connected by the ground connection line 151.

In the semiconductor integrated circuit configured as described above, in the unused cell 1, the PN junction capacitance due to the junction between the N type diffusion layer 34 and the P well 31 as well as the NMOS are provided.
The gate capacitance formed between the gate 32 and the P well 31 of No. 3 acts as a decoupling capacitor between the power supply and the ground. Further, the gate capacitance formed between the gate 23 of the PMOS 2 and the N well 21 together with the P-N junction capacitance due to the junction between the P type diffusion layer 26 and the N well 21 functions as a decoupling capacitor between the power supply and the ground. . Therefore, the voltage values of the power supply line 14 and the ground line 15 at the time of switching of the logic circuit can be further stabilized and the power supply voltage drop can be further suppressed, and the delay time of the logic circuit due to the power supply voltage drop can be increased and It is possible to further suppress the occurrence of malfunction.

In this embodiment, the case where the power supply line is connected to the NMOS gate and the N-type diffusion layer of the same unused cell has been described. However, the power supply line is connected to the NMOS gate formed in a different unused cell, It is also possible to connect to the N-type diffusion layer of NMOS. Similarly, the ground line has a PMOS gate and a PMOS P formed in different unused cells.
It is also possible to connect to the mold diffusion layer. The present invention also provides
It can be applied to all semiconductor integrated circuits having the gate array structure at least in a part of the chip.

[0027]

As described above, according to the first aspect of the invention, the gate capacitance formed between the P-well and the gate of the NMOS of the unused cell connected to the power supply line is
Acts as a decoupling capacitor between grounds,
Further, since the gate capacitance formed between the gate of the PMOS of the unused cell connected to the ground line and the N well functions as a decoupling capacitor between the power supply and the ground, the power supply line at the time of switching the logic circuit, The voltage value of the ground line can be stabilized. Therefore, it is possible to suppress an increase in the delay time of the logic circuit and the occurrence of malfunction. According to the invention of claim 2, a P-N is formed by joining an N-type diffusion layer of an unused cell connected to a power supply line and a P-well.
The junction capacitance acts as a decoupling capacitor between the power supply and the ground, and the P-N junction capacitance due to the junction between the P well of the unused cell connected to the ground line and the N well is Since it functions as a decoupling capacitor of the above, it is possible to obtain the same effect as the invention of claim 1.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a main part of a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a sectional view taken along line AA in FIG.

FIG. 3 is a waveform diagram of a power supply line and a ground line during switching of a logic circuit.

FIG. 4 is a layout diagram showing a main part of a second embodiment of a semiconductor integrated circuit according to the present invention.

5 is a sectional view taken along the line BB in FIG.

FIG. 6 is a layout diagram showing a main part of a third embodiment of a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

 1 cell 2 PMOS 3 NMOS 11 substrate 14 power line 15 ground line 21 N well 22, 23, 32, 33 gate 24, 25, 26 P-type diffusion layer 31 P-well 34, 35, 36 N-type diffusion layer 141 power connection line 151 ground connection line

Claims (3)

[Claims] 1. A P-channel MO comprising an N well formed on a substrate, a P-type diffusion layer formed on the surface side of the substrate with respect to the N well, and a gate formed on the substrate.
An N transistor including an S transistor, a P well formed in the base, an N-type diffusion layer formed on the surface of the base with respect to the P well, and a gate formed on the base.
A large number of cells each having a channel MOS transistor are regularly arranged, and some cells of the plurality of cells are connected by wiring to form a logic circuit using cell, and the rest is the logic circuit. In a semiconductor integrated circuit in which a logic circuit unused cell that is not used in, and a power supply line and a ground line are connected to the logic circuit used cell by wiring, at least one of the power supply line and the logic circuit unused cell A gate of the N-channel MOS transistor is connected by a power supply connection line, and the ground line and a gate of at least one P-channel MOS transistor of the logic circuit unused cells are connected by a ground connection line. A characteristic semiconductor integrated circuit. 2. A P-channel MO including an N well formed on a substrate, a P-type diffusion layer formed on the surface side of the substrate with respect to the N well, and a gate formed on the substrate.
An N transistor including an S transistor, a P well formed in the base, an N-type diffusion layer formed on the surface of the base with respect to the P well, and a gate formed on the base.
A large number of cells each having a channel MOS transistor are regularly arranged, and some cells of the plurality of cells are connected by wiring to form a logic circuit using cell, and the rest is the logic circuit. In a semiconductor integrated circuit in which a logic circuit unused cell that is not used in, and a power supply line and a ground line are connected to the logic circuit used cell by wiring, at least one of the power supply line and the logic circuit unused cell An N-type diffusion layer is connected by a power supply connection line, and the ground line and at least one P-type diffusion layer of the logic circuit unused cells are connected by a ground connection line. Integrated circuit. 3. The power supply connection line is connected to at least one N-type diffusion layer of the logic circuit unused cell, and the ground connection line is connected to at least one P of the logic circuit unused cell. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to the type diffusion layer.