WO2013147417A1 - Procédé de fabrication de carte de sonde mvp pour test de semi-conducteur - Google Patents

Procédé de fabrication de carte de sonde mvp pour test de semi-conducteur Download PDF

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Publication number
WO2013147417A1
WO2013147417A1 PCT/KR2013/001045 KR2013001045W WO2013147417A1 WO 2013147417 A1 WO2013147417 A1 WO 2013147417A1 KR 2013001045 W KR2013001045 W KR 2013001045W WO 2013147417 A1 WO2013147417 A1 WO 2013147417A1
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WO
WIPO (PCT)
Prior art keywords
wire
ceramic
hole
mvp
main pcb
Prior art date
Application number
PCT/KR2013/001045
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English (en)
Korean (ko)
Inventor
이동욱
Original Assignee
주식회사 브리지
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Filing date
Publication date
Application filed by 주식회사 브리지 filed Critical 주식회사 브리지
Publication of WO2013147417A1 publication Critical patent/WO2013147417A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips

Definitions

  • the present invention relates to a method for manufacturing a micro (Via Via Wire Plating) probe board for semiconductor test, and in particular, by placing the power and ground plane (GND plane) of the main PCB inside the ceramic to minimize the power loss accordingly
  • the present invention relates to a method of manufacturing a micro via wire plating (MVP) probe board for semiconductor test, which can reduce power loss due to a long length of a wire during a product test.
  • MVP micro via wire plating
  • semiconductor devices In general, semiconductor devices (LOGIC, CPU, Memory Device, etc.) have a fabrication process for forming a pattern on a wafer, and an assembly for assembling the wafer on which the pattern is formed into each chip. Manufactured through the assembly process.
  • EDS Electrical Die Sorting
  • the EDS process is a process for determining a defective chip among the chips constituting the wafer.
  • the EDS process applies an electrical signal to the chips constituting the wafer to determine a defect based on a signal checked from the applied electrical signal. Mainly used.
  • each chip constituting the wafer mainly uses a probe device called a probe card having a plurality of needles that come into contact with the patterns of the respective chips to apply an electrical signal. If it is determined that the result of the test using the product is good, the semiconductor device is manufactured as a finished product by a post-process such as packaging.
  • the electrical property inspection using the probe card of the semiconductor wafer is generally conducted by applying a specific current through the needle while the needle of the probe card is in contact with the electrode pad of each device of the wafer (eg, the wafer level test). To measure.
  • a probe card is formed using a micro electro mechanical system (MEMS) process similar to semiconductor etching technology. A method of producing cards has been tried.
  • MEMS micro electro mechanical system
  • a counterpart may be used by using a sub PCB, which is an expensive product such as MLC (Multi-Layered Ceramic) or MLO (Multi-Layered Organic).
  • MLC Multi-Layered Ceramic
  • MLO Multi-Layered Organic
  • MVP method for manufacturing a semiconductor test according to the present invention and MVP probe board manufactured by the method is manufactured using a unique design technology called MVP (Micro Via Wire Plating).
  • 1 is a diagram illustrating a general MVP design technique.
  • the MVP Mocro Via Wire Plating
  • the through hole 1 is processed in the ceramic 2, and the through hole 1 is coated with an insulator. By inserting the alloy wire (4) to implement the signal processing possible.
  • the MVP probe board manufactured by the MVP (Micro Via Wire Plating) manufacturing method is used for semiconductor testing, for example, it is mounted on a probe head (Probe He-ad) and used for semiconductor testing. It is used in the same way as described MLC or MLO.
  • FIG. 2 is a diagram illustrating a configuration of a conventional Micro Via Wire Plating (MVP) probe board for semiconductor testing.
  • MVP Micro Via Wire Plating
  • a conventional method for manufacturing a micro via wire plating (MVP) probe board for semiconductor testing is a process of processing a fine hole in a ceramic, and inserting an alloy wire into a hole of the ceramic, and then inserting the alloy wire.
  • MVP micro via wire plating
  • the power plane is configured on the main PCB side, and this is supplied to the individual pins through the wire, which causes a slight voltage drop due to the length of the wire. You can.
  • the conventional method requires a large number of holes on the main PCB side to use individual wires, and thus there are problems such as insufficient main PCB space, increased wire insertion time, and increased operator error.
  • the present invention has been made to solve the above problems, since the power and ground planes of the main PCB (Plan) and the ground plane (GND plane) is located inside the ceramic to minimize the power loss and to place the GND at the closest point of the device
  • the aim is to provide an MVP (Micro Via Wire Plating) probe board for semiconductor test that can minimize the power loss due to the long length of wire during high speed test.
  • the first step of processing the hole in place in the ceramic A second process of low and high frequency crimping and soldering to a copper portion, a third process of soldering the wires to be connected to the ground plane of the ceramic and the main PCB together, and inserting the wires into the prepared ceramic and the main PCB in a straight form
  • a sixth step of fixing the wire inserted into the through hole a seventh step of grinding the wire to have a planar shape, and a cross section of the wire
  • the eighth process of copper, nickel, and gold plating a pad is included.
  • the copper surface is removed by etching at the position of the signal line while leaving the copper surface at the position of the power line and the ground line, and the hole is processed.
  • the wire is soldered.
  • a bare wire is used for the workability of the wire, and the power and ground pins are located inside the ceramic so that the pins of power and ground are not individually wired with the main PCB and a few thick wires are used.
  • the wire is wired by using a thick wire having a diameter of 0.06 mm to 1.5 mm as the power line and the ground line, and an insulating layer made of ceramic and a high insulation material is formed between the power plane and the ground plane.
  • the present invention configured as described above places the power and ground plane of the main PCB (Po -wer plane and GND plane) inside the ceramic, thereby minimizing the power loss, and thus the wire at the time of high-speed product testing. There is an effect that can reduce the power loss by a minimum.
  • the present invention has an effect of stabilizing power supply and stabilizing GND characteristics by inserting a power line into a plane in an MVP module.
  • Fig. 1 is a view for explaining the appearance of a ceramic required for a general MVP product and a plating configuration of a contact PAD surface to be formed on the ceramic surface.
  • FIG. 2 is a diagram illustrating a configuration of a conventional Micro Via Wire Plating (MVP) probe board for semiconductor test.
  • MVP Micro Via Wire Plating
  • FIG. 3 is a view showing the configuration of an MVP (Micro Via Wire Plating) probe board for semiconductor testing of the present invention.
  • MVP Micro Via Wire Plating
  • FIG. 4 is a view showing a state in which holes are processed on ceramics as a result of the first process according to the present invention
  • FIG. 5 is a view showing a state in which ground wires are soldered as a result of the fifth and sixth processes according to the present invention.
  • Figure 6 is a flow chart showing the flow of the manufacturing method of the MVP probe board for semiconductor testing of the present invention.
  • a method for manufacturing an MVP probe board for semiconductor testing includes a first process of processing a hole into a ceramic in position, inserting a wire into a hole of a copper surface of the ceramic corresponding to a ground plane, and then applying a low and high frequency to a copper portion.
  • FIG. 3 is a view showing the configuration of a semiconductor test MVP (Micro Via Wire Plating) probe board of the present invention
  • Figure 7 is a flow chart showing the flow of a method for manufacturing a semiconductor test MVP probe board of the present invention.
  • a method of manufacturing a micro via wire plating (MVP) probe board for semiconductor testing may include a first process (S100) and a ground plane of processing holes in a ceramic in position.
  • the second step (S120) After inserting the wire into the hole of the copper surface of the ceramic corresponding to 160, the second step (S120) of low, high frequency pressing and soldering to the copper portion, the ground surface 160 of the ceramic and the main PCB (110)
  • a sixth step of fixing the wire inserted into the through hole of the S200) After inserting the wire into
  • FIG. 4 is a view illustrating a state in which copper is coated on a ceramic surface to which a ceramic and a ground line 130 are connected, and a portion where a hole of the signal line 140 is made is etched, and FIG. As a result of the first step, the hole is processed on the ceramic, and FIG. 6 is a view showing the ground line 130 soldered as a result of the fifth and sixth steps according to the present invention.
  • One side of the ceramic is coated with copper, but the seat of the signal line 140 is etched, and it can be seen that the seat of the ground wire 130 is coated with copper.
  • the wire connected to the MVP probe board for semiconductor test of the present invention is generally composed of power lines 120 and ground lines 130 or more.
  • the power plane 115 / ground plane 160 is positioned inside the ceramic in the second process S120, pins of power / ground are individually wired to the main PCB. Not) For example, with about 3,000 pin devices, typically more than 50% of the power / ground pins are connected to the main PCB by a few thick signal lines, instead of individual wires.
  • a wire having a size corresponding to the pitch of a hole whose diameter is to be used as the power line 120 and the ground line 130 is used, and the wire is an alloy wire shielded by a covering, and the power plane 115 and the ground plane ( An insulating layer 155 using a ceramic material and a film Fil-m having high insulation performance is formed between the 160.
  • the present invention places the power and ground planes of the main PCB inside the ceramic, minimizing power loss, thereby minimizing power loss by wires during high-speed product testing.
  • the invention can be reduced.
  • main PCB 115 power plane

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'une carte de sonde MVP, destinée à un test de semi-conducteur. Le procédé comprend : une première étape de traitement d'un céramique afin de former un orifice en un emplacement correct dans le céramique ; une deuxième étape d'insertion d'un fil dans l'orifice d'un plan de cuivre du céramique correspondant au plan de masse et de réalisation d'un processus de soudage et de compression à faible et haute fréquence dans la partie en cuivre ; une troisième étape de soudage du céramique avec le fil à connecter au plan de masse d'une PCB principale ; une quatrième étape d'insertion du fil dans une forme de ligne droite dans le céramique préparé et dans la PCB principale ; une cinquième étape de connexion d'un fil de masse au plan de masse de masse de la PCB principale au moyen de soudage ; une sixième étape de remplissage de la paroi interne d'un orifice traversant et d'un espace vide du céramique avec une résine époxy à travers un orifice d'injection de résine époxy de la PCB principale, de manière à fixer le fil inséré dans l'orifice traversant du céramique ; une septième étape de meulage du fil en une surface plate ; et une huitième étape de placage d'un chemin d'un seul côté du fil avec du cuivre, du nickel et de l'or.
PCT/KR2013/001045 2012-03-28 2013-02-08 Procédé de fabrication de carte de sonde mvp pour test de semi-conducteur WO2013147417A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2012-0031789 2012-03-28
KR1020120031789A KR101317634B1 (ko) 2012-03-28 2012-03-28 반도체 테스트용 ｍｖｐ 프로브 보드 제조방법

Publications (1)

Publication Number Publication Date
WO2013147417A1 true WO2013147417A1 (fr) 2013-10-03

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PCT/KR2013/001045 WO2013147417A1 (fr) 2012-03-28 2013-02-08 Procédé de fabrication de carte de sonde mvp pour test de semi-conducteur

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WO (1) WO2013147417A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700021400A1 (it) * 2017-02-24 2018-08-24 Technoprobe Spa Testa di misura a sonde verticali con migliorate proprietà in frequenza

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102263304B1 (ko) * 2013-11-05 2021-06-15 타이코에이엠피 주식회사 배터리 셀 연결보드

Citations (5)

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JP2003222637A (ja) * 2002-01-31 2003-08-08 Koyo Technos:Kk 検査冶具及びその製造方法
JP2006220662A (ja) * 2004-09-30 2006-08-24 Jsr Corp 回路装置検査用電極装置およびその製造方法並びに回路装置の検査装置
KR100632484B1 (ko) * 2006-03-14 2006-10-09 주식회사 맥퀸트로닉 수직 완충형 프로브카드
KR20100052959A (ko) * 2008-11-11 2010-05-20 삼성전자주식회사 웨이퍼 검사장치의 인터페이스 구조
KR20110115005A (ko) * 2010-04-14 2011-10-20 주식회사 브리지 웨이퍼 레벨 테스트용 ｍｖｐ 프로브카드 보드 제조방법

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JP4388620B2 (ja) * 1999-04-16 2009-12-24 株式会社アドバンテスト プローブカード及びプローブカード製造方法
US6847218B1 (en) * 2002-05-13 2005-01-25 Cypress Semiconductor Corporation Probe card with an adapter layer for testing integrated circuits
KR100661254B1 (ko) * 2005-01-06 2006-12-28 (주) 미코티엔 반도체 검사용 프로브 카드

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003222637A (ja) * 2002-01-31 2003-08-08 Koyo Technos:Kk 検査冶具及びその製造方法
JP2006220662A (ja) * 2004-09-30 2006-08-24 Jsr Corp 回路装置検査用電極装置およびその製造方法並びに回路装置の検査装置
KR100632484B1 (ko) * 2006-03-14 2006-10-09 주식회사 맥퀸트로닉 수직 완충형 프로브카드
KR20100052959A (ko) * 2008-11-11 2010-05-20 삼성전자주식회사 웨이퍼 검사장치의 인터페이스 구조
KR20110115005A (ko) * 2010-04-14 2011-10-20 주식회사 브리지 웨이퍼 레벨 테스트용 ｍｖｐ 프로브카드 보드 제조방법

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700021400A1 (it) * 2017-02-24 2018-08-24 Technoprobe Spa Testa di misura a sonde verticali con migliorate proprietà in frequenza
WO2018153963A1 (fr) * 2017-02-24 2018-08-30 Technoprobe S.P.A. Tête d'essai de sonde verticale à propriétés de fréquence améliorées
US11029337B2 (en) 2017-02-24 2021-06-08 Technoprobe S.P.A. Vertical probe testing head with improved frequency properties

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KR101317634B1 (ko) 2013-10-10
KR20130109773A (ko) 2013-10-08

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