WO2013139158A1 - 薄膜晶体管阵列基板及其制备方法和显示装置 - Google Patents

薄膜晶体管阵列基板及其制备方法和显示装置 Download PDF

Info

Publication number
WO2013139158A1
WO2013139158A1 PCT/CN2012/087232 CN2012087232W WO2013139158A1 WO 2013139158 A1 WO2013139158 A1 WO 2013139158A1 CN 2012087232 W CN2012087232 W CN 2012087232W WO 2013139158 A1 WO2013139158 A1 WO 2013139158A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
transistor array
array substrate
region
Prior art date
Application number
PCT/CN2012/087232
Other languages
English (en)
French (fr)
Inventor
盖翠丽
张卓
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/994,080 priority Critical patent/US8963160B2/en
Publication of WO2013139158A1 publication Critical patent/WO2013139158A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • Embodiments of the present invention relate to a thin film transistor (TFT) array substrate, a method of fabricating the same, and a display device.
  • TFT thin film transistor
  • Active matrix drive technology is required for any active display device (liquid crystal display, electronic paper display, etc.).
  • TFT technology is one that implements an active matrix.
  • the electronic paper display is usually formed by pairing a thin film transistor array substrate and an electronic paper substrate.
  • the thin film transistor array substrate is responsible for inputting the data signal to control the image display, and consists of the active pixel area and the wiring area around the active pixel area.
  • the active pixel area (display area) is composed of a plurality of active pixel units arranged in a matrix form. Each of the pixel units is a rectangular region formed by crossing gate lines and data lines, and a TFT and a pixel electrode are disposed therein.
  • a thin film transistor array substrate of a conventional electronic paper display device includes an active pixel region 1 and a wiring region 2.
  • the wiring area 2 includes: a data line and a scan line driving IC bonding area 202, a data line and a scanning line peripheral wiring area (fan-out) 203, a connection area 204 between the driving IC and the external FPC, and an FPC bonding area. 205.
  • the driver IC bonding area 202 is used to set the driving IC.
  • the thin film transistor array substrate In the preparation process of the active display device, the thin film transistor array substrate is always exposed to the air after the fabrication of the thin film transistor array substrate to the module stage before the display is completed. At this stage, static electricity of up to several thousand volts is usually generated due to friction, and is transmitted to the inside of the panel to generate a high-intensity instantaneous current, which causes irreparable damage to the panel. Summary of the invention
  • An embodiment of the present invention provides a thin film transistor array substrate, including: an active pixel region and a wiring region, wherein a conductive electrode is formed in the wiring region, and the conductive electrode is connected Ground.
  • Another embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, including: forming a thin film transistor array in an active pixel region of a substrate; and forming a conductive electrode in a wiring region located at a periphery of the active pixel region .
  • the thin film transistor array substrate and the preparation method thereof, the liquid crystal display device, and the electronic paper display device of the present invention can release high-voltage static electricity generated in the thin film transistor array substrate during the manufacturing of the module segment without increasing the manufacturing cost, thereby improving the product. Reliability. DRAWINGS
  • FIG. 1 is a schematic structural view of a conventional thin film transistor array substrate of an electronic paper display device
  • FIG. 2 is a schematic cross-sectional view of a TFT array substrate prepared by a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view of a thin film transistor array substrate of an electronic paper display device according to an embodiment of the present invention.
  • a thin film transistor array substrate includes: an active pixel region and a wiring region, a conductive electrode is formed in the wiring region, and the conductive electrode is grounded, thereby being discharged through the conductive electrode during production of the active device High-voltage static electricity generated on the transistor array substrate improves product reliability.
  • the conductive electrode is formed in a region where there is no pixel electrode pattern in part or all of the wiring region.
  • the conductive electrode may be in the same layer as the pixel electrode.
  • the conductive electrode can be formed in the same preparation process as the pixel electrode by the same material (for example, indium tin oxide ITO) to save cost.
  • the conductive electrode can be formed in a different preparation process from the pixel electrode.
  • the conductive electrode may be formed of a material having no pixel electrode pattern in part or all of the wiring region after forming the pixel electrode by using a material different from the pixel electrode.
  • conductive electrodes are formed over the data line and the scan line peripheral wiring region, the driving IC bonding region, and the wiring region. Therefore, it is possible to better release the high-voltage static electricity generated in the thin film transistor array substrate during the fabrication of the module segment.
  • the present invention also provides a method for fabricating the above-mentioned thin film transistor array substrate, which is consistent with the process of preparing a thin film transistor array substrate such as 4MASK, 5MASK or the like before the preparation of the conductive electrode.
  • the prepared thin film transistor array substrate is as shown in FIG. 2, wherein each layer is deposited, coated with photoresist, exposed by, for example, sputtering or plasma enhanced chemical vapor deposition (PECVD). , developing, etching, and stripping photoresist processes.
  • 2 is a partial cross-sectional view showing the active pixel region 1 and the wiring region 2 of the array substrate.
  • the conductive electrode 108 is mainly shown only in the wiring region 2.
  • the fabrication of the array substrate according to the embodiment of the present invention is not limited to the specific process described above.
  • the method includes the steps of:
  • a gate metal (eg, Mo) layer 102 on the substrate (eg, glass substrate) 101 by sputtering, forming a gate and a storage capacitor pattern from the mask;
  • step S1 depositing a first insulating layer 103, an active layer, and a doping layer 104 on the substrate obtained in step S1 by plasma enhanced chemical vapor deposition (PECVD), and forming an active layer pattern by using a mask;
  • PECVD plasma enhanced chemical vapor deposition
  • a pixel electrode pattern is formed by sputtering deposition of indium tin oxide (ITO) using a pixel electrode mask, which forms a pixel electrode 107, and a conductive electrode 108 is formed in part or all of the wiring region.
  • ITO indium tin oxide
  • Step S5 is:
  • ITO ITO by sputtering, forming a pixel electrode pattern by using a pixel electrode mask, forming a pixel electrode 107, and depositing a conductive electrode 108 in a region having no pixel electrode pattern in part or all of the wiring region, the material of the conductive electrode 108 being The pixel electrode 107 is the same as ITO, or not Same.
  • Embodiments of the present invention also provide any active device including the above-described thin film transistor array substrate, such as a liquid crystal display device, an organic light emitting display (OLED), or an electronic paper display device.
  • a liquid crystal display device such as a liquid crystal display device, an organic light emitting display (OLED), or an electronic paper display device.
  • OLED organic light emitting display
  • This embodiment will be described by taking an electronic paper display device as an example.
  • the electronic paper display device is formed by pairing a thin film transistor array substrate and an electronic paper substrate.
  • the electronic paper substrate comprises: a cover, a common electrode layer, and an electronic ink material layer disposed between the common electrode layer and the thin film transistor array substrate. .
  • the above-mentioned and non-mentioned components constituting the electronic paper display device other than the thin film transistor array substrate are not mentioned here, nor should they be construed as limiting the invention.
  • FIG. 3 is a schematic view showing the structure of an array substrate according to an embodiment of the present invention.
  • the same components as those in Fig. 1 use the same reference numerals.
  • illustration of thin film transistors, data lines, scanning lines, pixel electrodes, and the like is omitted in the active pixel region in Fig. 3.
  • a conductive electrode 108 is formed in a region where the partial wiring region 2 has no pixel electrode, FPC.
  • a grounding terminal is disposed in the bonding area 205, and the conductive electrode 108 is connected to the grounding terminal.
  • the conductive electrode 108 may be separated from the data line, the scan line peripheral routing area, the driver IC bonding area, and the wiring area by an insulating layer.
  • the pixel electrode 107 in the pixel region is separated from certain conductive members (e.g., common electrodes) by an insulating layer such as a passivation layer.
  • the conductive electrode 108 and the pixel electrode 107 are formed in the same layer (or formed synchronously), the conductive electrode 108 may also extend to a portion in the wiring region and a data line in the wiring region and a peripheral line of the scanning line by the insulating layer.
  • the driver IC bonding area and the connection area are separated to avoid affecting their normal work.
  • the embodiment according to the present invention is not limited to the above structure.
  • the conductive electrode 108 may be formed independently of the pixel electrode 107, and the insulating layer for isolation in the wiring region may be independent of, for example, passivation in the pixel region.
  • the insulating layer of the layer is formed separately, and the present invention is not particularly limited thereto.
  • the conductive electrode 108 is grounded by the ground terminal of the bonding region of the flexible circuit board, it is necessary to leave a lead wire in the flexible circuit board region to ground the conductive electrode 108 through the flexible circuit board.
  • the embodiment of the present invention has no particular limitation on the connection form of the conductive electrode 108 and the ground terminal. Various suitable connection forms can be used, and will not be described again here.
  • a thin film transistor array substrate comprising: an active pixel region and a wiring region, wherein a conductive electrode is formed in the wiring region, and the conductive electrode is grounded.
  • the wiring region further includes a flexible circuit board bonding region, the flexible circuit board bonding region is provided with a grounding terminal, and the conductive electrode is The ground terminals are connected.
  • the thin film transistor array substrate according to any one of (1), wherein a pixel electrode is formed in the active pixel region, and the conductive electrode is formed in the same layer as the pixel electrode .
  • the thin film transistor array substrate according to any one of (1), wherein the wiring region is on a periphery of the active pixel region.
  • the thin film transistor array substrate according to any one of (2), further comprising: a data line and a scan line in the active pixel region, and a data line in the wiring area And the scan line peripheral wiring area, the driver IC bonding area, and the connection area,
  • the data line and the scan line in the active pixel area are connected to the data line and the scan line peripheral wiring area in the wiring area, and the data line and the scan line peripheral wiring area are connected to the driving IC,
  • the driver IC is connected to the flexible circuit board bonding area through the connection area.
  • a method of fabricating a thin film transistor array substrate comprising:
  • a conductive electrode is formed in a wiring region located at a periphery of the active pixel region.
  • a display device comprising the thin film transistor array substrate according to any one of (1) to (8).

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明的实施例公开了一种薄膜晶体管阵列基板及其制备方法和显示装置。该薄膜晶体管阵列基板，包括：有源像素区域以及布线区域，其中，所述布线区域内形成有导电电极，所述导电电极接地。该制备方法包括在基板的有源像素区域内形成薄膜晶体管阵列；以及在位于所述有源像素区域外围的布线区域内形成导电电极。

Description

薄膜晶体管阵列基板及其制备方法和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管 （TFT ) 阵列基板及其制备方法和 显示装置。 背景技术
无论何种有源显示器件（液晶显示器、 电子纸显示器等等） 均需要使用 有源矩阵驱动技术。 例如， TFT技术就是实现有源矩阵的一种。 电子纸显示 器通常由薄膜晶体管阵列基板以及电子纸基板对盒而成。 薄膜晶体管阵列基 板负责输入数据信号对图像显示进行控制， 由有源像素区域以及有源像素区 域外围的布线区域组成。 有源像素区域（显示区） 由矩阵形式排列的多个有 源像素单元组成。 每个像素单元为栅线和数据线交叉所形成的矩形区域， 其 内设置 TFT 以及像素电极。 每个 TFT的栅极及源极均分别与栅线及数据线 相连，数据线和扫描线引线至布线区域，分别与数据线驱动 IC以及扫描线驱 动 IC相连。数据线驱动 IC以及扫描线驱动 IC再与外部柔性电路板（ Flexible Printed Circuit, FPC )连接， 以由 FPC为 TFT的栅极及源极提供驱动电压。 如图 1所示， 传统的电子纸显示装置的薄膜晶体管阵列基板包括有源像素区 域 1以及布线区域 2。布线区域 2包括：数据线及扫描线驱动 IC邦定区 202、 数据线及扫描线外围布线区 （fan-out ) 203、 驱动 IC与外部 FPC之间的连线 区 204、 以及 FPC邦定区 205, 驱动 IC邦定区 202用于设置驱动 IC。
在有源显示器件的制备过程中， 薄膜晶体管阵列基板制作完成后至显示 器制作完成前的模组阶段， 薄膜晶体管阵列基板是一直棵露在空气中的。 在 这个阶段中通常会由于摩擦而产生电压高达数千伏的静电， 传导至面板内部 产生高强度的瞬间电流， 这会对面板产生不可修复的破坏。 发明内容
本发明的一个实施例提供一种薄膜晶体管阵列基板， 包括： 有源像素区 域以及布线区域， 其中， 所述布线区域内形成有导电电极， 所述导电电极接 地。
本发明的另一个实施例提供一种薄膜晶体管阵列基板的制备方法，包括: 在基板的有源像素区域内形成薄膜晶体管阵列； 以及在位于所述有源像素区 域外围的布线区域内形成导电电极。
本发明的薄膜晶体管阵列基板及其制备方法、 液晶显示装置、 以及电子 纸显示装置在不增加制造成本的情况下， 可以释放模组段制作期间产生在薄 膜晶体管阵列基板的高压静电， 进而提高产品的可靠性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统的电子纸显示装置薄膜晶体管阵列基板的结构示意图； 图 2为依照本发明一实施方式的薄膜晶体管阵列基板的制备方法制备的 TFT阵列基板的剖面示意图； 以及
图 3为本发明实施例的电子纸显示装置薄膜晶体管阵列基板的结构示意
具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
依照本发明一种实施方式的薄膜晶体管阵列基板包括： 有源像素区域以 及布线区域， 布线区域内形成有导电电极， 且该导电电极接地， 从而通过该 导电电极释放在有源器件制作期间在薄膜晶体管阵列基板上产生的高压静 电， 提高产品的可靠性。 该导电电极形成于部分或全部布线区域内没有像素 电极图形的区域。
在本发明的薄膜晶体管阵列基板中， 导电电极可与像素电极在同一层。 导电电极可与像素电极由同样的材料（例如： 氧化铟锡 ITO )在同一制备过 程中形成， 以节省成本。 或者， 导电电极可与像素电极在不同的制备过程中 形成。 或者， 导电电极可以利用与像素电极不同的材料， 在形成像素电极之 后， 在部分或全部布线区域内没有像素电极图形的区域形成。
在一个实施例中， 在布线区域内， 导电电极形成于数据线和扫描线外围 布线区、驱动 IC邦定区和连线区的上方。 因此， 能够更好地释放模组段制作 期间产生在薄膜晶体管阵列基板的高压静电。
本发明还提供了一种上述薄膜晶体管阵列基板的制备方法， 该方法在制 备导电电极之前的过程与传统的 4MASK、 5MASK等薄膜晶体管阵列基板的 制备工艺的过程一致。 以 5MASK工艺为例， 制备的薄膜晶体管阵列基板如 图 2所示， 其中每一层例如都经过溅射 ( Sputter )或等离子体增强化学气相 沉积（PECVD )方法沉积、 涂覆光刻胶、 曝光、 显影、 刻蚀、 以及剥离光刻 胶工序。 图 2为示出阵列基板有源像素区域 1和布线区域 2的局部截面图。 为了图示的简洁， 仅在布线区域 2主要示出了导电电极 108。 然而， 制造根 据本发明实施例的阵列基板并不限于上述具体工艺。例如，该方法包括步骤：
51. 在基板（例如玻璃基板） 101上利用溅射沉积栅层金属（如 Mo )层 102, 由掩模板形成栅极和存储电容图形；
52. 利用等离子体增强化学气相沉积（PECVD )在步骤 S1得到的基板 上分别沉积第一绝缘层 103、有源层及掺杂层 104,利用掩模板形成有源层图 形；
53. 利用溅射沉积源漏金属（如 Mo )层，利用掩模板形成源漏图形 105；
54. 形成钝化层 106, 并在钝化层中形成过孔； 例如， 该过孔是后面形 成的像素电极与漏极之间的连接路径。
55. 利用溅射沉积铟锡氧化物（ITO ) , 利用像素电极掩模板形成像素电 极图形， 该像素电极图形形成像素电极 107, 并在部分或全部布线区域形成 导电电极 108。 或者：
步骤 S5为：
利用溅射沉积 ITO, 利用像素电极掩模板形成像素电极图形， 形成像素 电极 107 , 再在部分或全部布线区域内没有像素电极图形的区域沉积一层导 电电极 108, 该导电电极 108的材料可与像素电极 107相同为 ITO, 也可不 同。
本发明的实施例还提供包括上述薄膜晶体管阵列基板的任意有源器件， 例如液晶显示装置、 有机发光显示器（OLED )或电子纸显示装置等。
本实施例以电子纸显示装置为例进行说明。
电子纸显示装置由薄膜晶体管阵列基板与电子纸基板对盒而成， 该电子 纸基板依次包括： 封盖、 公共电极层以及配置在该公共电极层与薄膜晶体管 阵列基板之间的电子墨水材料层。 除薄膜晶体管阵列基板之外的构成电子纸 显示装置的必要的上述以及未提到的组成部件在此不做赞述， 也不应作为对 本发明的限制。
图 3示出了根据本发明实施例的阵列基板的结构示意图。 为了能够便于 说明， 与图 1中相同的部件使用了相同的附图标记。 另外， 为了说明的简便， 图 3中的有源像素区域中省略了对薄膜晶体管、 数据线、 扫描线和像素电极 等的图示。 如图 3所示， 本实施例的电子纸显示装置的薄膜晶体管阵列基板 在图 1所示的薄膜晶体管阵列基板的基础上， 在部分布线区域 2没有像素电 极的区域形成有导电电极 108, FPC邦定区 205 内接地端子， 导电电极 108 连接至该接地端子。 对于电子纸显示装置的阵列基板的其他特征， 可以参考 上述对根据本发明实施例的阵列基板的详细描述， 这里不再赘述。
在根据本发明的实施例中， 导电电极 108可以通过一绝缘层与数据线、 扫描线外围布线区、驱动 IC邦定区和连线区隔开。 一般而言，像素区域内的 像素电极 107通过诸如钝化层的绝缘层与某些导电部件（例如公共电极） 隔 开。在导电电极 108与像素电极 107形成于同一层（或同步形成）的情况下， 导电电极 108也可以依靠该绝缘层延伸到布线区域中的部分与布线区域内的 数据线、扫描线外围布线区、驱动 IC邦定区和连线区隔开， 以避免影响它们 的正常工作。 然而， 才艮据本发明的实施例并不限制于上述结构， 例如， 导电 电极 108可以独立于像素电极 107形成， 而布线区域内用于隔离的绝缘层也 可以独立于像素区域内诸如钝化层的绝缘层而单独地形成， 本发明对此没有 特别的限制。
当然，在导电电极 108依靠柔性电路板邦定区的接地端子接地的情况下， 需要在柔性电路板区域为其留下一条引线， 以将导电电极 108通过柔性电路 板接地。本发明实施例对导电电极 108与接地端子的连接形式没有特别限制， 可以使用各种适合的连接形式， 这里不再赘述。
(1)一种薄膜晶体管阵列基板， 包括： 有源像素区域以及布线区域， 其中， 所述布线区域内形成有导电电极， 所述导电电极接地。
(2)如（1)所述的薄膜晶体管阵列基板， 其中， 所述布线区域内还包 括柔性电路板邦定区， 所述柔性电路板邦定区内设置有接地端子， 所述导电 电极与所述接地端子相连。
( 3 )如（ 1 )或（ 2 )所述的薄膜晶体管阵列基板， 其中， 所述导电电极 形成于部分或全部所述布线区域内没有像素电极图形的区域。
(4)如（1) - (3) 中任一项所述的薄膜晶体管阵列基板， 其中， 所述 有源像素区域内形成有像素电极， 所述导电电极与所述像素电极形成在同一 层。
(5)如（1) - (4) 中任一项所述的薄膜晶体管阵列基板， 其中， 所述 导电电极为氧化铟锡电极。
(6)如（1) - (5) 中任一项所述的薄膜晶体管阵列基板， 其中所述布 线区域在所述有源像素区域的外围。
(7)如（2) - (6) 中任一项所述的薄膜晶体管阵列基板， 还包括： 在 所述有源像素区域内的数据线和扫描线， 在所述布线区域内的数据线和扫描 线外围布线区、 驱动 IC邦定区和连线区，
其中所述有源像素区域内的数据线和扫描线与所述布线区域内的数据线 和扫描线外围布线区相连， 所述数据线和扫描线外围布线区与所述驱动 IC 相连， 所述驱动 IC通过所述连线区连接到柔性电路板邦定区。
(8)如（7)所述的薄膜晶体管阵列基板， 其中在所述布线区域内， 所 述导电电极形成于所述数据线和扫描线外围布线区、所述驱动 IC邦定区和所 述连线区的上方。
(9)一种薄膜晶体管阵列基板的制备方法， 包括：
在基板的有源像素区域内形成薄膜晶体管阵列； 以及
在位于所述有源像素区域外围的布线区域内形成导电电极。
( 10 )如（ 9 )所述的薄膜晶体管阵列基板的制备方法， 还包括： 图案化 形成在所述基板上的像素电极薄膜而在所述有源像素区域内形成像素电极的 步骤。
(11)如（10)所述的薄膜晶体管阵列基板的制备方法， 其中形成于所 述布线区域内的导电电极是通过图案化所述像素电极薄膜而与所述像素电极 同步形成。
(12)如（10)所述的薄膜晶体管阵列基板的制备方法， 其中， 所述导 电电极利用与所述像素电极不同的材料形成。
( 13 )如（ 9 ) - ( 12 )中任一项所述的薄膜晶体管阵列基板的制造方法， 还包括在形成所述导电电极之前在所述布线区域内形成数据线和扫描线外围 布线区、驱动 IC邦定区和连线区，其中所述导电电极形成于所述数据线和扫 描线外围布线区、 所述驱动 IC邦定区和所述连线区的上方。
( 14 )一种显示装置， 包括（ 1 ) - ( 8 )中任一项所述的薄膜晶体管阵列 基板。
(15)才艮据 (14)所述的显示装置， 该显示装置为液晶显示器或电子纸 显示器。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管阵列基板， 包括： 有源像素区域以及布线区域， 其中， 所述布线区域内形成有导电电极， 所述导电电极接地。
2、如权利要求 1所述的薄膜晶体管阵列基板， 其中， 所述布线区域内还 包括柔性电路板邦定区， 所述柔性电路板邦定区内设置有接地端子， 所述导 电电极与所述接地端子相连。
3、如权利要求 1或 2所述的薄膜晶体管阵列基板， 其中， 所述导电电极 形成于部分或全部所述布线区域内没有像素电极图形的区域。
4、 如权利要求 1-3中任一项所述的薄膜晶体管阵列基板， 其中， 所述有 源像素区域内形成有像素电极，所述导电电极与所述像素电极形成在同一层。
5、 如权利要求 1-4中任一项所述的薄膜晶体管阵列基板， 其中， 所述导 电电极为氧化铟锡电极。
6、如权利要求 1-5中任一项所述的薄膜晶体管阵列基板， 其中所述布线 区域在所述有源像素区域的外围。
7、 如权利要求 2-6中任一项所述的薄膜晶体管阵列基板， 还包括： 在所 述有源像素区域内的数据线和扫描线， 在所述布线区域内的数据线和扫描线 外围布线区、 驱动 IC邦定区和连线区，
其中所述有源像素区域内的数据线和扫描线与所述布线区域内的数据线 和扫描线外围布线区相连， 所述数据线和扫描线外围布线区与所述驱动 IC 相连， 所述驱动 IC通过所述连线区连接到柔性电路板邦定区。
8、 如权利要求 7所述的薄膜晶体管阵列基板， 其中在所述布线区域内， 所述导电电极形成于所述数据线和扫描线外围布线区、所述驱动 IC邦定区和 所述连线区的上方。
9、 一种薄膜晶体管阵列基板的制备方法， 包括：
在基板的有源像素区域内形成薄膜晶体管阵列； 以及
在位于所述有源像素区域外围的布线区域内形成导电电极。
10、 如权利要求 9所述的薄膜晶体管阵列基板的制备方法， 还包括： 图 案化形成在所述基板上的像素电极薄膜而在所述有源像素区域内形成像素电 极的步骤。
11、如权利要求 10所述的薄膜晶体管阵列基板的制备方法，其中形成于 所述布线区域内的导电电极是通过图案化所述像素电极薄膜而与所述像素电 极同步形成。
12、如权利要求 10所述的薄膜晶体管阵列基板的制备方法， 其中， 所述 导电电极利用与所述像素电极不同的材料形成。
13、 如权利要求 9-12中任一项所述的薄膜晶体管阵列基板的制造方法， 还包括在形成所述导电电极之前在所述布线区域内形成数据线和扫描线外围 布线区、驱动 IC邦定区和连线区，其中所述导电电极形成于所述数据线和扫 描线外围布线区、 所述驱动 IC邦定区和所述连线区的上方。
14、 一种显示装置， 包括权利要求 1-8中任一项所述的薄膜晶体管阵列 基板。
15、根据权利要求 14所述的显示装置，该显示装置为液晶显示器或电子 纸显示器。
PCT/CN2012/087232 2012-03-20 2012-12-23 薄膜晶体管阵列基板及其制备方法和显示装置 WO2013139158A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/994,080 US8963160B2 (en) 2012-03-20 2012-12-23 Thin film transistor array substrate, manufacturing method thereof and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210074046.9 2012-03-20
CN2012100740469A CN102655148A (zh) 2012-03-20 2012-03-20 Tft基板及其制备方法、液晶显示装置、及电子纸显示装置

Publications (1)

Publication Number Publication Date
WO2013139158A1 true WO2013139158A1 (zh) 2013-09-26

Family

ID=46730746

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/087232 WO2013139158A1 (zh) 2012-03-20 2012-12-23 薄膜晶体管阵列基板及其制备方法和显示装置

Country Status (3)

Country Link
US (1) US8963160B2 (zh)
CN (1) CN102655148A (zh)
WO (1) WO2013139158A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655148A (zh) 2012-03-20 2012-09-05 京东方科技集团股份有限公司 Tft基板及其制备方法、液晶显示装置、及电子纸显示装置
CN104091819B (zh) * 2014-06-30 2018-02-13 京东方科技集团股份有限公司 一种显示基板及显示装置
CN104716198B (zh) * 2015-03-25 2018-03-27 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示装置
CN107210534B (zh) * 2015-10-09 2018-10-09 夏普株式会社 Tft基板、使用该tft基板的扫描天线以及tft基板的制造方法
CN107799072B (zh) * 2016-09-07 2020-08-11 元太科技工业股份有限公司 电子纸显示器装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283677A (en) * 1991-05-31 1994-02-01 Alps Electric Co., Ltd. Liquid crystal display with ground regions between terminal groups
CN1963600A (zh) * 2005-11-10 2007-05-16 群康科技(深圳)有限公司 液晶显示面板
CN101093297A (zh) * 2006-06-23 2007-12-26 中华映管股份有限公司 液晶显示器的静电防护电路
CN101211051A (zh) * 2006-12-27 2008-07-02 爱普生映像元器件有限公司 液晶显示装置
CN102655148A (zh) * 2012-03-20 2012-09-05 京东方科技集团股份有限公司 Tft基板及其制备方法、液晶显示装置、及电子纸显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008203761A (ja) 2007-02-22 2008-09-04 Hitachi Displays Ltd 表示装置
JP2011203341A (ja) * 2010-03-24 2011-10-13 Hitachi Displays Ltd 表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283677A (en) * 1991-05-31 1994-02-01 Alps Electric Co., Ltd. Liquid crystal display with ground regions between terminal groups
CN1963600A (zh) * 2005-11-10 2007-05-16 群康科技(深圳)有限公司 液晶显示面板
CN101093297A (zh) * 2006-06-23 2007-12-26 中华映管股份有限公司 液晶显示器的静电防护电路
CN101211051A (zh) * 2006-12-27 2008-07-02 爱普生映像元器件有限公司 液晶显示装置
CN102655148A (zh) * 2012-03-20 2012-09-05 京东方科技集团股份有限公司 Tft基板及其制备方法、液晶显示装置、及电子纸显示装置

Also Published As

Publication number Publication date
US8963160B2 (en) 2015-02-24
US20140077301A1 (en) 2014-03-20
CN102655148A (zh) 2012-09-05

Similar Documents

Publication Publication Date Title
US10002847B2 (en) OLED pixel unit, transparent display device, method for fabricating the same, display apparatus
CN105161505B (zh) 一种阵列基板及其制作方法、显示面板
KR102080065B1 (ko) 박막 트랜지스터 어레이 기판 및 그 제조 방법
EP2782153B1 (en) Display device, thin film transistor, array substrate and manufacturing method thereof
WO2018176896A1 (zh) 静电放电单元、阵列基板和显示面板
US9825069B2 (en) Array substrate manufacturing method
WO2017071233A1 (zh) 制作阵列基板的方法和阵列基板
JP2013187536A (ja) アレイ基板及びその製造方法
US10355064B2 (en) AMOLED display substrate, method for fabricating the same and display device
US11233106B2 (en) Array substrate, display apparatus, and method of fabricating array substrate
US20160254275A1 (en) Array substrate and manufacturing method thereof, and display device
WO2013139158A1 (zh) 薄膜晶体管阵列基板及其制备方法和显示装置
US20160027797A1 (en) Array substrate, manufacturing method thereof, and display device
JP2010061095A (ja) 薄膜トランジスタ表示板及びその製造方法
US7768590B2 (en) Production method of active matrix substrate, active matrix substrate, and liquid crystal display device
US20200348784A1 (en) Touch display substrate, method of manufacturing the same and display device
US9230995B2 (en) Array substrate, manufacturing method thereof and display device
TW201411829A (zh) 有機電致發光顯示器及其製造方法
KR20140013166A (ko) 유기발광소자표시장치 및 그 제조방법
KR20130062122A (ko) 어레이 기판 및 이의 제조방법
WO2019047574A1 (zh) 阵列基板及其制作方法、显示装置
US8519393B2 (en) Thin film transistor array panel and manufacturing method thereof
CN102460548B (zh) 电流驱动像素电路及相关方法
WO2015085718A1 (zh) 阵列基板及其制作方法、显示装置
KR102059321B1 (ko) 액정 디스플레이 장치와 이의 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13994080

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12872159

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC - FORM 1205A (22.01.2015)

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC - FORM 1205A (24.02.2015)

122 Ep: pct application non-entry in european phase

Ref document number: 12872159

Country of ref document: EP

Kind code of ref document: A1