WO2013136857A1 - Système de traitement de données, circuit intégré semi-conducteur, et procédé de commande associé - Google Patents

Système de traitement de données, circuit intégré semi-conducteur, et procédé de commande associé Download PDF

Info

Publication number
WO2013136857A1
WO2013136857A1 PCT/JP2013/051539 JP2013051539W WO2013136857A1 WO 2013136857 A1 WO2013136857 A1 WO 2013136857A1 JP 2013051539 W JP2013051539 W JP 2013051539W WO 2013136857 A1 WO2013136857 A1 WO 2013136857A1
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
memory
data
memory block
processing unit
Prior art date
Application number
PCT/JP2013/051539
Other languages
English (en)
Japanese (ja)
Inventor
正吾 中谷
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2014504730A priority Critical patent/JP6115564B2/ja
Publication of WO2013136857A1 publication Critical patent/WO2013136857A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G06F9/3881—Arrangements for communication of instructions and data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Definitions

  • the present invention relates to a data processing system, a semiconductor integrated circuit, and a control method thereof.
  • a data processing system that processes data using a CPU (Central Processing Unit)
  • CPU Central Processing Unit
  • a method is widely used in which another circuit having an appropriate processing performance takes over.
  • offloading out of data processing to be processed by the CPU, performing specific data processing on behalf of another circuit is referred to as offloading.
  • a circuit that performs processing in place of the CPU is referred to as an offloader.
  • Data processing performed by the offloader is referred to as offload processing.
  • a general purpose offloader what can perform various data processing efficiently among offloaders.
  • FIG. 1 is a diagram showing a main configuration of a data processing system including a general-purpose offloader disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2006-338538) and Patent Document 2 (Japanese Patent Laid-Open No. 2007-034392). is there.
  • the data processing system shown in FIG. 1 includes a CPU 10, a memory 20, a general-purpose offloader 30, and a peripheral block 90 connected via a system bus 70.
  • circuits other than the CPU 10, the memory 20, and the general-purpose offloader 30 are collectively shown as a peripheral block 90.
  • Specific examples of the peripheral block 90 include an input / output circuit.
  • CPU 10 reads data from memory 20, performs data processing, and writes the processing result to memory 20.
  • the general-purpose offloader 30 performs specific data processing in place of the CPU 10 among data processing to be processed by the CPU 10.
  • the data processing performed by the CPU 10 and the data processing performed by the general-purpose offloader 30 are defined in advance by a program or the like.
  • a request for data processing defined as being performed by the CPU 10 is input via an input / output circuit (not shown)
  • the data processing is performed by the CPU 10 and the data defined as being performed by the general-purpose offloader 30
  • the general-purpose offloader 30 performs data processing.
  • FIG. 2 is a block diagram showing an example of the configuration of the general-purpose offloader 30. As shown in FIG.
  • the general-purpose offloader 30 includes an input FIFO (First-In First-Out) circuit 31, a data processing accelerator 50, an output FIFO circuit 33, a local memory 34, and a controller 39.
  • FIFO First-In First-Out
  • the input FIFO circuit 31 outputs the input data to the data processing accelerator 50 in the order of input.
  • the data processing accelerator 50 is a versatile and highly efficient processing circuit, and includes an array processor and a reconfigurable circuit.
  • the data processing accelerator 50 performs data processing using the data input from the input FIFO circuit 31 and outputs a processing result.
  • the output FIFO circuit 33 continuously outputs the data processing result input from the data processing accelerator 50 independently of the input FIFO circuit 31.
  • the local memory 34 is provided in order for the data processing accelerator 50 to perform data processing efficiently, and is accessed from the data processing accelerator 50 as needed.
  • FIG. 2 shows an example in which there is one local memory 34, a plurality of local memories 34 may be provided.
  • the controller 39 is a DMA (Direct Memory) that performs data transfer via the system bus 70 between the memory 20 and the input FIFO circuit 31 (not shown in FIG. 2) and between the memory 20 and the output FIFO circuit 33. Access) circuit, and controls data transfer.
  • DMA Direct Memory
  • a typical example of data processing that can be processed with high efficiency by the data processing accelerator 50 is streaming processing.
  • the streaming process is a process in which data input and data processing result output are performed simultaneously and continuously. Even when complicated processing is required, data is input continuously from the input FIFO circuit 31 to the data processing accelerator 50, and data processing results by the data processing accelerator 50 are output continuously from the output FIFO circuit 33. Can be realized.
  • the data transfer overhead increases.
  • the controller 39 including the DMA circuit is provided, the circuit scale overhead increases.
  • the overhead of data transfer and circuit scale increases, there arises a problem that processing time, circuit area, power consumption and the like increase.
  • the increase in processing time, circuit area, power consumption, etc. due to overhead as described above is relatively small and does not cause much problem.
  • MCU Micro Control Unit
  • An object of the present invention relates to a data processing system, a semiconductor integrated circuit, and a control method thereof that can reduce data transfer and circuit scale overhead.
  • the data processing system of the present invention provides: A first data processing unit for performing data processing; Of the data processing to be processed by the first data processing unit, a second data processing unit that performs specific data processing instead of the first data processing unit; A memory comprising at least first and second memory blocks; In the first operation mode, the first data processing unit accesses all the memory blocks included in the memory as one memory having a continuous address space, reads and writes data associated with the data processing, In the second operation mode, it is stopped.
  • the second data processing unit is stopped in the first operation mode, and in the second operation mode, the first memory block is a read-only memory, and the second data processing unit
  • the memory block is a write-only memory, data is read from the first memory block, the specific data processing is performed, and the result of the specific data processing is written to the second memory block.
  • a semiconductor integrated circuit of the present invention includes: A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit A memory comprising at least first and second memory blocks;
  • the first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks included in the memory, and performs a second operation. In the mode, it will be stopped.
  • the second processing unit is in a stopped state in the first operation mode, and in the second operation mode, the first memory block is a read-only memory and the second memory
  • the block is used as a write-only memory, data is read from the first memory block, the specific data processing is performed, and the result of the specific data processing is written to the second memory block.
  • a method for controlling a semiconductor integrated circuit includes: A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit
  • a method for controlling a semiconductor integrated circuit comprising: a memory including at least first and second memory blocks, In the first operation mode, The first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks provided in the memory, The second processing unit is stopped, In the second mode of operation, The first processing unit is stopped, The second processing unit sets the first memory block as a read-only memory, sets the second memory block as a write-only memory, reads data from the first memory block, and reads the specific memory block. Data processing is performed, and the result of the specific data processing is written into the second memory block.
  • FIG. 8 is a block diagram illustrating a configuration of a read circuit illustrated in FIG. 7.
  • FIG. 8 is a block diagram illustrating a configuration of a writing circuit illustrated in FIG. 7.
  • FIG. 3 is a block diagram showing the configuration of the data processing system according to the embodiment of the present invention. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
  • the 3 includes a CPU 10, a memory 20, a coupler 40, a data processing accelerator 50, a system bus 70, and a peripheral block 90.
  • the CPU 10 is an example of a first data processing unit
  • the data processing accelerator 50 is an example of a second data processing unit.
  • the memory 20, the coupler 40, and the data processing accelerator 50 constitute a general-purpose accelerator.
  • the memory 20 includes a plurality of memory blocks incorporating a memory cell array.
  • FIG. 3 shows an example in which the memory 20 includes two memory blocks. A 1-port memory is used as the memory block.
  • the combiner 40 combines a plurality of memory blocks provided in the memory 20 as one memory having a continuous address space.
  • the data processing accelerator 50 accesses the memory 20 via the coupler 40 and performs specific data processing on behalf of the CPU 10 among data processing to be processed by the CPU 10.
  • the data processing performed by the CPU 10 and the data processing performed by the data processing accelerator 50 are defined in advance by a program or the like.
  • a request for data processing defined as being performed by the CPU 10 is input via an input / output circuit (not shown)
  • the data processing is performed by the CPU 10 and the data processing accelerator 50 is defined as performing.
  • the data processing accelerator 50 performs data processing.
  • the system bus 70 connects the CPU 10, the coupler 40, and the peripheral circuit 90.
  • the data processing system 1 includes first and second operation modes.
  • the CPU 10 accesses the memory 20 via the coupler 40 and performs data processing.
  • the memory 20 includes a plurality of memory blocks, but the combiner 40 combines the plurality of memory blocks as one memory having a continuous address space.
  • the CPU 10 accesses the memory 20 as one memory having a continuous address space, and reads / writes data associated with data processing.
  • the data processing accelerator 50 is in a stopped state in the first operation mode.
  • the data processing accelerator 50 accesses the memory 20 via the coupler 40 and performs specific data processing in place of the CPU 10 among the data processing to be processed by the CPU 10.
  • the data processing accelerator 50 performs data processing by accessing each memory block included in the memory 20 as an independent memory.
  • the CPU 10 is in a stopped state in the second operation mode.
  • data processing is performed while switching between the first operation mode and the second operation mode.
  • first operation mode input data to be processed by the data processing accelerator 50 is held at an appropriate address in the memory 20.
  • second operation mode the input data held at an appropriate address is processed by the data processing accelerator 50, and the processing result is held at the appropriate address in the memory 20.
  • the CPU 10 can access the processing result of the data processing accelerator held at the appropriate address of the memory 20.
  • the input data and the processing result by the data processing accelerator 50 are held in different memory blocks.
  • FIG. 4 is a block diagram showing the internal configuration of the memory 20 and the coupler 40.
  • the memory 20 includes three memory blocks 21-1 to 21-3 each including a memory cell array.
  • the coupler 40 includes multiplexers 41-1, 41-2, 41-3, 42-2, and 42-3, and an output selector 45.
  • the memory 20 may include two or four or more memory blocks. If the memory 20 includes two memory blocks, the memory 20 includes a memory block 21-1 and a memory block 21-3.
  • an address / control signal 71 is input to the multiplexers 41-1, 41-2, 41-3 and the output selector 45 via a system bus 70 (not shown).
  • the write data signal 72 is input to the DI terminal of the memory block 21-1 and the multiplexers 42-2 and 42-3.
  • the mode signal 74 is input to the multiplexers 41-1, 41-2, 42-2, 41-3, 42-3, the output selector 45, and the data processing accelerator 50.
  • the address / control signal 71 includes an address signal indicating the address of the memory cell to be accessed and a control signal indicating the control input.
  • the write data signal 72 is a signal indicating data to be held in the memory block.
  • the mode signal 74 is a signal indicating the operation mode of the data processing system 1.
  • the data processing accelerator 50 inputs the address / control signals 51-1, 51-2, 51-3 to the multiplexers 41-1, 41-2, 41-3, respectively.
  • the data processing accelerator 50 inputs data signals 52-2 and 52-3 indicating the results of the data processing to the multiplexers 42-2 and 42-3, respectively. Further, when the data processing is completed, the data processing accelerator 50 inputs a data processing end signal 75 to the CPU 10 via the system bus 70.
  • Each of the memory blocks 21-1 to 21-3 has an address / control terminal (AC terminal), a data read terminal (DO terminal), and a data write terminal (DI terminal).
  • Each of the memory blocks 21-1 to 21-3 holds data input to the DI terminal in accordance with an address / control signal input from the AC terminal.
  • the memory block 21-1 outputs the held data from the data DO terminal as the data signal 53-1 to the output selector 45 and the data processing accelerator 50 in accordance with the address / control signal input from the AC terminal.
  • the memory block 21-2 outputs the held data from the DO terminal to the output selector 45 and the data processing accelerator 50 as the data signal 53-2 in accordance with the address / control signal input from the AC terminal.
  • the memory block 21-3 outputs the held data from the DO terminal to the output selector 45 as the data signal 53-3 in accordance with the address / control signal input from the AC terminal.
  • the multiplexer 41-1 selects either the address / control signal 71 input via the system bus 70 or the address / control signal 51-1 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-1.
  • the multiplexer 41-2 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-2 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-2.
  • the multiplexer 42-2 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-2 input from the data processing accelerator 50 according to the operation mode to the memory block 21-2. Input to the DI terminal.
  • the multiplexer 41-3 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-3 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-3.
  • the multiplexer 42-3 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-3 input from the data processing accelerator 50 according to the operation mode to the memory block 21-3. Input to the DI terminal.
  • the output selector 45 outputs one of the data signals 53-1, 53-2, and 53-3 as the read data signal 73 to the system bus 70 or outputs the read data signal 73 according to the operation mode. Stop.
  • the CPU 10 enters an operation state, and inputs an address / control signal 71 and a write data signal 72 to the coupler 40 via the system bus 70 in accordance with data processing.
  • the data processing accelerator 50 is stopped. Therefore, the value of the data processing end signal 75 is don't care.
  • the multiplexer 41-1 inputs an address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-1.
  • the multiplexer 41-2 inputs an address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-2.
  • the multiplexer 41-3 inputs an address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-3.
  • the address / control signal 71 includes an address signal and a control signal.
  • control signals include a data write enable signal WE, a data read enable signal RE, and an output enable signal OE that controls the input / output mode of the memory block.
  • control signals include a data write enable signal WE, a data read enable signal RE, and an output enable signal OE that controls the input / output mode of the memory block.
  • various memory block control methods such as a method in which the data write enable signal WE and the data read enable signal RE are combined into one signal in an inverted logic relationship, the present invention controls the memory block. It does not depend on the difference in method.
  • the remaining memory blocks are in a non-selected state in which reading and writing are not performed.
  • a specific address in the memory block 21-k is designated by lower bits other than the upper two bits of the address signal.
  • the multiplexer 42-2 inputs the write data signal 72 input via the system bus 70 to the DI terminal of the memory block 21-2.
  • the multiplexer 42-3 inputs the write data signal 72 input via the system bus 70 to the DI terminal of the memory block 21-3.
  • the memory block 21-k selects the data held at the address indicated by the lower bits other than the upper 2 bits of the address signal as the data signal 53-k. Input to the device 45.
  • the output selector 45 outputs the input data signal 53-k to the system bus 70 as a read data signal 73.
  • the read data signal 73 is input to the CPU 10 via the system bus 70.
  • the plurality of memory blocks included in the memory 20 are accessed from the system bus 70 and eventually the CPU 10 as one memory having a continuous address space.
  • the CPU 10 In the second operation mode, the CPU 10 is stopped.
  • the data processing accelerator 50 enters an operating state, and inputs the address / control signals 51-1, 51-2, 51-3 to the multiplexers 41-1, 41-2, 41-3, respectively, according to the data processing.
  • the data signals 52-2 and 52-3 are input to the multiplexers 42-2 and 42-3, respectively.
  • the multiplexer 41-1 inputs the address / control signal 51-1 input from the data processing accelerator 50 to the AC terminal of the memory block 21-1.
  • the multiplexer 41-2 inputs the address / control signal 51-2 input from the data processing accelerator 50 to the AC terminal of the memory block 21-2.
  • the multiplexer 41-3 inputs the address / control signal 51-3 input from the data processing accelerator 50 to the AC terminal of the memory block 21-3.
  • the memory block 21-1 becomes read-only according to the input of the address / control signal 51-1, and the memory block 21-3 becomes write-only according to the input of the address / control signal 51-3.
  • the memory block 21-1 outputs the data held at the address indicated by the address signal from the DO terminal to the data processing accelerator 50 as the data signal 53-1.
  • the data processing accelerator 50 performs data processing using the data signal 53-1, and outputs a data signal 52-3 indicating the processing result to the multiplexer 42-3.
  • the multiplexer 42-3 inputs the data signal 52-3 to the DI terminal of the memory block 21-3.
  • the memory block 21-3 holds the data indicated by the data signal 52-3 input from the multiplexer 42-3 at the address indicated by the address signal input from the multiplexer 41-3.
  • the data processing accelerator 50 performs the streaming process with high efficiency by continuously reading data from the memory block 21-1 and writing data into the memory block 21-3 independently. Can do.
  • the memory block 21-2 is addressed and controlled independently from other memory blocks by the address / control signal 51-2 from the data processing accelerator 50. That is, in the memory block 21-2, the data processing accelerator 50 appropriately reads out data from the memory block 21-2 or writes data into the memory block 21-2.
  • the work local memory may not be provided, or a plurality of independent work local memories may be provided.
  • the output selector 45 does not output the data read signal 73. At this time, if the output of the output selector 45 needs to be high impedance due to the specifications of the system bus 70, an output selector conforming to such specifications is used. In this case, in the second operation mode, the output of the output selector 45 is in a high impedance state. In the first operation mode, the output selector 45 outputs one of the input data signals.
  • the logical value of the data processing end signal 75 is set to the second logical value, and when the data processing is completed, the logical value of the data processing end signal 75 is set to the first logical value. Transition.
  • the logical value of the data processing end signal 75 changes from the second logical value to the first logical value
  • the logical value of the mode signal 74 changes from the second logical value to the first logical value.
  • the transition of the logical value of the mode signal 74 from the first logical value to the second logical value is, for example, to the memory block 21-1 by the CPU 10 of data necessary for the data processing accelerator 50 to perform data processing. This is done when writing is completed.
  • the CPU 10 and the data processing accelerator 50 share the memory 20.
  • the CPU 10 accesses a plurality of memory blocks included in the memory 20 as one memory having a continuous address space to perform data processing, and the data processing accelerator 50 is stopped.
  • the data processing accelerator 50 accesses each memory block as each of the plurality of memory blocks provided in the memory 20 as an independent memory block, and performs data processing. .
  • FIG. 5 is a diagram showing the states of the mode signal and the data processing end signal in the first and second operation modes, and the states of the CPU 10, the data processing accelerator 50, and the memory 20.
  • the operation mode is the first operation mode.
  • the data processing accelerator 50 is stopped, and the value of the data processing end signal output from the data processing accelerator 50 is don't care. Further, the CPU 10 enters an operating state, and accesses a plurality of memory blocks provided in the memory 20 as one memory having a continuous address space.
  • the logic value of the mode signal transitions from the first logic value to the second logic value.
  • the logic value of the mode signal changes from the first logic value to the second logic value.
  • the operation mode transitions to the second operation mode.
  • the CPU 10 is stopped.
  • the data processing accelerator 50 enters an operating state and changes the logical value of the data processing end signal from the first logical value (Low) to the second logical value (High).
  • the data processing accelerator 50 accesses a plurality of memory blocks provided in the memory 20 as independent memory blocks.
  • the data processing accelerator 50 changes the logical value of the data processing end signal from the first logical value to the second logical value.
  • the logic value of the mode signal transits from the second logic value to the first logic value, and at time t3, the first logic value changes. Transition to operation mode. Thereafter, although not shown in FIG. 5, at the time t4, the second operation mode is set again, and the first operation mode and the second operation mode are repeated.
  • the CPU 10 and the data processing accelerator 50 share the memory 20.
  • the CPU 10 accesses a plurality of memory blocks included in the memory 20 as one memory having a continuous address space, and the data processing accelerator 50 is in a stopped state.
  • the CPU 10 is stopped, and the data processing accelerator 50 accesses each memory block by setting each of the plurality of memory blocks included in the memory 20 as independent memory blocks.
  • a dedicated memory for general-purpose offloader is not required, so that the circuit area and power consumption for the dedicated memory can be reduced.
  • data transfer between the memory used by the CPU and the dedicated memory of the general-purpose offloader becomes unnecessary, an increase in processing time and power consumption associated with data transfer can be suppressed.
  • the circuit area can be reduced.
  • the data processing accelerator 50 makes one memory block read-only among a plurality of memory blocks and another one memory block in the second operation mode. Write only.
  • the memory block can be a one-port memory by separating the input-only memory block and the output-only memory block. Therefore, an inexpensive memory block can be used, and cost reduction can be achieved. Furthermore, when the general-purpose offloader (data processing accelerator) accesses the memory, the circuit configuration can be simplified and the cost can be reduced as compared with the case where all the memory blocks are read / writeable memory blocks.
  • the data processing system according to the second embodiment of the present invention differs from the data processing system 1 according to the first embodiment in the configuration of the coupler 40 and the memory block. Therefore, below, it demonstrates focusing on these structures.
  • FIG. 6 is a block diagram showing the configuration of the memory 20 and the coupler 40 of this embodiment.
  • the same components as those in FIG. 6 are identical components as those in FIG. 6
  • the memory 20 includes at least two memory blocks 21-10 and 21-30.
  • the memory 20 will be described using an example including two memory blocks.
  • the present invention is not limited to this, and the memory 20 may include three or more memory blocks as in the first embodiment. Good. Even when the memory 20 includes three or more memory blocks, the memory blocks other than the memory blocks 21-10 and 21-30 are incorporated in the same manner as in the first embodiment. Therefore, in FIG. 6, the description of the memory blocks other than the memory blocks 21-10 and 21-30 is omitted.
  • the coupler 40 includes multiplexers 41-1, 41-3, 42-0, 43, an output selector 45-2, an OR circuit 49, and buffers 220, 230.
  • the address / control signal 71 is input to the multiplexers 41-1 and 41-3, the output selector 45-2, and the OR circuit 49 via the system bus 70 (not shown).
  • the write data signal 72 is input to the multiplexer 42-0.
  • the mode signal 74 is input to the multiplexers 41-1, 41-3, 42-0, the output selector 45-2, the OR circuit 49, and the data processing accelerator 50.
  • the data processing accelerator 50 inputs the address / control signals 51-1 and 51-3 to the multiplexers 41-1 and 41-3, respectively. Further, the data processing accelerator 50 inputs the data signal 52-3 to the multiplexer 42-0.
  • the multiplexer 41-1 selects either the address / control signal 71 input via the system bus 70 or the address / control signal 51-1 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-10.
  • the multiplexer 41-3 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-3 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-30.
  • the multiplexer 42-0 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-3 input from the data processing accelerator 50 to the buffer 230 according to the operation mode.
  • the multiplexer 43 buffers either the output from the DO terminal of the memory block 21-10 or the output from the DO terminal of the memory block 21-30 in accordance with the logical value of the signal input from the OR circuit 49. Output to.
  • the OR circuit 49 calculates the logical sum of the address / control signal 71 and the mode signal 74 input via the system bus 70, and outputs the calculation result to the multiplexer 43.
  • the buffer 230 buffers the output of the multiplexer 42-0 and inputs it as a data signal 52 to the DI terminals of the memory block 21-10 and the memory block 21-30.
  • the buffer 220 buffers the output of the multiplexer 43 and inputs it to the output selector 45-2 and the data processing accelerator 50 as the data signal 53-1.
  • the output selector 45-2 reads either the data signal 53-1 output from the buffer 220 or the data signal 53-2 input from the DO terminal of another memory block (not shown in FIG. 6). The result is output to the system bus 70 as 73.
  • FIG. 7 is a block diagram showing a configuration of a general memory block 21.
  • the memory block 21 includes a read circuit 22 used for reading data from the memory cell array, and a write circuit 23 used for writing data to the memory cell array. Whether data is read or written is determined by a control signal included in the address / control signal.
  • FIG. 8 is a block diagram showing a configuration of the read circuit 22 shown in FIG.
  • the switch 221 receives the data read enable signal RE and enters a conductive state or a cut-off state depending on the logical value of the data read enable signal RE.
  • the data read enable signal RE becomes the first logical value in the read mode, and the switch 221 becomes conductive when the logical value of the data read enable signal RE is the first logical value.
  • the sense amplifier 222 amplifies the signal from the memory cell input via the switch 221 and outputs the amplified signal to the output buffer 223.
  • the output buffer 223 buffers the signal input from the sense amplifier 222 and outputs it to the DO terminal.
  • FIG. 9 is a block diagram showing a configuration of the write circuit 23 shown in FIG.
  • the write circuit 23 shown in FIG. 9 has an input buffer 231, a write buffer 232, and a switch 233.
  • the input buffer 231 buffers the data input signal input to the DI terminal and outputs it to the write buffer 232.
  • the write buffer 232 buffers the data input from the input buffer 231 and outputs it to the switch 233.
  • the switch 233 is supplied with the data write enable signal WE and enters a conductive state or a cut-off state according to the logical value of the data write enable signal WE.
  • the data write enable signal WE has a first logical value in the write mode, and the switch 233 becomes conductive when the logical value of the data write enable signal WE is the first logical value.
  • the switch 233 becomes conductive, the signal output from the write buffer 232 is written into the memory cell array.
  • the switch 221 and the switch 233 are generally switches composed of pass transistors and transmission gates.
  • the switches 221 and 233 are cut off when the logical values of the data read enable signal RE and the data write enable signal WE are the second logical value.
  • the data read enable signal RE and the data write enable signal WE are in a logically inverted relationship.
  • the memory blocks 21-10 and 21-30 do not have the sense amplifier 222 and the output buffer 223 shown in FIG. 8, and the input buffer 231 and the write buffer 232 shown in FIG.
  • the buffer 230 shown in FIG. 6 functions as a write buffer and an input buffer for the memory block 21-10 and the memory block 21-30
  • the buffer 220 senses the memory block 21-10 and the memory block 21-30. Functions as an amplifier and output buffer.
  • the first logical value of the mode signal 74 is 0 and the second logical value is 1.
  • the address / control signal 71 input from the system bus 70 is input to the AC terminal of the memory block 21-10 via the multiplexer 41-1, and the memory block via the multiplexer 41-3. Input to AC terminal 21-30.
  • the write data signal 72 input from the system bus 70 is input to the buffer 230 via the multiplexer 42-0.
  • the buffer 230 inputs the data signal 52 to the DI terminals of the memory block 21-10 and the memory block 21-30 in accordance with the input from the multiplexer 42-0. If there is a memory block in the write mode by the input of the address / control signal 71, the data signal 52 is held in the memory block.
  • the buffer 230 is shared as a writing circuit for the memory block 21-10 and the memory block 21-30. However, since only one memory block is in the writing mode at a certain time, the memory 230 The block 21-10 and the memory block 21-30 can share the buffer 230 as a writing circuit.
  • the OR circuit 49 calculates the logical sum of the address / control signal 71 and the mode signal 74 and outputs the calculation result to the multiplexer 43.
  • the address / control signal 71 includes a 1-bit signal for distinguishing between the memory block 21-10 and the memory block 21-30. Since the logical value of the mode signal is 0, the OR circuit 49 outputs a signal having the same logical value as the 1-bit signal that distinguishes the memory block 21-10 and the memory block 21-30 included in the address / control signal 71. Output to the multiplexer 43.
  • the multiplexer 43 sends the signal output from the DO terminal of one of the memory blocks 21-10 and 21-30 to the buffer 220 according to the logical value of the signal input from the OR circuit 49. Output.
  • the multiplexer 43 is a passive multiplexer composed of, for example, a pass transistor or a transmission gate, and does not have a buffering function.
  • the buffer 220 amplifies a weak signal input from the memory cell array of the memory block 21-10 or the memory block 21-30 via the DO terminal and the multiplexer 43, and outputs it to the output selector 45-2 as the data signal 53-1. Output.
  • the output selector 45-2 receives data according to the logical value of the address / control signal 71. Either one of the signal 53-1 and the data signal 53-2 is output as a read signal 73.
  • the buffer 220 is shared as a read circuit for the memory block 21-10 and the memory block 21-30. However, since only one memory block is in the read mode at a certain time, the memory 220 The block 21-10 and the memory block 21-30 can share the buffer 220 as a read circuit.
  • the multiplexer 41-1 inputs the address / control signal 51-1 output from the data processing accelerator 50 to the AC terminal of the memory block 21-10.
  • the memory block 21-10 is read-only.
  • the multiplexer 41-3 inputs the address / control signal 51-3 output from the data processing accelerator 50 to the AC terminal of the memory block 21-30.
  • the memory block 21-30 is dedicated to writing.
  • the output from the DO terminal of the memory block 21-10 is input to the multiplexer 43, and the multiplexer 43 outputs the signal output from the DO terminal of the memory block 21-10 to the buffer 220.
  • the buffer 220 amplifies the signal input from the multiplexer 43 and outputs it to the data processing accelerator 50 as the data signal 53-1.
  • the multiplexer 42-0 outputs the data signal 52-3 output from the data processing accelerator 50 to the buffer 230.
  • the buffer 230 buffers the signal input from the multiplexer 42-0, and outputs it as a data signal 52 to the memory buffer 21-10 and the memory buffer 21-30.
  • the data signal 52 output from the buffer 230 is held in the memory block 21-30. .
  • the memory block 21-10 and the memory block 21-30 share the buffer 230 as a writing circuit and share the buffer 220 as a reading circuit.
  • the memory block 21-10 is read-only and the memory block 21-30 is write-only. Therefore, the memory block 21-10 and the memory block 21-30 share the buffer 220 as a read circuit. can do.
  • the memory block 21-10 and the memory block 21-30 are read from the memory cell array and the write circuit for writing in the memory cell array incorporated therein. And a readout circuit for performing.
  • the circuit area can be reduced as compared with the case where a write circuit and a read circuit are provided in each of the plurality of memory blocks.
  • the circuit area can be reduced as compared with the case where a write circuit and a read circuit are provided in each of the plurality of memory blocks.
  • the memory capacity is small, the area ratio indicated by the writing circuit and the reading circuit is relatively large. Therefore, the writing circuit and the reading circuit are used in a plurality of memory blocks. By sharing the circuit, the effect of reducing the circuit area is increased.
  • the components such as the CPU 10, the general-purpose offloader (data processing accelerator 50), the peripheral block 90, and the system bus 70 are corrected to one semiconductor integrated circuit. It is not essential. However, when the general-purpose offloader including the memory 20 and the data processing accelerator 50 is integrated in one semiconductor integrated circuit, the CPU 10 and the system bus 70 are also integrated in the same semiconductor integrated circuit. The invention can achieve a greater effect.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un dispositif de traitement de données comprenant : une première unité de traitement de données qui effectue un traitement de données ; une seconde unité de traitement de données qui effectue un traitement de données spécifique, parmi le traitement des données devant être traité par la première unité de traitement de données, à la place de la première unité de traitement de données ; et une mémoire pourvue d'un premier et d'un second blocs de mémoire. Dans un premier mode de fonctionnement, la première unité de traitement de données réalise la lecture/écriture de données accompagnant le traitement de données en accédant à tous les blocs de mémoire en tant que mémoire unique, et s'arrête dans un second mode de fonctionnement. La seconde unité de traitement de données s'arrête dans le premier mode de fonctionnement, et dans le deuxième mode de fonctionnement, définit le premier bloc de mémoire comme étant en lecture seule, définit le second bloc de mémoire comme étant en écriture seule, exécute le traitement de données spécifique en lisant les données à partir du premier bloc de mémoire, et écrit le résultat correspondant sur le second bloc de mémoire.
PCT/JP2013/051539 2012-03-13 2013-01-25 Système de traitement de données, circuit intégré semi-conducteur, et procédé de commande associé WO2013136857A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014504730A JP6115564B2 (ja) 2012-03-13 2013-01-25 データ処理システム、半導体集積回路およびその制御方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012055903 2012-03-13
JP2012-055903 2012-03-13

Publications (1)

Publication Number Publication Date
WO2013136857A1 true WO2013136857A1 (fr) 2013-09-19

Family

ID=49160779

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/051539 WO2013136857A1 (fr) 2012-03-13 2013-01-25 Système de traitement de données, circuit intégré semi-conducteur, et procédé de commande associé

Country Status (2)

Country Link
JP (1) JP6115564B2 (fr)
WO (1) WO2013136857A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023155526A1 (fr) * 2022-02-17 2023-08-24 苏州浪潮智能科技有限公司 Procédé de traitement de flux de données, nœud de commande de stockage et support de stockage lisible non volatil

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03227177A (ja) * 1990-01-18 1991-10-08 Natl Semiconductor Corp <Ns> 共用内部メモリを有する集積化デジタル信号プロセサ／汎用ｃｐｕ
JPH0460744A (ja) * 1990-06-29 1992-02-26 Casio Comput Co Ltd デジタルマイクロコンピュータ
JPH11272631A (ja) * 1998-02-04 1999-10-08 Texas Instr Inc <Ti> データ処理システムおよびその方法
JP2001501330A (ja) * 1996-09-23 2001-01-30 エイアールエム リミテッド デジタル信号処理集積回路アーキテクチャ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2564805B2 (ja) * 1985-08-08 1996-12-18 日本電気株式会社 情報処理装置
JPS6488853A (en) * 1987-09-30 1989-04-03 Yokogawa Medical Syst Memory mechanism for high speed arithmetic unit
EP2317446A1 (fr) * 2005-06-30 2011-05-04 Imec Dispositif de mémoire pour système multiprocesseur

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03227177A (ja) * 1990-01-18 1991-10-08 Natl Semiconductor Corp <Ns> 共用内部メモリを有する集積化デジタル信号プロセサ／汎用ｃｐｕ
JPH0460744A (ja) * 1990-06-29 1992-02-26 Casio Comput Co Ltd デジタルマイクロコンピュータ
JP2001501330A (ja) * 1996-09-23 2001-01-30 エイアールエム リミテッド デジタル信号処理集積回路アーキテクチャ
JPH11272631A (ja) * 1998-02-04 1999-10-08 Texas Instr Inc <Ti> データ処理システムおよびその方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023155526A1 (fr) * 2022-02-17 2023-08-24 苏州浪潮智能科技有限公司 Procédé de traitement de flux de données, nœud de commande de stockage et support de stockage lisible non volatil

Also Published As

Publication number Publication date
JP6115564B2 (ja) 2017-04-19
JPWO2013136857A1 (ja) 2015-08-03

Similar Documents

Publication Publication Date Title
US7590774B2 (en) Method and system for efficient context swapping
US9043806B2 (en) Information processing device and task switching method
JP6146128B2 (ja) データ処理装置
US20110022759A1 (en) Multiprocessor system
JP2010244238A (ja) リコンフィギュラブル回路及びリコンフィギュラブル回路システム
JP2006338538A (ja) ストリームプロセッサ
JP6115564B2 (ja) データ処理システム、半導体集積回路およびその制御方法
US20100095068A1 (en) Cache memory control device and pipeline control method
JP6294732B2 (ja) データ転送制御装置及びメモリ内蔵装置
US8244929B2 (en) Data processing apparatus
US20080320185A1 (en) Buffering device and buffering method
CN112100098B (zh) Ddr控制系统及ddr存储系统
US20050135402A1 (en) Data transfer apparatus
JP2008158699A (ja) プロセッサ
US20140092123A1 (en) Drawing control device
US20120254530A1 (en) Microprocessor and memory access method
JPS63123130A (ja) パイプライン制御方式
JP2011227539A (ja) 画像処理装置
US8764874B2 (en) Arrangement, method, integrated circuit and device for routing requests
JP2010049511A (ja) 共有メモリへのアクセス方式およびマルチｃｐｕ構成のプログラマブルコントローラ
JPH07160655A (ja) メモリアクセス方式
JP2007087244A (ja) コプロセッサ及びコンピュータシステム
JP6608688B2 (ja) 半導体装置
US20020181456A1 (en) Switch device and data transfer system
JP5393626B2 (ja) 情報処理装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13761168

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014504730

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13761168

Country of ref document: EP

Kind code of ref document: A1