WO2013131742A1 - Halbleiterschaltung mit elektrischen anschlüssen mit mehrfacher signal- oder potentialbelegung - Google Patents
Halbleiterschaltung mit elektrischen anschlüssen mit mehrfacher signal- oder potentialbelegung Download PDFInfo
- Publication number
- WO2013131742A1 WO2013131742A1 PCT/EP2013/053277 EP2013053277W WO2013131742A1 WO 2013131742 A1 WO2013131742 A1 WO 2013131742A1 EP 2013053277 W EP2013053277 W EP 2013053277W WO 2013131742 A1 WO2013131742 A1 WO 2013131742A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor circuit
- electrical connection
- potential
- switching element
- circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 230000005669 field effect Effects 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Definitions
- the invention relates to a semiconductor circuit with electrical connections with multiple signal or
- Semiconductor circuits usually have one
- a successor circuit variant of a semiconductor integrated circuit includes the functional scopes and performance characteristics of all predecessor circuit variants and is installed in an identical housing with an identical number and an identical arrangement of electrical connections.
- each successor circuit variant of a semiconductor integrated circuit is constructed to be compatible with each of its predecessor circuit variants and can be retrofitted without changing the external circuit
- function-dependent bond variants leads to an increase in the chip area.
- the different wiring of the individual circuit variants of the semiconductor circuit requires a dependent on the selected circuit variant marker, which increases the manufacturing cost.
- the object of the invention is therefore, a
- Terminals called the semiconductor circuit - repeatedly occupied by a signal and / or a potential for each one of the circuit variants of the semiconductor circuit. In this way, multiple bond variants are no more
- switching elements are provided in the semiconductor circuit, which the first electrical connections with the inputs or outputs of the used
- Device preferably has a selection unit, which the individual switching elements depending on the used circuit variant of the semiconductor circuit controls.
- Terminals called the semiconductor circuit - evaluated.
- the multiple occupancy of first electrical connections of the semiconductor circuit may cause an input or an output of a
- Functional unit or a plurality of functional units which in a circuit variant of the semiconductor circuit due to a locked switching element of a first
- the control of the individual switching elements via the selection unit takes place in a preferred first variant of the invention on the basis of the applied to a single second electrical connection of the semiconductor circuit potential level.
- the number of potential levels to be distinguished by the selection unit corresponds to the number of realized in the semiconductor circuit circuit types.
- the activation of the individual switching elements takes place by evaluation of the two potential levels of a plurality of second electrical terminals by the selection unit.
- Function unit is performed.
- field-effect transistors are preferably used which have a comparatively high volume resistance in the blocked state and thus an optimum and almost galvanic separation between the respective first electrical connection and the associated inputs or outputs of the one connected to the respective first electrical connection
- Semiconductor circuit correspond to the arranged on the housing of the semiconductor circuit electrical connections, in the second preferred embodiment of the invention, a first electrical connection of the semiconductor circuit also realized as a wire bridge to an electrically conductive plate which is in direct communication with the semiconductor circuit and has a defined electrical potential.
- the electrically conductive plate having a defined electrical potential is preferably an electrically conductive plate located above or below the housing of the semiconductor circuit and having a reference potential for the latter
- This may be an exposed over the housing of the semiconductor circuit, exposed and on the ground potential of the semiconductor circuit located plate (so-called exposed Päd (ePad)) be.
- exposed Päd ePad
- a plate projecting beyond the housing of the semiconductor circuit and located on a positive or negative reference potential of the semiconductor circuit is also possible.
- FIG. 1 An exemplary representation of the signal or potential assignment of the individual electrical connections for two circuit variants of the semiconductor circuit
- a block diagram of a first embodiment of a semiconductor circuit according to the invention a block diagram of a second embodiment with a first circuit variant of a semiconductor circuit according to the invention
- 3B is a block diagram of a second embodiment with a second circuit variant of a semiconductor circuit according to the invention
- FIG. 4 shows a three-dimensional exemplary representation of an ePad connected via wire bridges to a semiconductor chip
- FIG. 5 is a block diagram of a third embodiment of a semiconductor circuit according to the invention.
- Fig. 1 the housing of a semiconductor circuit, for. As an ASIC, shown with a total of 48 electrical connections. While on the outside, the occupation (occupation_A) of the 48 electrical connections with signals or
- occupancy_C an occupancy (allocation_C) of the 48 electrical connections according to the invention
- occupancy_A the occupancy (occupancy_A) of the first circuit variant (ASIC-A)
- occupancy_A the occupancy of the first circuit variant (ASIC-A)
- Occupancy labels assigned twice.
- the invention also includes semiconductor circuits with each covered with any other number of electrical connections and with any other number of multiple occupancy of an electrical connection or multiple electrical connections.
- Integrating multiple occupancy of one or more electrical connections and thus avoiding multiple bond variants are in a first
- Connection 1 also with other types of signals and
- the ground potential V EE of the supply of the first functional unit 2 and at the same time the second functional unit 3 with the ground reference potential is used in a second circuit variant of
- Function unit 3 out, so is a generated by a selection unit 4 drive signal in the
- Function unit 2 and the second functional unit 3 befindliches switching element 5, which is realized in the embodiment as a field effect transistor, converted into the conductive state.
- Control signal in the locked state transferred. In this way it is prevented that on the first
- electrical terminal 1 is applied to the input / output terminal of the second functional unit 3 and possibly leads to a malfunction of the second functional unit 3.
- Input / output terminal of the second functional unit 3, as shown in Figures 3A and 3B, is not mandatory, since input / output terminals of functional units typically one
- this potential terminal would have to be maintained at the required potential level throughout the operating time of the semiconductor circuit and would thus the interposition of a locked
- Switching element 6 to avoid connection of the lying at ground potential first electrical connection 1 with the potential connection of the second functional unit 3 require.
- the switching element 5 in the signal path between the first electrical terminal 1 and the ground terminal of the first functional unit 2 and the second functional unit 3 about that of the
- Selection unit 4 generated inverted drive signal disabled, while simultaneously for connecting the first electrical terminal to the input / output terminal of the second functional unit 3, the switching element 6 in the signal path between the first electrical terminal 1 and the input / output terminal of the second
- Function unit 3 is transferred to the conductive state. At the same time, to supply the first
- Function unit 2 and the second functional unit 3 with a ground potential in a signal path between a further first electrical terminal 7 to ground potential and the ground terminals of the first
- Function unit 2 and the second functional unit 3 befindliches switching element 8, which is also preferably implemented as a field effect transistor and has a drive logic for the switching element 5 inverse control logic, via the same of the selection unit of 4 generated control signal in the conductive state
- the supply with a typically positive reference potential V C c and a ground potential V EE is required.
- Reference potential V C c and the ground potential V EE can, as shown in Fig. 2, over additional first
- electrical connections 10 and 11 are referred to or to save on the first electrical connections on the for the supply of the first functional unit 2 and the second functional unit 3 with a positive
- Function unit 3 with a ground potential in the case of a locked switching element 5 in the signal path between the first electrical terminal 1 and the ground terminals of the first functional unit 2 and the second
- Function unit 3 realized without interposition of a switching element 8 via a wire bridge 14 to a plate 16 which is located at the ground potential of the semiconductor circuit.
- This electrically conductive plate 16 is shown in FIG. 4 at the bottom of the
- the exposed surface of the electrically conductive plate 16 is at least one wire bridge 14, which is in communication with a contact on the semiconductor chip, attached, in particular bonded.
- the electrically conductive plate 16 is connected to a first electrical connection 7 of
- the semiconductor chip 15 is connected.
- the semiconductor chip 15 is over
- Bond wires 17 contacted with the individual electrical terminals 18 on the housing of the semiconductor circuit.
- Switching element 5 is determined from the level of the enable signal V EN for activating the second functional unit 3 at an electrical connection 19. In this case, the requirement of an additional second electrical connection 9 to which the potential V Se i to be evaluated is advantageously saved.
- a further switching elements 20 is connected in the signal path between the first electrical terminal 1 and the input / output terminal of the first functional unit 2.
- control of the switching elements 5 and 8, 6 and 20 is carried out in this technical embodiment by three separate control signals from a
- Selection unit 4 for the three circuit variants of Semiconductor circuit can be generated.
- the second variant of the invention for driving the individual switching elements not different signal or. Potential level of a single signal or potential V Se i evaluated as in the case of the first variant of the invention shown in Fig. 3A, but the signal or potential level of several
- Semiconductor circuit and a practical dimensioning of the individual serving as switching elements 5, 6, 8 and 20 field-effect transistors are the signals or potentials that alternatively abut against a first electrical terminal 1 to be selected so that their voltage or
- bipolar transistors can also be used instead of field-effect transistors.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112013000145.4T DE112013000145A5 (de) | 2012-03-08 | 2013-02-19 | Halbleiterschaltung mit elektrischen Anschlüssen mit mehrfacher Signal- oder Potentialbelegung |
US14/343,873 US9177946B2 (en) | 2012-03-08 | 2013-02-19 | Semiconductor circuit with electrical connections having multiple signal or potential assignments |
CN201380003493.8A CN103891146B (zh) | 2012-03-08 | 2013-02-19 | 包括具有多个信号配置或电位配置的电引脚的半导体电路 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE202012002379.9 | 2012-03-08 | ||
DE202012002379 | 2012-03-08 | ||
DE202012004532.6 | 2012-05-07 | ||
DE202012004532U DE202012004532U1 (de) | 2012-03-08 | 2012-05-07 | Halbleiterschaltung mit elektrischen Anschlüssen mit mehrfacher Signal- oder Potentialbelegung |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013131742A1 true WO2013131742A1 (de) | 2013-09-12 |
Family
ID=48784017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2013/053277 WO2013131742A1 (de) | 2012-03-08 | 2013-02-19 | Halbleiterschaltung mit elektrischen anschlüssen mit mehrfacher signal- oder potentialbelegung |
Country Status (4)
Country | Link |
---|---|
US (1) | US9177946B2 (de) |
CN (1) | CN103891146B (de) |
DE (2) | DE202012004532U1 (de) |
WO (1) | WO2013131742A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104767514B (zh) * | 2015-03-16 | 2018-04-13 | 福州大学 | 集成电路引脚多状态表示方法及其外接电路 |
CN105223492B (zh) * | 2015-10-23 | 2018-08-28 | 英特格灵芯片(天津)有限公司 | 一种芯片管脚配置系统及其方法 |
CN107329417B (zh) * | 2016-04-28 | 2023-08-15 | 深圳市博巨兴微电子科技有限公司 | 一种微控制器及其输入输出引脚映射电路 |
CN110164488A (zh) * | 2019-04-08 | 2019-08-23 | 苏州汇峰微电子有限公司 | 一种支持多元存储配置的存储器 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030141578A1 (en) | 1998-01-30 | 2003-07-31 | Corisis David J. | Redundant pinout configuration for signal enhancement in IC packages |
US20060055391A1 (en) * | 2004-08-26 | 2006-03-16 | International Business Machines Corporation | Power-gating cell for virtual power rail control |
US20090045677A1 (en) * | 2007-08-13 | 2009-02-19 | Arm Limited | Power control circuitry and method |
US20090051406A1 (en) * | 2007-08-20 | 2009-02-26 | Fujitsu Limited | Semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0573965B1 (de) * | 1992-06-10 | 1999-09-08 | Nec Corporation | Halbleiteranordnung mit anschlusswählender Schaltung |
US5646451A (en) * | 1995-06-07 | 1997-07-08 | Lucent Technologies Inc. | Multifunctional chip wire bonds |
JPH10303366A (ja) * | 1997-04-30 | 1998-11-13 | Mitsubishi Electric Corp | 半導体装置 |
US6385756B1 (en) * | 1999-03-23 | 2002-05-07 | Conexant Systems, Inc. | Selection of functions within an integrated circuit |
DE10238812B4 (de) | 2002-08-23 | 2005-05-25 | Infineon Technologies Ag | Halbleiterspeichervorrichtung mit veränderbarer Kontaktbelegung und entsprechende Halbleitervorrichtung |
-
2012
- 2012-05-07 DE DE202012004532U patent/DE202012004532U1/de not_active Expired - Lifetime
-
2013
- 2013-02-19 CN CN201380003493.8A patent/CN103891146B/zh active Active
- 2013-02-19 DE DE112013000145.4T patent/DE112013000145A5/de active Pending
- 2013-02-19 US US14/343,873 patent/US9177946B2/en active Active
- 2013-02-19 WO PCT/EP2013/053277 patent/WO2013131742A1/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030141578A1 (en) | 1998-01-30 | 2003-07-31 | Corisis David J. | Redundant pinout configuration for signal enhancement in IC packages |
US20060055391A1 (en) * | 2004-08-26 | 2006-03-16 | International Business Machines Corporation | Power-gating cell for virtual power rail control |
US20090045677A1 (en) * | 2007-08-13 | 2009-02-19 | Arm Limited | Power control circuitry and method |
US20090051406A1 (en) * | 2007-08-20 | 2009-02-26 | Fujitsu Limited | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
DE202012004532U1 (de) | 2013-06-10 |
US20140225664A1 (en) | 2014-08-14 |
CN103891146A (zh) | 2014-06-25 |
US9177946B2 (en) | 2015-11-03 |
CN103891146B (zh) | 2017-03-29 |
DE112013000145A5 (de) | 2014-04-17 |
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