WO2013125458A1 - 表示装置、それを備える電子機器、および表示装置の駆動方法 - Google Patents
表示装置、それを備える電子機器、および表示装置の駆動方法 Download PDFInfo
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- WO2013125458A1 WO2013125458A1 PCT/JP2013/053655 JP2013053655W WO2013125458A1 WO 2013125458 A1 WO2013125458 A1 WO 2013125458A1 JP 2013053655 W JP2013053655 W JP 2013053655W WO 2013125458 A1 WO2013125458 A1 WO 2013125458A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0613—The adjustment depending on the type of the information to be displayed
- G09G2320/062—Adjustment of illumination source parameters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
- G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
- G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/10—Special adaptations of display systems for operation with variable images
- G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
Definitions
- the present invention relates to a display device, and more particularly, to a display device that performs pause driving, an electronic device including the display device, and a method for driving the display device.
- Patent Document 1 After a scanning period (also referred to as a refresh period) T1 in which the gate lines of the liquid crystal display device are scanned to refresh the screen, all the gate lines are brought into a non-scanning state and the refresh is suspended.
- a driving method of a display device provided with a pause period (also referred to as a non-refresh period) T2 is disclosed.
- a control signal or the like can be prevented from being supplied to the gate driver and / or the source driver. Accordingly, the operation of the gate driver and / or the source driver can be paused, so that power consumption can be reduced.
- pause driving The driving performed by providing a non-refresh period after the refresh period as in the driving method described in Patent Document 1 is called “pause driving”, for example.
- This pause drive is also called “low frequency drive” or “intermittent drive”.
- Such pause driving is suitable for still image display.
- Inventions related to pause driving are disclosed in Patent Documents 2 to 5 in addition to Patent Document 1, for example.
- an image to be displayed on the screen of the display unit (hereinafter, simply referred to as “image to be displayed”) may be used.
- a CABC (Content-Adaptive-Brightness-Control) function that changes backlight luminance according to brightness is known.
- the backlight luminance is controlled based on a pulse width modulation signal output from a display control circuit in the liquid crystal display device.
- the backlight luminance is determined by the duty ratio of the pulse width modulation signal.
- the image to be displayed and the backlight luminance are linked with each other.
- the value of the duty ratio of the pulse width modulation signal is represented by the symbol “DR”.
- Japanese Unexamined Patent Publication No. 2001-31253 Japanese Unexamined Patent Publication No. 2000-347762 Japanese Unexamined Patent Publication No. 2002-278523 Japanese Unexamined Patent Publication No. 2004-78124 Japanese Unexamined Patent Publication No. 2005-37685
- FIG. 11 shows a state in which the image to be displayed is switched from the bright image X to the dark image Y in such a conventional liquid crystal display device.
- “R” represents a frame for refreshing the screen (hereinafter referred to as “refresh frame”)
- “N” represents a frame for which screen refresh is paused (hereinafter referred to as “non-refresh frame”). It is assumed that the refresh rate is 7.5 Hz. That is, the screen is refreshed once every 8 frames.
- the present invention provides a display device capable of changing the luminance of a light source in accordance with an image to be displayed while suppressing deterioration in display quality even when performing pause driving, an electronic device including the display device, and a display device thereof
- An object is to provide a driving method.
- a first aspect of the present invention includes a display unit including a plurality of pixel formation units and a light source that emits light to the display unit, and changes the luminance of the light source according to an image to be displayed on the screen of the display unit.
- a possible display device A display driving unit for driving the display unit; A light source driving unit for driving the light source; A control unit for controlling the display driving unit based on data received from the outside, The controller is A refresh rate control unit for controlling a refresh rate determined by a ratio of a refresh period for refreshing the screen and a non-refresh period for pausing the refresh of the screen;
- the refresh period The length of the first period from the start point of time to the start point of the refresh period immediately after the refresh period is set to be equal to or shorter than the length of the second period of each stage of the luminance of the light source. It is characterized by that.
- the control unit further includes a luminance control unit that performs control for changing the luminance of the light source in accordance with data indicating the image to be displayed included in data received from outside.
- the refresh rate controller may change the refresh rate so that the first period in the transition period is the refresh period.
- the first period in the transition period includes the refresh period and the non-refresh period.
- the refresh rate control unit sets the length of the first period in the transition period according to the length of the second period.
- a sixth aspect of the present invention is the fourth aspect of the present invention.
- the luminance control unit sets the length of the second period in the transition period according to the length of the first period.
- the length of the second period is a natural number times the length of the first period.
- the pixel forming unit has a control terminal connected to a scanning line in the display unit, a first conduction terminal connected to a signal line in the display unit, and a voltage corresponding to the image to be displayed should be applied, It includes a thin film transistor in which a second conductive terminal is connected to a pixel electrode in a display portion and a channel layer is formed using an oxide semiconductor.
- a ninth aspect of the present invention is an electronic device, A display device according to a first aspect of the present invention; And a luminance control unit that performs control for changing the luminance of the light source according to the image to be displayed.
- the refresh rate controller may change the refresh rate so that the first period in the transition period is the refresh period.
- An eleventh aspect of the present invention is the ninth aspect of the present invention,
- the first period in the transition period includes the refresh period and the non-refresh period.
- a twelfth aspect of the present invention is the eleventh aspect of the present invention.
- the refresh rate control unit sets the length of the first period in the transition period according to the length of the second period in the transition period.
- a thirteenth aspect of the present invention is the eleventh aspect of the present invention.
- the luminance control unit sets the length of the second period in the transition period according to the length of the first period.
- the pixel forming unit has a control terminal connected to a scanning line in the display unit, a first conduction terminal connected to a signal line in the display unit, and a voltage corresponding to the image to be displayed should be applied, It includes a thin film transistor in which a second conductive terminal is connected to a pixel electrode in a display portion and a channel layer is formed using an oxide semiconductor.
- a fifteenth aspect of the present invention is a display unit including a plurality of pixel forming units, a display driving unit that drives the display unit, a light source that irradiates light to the display unit, and a light source driving unit that drives the light source.
- a driving method of a display device comprising a control unit that controls the display driving unit based on data received from outside
- the screen is The length of the first period from the start point of the refresh period for refreshing to the start point of the refresh period immediately after the refresh period is made equal to or less than the length of the second period of each stage of the luminance of the light source.
- the transition step includes a refresh rate control step of controlling a refresh rate determined by a ratio between the refresh period and a non-refresh period for pausing refreshing of the screen.
- a sixteenth aspect of the present invention is the fifteenth aspect of the present invention, In the refresh rate control step, the refresh rate is changed so that the first period in the transition period is the refresh period.
- the first period in the transition period includes the refresh period and the non-refresh period.
- the length of the first period in the transition period is set according to the length of the second period.
- the length of the second period in the transition period is set according to the length of the first period.
- the length of the second period is set to a natural number multiple of the length of the first period.
- the luminance of the light source changes stepwise according to the change of the image to be displayed.
- the length of the first period is equal to or less than the length of the second period. Therefore, the screen is always refreshed at each stage where the luminance of the light source changes.
- the image displayed on the screen corresponds to the luminance of the light source that should originally correspond to the image. Therefore, the image displayed on the screen has the original brightness during the transition period.
- the luminance of the light source is set according to the image to be displayed on the screen.
- Deterioration of display quality when using a function to be changed (for example, a CABC function) can be sufficiently suppressed.
- the same effect as that of the first aspect of the present invention can be achieved in the aspect in which the luminance control unit is provided in the control unit.
- the screen is constantly refreshed at each stage where the luminance of the light source changes during the transition period. For this reason, in the transition period, the image displayed on the screen can be reliably associated with the luminance of the light source that should originally correspond to the image.
- pause driving is performed during the transition period. For this reason, power consumption can be reduced as compared with the third aspect or the tenth aspect of the present invention.
- the length of the first period in the transition period is set according to the length of the second period, whereby the fourth aspect of the present invention. Or the same effect as the 11th situation can be produced.
- the length of the second period in the transition period is set according to the length of the first period, whereby the fourth aspect of the present invention. Or the same effect as the 11th situation can be produced.
- the present invention since it is not necessary to change the length of the first period, that is, it is not necessary to change the refresh rate, for example, when driving at a relatively low refresh rate other than the transition period, the present invention The power consumption can be reduced as compared with the fifth aspect or the twelfth aspect.
- the seventh aspect of the present invention by making the length of the second period a natural number multiple of the length of the first period, the image displayed on the screen and the light source that should originally correspond to the image It is possible to more reliably correspond to the brightness.
- a thin film transistor in which a channel layer is formed of an oxide semiconductor is used as the thin film transistor in the pixel formation portion. For this reason, the voltage written in the pixel formation portion can be sufficiently held. The deterioration of display quality can be further suppressed.
- the same effect as that of the first aspect of the present invention can be achieved.
- the same effect as that of the first aspect of the present invention can be achieved in the display device driving method.
- the same effects as those of the third aspect or the tenth aspect of the present invention can be achieved.
- the same effects as those of the fourth aspect or the eleventh aspect of the present invention can be achieved.
- the same effects as those of the fifth aspect or the twelfth aspect of the present invention can be achieved.
- the same effects as in the sixth aspect or the thirteenth aspect of the present invention can be achieved.
- the same effect as in the seventh aspect of the present invention can be achieved.
- FIG. 3 is a block diagram for explaining a configuration of a display control circuit corresponding to video mode RAM through in the first embodiment.
- FIG. 3 is a block diagram for explaining a configuration of a display control circuit corresponding to video mode RAM capture in the first embodiment.
- 3 is a block diagram for explaining a configuration of a display control circuit corresponding to a command mode RAM write in the first embodiment.
- FIG. It is a figure for demonstrating an example of operation
- one frame refers to one frame (16.67 ms) in a general display device having a refresh rate of 60 Hz.
- driving performed at a refresh rate of XHz (X> 0) is referred to as “XHz driving”.
- refreshing the screen may be simply referred to as “refreshing”.
- FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to the first embodiment of the present invention.
- This electronic device is composed of a host (system) 1 and a liquid crystal display device 2.
- the host 1 is mainly composed of a CPU.
- the liquid crystal display device 2 includes a liquid crystal display panel 10, a backlight unit driving circuit 30 as a light source driving unit, and a backlight unit 40.
- the liquid crystal display panel 10 is a transmissive or transflective type.
- the liquid crystal display panel 10 is provided with an FPC (Flexible Printed Circuit) 20 for connection to the outside.
- FPC Flexible Printed Circuit
- a display unit 100 On the substrate of the liquid crystal display panel 10, a display unit 100, a display control circuit 200 as a control unit, a signal line driving circuit 300, and a scanning line driving circuit 400 are provided. Note that both or one of the signal line driver circuit 300 and the scan line driver circuit 400 may be provided in the display control circuit 200. In addition, both or one of the signal line driver circuit 300 and the scan line driver circuit 400 may be formed integrally with the display unit 100.
- the display unit 100 includes a plurality (m) of signal lines SL1 to SLm, a plurality (n) of scanning lines GL1 to GLn, and the m signal lines SL1 to SLm and n scanning lines.
- a plurality (m ⁇ n) of pixel forming portions 110 provided corresponding to the intersections with GL1 to GLn are formed.
- the m signal lines SL1 to SLm are not distinguished, these are simply referred to as “signal lines SL”
- the n scanning lines GL1 to GLn are not distinguished, these are simply referred to as “scanning lines GL”.
- the m ⁇ n pixel forming portions 110 are formed in a matrix.
- each pixel forming unit 110 a gate terminal as a control terminal is connected to the scanning line GL passing through the corresponding intersection, and a source terminal as a first conduction terminal is connected to the signal line SL passing through the intersection.
- a pixel capacitor Cp is constituted by the liquid crystal capacitor formed by the pixel electrode 112 and the common electrode 113. Note that, typically, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. Therefore, the pixel capacitor Cp is actually composed of a liquid crystal capacitor and an auxiliary capacitor.
- a TFT using an oxide semiconductor for a channel layer (hereinafter referred to as “oxide TFT”) is used as the TFT 111.
- the channel layer of the TFT 111 is formed of IGZO (InGaZnOx) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components.
- IGZO-TFT a TFT using IGZO as a channel layer.
- the IGZO-TFT has much smaller off-leakage current than a silicon-based TFT using amorphous silicon or the like as a channel layer. For this reason, the voltage written in the pixel capacitor Cp can be held for a longer period.
- oxide semiconductors other than IGZO for example, indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium (Ge), and lead ( A similar effect can be obtained even when an oxide semiconductor containing at least one of Pb) is used for the channel layer.
- oxide TFT as the TFT 111 is merely an example, and a silicon-based TFT or the like may be used instead.
- the display control circuit 200 is typically realized as an IC (Integrated Circuit).
- the display control circuit 200 receives the data DAT from the host 1 via the FPC 20, and generates a signal line control signal SCT, a scanning line control signal GCT, a pulse width modulation signal PWM, and a common potential Vcom in response thereto. Output.
- the signal line control signal SCT is given to the signal line driving circuit 300.
- the scanning line control signal GCT is supplied to the scanning line driving circuit 400.
- the pulse width modulation signal PWM is given to the backlight unit drive circuit 30.
- the common potential Vcom is supplied to the common electrode 113.
- transmission / reception of data DAT between the host 1 and the display control circuit 200 is performed via an interface conforming to the DSI (Display Serial Interface) standard proposed by MIPI (Mobile Industry Processor Interface) Alliance. Done.
- DSI Display Serial Interface
- MIPI Mobile Industry Processor Interface
- the video mode or command mode of the interface conforming to the DSI standard is used.
- the signal line driving circuit 300 generates and outputs a driving video signal to be supplied to the signal line SL in accordance with the signal line control signal SCT.
- the signal line control signal SCT includes, for example, a digital video signal corresponding to RGB data RGBD, a source start pulse signal, a source clock signal, and a latch strobe signal.
- the signal line driver circuit 300 operates a shift register, a sampling latch circuit, and the like (not shown) therein according to the source start pulse signal, the source clock signal, and the latch strobe signal, and the digital line obtained based on the digital video signal
- a video signal for driving is generated by converting the signal into an analog signal by a DA converter circuit (not shown).
- the scanning line driving circuit 400 repeats the application of the active scanning signal to the scanning line GL in a predetermined cycle in accordance with the scanning line control signal GCT.
- the scanning line control signal GCT includes, for example, a gate clock signal and a gate start pulse signal.
- the scanning line driving circuit 400 operates a shift register (not shown) and the like to generate a scanning signal.
- the scanning line driving circuit 400 and the signal line driving circuit 300 described above function as a display driving unit.
- the backlight unit 40 is provided on the back side of the liquid crystal display panel 10 and irradiates the back light of the liquid crystal display panel 10 with backlight light.
- the backlight unit 40 typically includes LEDs (Light Emitting Diode) as a plurality of light sources.
- CCFL ColdCCCathode Fluorescent Lamp
- the LED brightness (corresponding to the backlight brightness described above) is controlled by the backlight unit drive circuit 30.
- the backlight unit drive circuit 30 determines the LED brightness according to the pulse width modulation signal PWM. Specifically, the LED brightness increases as the duty ratio of the pulse width modulation signal PWM increases.
- the method of adjusting the LED brightness is not limited to this, and various changes can be made.
- the driving video signal is applied to the signal line SL
- the scanning signal is applied to the scanning line
- the backlight unit 40 is driven, so that the screen corresponding to the image data transmitted from the host 1 is displayed. Is displayed on the display unit 100 of the liquid crystal display panel 10.
- the configuration of the display control circuit 200 will be described in three modes.
- a video mode is used and no RAM (Random Access Memory) is provided.
- video mode RAM through a mode in which a video mode is used and a RAM is provided.
- video mode RAM capture a mode in which a command mode is used and a RAM is provided.
- this third mode is referred to as “command mode RAM write”. Since the present invention is not limited to an interface conforming to the DSI standard, the configuration of the display control circuit 200 is not limited to the three types of modes described here.
- FIG. 2 is a block diagram for explaining the configuration of a display control circuit 200 (hereinafter referred to as “video mode RAM through display control circuit 200”) corresponding to video mode RAM through in the present embodiment.
- the display control circuit 200 includes an interface unit 210, a command register 220, an NVM (Non-volatile memory) 221, a timing generator 230, an OSC (Oscillator) 231, a latch circuit 240,
- the circuit includes a CABC circuit 250, a built-in power supply circuit 260, a signal line control signal output unit 270, and a scanning line control signal output unit 280.
- the interface unit 210 includes a DSI receiving unit 211. Note that as described above, both or one of the signal line driver circuit 300 and the scan line driver circuit 400 may be provided in the display control circuit 200.
- the DSI receiving unit 211 in the interface unit 210 conforms to the DSI standard.
- the data DAT in the video mode includes RGB data RGBD indicating data relating to an image to be displayed, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a data enable signal DE, a clock signal CLK, and command data CM, which are synchronization signals. It is included.
- the command data CM includes data related to various controls.
- the DSI reception unit 211 transmits the RGB data RGBD included in the data DAT to the latch circuit 240, and the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the clock signal CLK is transmitted to the timing generator 230, and command data CM is transmitted to the command register 220.
- the command data CM may be transmitted from the host 1 to the command register 220 via an interface compliant with the I2C (Inter Integrated Circuit) standard or the SPI (Serial Peripheral Interface) standard.
- the interface unit 210 includes a receiving unit compliant with the I2C standard or the SPI standard.
- the command register 220 holds command data CM.
- the NVM 221 holds setting data SET for various controls.
- the command register 220 reads the setting data SET held in the NVM 221 and updates the setting data SET according to the command data CM.
- the command register 220 transmits a timing control signal TS to the timing generator 230 and transmits a voltage setting signal VS to the built-in power supply circuit 260 according to the command data CM and the setting data SET.
- the timing generator 230 is based on the internal clock signal ICK generated by the OSC 231 in response to the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the clock signal CLK and the timing control signal TS.
- a control signal for controlling the signal line control signal output unit 270 and the scanning line control signal output unit 280 is transmitted.
- the timing generator 230 is generated based on the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the built-in clock signal ICK generated by the OSC 231 in response to the clock signal CLK and the timing control signal TS.
- the request signal REQ is transmitted to the host 1.
- the request signal REQ is a signal that requests the host 1 to transmit data DAT.
- the OSC 231 is not essential in the video mode RAM through display control circuit 200.
- the timing generator 230 also receives later-described CABC processing data CABCD from the CABC circuit 250, generates a pulse width modulation signal PWM in response thereto, and transmits it to the backlight unit drive circuit 30.
- the pulse width modulation signal PWM may be transmitted to the backlight unit drive circuit 30 via the command register 220.
- the latch circuit 240 transmits RGB data RGBD for one line to the signal line control signal output unit 270 based on the control of the timing generator 230.
- the CABC circuit 250 determines the brightness of the image to be displayed indicated by the RGB data RGBD received from the latch circuit 240. As a result of the determination, the CABC circuit 250 transmits the CABC processing data CABCD to the timing generator 230.
- the CABC processing data CABCD indicates, for example, the brightness of the image to be displayed indicated by the RGB data RGBD.
- the CABC processing data CABCD may indicate a change in brightness from the image indicated by the RGB data RGBD received immediately before.
- the timing generator 230 that has received the CABC processing data CABCD generates the pulse width modulation signal PWM in accordance with the CABC processing data CABCD as described above, and transmits the pulse width modulation signal PWM to the backlight unit drive circuit 30.
- the transmitted pulse width modulation signal PWM has its duty ratio changed according to the CABC processing data CABCD.
- the duty ratio of the pulse width modulation signal PWM is set higher as the image to be displayed indicated by the RGB data RGBD is brighter, and the duty ratio of the pulse width modulation signal PWM is lower as the image to be displayed indicated by the RGB data RGBD is darker. Is set.
- the CABC circuit 250 transmits the CABC processing data CABCD as a determination result as described above, and performs data conversion of the received RGB data RGBD.
- the RGB data RGBD is converted so that the image to be displayed is brightened as the LED brightness obtained from the pulse width modulation signal PWM generated in accordance with the CABC processing data CABCD decreases (hereinafter, this is the case).
- This conversion is called “data conversion matched to LED brightness”). Thereby, it is possible to prevent the image displayed on the screen from becoming darker than desired brightness while lowering the LED luminance.
- the converted RGB data RGBD is transmitted to the signal line control signal output unit 270.
- the built-in power supply circuit 260 uses the power supply voltage to be used by the signal line control signal output unit 270 and the scanning line control signal output unit 280 based on the power supply given from the host 1 and the voltage setting signal VS given from the command register. A common potential Vcom is generated and output.
- the signal line control signal output unit 270 generates the signal line control signal SCT based on the RGB data RGBD from the CABC circuit 250, the control signal from the timing generator 230, and the power supply voltage from the built-in power supply circuit 260. Is transmitted to the signal line driver circuit 300.
- the scanning line control signal output unit 280 generates the scanning line control signal GCT based on the control signal from the timing generator 230 and the power supply voltage from the built-in power supply circuit 260 and transmits this to the scanning line drive circuit 400.
- FIG. 3 is a block diagram for explaining a configuration of a display control circuit 200 (hereinafter referred to as “video mode RAM capture display control circuit 200”) corresponding to the video mode RAM capture in the present embodiment.
- the video mode RAM capture display control circuit 200 is obtained by adding a frame memory (RAM) 290 to the video mode RAM through display control circuit 200 described above.
- RAM frame memory
- the RGB data RGBD is directly transmitted from the DSI receiver 211 to the latch circuit 240, but in the video mode RAM capture display control circuit 200, the RGB data RGBD transmitted from the DSI receiver 211. Is held in the frame memory 290. Then, the RGB data RGBD held in the frame memory 290 is read to the latch circuit 240 according to the control signal generated by the timing generator 230. Further, the timing generator 230 transmits a vertical synchronization output signal VSOUT to the host 1 instead of the request signal REQ.
- the vertical synchronization output signal VSOUT is a signal for controlling the transmission timing of the data DAT from the host 1 so that the writing timing and the reading timing of the RGB data RGBD in the frame memory 290 do not overlap.
- the RGB data RGBD can be held in the frame memory 290. Therefore, when there is no screen update, there is no need to transmit the data DAT from the host 1 to the display control circuit 200 again.
- FIG. 4 is a block diagram for explaining a configuration of a display control circuit 200 (hereinafter referred to as “command mode RAM write display control circuit 200”) corresponding to the command mode RAM write in the present embodiment.
- the command mode RAM write display control circuit 200 has the same configuration as the video mode RAM capture display control circuit 200 described above, but the type of data included in the data DAT is different.
- the data DAT in the command mode includes the command data CM, and does not include the RGB data RGBD, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the clock signal CLK.
- the command data CM in the command mode includes data relating to images and data relating to various timings.
- the command register 220 transmits a RAM write signal RAMW corresponding to data related to an image to be displayed in the command data CM to the frame memory 290.
- the RAM write signal RAMW corresponds to the RGB data RGBD.
- the timing generator 230 does not receive the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, the internal vertical synchronization signal IVSYNC and the internal horizontal synchronization signal corresponding to the internal clock signal ICK and the timing control signal TS based on the built-in clock signal ICK and the timing control signal TS.
- IHSYNC is generated internally.
- the timing generator 230 controls the latch circuit 240, the signal line control signal output unit 270, the scan line control signal output unit 280, and the frame memory 290 based on the internal vertical synchronization signal IVSYNC and the internal horizontal synchronization signal IHSYNC. . Further, the timing generator 230 transmits a transmission control signal TE corresponding to the vertical synchronization output signal VSOUT to the host 1.
- FIG. 5 is a diagram for explaining an example of the operation of the liquid crystal display device 2 in the present embodiment.
- the image to be displayed is switched from the bright image X as the first image to the dark image Y as the second image
- the frame type (R / N) the refresh rate
- the duty ratio DR of the pulse width modulation signal PWM the displayed image
- two types of driving are performed: pause driving that is driving at 60 Hz or less (for example, 7.5 Hz) and normal driving that is driving at 60 Hz.
- the operations described below are basically the same for any of video mode RAM through, video mode RAM capture, and command mode RAM write.
- the normal driving in the present embodiment refers to driving for refreshing the screen in each frame.
- pause driving in the present embodiment refers to driving in which a non-refresh frame is provided after a refresh frame and the refresh frame and the non-refresh frame are alternately repeated by a predetermined number of frames.
- Each rectangular box corresponding to the frame type in FIG. 5 represents one frame, and “R” is attached to the refresh frame and “N” is attached to the non-refresh frame.
- polarity inversion driving (AC driving) is performed, and for example, the polarity of the potential written in the pixel capacitor Cp is inverted every refresh.
- the first period that is a period from the start time of the refresh frame to the start time of the refresh frame immediately after the refresh frame is referred to as a “vertical display period”.
- the second period which is the period of each stage of LED luminance (and the image to be displayed corresponding to this) that changes during the transition period, is referred to as “sub-transition period”.
- Each length of the vertical display period and the sub transition period is represented by the number of frames.
- a driving video signal is supplied from the signal line driving circuit 300 to the signal lines SL1 to SLm in accordance with a signal line control signal SCT including a digital video signal corresponding to RGB data RGBD, and for the scanning line.
- the scanning lines GL1 to GLn are scanned (selected sequentially) by the scanning line driving circuit 400 in accordance with the control signal GCT.
- the TFT 111 corresponding to the selected scanning line GL is turned on, and the voltage of the driving video signal is written into the pixel capacitor Cp. In this way, the screen is refreshed. Thereafter, the TFT 111 is turned off, and the written voltage, that is, the liquid crystal voltage is held until the screen is next refreshed.
- the screen refresh is paused as described above. More specifically, since the supply of the scanning line control signal GCT to the scanning line driving circuit 400 is stopped or the scanning line control signal GCT becomes a fixed potential, the operation of the scanning line driving circuit 400 is stopped. The scanning lines GL1 to GLn are not scanned. That is, the voltage of the driving video signal is not written to the pixel capacitor Cp in the non-refresh frame. However, since the liquid crystal voltage is maintained as described above, the screen refreshed in the immediately preceding refresh frame is continuously displayed. In the non-refresh frame, the operation of the signal line driver circuit 300 is stopped when the supply of the signal line control signal SCT to the signal line driver circuit 300 is stopped or the signal line control signal SCT becomes a fixed potential.
- the operations of the scan line driver circuit 400 and the signal line driver circuit 300 are stopped in this way, so that power consumption can be reduced.
- the signal line driver circuit 300 may be operated. In this case, it is desirable to output a predetermined fixed potential as a driving video signal.
- the refresh rate is 60 Hz
- the refresh frame is repeated and no non-refresh frame is provided.
- the vertical display period is one frame.
- the refresh rate is 12 Hz
- four non-refresh frames are provided immediately after one refresh frame.
- the refresh rate is 12 Hz
- the vertical display period is 5 frames.
- the refresh rate is 7.5 Hz
- seven non-refresh frames are provided immediately after one refresh frame.
- the vertical display period is 8 frames. Since the proportion of non-refresh frames increases as the refresh frame is lower, the amount of reduction in power consumption increases.
- Rate data Data such as the number of refresh frames and non-refresh frames (hereinafter referred to as “rate data”) at each refresh rate is included in, for example, command data CM.
- the timing control signal TS corresponding to the rate data is transmitted to the timing generator 230, whereby driving according to the refresh rate is performed.
- the timing generator 230 functions as a refresh rate control unit.
- the refresh rate is switched by, for example, transmitting rate data of the refresh rate after the switching from the host 1 to the command register 220 and updating the rate data held in the command register 220.
- the timing generator 230 can transmit a control signal for transmitting new rate data from the host 1 to the host 1 in this way.
- the refresh rate may be switched based on CABC processing data CABCD transmitted from the CABC circuit 250 to the timing generator 230.
- the image to be displayed when the image to be displayed is switched from the bright image X to the dark image Y, the image to be displayed is changed stepwise, and the duty ratio of the pulse width modulation signal PWM is changed stepwise according to this change.
- a transition period for changing to is provided.
- the image to be displayed changes stepwise from the image A to the image I
- the length of the sub transition period is 5 frames. However, the length of the sub transition period is not limited to this.
- the stepwise change of the duty ratio of the pulse width modulation signal PWM in the transition period is performed based on, for example, CABC processing data CABCD transmitted from the CABC circuit 250 to the timing generator 230.
- the stepwise change of the image to be displayed in the transition period is performed by stepwise changing the contents of the RGB data RGBD included in the data DAT transmitted from the host 1 to the display control circuit 200, for example.
- the method of changing the image to be displayed stepwise is not limited to this.
- the CABC circuit 250 may convert the RGB data RGBD so that the image to be displayed changes stepwise.
- the vertical display period is 8 frames longer than the sub-transition period.
- the drive is continuously performed at the same refresh rate as the refresh rate in the period before the transition period (see FIG. 11).
- the pause driving at 7.5 Hz is switched to the normal driving at 60 Hz.
- the length of the vertical display period is one frame.
- the normal driving at 60 Hz continues until the end of the transition period. In this way, by setting the length of the vertical display period to be equal to or shorter than the length of the sub-transition period, the screen is always refreshed in each sub-transition period in the transition period. More specifically, refresh is performed five times in each sub transition period.
- the screen is refreshed to image A.
- the screen is refreshed to the image B.
- the image displayed on the screen corresponds to the duty ratio of the pulse width modulation signal PWM that should originally correspond to the image. That is, the image displayed on the screen corresponds to the LED brightness that should originally correspond to the image. Note that the screen is refreshed to an image Y after the end of the transition period.
- the start time of the first vertical display period in the transition period coincides with the start time of the first sub transition period
- the length of the sub transition period (5 frames) is the length of the vertical display period. Since it is a natural number multiple of (1 frame), the correspondence of the image displayed on the screen to the LED luminance that should be originally associated with the image is more reliable.
- the length of the vertical display period is equal to or less than the length of the sub transition period. For this reason, when the CABC function is used during pause driving, the screen is always refreshed in each sub-transition period of the transition period. For this reason, in the transition period, the image displayed on the screen corresponds to the LED luminance that should originally correspond to the image. Thereby, the image displayed on the screen becomes the original brightness in the transition period. Therefore, even in the case of performing the rest driving, it is possible to sufficiently suppress the deterioration of the display quality when using the CABC function as in the case of performing the normal driving.
- the start time of the first vertical display period in the transition period coincides with the start time of the first sub transition period
- the length of the sub transition period is the length of the vertical display period. It is a natural number multiple of (one frame). For this reason, the image displayed on the screen can be surely made to correspond to the LED luminance that should originally correspond to the image.
- the screen is constantly refreshed in each sub-transition period of the transition period by performing normal driving at 60 Hz in the transition period. For this reason, the image displayed on the screen can be reliably associated with the LED luminance that should originally correspond to the image.
- the IGZO-TFT is used as the TFT 111 in the pixel forming portion 110, the voltage written in the pixel capacitor Cp can be sufficiently held. Thereby, it is possible to further suppress the deterioration of the display quality particularly during the pause driving.
- FIG. 6 is a diagram for explaining an example of the operation of the liquid crystal display device 2 according to the second embodiment of the present invention. Since the present embodiment is basically the same as the first embodiment except for the operation, the description of the common parts is omitted.
- the length of the sub-transition period is 5 frames, and 7.5 Hz pause driving is performed before the transition period, during which the image X is displayed on the screen. Has been done. That is, the length of the vertical display period is 8 frames.
- the pause driving at 7.5 Hz is switched to the normal driving at 60 Hz, whereby the length of the vertical display period is switched from 8 frames to 1 frame.
- the pause driving at 7.5 Hz is switched to the pause driving at 12 Hz.
- the length of the vertical display period is switched from 8 frames to 5 frames which is the same as the length of the sub transition period.
- the screen is always refreshed in each sub-transition period in the transition period, as in the first embodiment. Done. Note that, as shown in FIG. 6, it is desirable that the start time of the first vertical display period in the transition period coincides with the start time of the first sub-transition period.
- This embodiment is not limited to the example shown in FIG.
- the length of the sub-transition period is 6 frames
- switching to 10 Hz pause driving in which the length of the vertical display period is 6 frames in the transition period if the length of the sub-transition period is 4 frames, the transition to the 15 Hz pause drive in which the length of the vertical display period is 4 frames in the transition period.
- a vertical display period that is shorter than the sub-transition period may be employed as the fresh rate in the transition period.
- it is desirable that the length of the sub transition period is a natural number times the length of the vertical display period.
- the length of the sub-transition period is 6 frames
- the length of the sub-transition period is 16 frames
- pause driving is performed in the transition period, and the length of the vertical display period is the same (1 time) as the length of the sub-transition period. For this reason, it is possible to reduce the power consumption as compared with the first embodiment while making the image displayed on the screen corresponding to the LED luminance that should originally correspond to the image as in the first embodiment.
- FIG. 7 is a diagram for explaining an example of the operation of the liquid crystal display device 2 according to the third embodiment of the present invention. Since the present embodiment is basically the same as the first embodiment except for the operation, the description of the common parts is omitted.
- the length of the sub-transition period is 5 frames
- the period before the transition period is the period when the image X is displayed on the screen.
- a pause drive of 7.5 Hz is performed. That is, the length of the vertical display period is 8 frames.
- the pause driving at 7.5 Hz is switched to the normal driving at 60 Hz, whereby the length of the vertical display period is switched from 8 frames to 1 frame.
- the length of the vertical display period is 8 frames.
- the length of the vertical display period does not change between the transition period and the other periods as in the conventional liquid crystal display device (see FIG. 11).
- the length of the sub-transition period is set to 8 frames which is the same as the length of the vertical display period.
- a setting method is as follows.
- the timing generator 230 changes the timing control of the latch circuit 240 and the like according to the length of the vertical display period (refresh rate).
- the contents of the CABC processing data CABCD and the RGB data RGBD transmitted by the CABC circuit 250 are changed according to the length of the vertical display period. That is, the length of the sub transition period is set by the CABC circuit 250 according to the length of the vertical display period.
- the method for setting the length of the sub-transition period is not limited to this, and any method may be used as long as the length of the sub-transition period is set by any component in the electronic device. Can be adopted.
- the refresh of the screen is always performed in each sub-transition period in the transition period, as in the first embodiment. Done.
- the refresh rate in order to make the image displayed on the screen correspond to the LED luminance that should originally correspond to the image, it is desirable to switch the refresh rate so that the first frame in the sub-transition period becomes the refresh frame. Note that, as shown in FIG. 7, the screen is always refreshed in each sub-transition period. Note that, as shown in FIG. 6, it is desirable that the start time of the first vertical display period in the transition period coincides with the start time of the first sub-transition period.
- This embodiment is not limited to the example shown in FIG.
- the length of the sub-transition period is 5 frames.
- 10 Hz pause driving is performed in which the length of the vertical display period is 6 frames
- the length of the sub-transition period is 6 frames.
- the sub-transition period may be longer than the vertical display period.
- it is desirable that the length of the sub-transition period is a natural number multiple of the length of the vertical display period. For example, when the length of the vertical display period is 8 frames, the length of the sub-transition period can be 16 frames (twice the vertical display period). When the length of the vertical display period is 4 frames, the length of the sub transition period can be 16 frames (4 times the vertical display period).
- pause driving is performed in the transition period, and the length of the sub-transition period is the same (1 time) as the length of the vertical display period. For this reason, the same effect as the second embodiment can be obtained. Further, there is no need to change the refresh rate during the transition period. Thereby, power consumption can be reduced as compared with the second embodiment.
- the CABC circuit 250 is provided in the display control circuit 200.
- the CABC circuit 250 is provided in the host 1. Note that this embodiment is basically the same as the first embodiment except for the configuration of the host 1 and the display control circuit 200, and thus description of common parts is omitted.
- the same elements as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
- FIG. 8 is a block diagram for explaining the configuration of the host 1 and the video mode RAM through display control circuit 200 in the present embodiment.
- the CABC circuit 250 is provided in the host 1 instead of in the display control circuit 200.
- the CABC circuit 250 in the present embodiment transmits CABC processing data CABCD to the timing generator 230. Further, the CABC circuit 250 generates the pulse width modulation signal PWM generated by the timing generator 230 in the first embodiment and transmits it to the backlight unit drive circuit 30.
- the CABC processing data CABCD in the present embodiment is obtained from the brightness of the image to be displayed indicated by the RGB data RGBD included in the data DAT and / or the image indicated by the immediately preceding RGB data RGBD, as in the first embodiment. Shows the change in brightness. Further, the CABC processing data CABCD in the present embodiment may be 1-bit data indicating whether or not the pulse width modulation signal PWM generated by the CABC circuit 250 is changing. The CABC processing data CABCD may be transmitted directly to the timing generator 230 or may be transmitted via the command register 220.
- the switching of the refresh rate in the present embodiment is performed by updating the rate data held in the command register 220 as in the first embodiment. Further, the refresh rate may be switched based on CABC processing data CABCD transmitted from the CABC circuit 250 to the timing generator 230.
- the CABC circuit 250 in the display control circuit 200 performs data conversion on the RGB data RGBD in accordance with the LED brightness.
- the RGB data RGBD included in the data DAT to be transmitted from the host 1 to the display control circuit 200 is subjected to data conversion in accordance with the LED luminance by the CABC circuit 250 in the host 1. Done.
- FIG. 9 is a block diagram for explaining the configuration of the host 1 and the display control circuit 200 of the video mode RAM capture in the present embodiment.
- the CABC circuit 250 is provided not in the display control circuit 200 but in the host 1.
- the operations of the CABC circuit 250 and the timing generator 230 shown in FIG. 9 are the same as those shown in FIG.
- FIG. 10 is a block diagram for explaining the configuration of the display control circuit 200 of the host 1 and the command mode RAM write in this embodiment.
- the CABC circuit 250 is provided not in the display control circuit 200 but in the host 1.
- the operations of the CABC circuit 250 and the timing generator 230 shown in FIG. 10 are basically the same as those shown in FIG.
- the data conversion in accordance with the LED luminance by the CABC circuit 250 is different from the video mode RAM through example, for example, of the command data CM included in the data DAT to be transmitted from the host 1 to the display control circuit 200. This is performed by the CABC circuit 250 in the host 1 for the RAM write signal RAMW corresponding to the data relating to the image to be displayed.
- the image to be displayed is exemplified as switching from the bright image X as the first image to the dark image Y as the second image, but the present invention is not limited to this. Absent.
- the present invention can also be applied to a case where the image to be displayed is switched from the dark image Y as the first image to the bright image Y as the second image. In this case, the same effects as those of the above embodiments can be obtained.
- the CABC circuit 250 is provided in the host 1 in the first embodiment.
- the CABC circuit 250 may be provided outside the host 1 and the display control circuit 200.
- the CABC circuit 250 and the display control circuit 200 function as a control unit.
- the fourth embodiment may be used in combination with the second embodiment or the third embodiment.
- the setting of the length of the sub transition period according to the length of the vertical display period is, for example, the timing control signal CS and the rate data. This is performed by the CABC circuit 250 setting the length of the sub-transition period on the host 1 side in accordance with data corresponding to the command data CM that is the source of the above.
- a display device capable of changing the luminance of a light source according to an image to be displayed while suppressing a reduction in display quality even when performing pause driving, an electronic device including the display device, and the device A driving method of a display device can be provided.
- the present invention can be applied to a display device that performs pause driving, an electronic device including the display device, and a method for driving the display device.
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Abstract
Description
前記表示部を駆動する表示駆動部と、
前記光源を駆動する光源駆動部と、
外部から受け取るデータに基づいて前記表示駆動部を制御する制御部とを備え、
前記制御部は、
前記画面をリフレッシュするためのリフレッシュ期間と前記画面のリフレッシュを休止するための非リフレッシュ期間との割合によって決定されるリフレッシュレートを制御するリフレッシュレート制御部を含み、
前記表示すべき画像が第1の画像から第2の画像に段階的に変化する場合に前記表示すべき画像の変化に応じて前記光源の輝度が段階的に変化する遷移期間において、前記リフレッシュ期間の開始時点から当該リフレッシュ期間の直後のリフレッシュ期間の開始時点までの第1の期間の長さを、前記光源の輝度の各段階の第2の期間の長さ以下にするように構成されていることを特徴とする。
前記制御部は、外部から受け取るデータに含まれる、前記表示すべき画像を示すデータに応じて前記光源の輝度を変更するための制御を行う輝度制御部をさらに含むことを特徴とする。
前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートを変更することを特徴とする。
前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする。
前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間の長さを前記第2の期間の長さに応じて設定することを特徴とする。
前記輝度制御部は、前記遷移期間における前記第2の期間の長さを前記第1の期間の長さに応じて設定することを特徴とする。
前記第2の期間の長さは前記第1の期間の長さの自然数倍であることを特徴とする。
前記画素形成部は、前記表示部内の走査線に制御端子が接続され、前記表示部内の信号線に第1導通端子が接続され、前記表示すべき画像に応じた電圧が印加されるべき、前記表示部内の画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする。
本発明の第1の局面に係る表示装置と、
前記表示すべき画像に応じて前記光源の輝度を変更するための制御を行う輝度制御部とを備えることを特徴とする。
前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートを変更することを特徴とする。
前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする。
前記リフレッシュレート制御部は、前記遷移期間において、前記遷移期間における前記第1の期間の長さを前記第2の期間の長さに応じて設定することを特徴とする。
前記輝度制御部は、前記遷移期間における前記第2の期間の長さを前記第1の期間の長さに応じて設定することを特徴とする。
前記画素形成部は、前記表示部内の走査線に制御端子が接続され、前記表示部内の信号線に第1導通端子が接続され、前記表示すべき画像に応じた電圧が印加されるべき、前記表示部内の画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする。
前記表示すべき画像が第1の画像から第2の画像に段階的に変化する場合に前記表示すべき画像の変化に応じて前記光源の輝度が段階的に変化する遷移期間において、前記画面をリフレッシュするためのリフレッシュ期間の開始時点から当該リフレッシュ期間の直後のリフレッシュ期間の開始時点までの第1の期間の長さを、前記光源の輝度の各段階の第2の期間の長さ以下にする遷移ステップを備え、
前記遷移ステップは、前記リフレッシュ期間と、前記画面のリフレッシュを休止するための非リフレッシュ期間との割合によって決定されるリフレッシュレートを制御するリフレッシュレート制御ステップを含むことを特徴とする。
前記リフレッシュレート制御ステップでは、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートが変更されることを特徴とする。
前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする。
前記リフレッシュレート制御ステップでは、前記遷移期間における前記第1の期間の長さが前記第2の期間の長さに応じて設定されることを特徴とする。
前記遷移ステップでは、前記遷移期間における前記第2の期間の長さが前記第1の期間の長さに応じて設定されることを特徴とする。
前記遷移ステップでは、前記第2の期間の長さは、前記第1の期間の長さの自然数倍に設定されることを特徴とする。
<1.1 全体構成および動作概要>
図1は、本発明の第1の実施形態に係る電子機器の構成を示すブロック図である。この電子機器は、ホスト(システム)1および液晶表示装置2により構成されている。ホスト1は、主としてCPUにより構成される。液晶表示装置2には、液晶表示パネル10、光源駆動部としてのバックライトユニット駆動回路30、およびバックライトユニット40が含まれている。液晶表示パネル10は、透過型または半透過型である。液晶表示パネル10には、外部との接続用のFPC(Flexible Printed Circuit)20が設けられている。また、液晶表示パネル10の基板上には、表示部100、制御部としての表示制御回路200、信号線駆動回路300、および走査線駆動回路400が設けられている。なお、信号線駆動回路300および走査線駆動回路400の双方またはいずれか一方は表示制御回路200内に設けられていても良い。また、信号線駆動回路300および走査線駆動回路400の双方またはいずれか一方は表示部100と一体的に形成されていても良い。
以下では、表示制御回路200の構成について、3つの態様に分けて説明する。第1の態様は、ビデオモードを用い、かつRAM(Random Access Memory)を設けない態様である。以下では、このような第1の態様のことを「ビデオモードRAMスルー」という。第2の態様は、ビデオモードを用い、かつRAMを設ける態様である。以下では、このような第2の態様のことを「ビデオモードRAMキャプチャー」という。第3の態様は、コマンドモードを用い、かつRAMを設ける態様である。以下では、このような第3の態様のことを「コマンドモードRAMライト」という。なお、本発明はDSI規格に準拠したインターフェースに限定されるものではないので、表示制御回路200の構成は、ここで説明する3種類の態様に限定されるものではない。
図2は、本実施形態における、ビデオモードRAMスルーに対応した表示制御回路200(以下「ビデオモードRAMスルーの表示制御回路200」という。)の構成を説明するためのブロック図である。図2に示すように、表示制御回路200は、インターフェース部210、コマンドレジスタ220、NVM(Non-volatile memory:不揮発性メモリ)221、タイミングジェネレータ230、OSC(Oscillator:発振器)231、ラッチ回路240、CABC回路250、内蔵電源回路260、信号線用制御信号出力部270、走査線用制御信号出力部280により構成されている。インターフェース部210にはDSI受信部211が含まれている。なお、上述のように、信号線駆動回路300および走査線駆動回路400の双方またはいずれか一方が表示制御回路200内に設けられていても良い。
図3は、本実施形態における、ビデオモードRAMキャプチャーに対応した表示制御回路200(以下「ビデオモードRAMキャプチャーの表示制御回路200」という。)の構成を説明するためのブロック図である。ビデオモードRAMキャプチャーの表示制御回路200は、図3に示すように、上述のビデオモードRAMスルーの表示制御回路200にフレームメモリ(RAM)290を追加したものである。
図4は、本実施形態における、コマンドモードRAMライトに対応した表示制御回路200(以下「コマンドモードRAMライトの表示制御回路200」という。)の構成を説明するためのブロック図である。コマンドモードRAMライトの表示制御回路200は、図4に示すように、上述のビデオモードRAMキャプチャーの表示制御回路200と同様の構成であるが、データDATに含まれるデータの種類が異なる。
図5は、本実施形態における液晶表示装置2の動作の一例を説明するための図である。ここでは、表示すべき画像を、第1の画像としての明るい画像Xから第2の画像としての暗い画像Yに切り替える例を挙げて説明する。図5の上から順に、フレームの種類(R/N)、リフレッシュレート、パルス幅変調信号PWMのデューティー比DR、および表示される画像を示す。図5に示す例では、60Hz以下(例えば7.5Hzなど)の駆動である休止駆動と60Hzの駆動である通常駆動との2種類の駆動が行われる。以下で説明する動作は、ビデオモードRAMスルー、ビデオモードRAMキャプチャー、およびコマンドモードRAMライトのいずれにおいても基本的に同様である。ここで、本実施形態における通常駆動とは、各フレームで画面をリフレッシュする駆動のことをいう。また、本実施形態における休止駆動とは、リフレッシュフレームの後に、非リフレッシュフレームを設け、これらのリフレッシュフレームと非リフレッシュフレームを所定フレーム数ずつ交互に繰り返す駆動のことをいう。図5中のフレームの種類に対応する各矩形ボックスは1フレームを示し、リフレッシュフレームには「R」を付し、非リフレッシュフレームには「N」を付している。なお、本実施形態では極性反転駆動(交流駆動)が行われ、例えば1回のリフレッシュ毎に画素容量Cpに書き込まれる電位の極性が反転するものとする。これにより、液晶電圧の正負のバランスをとることができるので、液晶の劣化が抑制される。
本実施形態によれば、遷移期間において、垂直表示期間の長さが副遷移期間の長さ以下になる。このため、休止駆動中にCABC機能を使用する際に、遷移期間の各副遷移期間で画面が必ずリフレッシュされる。このため、遷移期間において、画面に表示される画像が、当該画像に本来対応すべきLED輝度に対応する。これにより、遷移期間において、画面に表示される画像が本来の明るさになる。したがって、休止駆動を行う場合であっても、通常駆動を行う場合と同様にCABC機能を使用する際の表示品位の低下を十分に抑制することができる。
<2.1 動作>
図6は、本発明の第2の実施形態における液晶表示装置2の動作の一例を説明するための図である。なお、本実施形態は動作を除き上記第1の実施形態と基本的に同様であるので、共通する部分については説明を省略する。本実施形態では、上記第1の実施形態と同様に、副遷移期間の長さは5フレームであり、遷移期間前である、画面に画像Xが表示されている期間では7.5Hzの休止駆動が行われている。すなわち、垂直表示期間の長さが8フレームとなっている。上記第1の実施形態では、遷移期間が開始すると7.5Hzの休止駆動が60Hzの通常駆動に切り替わることにより、垂直表示期間の長さが8フレームから1フレームに切り替わる。
本実施形態によれば、遷移期間において休止駆動が行われ、垂直表示期間の長さが副遷移期間の長さと同じ(1倍)になる。このため、上記第1の実施形態と同様に画面に表示される画像を、当該画像に本来対応すべきLED輝度に対応させつつ、第1の実施形態よりも消費電力を低減することができる。
<3.1 動作>
図7は、本発明の第3の実施形態における液晶表示装置2の動作の一例を説明するための図である。なお、本実施形態は動作を除き上記第1の実施形態と基本的に同様であるので、共通する部分については説明を省略する。本実施形態では、本実施形態では、上記第1の実施形態と同様に、副遷移期間の長さは5フレームであり、遷移期間前である、画面に画像Xが表示されている期間では上記第1の実施形態と同様に7.5Hzの休止駆動が行われている。すなわち、垂直表示期間の長さが8フレームとなっている。上記第1の実施形態では、遷移期間が開始すると7.5Hzの休止駆動が60Hzの通常駆動に切り替わることにより、垂直表示期間の長さが8フレームから1フレームに切り替わる。本実施形態では、遷移期間が開始しても、7.5Hzの休止駆動が継続する。すなわち、遷移期間前後と同様に、垂直表示期間の長さは8フレームである。このように遷移期間とそれ以外の期間とで垂直表示期間の長さが変わらない点は、従来の液晶表示装置と同様である(図11を参照)。
本実施形態によれば、遷移期間において休止駆動が行われ、副遷移期間の長さが垂直表示期間の長さと同じ(1倍)になる。このため、上記第2の実施形態と同様の効果を奏することができる。また、遷移期間においてリフレッシュレートを変更する必要がない。これにより、上記第2の実施形態よりも消費電力を低減することができる。
<4.1 ホストおよび表示制御回路の構成>
上記第1の実施形態では、CABC回路250は表示制御回路200内に設けられている。しかし、本実施形態では、CABC回路250はホスト1内に設けられている。なお、本実施形態はホスト1および表示制御回路200の構成を除き上記第1の実施形態と基本的に同様であるので、共通する部分については説明を省略する。また、本実施形態の構成要素のうち上記第1の実施形態と同一の要素についても、同一の参照符号を付して適宜説明を省略する。
本実施形態によれば、CABC回路250がホスト1内に設けられた態様において、上記第1の実施形態と同様の効果を奏することができる。
上記各実施形態では、表示すべき画像を、第1の画像としての明るい画像Xから第2の画像としての暗い画像Yに切り替える例に挙げてしたが、本発明はこれに限定されるものではない。表示すべき画像を、第1の画像としての暗い画像Yから第2の画像としての明るい画像Yに切り替える場合についても、本発明を適用することができる。この場合、上記各実施形態と同様の効果を奏することができる。
2…液晶表示装置
10…液晶表示パネル
20…FPC
30…バックライトユニット駆動回路(光源駆動部)
40…バックライトユニット
100…表示部
110…画素形成部
111…TFT(薄膜トランジスタ)
200…表示制御回路
210…インターフェース部
211…DSI受信部
220…コマンドレジスタ
221…NVM(不揮発性メモリ)
230…タイミングジェネレータ(リフレッシュレート制御部)
231…OSC(発振器)
240…ラッチ回路
250…CABC回路(輝度制御部)
260…内蔵電源回路
270…信号線用制御信号出力部
280…走査線用制御信号出力部
290…フレームメモリ(RAM)
300…信号線駆動回路
400…走査線駆動回路
SL…信号線
GL…走査線
R…リフレッシュ
N…非リフレッシュ
Claims (20)
- 複数の画素形成部を含む表示部と前記表示部に光を照射する光源とを備え、前記表示部の画面に表示すべき画像に応じて光源の輝度を変更可能な表示装置であって、
前記表示部を駆動する表示駆動部と、
前記光源を駆動する光源駆動部と、
外部から受け取るデータに基づいて前記表示駆動部を制御する制御部とを備え、
前記制御部は、
前記画面をリフレッシュするためのリフレッシュ期間と前記画面のリフレッシュを休止するための非リフレッシュ期間との割合によって決定されるリフレッシュレートを制御するリフレッシュレート制御部を含み、
前記表示すべき画像が第1の画像から第2の画像に段階的に変化する場合に前記表示すべき画像の変化に応じて前記光源の輝度が段階的に変化する遷移期間において、前記リフレッシュ期間の開始時点から当該リフレッシュ期間の直後のリフレッシュ期間の開始時点までの第1の期間の長さを、前記光源の輝度の各段階の第2の期間の長さ以下にするように構成されていることを特徴とする、表示装置。 - 前記制御部は、外部から受け取るデータに含まれる、前記表示すべき画像を示すデータに応じて前記光源の輝度を変更するための制御を行う輝度制御部をさらに含むことを特徴とする、請求項1に記載の表示装置。
- 前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートを変更することを特徴とする、請求項2に記載の表示装置。
- 前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする、請求項2に記載の表示装置。
- 前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間の長さを前記第2の期間の長さに応じて設定することを特徴とする、請求項4に記載の表示装置。
- 前記輝度制御部は、前記遷移期間における前記第2の期間の長さを前記第1の期間の長さに応じて設定することを特徴とする、請求項4に記載の表示装置。
- 前記第2の期間の長さは前記第1の期間の長さの自然数倍であることを特徴とする、請求項1に記載の表示装置。
- 前記画素形成部は、前記表示部内の走査線に制御端子が接続され、前記表示部内の信号線に第1導通端子が接続され、前記表示すべき画像に応じた電圧が印加されるべき、前記表示部内の画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする、請求項1から7までのいずれか1項に記載の表示装置。
- 請求項1に記載の表示装置と、
前記表示すべき画像に応じて前記光源の輝度を変更するための制御を行う輝度制御部とを備えることを特徴とする、電子機器。 - 前記リフレッシュレート制御部は、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートを変更することを特徴とする、請求項9に記載の電子機器。
- 前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする、請求項9に記載の電子機器。
- 前記リフレッシュレート制御部は、前記遷移期間において、前記遷移期間における前記第1の期間の長さを前記第2の期間の長さに応じて設定することを特徴とする、請求項11に記載の電子機器。
- 前記輝度制御部は、前記遷移期間における前記第2の期間の長さを前記第1の期間の長さに応じて設定することを特徴とする、請求項11に記載の電子機器。
- 前記画素形成部は、前記表示部内の走査線に制御端子が接続され、前記表示部内の信号線に第1導通端子が接続され、前記表示すべき画像に応じた電圧が印加されるべき、前記表示部内の画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする、請求項9から13までのいずれか1項に記載の電子機器。
- 複数の画素形成部を含む表示部と、前記表示部を駆動する表示駆動部と、前記表示部に光を照射する光源と、前記光源を駆動する光源駆動部と、外部から受け取るデータに基づいて前記表示駆動部を制御する制御部とを備える表示装置の駆動方法であって、
前記表示すべき画像が第1の画像から第2の画像に段階的に変化する場合に前記表示すべき画像の変化に応じて前記光源の輝度が段階的に変化する遷移期間において、前記画面をリフレッシュするためのリフレッシュ期間の開始時点から当該リフレッシュ期間の直後のリフレッシュ期間の開始時点までの第1の期間の長さを、前記光源の輝度の各段階の第2の期間の長さ以下にする遷移ステップを備え、
前記遷移ステップは、前記リフレッシュ期間と、前記画面のリフレッシュを休止するための非リフレッシュ期間との割合によって決定されるリフレッシュレートを制御するリフレッシュレート制御ステップを含むことを特徴とする、駆動方法。 - 前記リフレッシュレート制御ステップでは、前記遷移期間における前記第1の期間が前記リフレッシュ期間からなるように前記リフレッシュレートが変更されることを特徴とする、請求項15に記載の駆動方法。
- 前記遷移期間における前記第1の期間は、前記リフレッシュ期間および前記非リフレッシュ期間からなることを特徴とする、請求項15に記載の駆動方法。
- 前記リフレッシュレート制御ステップでは、前記遷移期間における前記第1の期間の長さが前記第2の期間の長さに応じて設定されることを特徴とする、請求項17に記載の駆動方法。
- 前記遷移ステップでは、前記遷移期間における前記第2の期間の長さが前記第1の期間の長さに応じて設定されることを特徴とする、請求項17に記載の駆動方法。
- 前記遷移ステップでは、前記第2の期間の長さは、前記第1の期間の長さの自然数倍に設定されることを特徴とする、請求項15に記載の駆動方法。
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TW201422053A (zh) * | 2012-11-29 | 2014-06-01 | Beyond Innovation Tech Co Ltd | 關聯於發光二極體的負載驅動裝置 |
US9210769B2 (en) * | 2013-03-15 | 2015-12-08 | Microchip Technology Incorporated | Constant brightness LED drive communications port |
TWI633789B (zh) * | 2013-04-12 | 2018-08-21 | 聯詠科技股份有限公司 | 資料讀取方法、資料傳送方法及相關行動裝置 |
CN106663404A (zh) * | 2014-07-15 | 2017-05-10 | 夏普株式会社 | 显示装置及其驱动方法 |
US10453402B2 (en) * | 2015-03-26 | 2019-10-22 | Motorola Mobility Llc | Method and apparatus for content adaptive backlight control |
US9875694B2 (en) * | 2015-09-16 | 2018-01-23 | Sony Corporation | Smoothing brightness transition during channel change |
CN106250085A (zh) * | 2016-07-29 | 2016-12-21 | 北京小米移动软件有限公司 | 刷新率调整方法及装置 |
JP6961457B2 (ja) * | 2016-11-02 | 2021-11-05 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2019184725A (ja) * | 2018-04-05 | 2019-10-24 | シャープ株式会社 | 表示装置 |
CN108957862B (zh) * | 2018-10-09 | 2022-05-10 | 京东方科技集团股份有限公司 | 透明显示装置和容器 |
CN109616083B (zh) * | 2019-01-29 | 2021-04-02 | 惠科股份有限公司 | 一种驱动方法、驱动模块和显示装置 |
CN109637425A (zh) * | 2019-01-29 | 2019-04-16 | 惠科股份有限公司 | 一种驱动方法、驱动模块和显示装置 |
JP7386688B2 (ja) * | 2019-12-13 | 2023-11-27 | シャープ株式会社 | 表示制御装置、表示装置、表示制御装置の制御プログラムおよび制御方法 |
CN114512102A (zh) * | 2020-11-17 | 2022-05-17 | 瑞昱半导体股份有限公司 | 显示器背光源控制方法 |
US11978410B2 (en) * | 2022-06-23 | 2024-05-07 | Novatek Microelectronics Corp. | Backlight control method and related display driver circuit for variable refresh rate display panel |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000347762A (ja) | 1999-06-07 | 2000-12-15 | Denso Corp | マイクロコンピュータ |
JP2001312253A (ja) | 2000-04-28 | 2001-11-09 | Sharp Corp | 表示装置の駆動方法およびそれを用いた表示装置ならびに携帯機器 |
JP2002278523A (ja) | 2001-01-12 | 2002-09-27 | Sharp Corp | 表示装置の駆動方法および表示装置 |
JP2004078124A (ja) | 2002-08-22 | 2004-03-11 | Sharp Corp | 表示装置およびその駆動方法 |
JP2005037685A (ja) | 2003-07-15 | 2005-02-10 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示パネルの駆動装置、及び液晶表示パネルの駆動方法 |
WO2012017899A1 (ja) * | 2010-08-03 | 2012-02-09 | シャープ株式会社 | 表示制御方法、表示制御装置、液晶表示装置、表示制御プログラムおよびコンピュータ読取可能な記録媒体 |
WO2012137791A1 (ja) * | 2011-04-07 | 2012-10-11 | シャープ株式会社 | 表示装置、その駆動方法および電子機器 |
WO2012141142A1 (ja) * | 2011-04-13 | 2012-10-18 | シャープ株式会社 | 表示装置、表示方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1220098C (zh) | 2000-04-28 | 2005-09-21 | 夏普株式会社 | 显示器件、显示器件驱动方法和装有显示器件的电子设备 |
CN100507646C (zh) * | 2000-04-28 | 2009-07-01 | 夏普株式会社 | 显示器件、显示器件驱动方法和装有显示器件的电子设备 |
KR100509501B1 (ko) * | 2003-05-26 | 2005-08-22 | 삼성전자주식회사 | 액정 패널 디스플레이 장치 |
JP2008026378A (ja) * | 2006-07-18 | 2008-02-07 | Epson Imaging Devices Corp | 電気光学装置及び電子機器 |
EP2202717B1 (en) * | 2007-10-05 | 2013-12-25 | Sharp Kabushiki Kaisha | Image display |
JP5798707B2 (ja) * | 2008-01-28 | 2015-10-21 | セイコーエプソン株式会社 | 画像表示装置、その制御方法及び電子機器 |
US20120242923A1 (en) | 2010-02-25 | 2012-09-27 | Sharp Kabushiki Kaisha | Thin film transistor substrate, method for manufacturing the same, and display device |
US9165525B2 (en) * | 2011-04-08 | 2015-10-20 | Sharp Kabushiki Kaisha | Display device and method for driving same |
WO2013021846A1 (ja) * | 2011-08-05 | 2013-02-14 | シャープ株式会社 | 表示装置およびその制御方法 |
WO2013115088A1 (ja) * | 2012-02-02 | 2013-08-08 | シャープ株式会社 | 表示装置およびその駆動方法 |
US20150228239A1 (en) * | 2012-02-07 | 2015-08-13 | Sharp Kabushiki Kaisha | Display device and method of driving the same |
US9349335B2 (en) * | 2012-02-24 | 2016-05-24 | Sharp Kabushiki Kaisha | Display device, electronic device comprising same, and drive method for display device |
-
2013
- 2013-02-15 CN CN201380010274.2A patent/CN104145302B/zh active Active
- 2013-02-15 WO PCT/JP2013/053655 patent/WO2013125458A1/ja active Application Filing
- 2013-02-15 SG SG11201404536VA patent/SG11201404536VA/en unknown
- 2013-02-15 US US14/378,663 patent/US9299292B2/en active Active
- 2013-02-15 EP EP13752285.0A patent/EP2819120B1/en active Active
- 2013-02-15 MY MYPI2014002260A patent/MY167845A/en unknown
- 2013-02-15 JP JP2014500690A patent/JP5781215B2/ja active Active
- 2013-02-15 KR KR1020147025528A patent/KR101577557B1/ko active IP Right Grant
- 2013-02-21 TW TW102106089A patent/TWI545547B/zh not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000347762A (ja) | 1999-06-07 | 2000-12-15 | Denso Corp | マイクロコンピュータ |
JP2001312253A (ja) | 2000-04-28 | 2001-11-09 | Sharp Corp | 表示装置の駆動方法およびそれを用いた表示装置ならびに携帯機器 |
JP2002278523A (ja) | 2001-01-12 | 2002-09-27 | Sharp Corp | 表示装置の駆動方法および表示装置 |
JP2004078124A (ja) | 2002-08-22 | 2004-03-11 | Sharp Corp | 表示装置およびその駆動方法 |
JP2005037685A (ja) | 2003-07-15 | 2005-02-10 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示パネルの駆動装置、及び液晶表示パネルの駆動方法 |
WO2012017899A1 (ja) * | 2010-08-03 | 2012-02-09 | シャープ株式会社 | 表示制御方法、表示制御装置、液晶表示装置、表示制御プログラムおよびコンピュータ読取可能な記録媒体 |
WO2012137791A1 (ja) * | 2011-04-07 | 2012-10-11 | シャープ株式会社 | 表示装置、その駆動方法および電子機器 |
WO2012141142A1 (ja) * | 2011-04-13 | 2012-10-18 | シャープ株式会社 | 表示装置、表示方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160060332A (ko) * | 2014-11-20 | 2016-05-30 | 엘지디스플레이 주식회사 | 액정표시장치 및 그 구동방법 |
KR102277937B1 (ko) | 2014-11-20 | 2021-07-14 | 엘지디스플레이 주식회사 | 액정표시장치 및 그 구동방법 |
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US9299292B2 (en) | 2016-03-29 |
EP2819120B1 (en) | 2019-04-24 |
US20150054863A1 (en) | 2015-02-26 |
CN104145302A (zh) | 2014-11-12 |
KR101577557B1 (ko) | 2015-12-14 |
JPWO2013125458A1 (ja) | 2015-07-30 |
CN104145302B (zh) | 2016-09-07 |
KR20140127318A (ko) | 2014-11-03 |
EP2819120A1 (en) | 2014-12-31 |
TW201340086A (zh) | 2013-10-01 |
JP5781215B2 (ja) | 2015-09-16 |
TWI545547B (zh) | 2016-08-11 |
MY167845A (en) | 2018-09-26 |
EP2819120A4 (en) | 2015-04-08 |
SG11201404536VA (en) | 2014-11-27 |
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