WO2013120990A1 - Hétérostructure hemt et procédé de fabrication d'hemt - Google Patents

Hétérostructure hemt et procédé de fabrication d'hemt Download PDF

Info

Publication number
WO2013120990A1
WO2013120990A1 PCT/EP2013/053067 EP2013053067W WO2013120990A1 WO 2013120990 A1 WO2013120990 A1 WO 2013120990A1 EP 2013053067 W EP2013053067 W EP 2013053067W WO 2013120990 A1 WO2013120990 A1 WO 2013120990A1
Authority
WO
WIPO (PCT)
Prior art keywords
thickness
layer
substrate
barrier layer
gan
Prior art date
Application number
PCT/EP2013/053067
Other languages
English (en)
Inventor
Piotr CABAN
Wlodzimierz Strupinski
Original Assignee
Isos Technologies Sarl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Isos Technologies Sarl filed Critical Isos Technologies Sarl
Publication of WO2013120990A1 publication Critical patent/WO2013120990A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432—Heterojunction gate for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to HEMT epitaxial heterostructures manufactured using a highly resistive GaN buffer layer deposited on an AI2O3 substrate, SiC substrate (4H or 6H polytype), a Si substrate and a SiC substrate with a thin film of cubic SiC (3C-SiC/Si) as well as on GaN substrates obtained by various methods in a device for epitaxy of lll-V semiconductor compounds.
  • the study was conducted employing the AIXTRON200/4RF-S system with an inductively heated horizontal reactor with a modified configuration for the separation of carrier gases (H2 and N 2 ) and reagents (TMAI, TMGa, TEGa, TMIn, NH 3 and SiH 4 ).
  • a HEMT heterostructure is obtained by epitaxy in a ccord a nce with the u nd erm entio ned optimized key technological parameters of growth. Layers are produced in such an order that a buffer layer 7 is formed on a substrate 8, then a GaN layer on it and successively layers no. 5, 4, 3, 2 and 1 are created. Below, one may find composition, thickness and epitaxial growth parameters for particular layers.
  • buffer layer (adapted to the substrate),

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne une hétérostructure HEMT, qui comprend un substrat (8) et une couche tampon (7), caractérisée en ce qu'elle comprend les couches successives suivantes : • (1) une couche de passivation/contact de GaN, épaisseur de 3 nm, • (2) c) une couche barrière : AlxGa1-xN 0,15<x<0,6, épaisseur de 3 nm à 5 nm, • (3) b)une couche barrière : InxAl1-xN 0,05<x<0,3, épaisseur de 2 nm à 15 nm, • (4) a) une couche barrière : AlxGa 1-xN 0,15<x<0,4, épaisseur de 3 nm à 15 nm, • (5) de préférence une couche d'AlN, épaisseur de 0 nm à 2 nm, • (6) une couche de GaN, épaisseur de 1000 nm à 3000 nm, • (7) une couche tampon, • (8) un substrat, de préférence un substrat de SiC, Al2O3, Si ou 3C-SiC. La présente invention concerne également un procédé de fabrication de ladite hétérostructure HEMT par épitaxie sur un substrat (8).
PCT/EP2013/053067 2012-02-17 2013-02-15 Hétérostructure hemt et procédé de fabrication d'hemt WO2013120990A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PL398149A PL398149A1 (pl) 2012-02-17 2012-02-17 Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT
PLP.398149 2012-02-17

Publications (1)

Publication Number Publication Date
WO2013120990A1 true WO2013120990A1 (fr) 2013-08-22

Family

ID=47901946

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2013/053067 WO2013120990A1 (fr) 2012-02-17 2013-02-15 Hétérostructure hemt et procédé de fabrication d'hemt

Country Status (2)

Country Link
PL (1) PL398149A1 (fr)
WO (1) WO2013120990A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018196948A1 (fr) * 2017-04-24 2018-11-01 Swegan Ab Barrière intercouche

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1863075A1 (fr) * 2005-03-23 2007-12-05 Sumitomo Electric Industries, Ltd. Dispositif semi-conducteur au nitrure du groupe iii et substrat epitaxial
US20080067549A1 (en) * 2006-06-26 2008-03-20 Armin Dadgar Semiconductor component
US20100270559A1 (en) * 2007-11-19 2010-10-28 Nec Corporation Field effect transistor and process for manufacturing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1863075A1 (fr) * 2005-03-23 2007-12-05 Sumitomo Electric Industries, Ltd. Dispositif semi-conducteur au nitrure du groupe iii et substrat epitaxial
US20080067549A1 (en) * 2006-06-26 2008-03-20 Armin Dadgar Semiconductor component
US20100270559A1 (en) * 2007-11-19 2010-10-28 Nec Corporation Field effect transistor and process for manufacturing same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MASANOBU HIROKI ET AL: "Dependence of Electrical Properties of InAlN/GaN and InAlN/AlGaN/GaN Heterostructures FETs on the AlN Interlayer Thickness", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS, TOKYO, JP, vol. E93C, no. 5, May 2010 (2010-05-01), pages 579 - 584, XP001555438, ISSN: 0916-8524, DOI: 10.1587/TRANSELE.E93.C.579 *
RUDIGER QUAY: "Gallium Nitride Electronics", 2008, SPRINGER-VERLAG, pages: 32 - 38

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018196948A1 (fr) * 2017-04-24 2018-11-01 Swegan Ab Barrière intercouche

Also Published As

Publication number Publication date
PL398149A1 (pl) 2013-08-19

Similar Documents

Publication Publication Date Title
KR101854021B1 (ko) 헤테로기판 상의 iii족-질화물 버퍼 층 구조의 p-도핑
US7456443B2 (en) Transistors having buried n-type and p-type regions beneath the source region
US10109736B2 (en) Superlattice buffer structure for gallium nitride transistors
US7709859B2 (en) Cap layers including aluminum nitride for nitride-based transistors
US9627222B2 (en) Method for fabricating nitride semiconductor device with silicon layer
JP2009049121A (ja) ヘテロ接合型電界効果トランジスタ及びその製造方法
JP2017059671A (ja) 高電子移動度トランジスタ、及び高電子移動度トランジスタの製造方法
JP2016100471A (ja) 半導体装置及び半導体装置の製造方法
CN108352324B (zh) 用于族iiia-n装置的非蚀刻性气体冷却外延堆叠
JP2015527749A (ja) Ｉｎｇａｎチャネルのｎ極のｇａｎｈｅｍｔ特性
US20140167058A1 (en) Compositionally graded nitride-based high electron mobility transistor
EP3235004A1 (fr) Empilement tampon pour dispositifs au nitrure du groupe iiia
JP6305137B2 (ja) 窒化物半導体積層物および半導体装置
US20140346530A1 (en) Semiconductor device and method of manufacturing the same
WO2013120990A1 (fr) Hétérostructure hemt et procédé de fabrication d&#39;hemt
TWI572036B (zh) Nitride crystal structure
JP6416705B2 (ja) 電界効果トランジスタおよびその製造方法
US20170256635A1 (en) Nitride semiconductor and nitride semiconductor manufacturing method
JP2013229499A5 (fr)
WO2017077733A1 (fr) Semi-conducteur au nitrure, procédé de fabrication d&#39;un semi-conducteur au nitrure et dispositif électronique
JP7037801B2 (ja) 電界効果トランジスタ及びその製造方法
JP2011210781A (ja) 縦型ＡｌＧａＮ／ＧａＮ−ＨＥＭＴおよびその製造方法
Jatal et al. AlGaN/GaN based HEMTs on SiC/Si-substrates: influences on high frequency performance
Su et al. Influence of MOCVD growth conditions on the two-dimensional electron gas in AlGaN/GaN heterostructures
Mukhopadhyay Epitaxial Growth Optimization of III-Arsenide and III-Nitride on Silicon: Influence of Buffer on MODFET for Low Cost Power Amplifier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13710795

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13710795

Country of ref document: EP

Kind code of ref document: A1