WO2013118646A1 - 撮像素子、製造装置および方法、並びに、撮像装置 - Google Patents
撮像素子、製造装置および方法、並びに、撮像装置 Download PDFInfo
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- WO2013118646A1 WO2013118646A1 PCT/JP2013/052328 JP2013052328W WO2013118646A1 WO 2013118646 A1 WO2013118646 A1 WO 2013118646A1 JP 2013052328 W JP2013052328 W JP 2013052328W WO 2013118646 A1 WO2013118646 A1 WO 2013118646A1
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Definitions
- the present disclosure relates to an imaging element, a manufacturing apparatus and method, and an imaging apparatus, and more particularly, to an imaging element, a manufacturing apparatus and method, and an imaging apparatus that can increase a charge storage region.
- CMOS Complementary Metal Oxide Semiconductor
- a method may be considered in which a signal diffusion accumulated in the photodiode is read out from the periphery of the transfer gate to the floating diffusion by arranging a floating diffusion surrounded by the gate electrode in the photodiode region. (For example, see Patent Document 1).
- the charge storage region is a portion other than the other components of the pixel region at the maximum and cannot be made larger than that. That is, the size of the charge storage region may be limited by other configurations.
- the size of the charge accumulation region affects the accumulated charge amount Qs of the pixel.
- the accumulated charge amount Qs has an important influence on the image quality. That is, in the conventional case, the maximum value of the accumulated charge amount Qs of each pixel is limited by the configuration of the transfer gate, the floating diffusion, the transistor that performs amplification, selection, or reset, and the image quality may be reduced. was there.
- the present disclosure has been made in view of such a situation, and an object thereof is to increase a charge storage region, increase a stored charge amount, and suppress a reduction in image quality.
- One aspect of the present disclosure is an imaging device in which a channel portion of a readout transistor and a floating diffusion that form a pixel are formed so that at least a part of each other overlaps.
- a part or all of the channel portion and the floating diffusion may be exposed to the outside of the photodiode constituting the pixel.
- the channel portion and the floating diffusion can be formed in a columnar shape on the surface of the photodiode constituting the pixel.
- the channel portion and the floating diffusion can be formed in a region of a photodiode constituting one pixel.
- the channel part and the floating diffusion can be shared by a plurality of pixels.
- the gate electrode of the read transistor can be formed so as to surround a part or all of the side surface of the channel portion and the floating diffusion.
- the second chip to be connected can be overlapped with each other.
- the wiring in the pixel of the first chip and the wiring of the second chip are bonded to a circuit corresponding to each pixel or a plurality of pixels. Can be combined.
- the second chip combined with the first chip further overlaps and is combined with a third chip on which a logic circuit including the input system and output system transistors of the pixel is formed. be able to.
- the P ⁇ layer of at least one of the amplifying transistor, the selecting transistor, and the resetting transistor constituting the pixel is formed so as to overlap the P + layer. Can do.
- Another aspect of the present disclosure is a manufacturing apparatus that manufactures an image sensor, which includes a channel formation unit that forms a channel unit of a readout transistor that forms a pixel, and the channel unit that is formed by the channel formation unit. And a floating diffusion forming part that forms the floating diffusion so that at least a part of each other overlaps.
- a photodiode forming part for forming a photodiode is further provided, wherein the channel forming part forms the channel part on the surface of the photodiode formed by the photodiode forming part, and the floating diffusion forming part includes the photodiode
- the floating diffusion can be formed so as to overlap the channel portion formed on the surface.
- the floating diffusion formation part forms the floating diffusion on the surface of the photodiode formed by the photodiode formation part, and the channel formation part overlaps the floating diffusion formed by the floating diffusion formation part.
- the channel portion can be formed inside the photodiode.
- Transistor forming portion for forming at least one of the amplification transistor, the selection transistor, and the resetting transistor constituting the pixel so that the P ⁇ layer of each channel portion overlaps the P + layer Can further be provided.
- a second chip As a chip different from the first chip on which the readout transistor and the floating diffusion are formed, a second chip on which an amplifying transistor, a selection transistor, and a reset transistor that form the pixel are formed. And a coupling unit that overlaps and couples the second chip manufactured by the manufacturing unit with the first chip.
- the coupling unit bonds the wiring in the pixel of the first chip and the wiring of the second chip to a circuit corresponding to each pixel or each of a plurality of pixels, so that the first chip A chip and the second chip can be combined.
- a third chip manufacturing unit for manufacturing a third chip on which a logic circuit including an input system and an output system transistor of the pixel is formed; and the third chip manufactured by the third chip manufacturing unit.
- a third chip coupling unit coupled to the second chip coupled to the first chip by the coupling unit.
- Another aspect of the present disclosure is also a manufacturing method of a manufacturing apparatus for manufacturing an imaging element, in which a channel formation unit forms a channel part of a readout transistor that constitutes a pixel of the imaging element, and a floating diffusion formation unit However, in the manufacturing method, the floating diffusion is formed so that at least a part of the floating diffusion overlaps the formed channel portion.
- an image sensor in which a channel portion of a readout transistor and a floating diffusion that form a pixel are formed so that at least a part of each other overlaps, and an image of a subject obtained in the image sensor And an image processing unit that performs image processing.
- the channel portion and the floating diffusion of the imaging device can be formed in a columnar shape on the surface of the photodiode constituting the pixel.
- the channel portion of the readout transistor and the floating diffusion that form the pixel are formed so that at least a part of each other overlaps.
- a channel portion of a readout transistor that constitutes a pixel of an image sensor is formed, and a floating diffusion is formed so that at least a part of each other overlaps the channel portion.
- the channel portion of the readout transistor that constitutes the pixel and the floating diffusion are formed so that at least a part of each other overlaps, and the subject obtained in the imaging device The image is image processed.
- the charge accumulation region can be made larger.
- First embodiment imaging device / manufacturing apparatus / manufacturing method
- Second Embodiment Image Sensor / Manufacturing Apparatus / Manufacturing Method
- Third Embodiment Image Sensor / Manufacturing Apparatus / Manufacturing Method
- Fourth embodiment imaging device / manufacturing apparatus / manufacturing method
- Fifth embodiment imaging device
- FIG. 1 is a cross-sectional view illustrating a main configuration example of a part of an image sensor to which the present technology is applied.
- An image sensor 100 shown in FIG. 1 outputs an image of a subject as an electrical signal by photoelectrically converting light incident from the lower side in the figure.
- FIG. 1 shows the configuration of one pixel of the image sensor 100.
- the photodiode 111 that constitutes one pixel is partitioned by a pixel isolation region 112. Further, a transfer gate (TG) 141 (readout transistor) indicated by a one-dot chain line and a floating diffusion (FD) 142 indicated by a dotted line are formed on the upper side of the photodiode 111 in the drawing. That is, in the plan view seen from the upper side or the lower side in FIG. 1, the pixel isolation region 112 is formed so as to surround the region of the photodiode 111, and the TG 141 and the FD 142 are formed in the region of the photodiode 111. .
- TG transfer gate
- FD floating diffusion
- the N region 121 that is a photoelectric conversion and charge storage region of the photodiode 111 is partitioned by a pixel isolation region 112 composed of a P + region 122 (P + region 122-1 and P + region 122-2).
- P + region 122-1 and P + region 122-2 can be one connected region.
- P + region 122 When there is no need to distinguish between the P + region 122-1 and the P + region 122-2, they are simply referred to as a P + region 122.
- a P-layer 123 that is a channel portion of the TG 141 is formed on the upper side of a part of the N region 121 in the drawing, and further, an FD 142 is formed on the upper side of the P-layer 123 in the drawing.
- An N + layer 124 is formed.
- a high impurity concentration P + layer 125 (P + layer 125-1 and P + layer 125-2) is formed on the portion of the N region 121 where the P ⁇ layer 123 is not stacked and on the upper side of the P + region 122 in the figure.
- the P + layer 125-1 and the P + layer 125-2 can be one connected region. When there is no need to distinguish between the P + layer 125-1 and the P + layer 125-2, they are simply referred to as a P + layer 125.
- an insulating film 126 made of SiO 2, a high-k material, or the like is formed on the upper side of the P + layer 125 and the N + layer 124 in the drawing.
- the gate of TG 141 is formed so as to cover (or surround) the channel portion of TG 141. That is, as shown in FIG. 1, the gate electrode 127 (the gate electrode 127-1 and the gate electrode 127) made of polysilicon (Poly Si) or the like is provided so as to cover the P ⁇ layer 123 from the upper side of the insulating film 126 in the drawing. -2) is formed. In practice, the gate electrode 127-1 and the gate electrode 127-2 can be one connected region. When the gate electrode 127-1 and the gate electrode 127-2 do not need to be distinguished from each other, they are simply referred to as the gate electrode 127.
- an interlayer insulating film 128 made of SiO 2 or the like is formed above the insulating film 126 and the gate electrode 127 in the drawing.
- a wiring layer 130 on which the wiring 131 is formed is formed on the upper side of the interlayer insulating film 128 in the drawing.
- a contact 129 that penetrates the insulating film 126 and the interlayer insulating film 128 is formed on the upper side of the N + layer 124 of the FD 142.
- a contact 129 connects the N + layer 124 of the FD 142 and the wiring 131.
- the wiring 131 is made of, for example, a conductive metal (Metal) such as copper (Cu) or aluminum (Al), and the FD 142 (N + layer 124) connected through the contact 129 is connected to another element. .
- the FD 142 (N + layer 124) is formed (columnar) so as to overlap the channel portion (P ⁇ layer 123) of the TG 141 (FD 142 (N + layer 124), and ,
- the channel portion (P-layer 123) of TG 141 has a laminated structure).
- N region 121 of the photodiode 111 when the charge accumulated in the N region 121 of the photodiode 111 is moved to the FD 142, the charge can be moved in the stacking direction (vertical direction in the figure), so the FD 142 (N + layer 124).
- An N region 121 can also be formed on the lower side of the channel portion (P-layer 123) of TG 141 in the drawing.
- the photodiode 111 (N region 121), the channel portion (P ⁇ layer 123) of the TG 141, and the FD 142 (N + layer 124) are formed so as to overlap each other.
- the N region 121 which is a charge storage region, can be made larger than when a TG or a photodiode is formed around the FD, and the charge storage amount Qs can be increased. Can do. Therefore, the image sensor 100 can improve the image quality of the captured image (output a captured image with higher image quality).
- FIG. 2 is a block diagram illustrating a main configuration example of a manufacturing apparatus for manufacturing an image sensor to which the present technology is applied.
- a manufacturing apparatus 200 shown in FIG. 2 is an apparatus that manufactures the image sensor 100 (FIG. 1) to which the present technology is applied. That is, the manufacturing apparatus 200 manufactures an image sensor in which the FD 142 (N + layer 124) and the channel portion (P ⁇ layer 123) of the TG 141 are formed so that at least a part of each other overlaps.
- the manufacturing apparatus 200 includes a control unit 201 and a manufacturing unit 202.
- the control unit 201 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like.
- the control unit 201 controls each unit of the manufacturing unit 202 and controls processing related to the manufacturing of the image sensor 100. I do.
- the CPU of the control unit 201 executes various processes according to programs stored in the ROM. Further, the CPU executes various processes according to programs loaded from the storage unit 213 to the RAM.
- the RAM also appropriately stores data necessary for the CPU to execute various processes.
- the manufacturing apparatus 200 includes an input unit 211, an output unit 212, a storage unit 213, a communication unit 214, and a drive 215.
- the input unit 211 includes a keyboard, a mouse, a touch panel, an external input terminal, and the like, and receives user instructions and input of information from the outside and supplies them to the control unit 201.
- the output unit 212 includes a display such as a CRT (Cathode Ray Tube) display or an LCD (Liquid Crystal Display), a speaker, an external output terminal, and the like.
- Various types of information supplied from the control unit 201 can be displayed as images, sounds, or analog. Output as a signal or digital data.
- the storage unit 213 includes a solid state drive (SSD) such as a flash memory, a hard disk, and the like, stores information supplied from the control unit 201, and reads and supplies stored information according to a request from the control unit 201. To do.
- SSD solid state drive
- the communication unit 214 includes, for example, a wired LAN (Local Area Network), a wireless LAN interface, a modem, and the like, and performs communication processing with an external device via a network including the Internet. For example, the communication unit 214 transmits information supplied from the control unit 201 to the communication partner, or supplies information received from the communication partner to the control unit 201.
- a wired LAN Local Area Network
- a wireless LAN interface Wireless Local Area Network
- modem Wireless Local Area Network
- the communication unit 214 transmits information supplied from the control unit 201 to the communication partner, or supplies information received from the communication partner to the control unit 201.
- the drive 215 is connected to the control unit 201 as necessary. Then, a removable medium 221 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately attached to the drive 215. Then, the computer program read from the removable medium 221 via the drive 215 is installed in the storage unit 213 as necessary.
- a removable medium 221 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately attached to the drive 215.
- the computer program read from the removable medium 221 via the drive 215 is installed in the storage unit 213 as necessary.
- the manufacturing unit 202 is controlled by the control unit 201 to perform processing related to the manufacturing of the imaging device 100 to which the present technology is applied.
- the manufacturing unit 202 includes a PD (Photo Diode) forming unit 231, a pixel isolation region forming unit 232, a P ⁇ layer forming unit 233, an N + layer forming unit 234, a P + layer forming unit 235, an insulating film.
- a formation portion 236, a gate electrode formation portion 237, an interlayer insulating film formation portion 238, a contact formation portion 239, and a wiring layer formation portion 240 are included.
- the PD forming unit 231 is controlled by the control unit 201 in step S101, and an N-type photoelectric conversion and charge accumulation region N is formed on the surface of the silicon (Si) substrate supplied from the outside. Region 121 (photodiode 111) is formed.
- step S102 the pixel separation region forming unit 232 is controlled by the control unit 201 to form the P + region 122 (pixel separation region 112) so as to surround the photodiode 111 of the device supplied from the PD forming unit 231.
- step S ⁇ b> 103 the P ⁇ layer formation unit 233 is controlled by the control unit 201 and the device photodiode 111 (N region 121) or pixel separation region 112 (P + region 12) supplied from the pixel separation region formation unit 232.
- a P ⁇ layer 123 corresponding to the channel portion of TG 141 is formed on the surface of the substrate.
- step S104 the N + layer forming unit 234 is controlled by the control unit 201 to form the N + layer 124 of the FD 142 on the surface of the P ⁇ layer 123 of the device supplied from the P ⁇ layer forming unit 233 (FIG. 4). A).
- step S105 the P + layer forming unit 235 is controlled by the control unit 201 to remove a part of the N + layer 124 and the P ⁇ layer 123 of the device supplied from the N + layer forming unit 234, and the N region 121 and the P + A P + layer 125 is formed on the surface of the region 122. More specifically, the P + layer forming unit 235 applies a resist to the surface of the N + layer 124, and uses a mask and a lithography technique to form a resist opening region other than the channel portion and the FD 142 portion of the TG 141. . Then, the P + layer forming part 235 removes the P ⁇ layer 123 and the N + layer 124 in the resist opening region by a method such as dry etching.
- the P + layer forming unit 235 leaves the P ⁇ layer 123 and the N + layer 124 as the channel portion of the TG 141 and the FD 142, and removes the P ⁇ layer 123 and the N + layer 124 as other portions. Thereby, the P ⁇ layer 123 and the N + layer 124 stacked in a columnar shape are formed. Thereafter, the P + layer forming portion 235 forms a P + layer 125 (B in FIG. 4) in the resist opening region (a portion other than the P ⁇ layer 123 and the N + layer 124 stacked in a columnar shape), and the N + layer 124 by ashing. The resist left on the surface of is removed.
- step S106 the insulating film forming unit 236 is controlled by the control unit 201 to form the insulating film 126 on the surfaces of the N + layer 124 and the P + layer 125 of the device supplied from the P + layer forming unit 235 (FIG. 4). C).
- step S ⁇ b> 107 the gate electrode formation unit 237 is controlled by the control unit 201, and the P ⁇ layer 123 and the N + layer formed in a column shape from the top of the insulation film 126 of the device supplied from the insulation film formation unit 236.
- a gate electrode 127 is formed so as to surround (cover) the periphery of 124 (D in FIG. 4). More specifically, the gate electrode formation unit 237 forms a gate electrode material such as polysilicon on the insulating film 126, and performs resist coating, resist opening by a mask and a lithography technique, and dry etching. Then, the gate electrode 127 is formed.
- step S108 the interlayer insulating film forming unit 238 is controlled by the control unit 201 to form the interlayer insulating film 128 on the surface of the device (the insulating film 126 and the gate electrode 127) supplied from the gate electrode forming unit 237. (A in FIG. 5).
- step S109 the contact formation unit 239 is controlled by the control unit 201 so as to penetrate the interlayer insulation film 128 and the insulation film 126 from the surface of the device supplied from the interlayer insulation film formation unit 238 to the N + layer 124.
- a contact 129 is formed (FIG. 5B).
- step S110 the wiring layer forming unit 240 is controlled by the control unit 201 to form the wiring layer 130 on the surface of the device supplied from the contact forming unit 239 (C in FIG. 5).
- the manufacturing unit 202 supplies the imaging device 100 manufactured as described above to the outside, and ends the manufacturing process.
- the manufacturing apparatus 200 can easily manufacture the image sensor 100 with the same number of steps as in the case of manufacturing a conventional image sensor.
- FIG. 1 shows an example of the structure of one pixel as the image sensor 100
- the image sensor 100 can actually have any number of pixels.
- the gate electrode 127 is shown to cover the upper part of the FD 142 in the drawing, but the gate electrode 127 can apply a voltage to at least the P ⁇ layer 123 that is the channel portion of the TG 141.
- the gate electrode 127 may be arranged at any position as long as it is within the range.
- the gate electrode 127 may be formed on the surface of the insulating film 126 so as to surround part or all of the side surface of the P ⁇ layer 123 or the N + layer 124, or the P ⁇ layer 123 and the N + layer. It may be formed so as to surround part or all of the side surface of 124.
- the gate electrode 127 does not have to surround the entire periphery of the side surfaces of the P ⁇ layer 123 and the N + layer 124.
- the P ⁇ layer 123 and the N + layer 124 are described so as to overlap each other. May be overlapped.
- the FD 142 (N + layer 124) may overlap a part of the channel portion (P ⁇ layer 123) of the TG 141.
- a part of the FD 142 (N + layer 124) may overlap with a part of the channel part (P ⁇ layer 123) of the TG 141. That is, at least a part of the channel portion (P ⁇ layer 123) and the FD 142 (N + layer 124) of the TG 141 may overlap each other.
- the TG 141 and the FD 142 may be displaced from each other (positions may be different) on the plane viewed from the upper side or the lower side in FIG.
- Each shape of TG 141 and FD 142 is arbitrary and may be different from each other. Further, in the plane viewed from the upper side or the lower side in FIG. 1, the positions of the TG 141 and the FD 142 are such that the portion where the channel portion (P ⁇ layer 123) and the FD 142 (N + layer 124) of the TG 141 overlap is the photodiode 111. As long as it is within the area of
- the TG 141 and the FD 142 are formed in a substantially circular shape (substantially cylindrical) at the approximate center of the region of the photodiode 111 as shown in FIG. 6A in the plane viewed from the upper side or the lower side in FIG. You may make it do.
- the TG 141 and the FD 142 are formed in a rectangle (quadrangular prism shape) substantially at the center of the region of the photodiode 111 as shown in FIG. 6B on the plane viewed from the upper side or the lower side in FIG. You may make it do.
- the TG 141 and the FD 142 are formed in a triangle (triangular prism shape) at the end of the region of the photodiode 111 as shown in FIG. 6C in the plane viewed from the upper side or the lower side in FIG. You may make it do.
- the TG 141 and the FD 142 have a polygon (polygon) such as an octagon at the approximate center of the region of the photodiode 111 as shown in FIG. It may be formed in a columnar shape. Further, for example, the octagonal TG 141 and FD 142 are formed at the end of the region of the photodiode 111 as shown in E of FIG. 6 in the plane viewed from the upper side or the lower side of FIG. May be.
- a part of the octagonal TG 141 and FD 142 are formed at the end of the region of the photodiode 111 as shown in FIG. 6F in the plane viewed from the upper side or the lower side of FIG. You may make it do. That is, the gate electrode 127 does not have to surround the entire periphery of the FD 142 as in the examples of FIG. 6C and FIG.
- the readout distance from the photodiode 111 to the FD 142 is provided by providing the TG 141 and the FD 142 substantially at the center of the region of the photodiode 111. Since the longest distance is shortened, signal charges can be easily read out, and afterimages can be reduced.
- the FD 142 may be shared by a plurality of pixels as in the example shown in FIG. In that case, TGs 141 for the FD 142 need to be prepared for the number of pixels sharing the FD 142. In the example of FIG. 7, one FD 142 is shared by four pixels. Therefore, four photodiodes 111 and TG 141 are provided for one FD 142.
- the image sensor 100 includes an amplification transistor (amplifier (Amp)), a selection transistor (selector (Sel)), and a reset transistor (reset) for each pixel. (Rst)).
- These transistors may be formed in any way, for example, formed as a chip different from the chip having the photodiode 111 shown in FIG. 1, and these chips are connected to each other (Metal), Lamination may be performed by pasting the corresponding circuits for each pixel or for each of a plurality of pixels.
- FIG. 8 is a cross-sectional view showing a main configuration example of the image sensor in that case.
- An image sensor 300 shown in FIG. 8 outputs an image of a subject as an electrical signal by photoelectrically converting light incident from the upper side in the drawing.
- the image sensor 300 has a structure in which each chip of an image sensor chip (CIS (Contact Image Sensor)) 301, a logic circuit chip (Logic 1) 302, and a logic circuit chip (Logic 2) 303 is bonded. It has become.
- CIS Contact Image Sensor
- pixels having the same configuration as the image sensor 100 are formed. 8 corresponds to the image sensor 100 (a color filter and a condenser lens are added to the image sensor 100).
- the logic circuit chip (Logic1) 302 includes an amplification transistor (amplifier (Amp)), a selection transistor (selector (Sel)), and a reset transistor (pixels) of the pixel configuration of the image sensor chip (CIS) 301.
- a logic circuit such as reset (Rst) is formed.
- logic circuit chip (Logic 2) 303, other logic circuits including a pixel input system and an output system transistor are formed.
- the wirings of the image sensor chip (CIS) 301, the logic circuit chip (Logic 1) 302, and the logic circuit chip (Logic 2) 303 are connected to each other by vias (VIA) or the like. Particularly, the wiring of the image sensor 100 of the image sensor chip (CIS) 301 is bonded to the wiring of the logic circuit chip (Logic 1) 302 in the vicinity of the image sensor 100.
- the wiring of the image sensor chip (CIS) 301 and the logic circuit chip (Logic1) 302 in the pixel are connected to a circuit corresponding to each pixel or a plurality of pixels.
- the layout of the wiring connecting the FD142 to the transistor such as the amplifier (Amp) and reset (Rst) is further simplified, so the degree of freedom in wiring design is improved and the design becomes easier. .
- the wiring connecting the transistor such as the amplifier (Amp) and reset (Rst) from the FD 142 becomes long, and the conversion efficiency may be lowered due to the wiring capacity or the like.
- the wiring length of both chips in the pixel is bonded to the circuit corresponding to each pixel or each of the plurality of pixels, so that the wiring length can be shortened and the conversion efficiency is reduced. Can be suppressed.
- transistors such as an amplifier, a selector, and a reset can be superimposed on the photodiode 111. Therefore, in the conventional case, as shown in FIG. 9A, in addition to the region of the photodiode 111, it is necessary to provide a transistor region in which these transistors are arranged. Thus, as shown in FIG. 9B, this transistor region becomes unnecessary. Therefore, the photodiode 111 of each pixel can be enlarged. That is, the accumulated charge amount Qs can be increased, and the image quality of the captured image can be improved.
- the image sensor chip (CIS) 301 by separating the image sensor chip (CIS) 301 and the logic circuit chip (Logic 1) 302, the number of steps of each chip can be reduced, and each chip can be manufactured more easily. Further, since the image sensor chip (CIS) 301 only needs to form the photodiode 111, the TG 141, and the FD 142, the heat treatment can be performed regardless of the operation characteristics of the transistor (logic circuit). A low noise image sensor with fewer crystal defects can be realized.
- logic circuit of the logic circuit chip (Logic 2) 303 may be configured in the logic circuit chip (Logic 1) 302.
- the chip size can be further reduced by using a laminated structure as shown in FIG.
- FIG. 10 is a block diagram illustrating a main configuration example of a manufacturing apparatus for manufacturing an image sensor to which the present technology is applied.
- a manufacturing apparatus 400 illustrated in FIG. 10 is an apparatus that manufactures the image sensor 300 (FIG. 8) to which the present technology is applied.
- the manufacturing apparatus 400 includes a control unit 401 and a manufacturing unit 402.
- the manufacturing apparatus 400 further includes an input unit 211, an output unit 212, a storage unit 213, a communication unit 214, and a drive 215 to which the removable medium 221 is attached.
- the control unit 401 basically has the same configuration as that of the control unit 201, controls each unit of the manufacturing unit 402, and performs control processing related to the manufacturing of the image sensor 300.
- the manufacturing unit 402 is controlled by the control unit 401 to perform processing related to manufacturing of the imaging device 300 to which the present technology is applied.
- the manufacturing unit 402 includes a CIS manufacturing unit 431, a LOGIC1 manufacturing unit 432, a LOGIC1 coupling unit 433, a LOGIC2 manufacturing unit 434, a LOGIC2 coupling unit 435, a filter forming unit 436, and a condenser lens forming unit 437.
- the CIS manufacturing unit 431 is controlled by the control unit 401 in step S401 to manufacture the image sensor chip (CIS) 301 using a silicon (Si) substrate supplied from the outside ( FIG. 12A).
- This process is performed, for example, in the same manner as the flow of the manufacturing process of the image sensor 100 described with reference to the flowchart of FIG.
- step S ⁇ b> 402 the LOGIC1 manufacturing unit 432 is controlled by the control unit 401 and uses a silicon (Si) substrate supplied from the outside, and the amplifier (Amp) and selector of the pixel configuration of the image sensor chip (CIS) 301.
- a logic circuit chip (Logic 1) 302 in which transistors such as (Sel) and reset (Rst) are formed is manufactured (B in FIG. 12). This process is performed in the same manner as the conventional logic circuit manufacturing method.
- step S403 the LOGIC1 coupling unit 433 is controlled by the control unit 401 to invert the logic circuit chip (Logic1) 302 manufactured in step S402 and to invert the logic circuit chip (Logic1) 302.
- the lower surface (wiring side) is overlapped with the upper surface (wiring side) of the image sensor chip (CIS) 301 manufactured in step S401 and coupled.
- the LOGIC1 coupling unit 433 bonds the intra-pixel wiring of the image sensor chip (CIS) 301 and the wiring of the logic circuit chip (Logic1) 302 to a circuit corresponding to each pixel or each of a plurality of pixels.
- the circuits of both chips are connected.
- the configuration within the pixel of the CMOS image sensor is realized by a structure in which logic circuits such as an amplifier (Amp), a selector (Sel), and a reset (Rst) are superimposed on the side opposite to the light incident surface of the photodiode. Therefore, as described with reference to FIG. 9, the charge storage layer can be made larger.
- logic circuits such as an amplifier (Amp), a selector (Sel), and a reset (Rst) are superimposed on the side opposite to the light incident surface of the photodiode. Therefore, as described with reference to FIG. 9, the charge storage layer can be made larger.
- the LOGIC1 coupling unit 433 may further connect the circuits of both chips outside the pixel by using vias.
- the device (CIS + Logic1) 311 in which the image sensor chip (CIS) 301 and the logic circuit chip (Logic1) 302 are superimposed is manufactured.
- the LOGIC1 coupling unit 433 further thins the substrate of the logic circuit chip (Logic1) 302 corresponding to the upper surface of the device (CIS + Logic1) 311 (C in FIG. 12).
- step S ⁇ b> 404 the LOGIC2 manufacturing unit 434 is controlled by the control unit 401 to use other silicon (Si) substrates supplied from the outside and use other input / output systems for the pixels of the image sensor chip (CIS) 301.
- a logic circuit chip (Logic 2) 303 in which a logic circuit is formed is manufactured (A in FIG. 13). This process is performed in the same manner as the conventional logic circuit manufacturing method.
- step S405 the LOGIC2 coupling unit 435 is controlled by the control unit 401 to invert the logic circuit chip (Logic2) 303 manufactured in step S404 and to invert the logic circuit chip (Logic2) 303.
- the lower surface (wiring side) is overlapped and coupled to the upper surface (the substrate side of the thinned logic circuit chip (Logic1) 302) of the device (CIS + Logic1) 311 manufactured in step S403.
- the LOGIC1 coupling unit 433 uses vias to connect the wiring of the logic circuit chip (Logic2) 303 and the wiring of the device (CIS + Logic1) 311, so that the image sensor chip (CIS) 301, the logic The circuits of the circuit chip (Logic 1) 302 and the logic circuit chip (Logic 2) 303 are connected.
- a device (CIS + Logic1 + Logic2) 321 in which the image sensor chip (CIS) 301, the logic circuit chip (Logic1) 302, and the logic circuit chip (Logic2) 303 overlap each other is manufactured (B in FIG. 13). ).
- step S406 the LOGIC2 coupling unit 435 is controlled by the control unit 401 to invert the device (CIS + Logic1 + Logic2) 321 manufactured in step S405, and the device (CIS + Logic1 + Logic2) 321 is inverted.
- the substrate of the image sensor chip (CIS) 301 corresponding to the upper surface is thinned.
- step S407 the filter forming unit 436 is controlled by the control unit 401, and in step S406, the pixel portion of the image sensor chip (CIS) 301 on the upper surface of the device (CIS + Logic1 + Logic2) 321 whose substrate is thinned (step S406).
- a filter such as a color filter or an infrared filter is formed on the photodiode 111).
- step S408 the condensing lens forming unit 437 is controlled by the control unit 401, and forms a condensing lens on the surface of the filter (on the photodiode 111) formed in step S406.
- the manufacturing unit 402 supplies the imaging device 300 manufactured as described above to the outside, and ends the manufacturing process.
- the manufacturing apparatus 400 is basically similar to the process for manufacturing the image sensor chip (CIS) 301, the logic circuit chip (Logic1) 302, and the logic circuit chip (Logic2) 303 in the conventional imaging device.
- the image pickup device 300 can be easily manufactured only by manufacturing by number and bonding them together.
- FIG. 14 is a cross-sectional view showing a main configuration example of a part of an image sensor to which the present invention is applied.
- An image sensor 500 shown in FIG. 14 is basically the same image sensor as the image sensor 100 of FIG. 1 and has the same configuration as the image sensor 100.
- the P-layer 525 that is the channel portion of the TG 141 is formed inside the N region 121.
- the N + layer 523 of the FD 142 is formed so as to overlap with the upper side of the P ⁇ layer 525 in the drawing. Therefore, the N + layer 523 is formed so as to overlap the photodiode 111.
- the P + layer 524 (P + layer 524-1 and P + layer 524-2) is formed in the same manner as the P + layer 125. Therefore, a P + layer 524 and a P ⁇ layer 525 are formed on the upper surface of the photodiode 111 in the drawing.
- the thickness of the image sensor 500 (the length in the vertical direction (stacking direction) in the figure) can be made thinner than that of the image sensor 100.
- the image sensor 500 can proceed with subsequent processing steps at a lower step than in the case of the image sensor 100, it is possible to perform pattern formation with higher accuracy. Furthermore, since the stepped portion near the FD portion is formed with a stronger P + type, noise resistance such as white spots can be improved.
- FIG. 15 is a block diagram illustrating a main configuration example of a manufacturing apparatus for manufacturing an image sensor to which the present technology is applied.
- a manufacturing apparatus 600 shown in FIG. 15 is an apparatus that manufactures an image sensor 500 (FIG. 14) to which the present technology is applied.
- the manufacturing apparatus 600 includes a control unit 601 and a manufacturing unit 602.
- the manufacturing apparatus 600 further includes an input unit 211, an output unit 212, a storage unit 213, a communication unit 214, and a drive 215 to which the removable medium 221 is attached.
- the control unit 601 basically has the same configuration as that of the control unit 201, controls each unit of the manufacturing unit 602, and performs a control process related to manufacturing of the image sensor 500.
- the manufacturing unit 602 is controlled by the control unit 601 and performs processing related to manufacturing of the image sensor 500 to which the present technology is applied. As shown in FIG. 15, manufacturing unit 602 basically has the same configuration as manufacturing unit 202 (FIG. 2), but P ⁇ layer formation unit 233, N + layer formation unit 234, and P + layer formation unit 235. Instead, the N + layer forming unit 633, the P + layer forming unit 634, and the P ⁇ layer forming unit 635 are provided.
- step S601 and step S602 are performed similarly to each process of step S101 and step S102 of FIG.
- step S ⁇ b> 603 the N + layer formation unit 633 is controlled by the control unit 601, and the device photodiode 111 (N region 121) and the pixel separation region 112 (P + region 12) supplied from the pixel separation region formation unit 232.
- An N + layer 523 of FD142 is formed on the surface (A in FIG. 17).
- step S ⁇ b> 604 the P + layer forming unit 634 is controlled by the control unit 601 to remove a part of the N + layer 523 of the device supplied from the N + layer forming unit 633, so that the surface of the N region 121 and the P + region 122 is removed.
- a P + layer 524 is formed. More specifically, the P + layer forming unit 634 applies a resist to the surface of the N + layer 523, and forms a resist opening region other than the portion to be the FD 142 by using a mask and a lithography technique. Then, the P + layer forming unit 634 removes the N + layer 523 in the resist opening region by a method such as dry etching.
- the P + layer forming unit 634 leaves the portion of the N + layer 523 to be the FD 142 and removes the other portion of the N + layer 523. Thereby, the N + layer 523 stacked in a columnar shape is formed. Thereafter, the P + layer forming portion 634 forms a P + layer 524 in the resist opening region (a portion other than the N + layer 523 stacked in a columnar shape) (B in FIG. 17), and is left on the surface of the N + layer 523 by ashing. Remove the resist.
- step S605 the P-layer forming unit 635 is controlled by the control unit 601 to form the P-layer 525. More specifically, the P-layer forming unit 635 applies a resist in the same manner as in step S604, and uses a mask and a lithography technique to set a region slightly wider than the FD 142 including the FD 142 as a resist opening region.
- a P ⁇ layer 525 is formed in the N region 121 of the resist opening region (FIG. 17C). Since the P ⁇ layer 525 has a concentration sufficiently lower than the N-type impurity concentration formed in the N + layer 523 of the FD 142, the N + layer 523 is not affected. Thereafter, the P ⁇ layer forming unit 635 removes the resist left on the surface of the P + layer 524 by ashing.
- step S606 to step S610 is executed in the same manner as each processing from step S106 to step S110 in FIG. 3 (D in FIG. 17 and A in FIG. 18 to C in FIG. 18).
- the manufacturing unit 602 supplies the imaging device 500 manufactured as described above to the outside, and ends the manufacturing process.
- the manufacturing apparatus 600 can easily manufacture the image sensor 500 with the same number of steps as in the case of manufacturing a conventional image sensor. it can.
- the gate electrode 127 (a part or all of it) may also be formed (embedded) in the N region 121.
- a part or all of the N + layer 523 may be formed (embedded) in the N region 121 so that the thickness of the imaging element is further reduced. That is, the extent (height) of TG 141 and FD 142 having a structure in which at least a part of each other is stacked is exposed to the outside in the stacking direction from the surface opposite to the light incident surface of the photodiode 111, that is, in other words, photo The degree (depth) formed inside the diode 111 is arbitrary.
- FIG. 19 is a cross-sectional view showing a main configuration example of the image sensor in that case.
- An image pickup device 700 shown in FIG. 19 is basically an image pickup device similar to the image pickup device 100 shown in FIG. 1, in addition to an FD / TG unit 711, an amplifier (Amp), a selector (Sel), a reset (Rst), and the like.
- a TR portion 712 which is a transistor of
- the TR portion 712 is formed on the upper side of the pixel separation region 112 (P + region 122) in the drawing.
- FIG. 19 a cross-sectional view of the channel portion of the TR portion 712 is shown.
- the P ⁇ layer 722 of the channel portion is formed so as to overlap with the upper side of the P + layer 721 in the drawing. That is, the channel portion of the TR portion 712 is formed in a column shape.
- the N layer of the source portion and drain portion of the TR portion 712 is formed side by side in this channel portion (not shown).
- An insulating film 126 is formed on the surface of the channel portion, and a gate electrode 723 is formed so as to cover the channel portion from above.
- an interlayer insulating film 128 is formed on the upper side of the gate electrode 723 and the insulating film 126 in the drawing, and a contact 724 is formed on the upper side of the gate electrode 723 in the drawing so as to penetrate the interlayer insulating film 128.
- a wiring layer 130 including a wiring 725 for connecting the FD / TG portion 711 and the TR portion 712 is formed.
- an interlayer insulating film may be formed on the upper side of the wiring layer 130 in the drawing.
- FIG. 20 is a perspective view of the configuration of the FD / TG unit 711 and the TR unit 712 of the image sensor 700 when viewed obliquely from above.
- FIG. 21 is a plan view seen from the upper side in FIG.
- the gate width and gate length of the channel portion of the TR portion 712 can be increased. Thereby, the ON / OFF characteristic of the TR unit 712, the 1 / f noise characteristic, and the like can be improved.
- the TR portion 712 can be formed in the pixel isolation region 112 like the selector 741, the amplifier 742, and the reset 743 shown in FIG. 21, the photodiode 111 can be enlarged.
- FIG. 22 is a block diagram illustrating a main configuration example of a manufacturing apparatus for manufacturing an image sensor to which the present technology is applied.
- a manufacturing apparatus 800 shown in FIG. 22 is an apparatus that manufactures an image sensor 700 (FIG. 19) to which the present technology is applied.
- the manufacturing apparatus 800 includes a control unit 801 and a manufacturing unit 802.
- the manufacturing apparatus 800 further includes an input unit 211, an output unit 212, a storage unit 213, a communication unit 214, and a drive 215 to which the removable medium 221 is attached.
- the control unit 801 basically has the same configuration as that of the control unit 201, controls each unit of the manufacturing unit 802, and performs control processing related to the manufacturing of the image sensor 700.
- the manufacturing unit 802 is controlled by the control unit 801 and performs processing related to the manufacturing of the image sensor 700 to which the present technology is applied.
- the manufacturing unit 802 basically has the same configuration as the manufacturing unit 202 (FIG. 2), but the P ⁇ layer forming unit 233, the N + layer forming unit 234, the P + layer forming unit 235, Instead of the gate electrode formation portion 237, the contact formation portion 239, and the wiring layer formation portion 240, a P ⁇ layer formation portion 833, an N + layer formation portion 834, a transistor formation portion 835, a P + layer formation portion 836, and a gate electrode formation portion 838 A contact formation portion 840 and a wiring layer formation portion 841.
- step S801 and step S802 are performed similarly to each process of step S101 and step S102 of FIG.
- step S ⁇ b> 803 the P ⁇ layer forming unit 833 is controlled by the control unit 801, and the P ⁇ layer 123 of the TG 141 is formed on the surface of the photodiode 111 (N region 121) of the device supplied from the pixel isolation region forming unit 232. Form.
- step S804 the N + layer formation unit 834 is controlled by the control unit 801, and the FD 142 is placed on the surface of the P ⁇ layer 123 on the N region 121 of the photodiode 111 of the device supplied from the P ⁇ layer formation unit 833. N + layer 124 is formed.
- step S805 the transistor formation unit 835 is controlled by the control unit 801 to overlap the P + layer 721 on the upper side of the pixel isolation region 112 (P + region 122) of the device supplied from the N + layer formation unit 834.
- a channel part (P-layer 722) and source / drain parts (not shown) are formed (A in FIG. 24).
- the P + layer 721 and the P ⁇ layer 722 may be formed on the pixel isolation region 112 and the photodiode 111 on the upper side in the drawing.
- step S806 the P + layer formation unit 836 is controlled by the control unit 601, and the P ⁇ layer 123 and the N + layer 124, and the P + layer 721 and the P ⁇ layer 722 of the devices supplied from the transistor formation unit 835 are controlled. Each part is removed, and a P + layer 125 is formed on the surface of the N region 121.
- the P + layer forming portion 836 includes a portion that forms a FD / TG portion 711 by applying a resist to the surfaces of the N + layer 124 and the P ⁇ layer 722 and uses a mask and a lithography technique, and a TR portion. A resist opening region is formed in a portion other than the portion 712. Then, P + layer forming portion 836 removes P ⁇ layer 123 and N + layer 124, and P + layer 721 and P ⁇ layer 722 in the resist opening region by a method such as dry etching.
- the P + layer forming unit 834 leaves the P ⁇ layer 123 and the N + layer 124 as the FD / TG portion 711, and the P + layer 721 and the P ⁇ layer 722 as the TR portion 712, and other parts.
- the P-layer 123, the N + layer 124, the P + layer 721, and the P-layer 722 are partially removed. Thereby, not only the P ⁇ layer 123 and the N + layer 124 stacked in a columnar shape, but also a P + layer 721 and a P ⁇ layer 722 formed in a columnar shape are formed.
- the P + layer forming unit 836 forms the P + layer 125 in the resist opening region (B in FIG. 24), and strips the resist left on the surfaces of the N + layer 124 and the P ⁇ layer 722 by ashing.
- step S807 is executed in the same manner as in step S106 (C in FIG. 24).
- step S808 the gate electrode formation unit 838 is controlled by the control unit 801, and the P ⁇ layer 123 and the N + layer formed in a column shape from the top of the insulation film 126 of the device supplied from the insulation film formation unit 236.
- a gate electrode 127 is formed so as to surround (cover) the periphery of 124.
- the gate electrode formation portion 838 forms the gate electrode 723 so as to cover the P + layer 721 and the P ⁇ layer 722 formed in a column shape from above the insulating film 126 of the device (D in FIG. 24). .
- the gate electrode formation portion 838 forms a gate electrode material such as polysilicon on the insulating film 126, and performs resist coating, resist opening using a mask and a lithography technique, and dry etching. Then, the gate electrode 127 and the gate electrode 723 are formed.
- a gate electrode material such as polysilicon
- step S809 is executed in the same manner as in step S108 (A in FIG. 25).
- step S810 the contact forming unit 840 is controlled by the control unit 801 so as to penetrate the interlayer insulating film 128 and the insulating film 126 from the surface of the device supplied from the interlayer insulating film forming unit 238 to the N + layer 124.
- a contact 129 is formed.
- the contact forming portion 840 further forms a contact 724 from the surface of the device to the gate electrode 723 so as to penetrate the interlayer insulating film 128 (B in FIG. 25).
- step S811 the wiring layer forming unit 841 is controlled by the control unit 801, and the wiring 131 connected to the contact 129 of the FD / TG unit 711, for example, on the surface of the device supplied from the contact forming unit 840, and Then, the wiring layer 130 including the wiring 725 connected to the contact 724 of the TR portion 712 is formed (C in FIG. 25).
- An interlayer insulating film may be further formed on the upper side of the wiring layer 130 in the drawing.
- the manufacturing unit 802 supplies the imaging element 700 manufactured as described above to the outside, and ends the manufacturing process.
- the manufacturing apparatus 800 can easily manufacture the image sensor 700 with the same number of steps as in the case of manufacturing a conventional image sensor.
- the TR unit 712 includes at least one of an amplifier (Amp), a selector (Sel), and a reset (Rst). Formed as.
- FIG. 26 is a diagram illustrating a configuration example of an imaging apparatus to which the present technology is applied.
- An imaging apparatus 900 shown in FIG. 26 is an apparatus that images a subject and outputs an image of the subject as an electrical signal.
- the imaging apparatus 900 includes a lens unit 911, a CMOS sensor 912, an A / D conversion unit 913, an operation unit 914, a control unit 915, an image processing unit 916, a display unit 917, a codec processing unit 918, and A recording unit 919 is included.
- the lens unit 911 adjusts the focus to the subject, collects light from the focused position, and supplies the light to the CMOS sensor 912.
- the CMOS sensor 912 photoelectrically converts light from the subject supplied via the lens unit 911 and supplies the converted light to the A / D converter 913 as an electrical signal.
- the A / D converter 913 converts the electrical signal for each pixel supplied from the CMOS sensor 912 at a predetermined timing into a digital image signal (hereinafter also referred to as a pixel signal or image data as appropriate)
- the images are sequentially supplied to the image processing unit 916 at the timing.
- the operation unit 914 includes, for example, a jog dial (trademark), a key, a button, a touch panel, or the like, receives an operation input by the user, and supplies a signal corresponding to the operation input to the control unit 915.
- the control unit 915 Based on the signal corresponding to the user's operation input input by the operation unit 914, the control unit 915, the lens unit 911, CMOS sensor 912, A / D converter 913, image processing unit 916, display unit 917, codec processing
- the driving of the unit 918 and the recording unit 919 is controlled to cause each unit to perform processing related to imaging.
- the image processing unit 916 performs, for example, the above-described black level correction, color mixture correction, defect correction, demosaic processing, matrix processing, gamma correction, and YC conversion on the image signal supplied from the A / D converter 913. Various image processing is performed.
- the image processing unit 916 supplies the image signal subjected to the image processing to the display unit 917 and the codec processing unit 918.
- the display unit 917 is configured, for example, as a liquid crystal display or the like, and displays an image of a subject based on an image signal from the image processing unit 916.
- the codec processing unit 918 performs a predetermined encoding process on the image signal from the image processing unit 916 and supplies the image data obtained as a result of the encoding process to the recording unit 919.
- the recording unit 919 records the image data from the codec processing unit 918.
- the image data recorded in the recording unit 919 is read by the image processing unit 916 as necessary, and is supplied to the display unit 917 to display the corresponding image.
- CMOS sensor 912 of the imaging apparatus 900 an imaging element in which the FD (N + layer) and the TG channel part (P ⁇ layer) as described above are stacked so that at least a part of each other overlaps each other.
- the image pickup apparatus 900 has a larger charge accumulation region. can do. As a result, the amount of accumulated charge can be increased and the reduction in image quality can be suppressed.
- the imaging element to which the present technology is applied is not limited to the imaging device having the above-described configuration, and is an arbitrary one having an imaging function, such as a digital still camera, a video camera, a mobile phone, a smartphone, a tablet device, or a personal computer. It can be applied to the information processing apparatus.
- the present invention can also be applied to a camera module that is used by being mounted on another information processing apparatus (or mounted as an embedded device).
- the series of processes described above can be executed by hardware or software.
- a program constituting the software is installed from a network or a recording medium.
- this recording medium is a removable medium that distributes a program to a user separately from the apparatus main body and stores the program.
- the medium 221 is configured.
- the removable medium 221 includes a magnetic disk (including a flexible disk) and an optical disk (including a CD-ROM and a DVD). Further, magneto-optical disks (including MD (Mini-Disc)) and semiconductor memories are also included.
- MD Mini-Disc
- the above-described recording medium is not only such a removable medium 221, but also a ROM in which a program is recorded and a hard disk included in the storage unit 213, which is distributed to the user in a state of being incorporated in the apparatus main body in advance. It may be configured by.
- the program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.
- the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.
- system represents the entire apparatus composed of a plurality of devices (apparatuses).
- the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
- the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
- a configuration other than that described above may be added to the configuration of each device (or each processing unit).
- a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
- this technique can also take the following structures.
- the imaging device according to any one of (1) to (4), wherein the channel portion and the floating diffusion are shared by a plurality of pixels.
- a gate electrode of the read transistor is formed so as to surround a part or all of a side surface of the channel portion and the floating diffusion.
- the imaging device according to any one of (1) to (6), wherein a second chip on which a transistor is formed is coupled to overlap each other.
- the first chip and the second chip are circuits in which the wiring in the pixel of the first chip and the wiring of the second chip correspond to each pixel or every plurality of pixels.
- the imaging device according to (7). Of the amplifying transistor, the selecting transistor, and the resetting transistor constituting the pixel, the P ⁇ layer of each channel portion is formed so as to overlap the P + layer.
- a manufacturing apparatus for manufacturing an image sensor A channel forming portion that forms a channel portion of a readout transistor that constitutes a pixel of the imaging element;
- a manufacturing apparatus comprising: a floating diffusion forming part that forms a floating diffusion so that at least a part of each other overlaps the channel part formed by the channel forming part.
- It further includes a photodiode forming part for forming a photodiode, The channel forming portion forms the channel portion on the surface of the photodiode formed by the photodiode forming portion, The manufacturing apparatus according to (11), wherein the floating diffusion forming portion forms the floating diffusion so as to overlap with the channel portion formed on the surface of the photodiode.
- the floating diffusion formation part forms the floating diffusion on the surface of the photodiode formed by the photodiode formation part,
- the manufacturing apparatus according to (12) wherein the channel forming part forms the channel part inside the photodiode so as to overlap the floating diffusion formed by the floating diffusion forming part.
- At least one of the amplification transistor, the selection transistor, and the reset transistor constituting the pixel is formed so that the P ⁇ layer of each channel portion overlaps the P + layer.
- the manufacturing apparatus according to any one of (11) to (13), further including a transistor formation unit.
- an amplification transistor, a selection transistor, and a reset transistor that form the pixel are formed.
- a manufacturing department for manufacturing two chips The manufacturing apparatus according to any one of (11) to (14), further including: a coupling unit that overlaps and couples the second chip manufactured by the manufacturing unit with the first chip.
- the coupling unit bonds the wiring in the pixel of the first chip and the wiring of the second chip to a circuit corresponding to each pixel or each of a plurality of pixels.
- a third chip manufacturing unit that manufactures a third chip on which a logic circuit including an input system and an output system transistor of the pixel is formed;
- a third chip coupling unit that couples the third chip manufactured by the third chip manufacturing unit to the second chip coupled to the first chip by the coupling unit;
- a manufacturing method of a manufacturing apparatus for manufacturing an image sensor A channel forming part forms a channel part of a readout transistor constituting a pixel of the image sensor; The manufacturing method in which the floating diffusion forming portion forms the floating diffusion so that at least a part of each other overlaps the formed channel portion.
- An image processing apparatus comprising: an image processing unit that performs image processing on an image of a subject obtained by the image sensor.
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Abstract
Description
1.第1の実施の形態(撮像素子・製造装置・製造方法)
2.第2の実施の形態(撮像素子・製造装置・製造方法)
3.第3の実施の形態(撮像素子・製造装置・製造方法)
4.第4の実施の形態(撮像素子・製造装置・製造方法)
5.第5の実施の形態(撮像装置)
[撮像素子]
図1は、本技術を適用した撮像素子の一部について、主な構成例を示す断面図である。図1に示される撮像素子100は、図中下側から入射される光を光電変換することにより、被写体の画像を電気信号として出力する。
図2は、本技術を適用した撮像素子を製造するための製造装置の主な構成例を示すブロック図である。図2に示される製造装置200は、本技術を適用した撮像素子100(図1)を製造する装置である。つまり、製造装置200は、FD142(N+層124)と、TG141のチャネル部(P-層123)とが、少なくとも互いの一部が重畳するように形成される撮像素子を製造する。
図3のフローチャートを参照して、この製造部202により実行される製造処理の流れの例を説明する。必要に応じて、図4および図5を参照して説明する。
図1においては、撮像素子100として1画素分の構造例を示したが、実際には、撮像素子100は、任意の数の画素を有することができる。撮像素子100が複数の画素を有する場合、その内の少なくとも1画素以上が、図1に示されるような構造を有していれば良い。
[撮像素子]
なお、図1においては図示を省略したが、撮像素子100は、画素毎に、増幅用のトランジスタ(アンプ(Amp))、選択用のトランジスタ(セレクタ(Sel))、およびリセット用のトランジスタ(リセット(Rst))等の論理回路も有する。
図10は、本技術を適用した撮像素子を製造するための製造装置の主な構成例を示すブロック図である。図10に示される製造装置400は、本技術を適用した撮像素子300(図8)を製造する装置である。
図11のフローチャートを参照して、この製造部402により実行される製造処理の流れの例を説明する。必要に応じて、図12および図13を参照して説明する。
[撮像素子]
図1においては、フォトダイオード111(N領域121)の図中上側に、柱状に形成されるP-層123およびN+層124が重畳するように説明したが、これに限らず、P-層123およびN+層124は、図中上下方向(積層方向)について、その一部若しくは全部がN領域121の内部に(埋め込まれるように)形成されるようにしてもよい。
図15は、本技術を適用した撮像素子を製造するための製造装置の主な構成例を示すブロック図である。図15に示される製造装置600は、本技術を適用した撮像素子500(図14)を製造する装置である。
図16のフローチャートを参照して、この製造部602により実行される製造処理の流れの例を説明する。必要に応じて、図17および図18を参照して説明する。
なお、図14の例において、ゲート電極127(の一部若しくは全部)もN領域121内部に形成される(埋め込む)ようにしても良い。
[撮像素子]
以上においては、フォトダイオード、TG、およびFDについて説明したが、アンプ(Amp)、セレクタ(Sel)、およびリセット(Rst)等のトランジスタのチャネル部のP-層がP+層に重なるように形成されるようにしてもよい。
図22は、本技術を適用した撮像素子を製造するための製造装置の主な構成例を示すブロック図である。図22に示される製造装置800は、本技術を適用した撮像素子700(図19)を製造する装置である。
図23のフローチャートを参照して、この製造部802により実行される製造処理の流れの例を説明する。必要に応じて、図24および図25を参照して説明する。
[撮像装置]
図26は、本技術を適用した撮像装置の構成例を示す図である。図26に示される撮像装置900は、被写体を撮像し、その被写体の画像を電気信号として出力する装置である。
(1) 画素を構成する読み出しトランジスタのチャネル部およびフローティングディフュージョンが、少なくとも互いの一部が重畳するように形成される
撮像素子。
(2) 前記チャネル部および前記フローティングディフュージョンの一部若しくは全部が、前記画素を構成するフォトダイオードの外側に露出している
前記(1)に記載の撮像素子。
(3) 前記チャネル部および前記フローティングディフュージョンは、前記画素を構成するフォトダイオードの表面に柱状に形成される
前記(1)または(2)に記載の撮像素子。
(4) 前記チャネル部および前記フローティングディフュージョンは、1画素を構成するフォトダイオードの領域内に形成される
前記(1)乃至(3)のいずれかに記載の撮像素子。
(5) 前記チャネル部および前記フローティングディフュージョンは、複数画素により共有される
前記(1)乃至(4)のいずれかに記載の撮像素子。
(6) 前記チャネル部および前記フローティングディフュージョンの側面の一部若しくは全部を囲むように、前記読み出しトランジスタのゲート電極が形成される
前記(1)乃至(5)のいずれかに記載の撮像素子。
(7) 前記読み出しトランジスタ、前記フローティングディフュージョン、および、前記画素を構成するフォトダイオードが形成される第1のチップと、前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタが形成される第2のチップとが互いに重畳されて結合される
前記(1)乃至(6)のいずれかに記載の撮像素子。
(8) 前記第1のチップと前記第2のチップは、前記第1のチップの前記画素内の配線と、前記第2のチップの配線が、画素毎若しくは、複数画素毎に対応する回路に対して張り合わされるように、結合される
前記(7)に記載の撮像素子。
(9) 前記第1のチップと結合された前記第2のチップには、前記画素の入力系や出力系のトランジスタを含む論理回路が形成される第3のチップがさらに重畳され、結合される
前記(7)に記載の撮像素子。
(10) 前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタの内、少なくともいずれか1つの各チャネル部のP-層がP+層に重なるように形成される
前記(1)乃至(9)のいずれかに記載の撮像素子。
(11) 撮像素子を製造する製造装置であって、
前記撮像素子の画素を構成する読み出しトランジスタのチャネル部を形成するチャネル形成部と、
前記チャネル形成部により形成された前記チャネル部に対して、フローティングディフュージョンを、少なくとも互いの一部が重畳するように形成するフローティングディフュージョン形成部と
を備える製造装置。
(12) フォトダイオードを形成するフォトダイオード形成部をさらに備え、
前記チャネル形成部は、前記フォトダイオード形成部により形成された前記フォトダイオード表面に前記チャネル部を形成し、
前記フローティングディフュージョン形成部は、前記フォトダイオード表面に形成される前記チャネル部に重畳するように前記フローティングディフュージョンを形成する
前記(11)に記載の製造装置。
(13) 前記フローティングディフュージョン形成部は、前記フォトダイオード形成部により形成された前記フォトダイオード表面に前記フローティングディフュージョンを形成し、
前記チャネル形成部は、前記フローティングディフュージョン形成部により形成される前記フローティングディフュージョンに重畳するように、前記フォトダイオード内部に前記チャネル部を形成する
前記(12)に記載の製造装置。
(14) 前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタの内、少なくともいずれか1つを、各チャネル部のP-層がP+層に重なるように形成するトランジスタ形成部をさらに備える
前記(11)乃至(13)のいずれかに記載の製造装置。
(15) 前記読み出しトランジスタおよび前記フローティングディフュージョンが形成される第1のチップとは異なるチップとして、前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタが形成される第2のチップを製造する製造部と、
前記製造部により製造された前記第2のチップを、前記第1のチップに重畳し結合する結合部と
をさらに備える前記(11)乃至(14)のいずれかに記載の製造装置。
(16) 前記結合部は、前記第1のチップの前記画素内の配線と、前記第2のチップの配線を、画素毎若しくは、複数画素毎に対応する回路に対して張り合わせることにより、前記第1のチップと前記第2のチップとを結合する
前記(15)に記載の製造装置。
(17) 前記画素の入力系や出力系のトランジスタを含む論理回路が形成される第3のチップを製造する第3のチップ製造部と、
前記第3のチップ製造部により製造された前記第3のチップを、前記結合部により前記第1のチップと結合された前記第2のチップに結合する第3のチップ結合部と
をさらに備える前記(15)または(16)に記載の製造装置。
(18) 撮像素子を製造する製造装置の製造方法であって、
チャネル形成部が、前記撮像素子の画素を構成する読み出しトランジスタのチャネル部を形成し、
フローティングディフュージョン形成部が、形成された前記チャネル部に対して、フローティングディフュージョンを、少なくとも互いの一部が重畳するように形成する
製造方法。
(19) 画素を構成する読み出しトランジスタのチャネル部およびフローティングディフュージョンが、少なくとも互いの一部が重畳するように形成される撮像素子と、
前記撮像素子において得られた被写体の画像を画像処理する画像処理部と
を備える撮像装置。
(20) 前記撮像素子の前記チャネル部および前記フローティングディフュージョンは、前記画素を構成するフォトダイオードの表面に柱状に形成される
前記(19)に記載の撮像装置。
Claims (20)
- 画素を構成する読み出しトランジスタのチャネル部およびフローティングディフュージョンが、少なくとも互いの一部が重畳するように形成される
撮像素子。 - 前記チャネル部および前記フローティングディフュージョンの一部若しくは全部が、前記画素を構成するフォトダイオードの外側に露出している
請求項1に記載の撮像素子。 - 前記チャネル部および前記フローティングディフュージョンは、前記画素を構成するフォトダイオードの表面に柱状に形成される
請求項1に記載の撮像素子。 - 前記チャネル部および前記フローティングディフュージョンは、1画素を構成するフォトダイオードの領域内に形成される
請求項1に記載の撮像素子。 - 前記チャネル部および前記フローティングディフュージョンは、複数画素により共有される
請求項1に記載の撮像素子。 - 前記チャネル部および前記フローティングディフュージョンの側面の一部若しくは全部を囲むように、前記読み出しトランジスタのゲート電極が形成される
請求項1に記載の撮像素子。 - 前記読み出しトランジスタ、前記フローティングディフュージョン、および、前記画素を構成するフォトダイオードが形成される第1のチップと、前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタが形成される第2のチップとが互いに重畳されて結合される
請求項1に記載の撮像素子。 - 前記第1のチップと前記第2のチップは、前記第1のチップの前記画素内の配線と、前記第2のチップの配線が、画素毎若しくは、複数画素毎に対応する回路に対して張り合わされるように、結合される
請求項7に記載の撮像素子。 - 前記第1のチップと結合された前記第2のチップには、前記画素の入力系や出力系のトランジスタを含む論理回路が形成される第3のチップがさらに重畳され、結合される
請求項7に記載の撮像素子。 - 前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタの内、少なくともいずれか1つの各チャネル部のP-層がP+層に重なるように形成される
請求項1に記載の撮像素子。 - 撮像素子を製造する製造装置であって、
前記撮像素子の画素を構成する読み出しトランジスタのチャネル部を形成するチャネル形成部と、
前記チャネル形成部により形成された前記チャネル部に対して、フローティングディフュージョンを、少なくとも互いの一部が重畳するように形成するフローティングディフュージョン形成部と
を備える製造装置。 - フォトダイオードを形成するフォトダイオード形成部をさらに備え、
前記チャネル形成部は、前記フォトダイオード形成部により形成された前記フォトダイオード表面に前記チャネル部を形成し、
前記フローティングディフュージョン形成部は、前記フォトダイオード表面に形成される前記チャネル部に重畳するように前記フローティングディフュージョンを形成する
請求項11に記載の製造装置。 - 前記フローティングディフュージョン形成部は、前記フォトダイオード形成部により形成された前記フォトダイオード表面に前記フローティングディフュージョンを形成し、
前記チャネル形成部は、前記フローティングディフュージョン形成部により形成される前記フローティングディフュージョンに重畳するように、前記フォトダイオード内部に前記チャネル部を形成する
請求項12に記載の製造装置。 - 前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタの内、少なくともいずれか1つを、各チャネル部のP-層がP+層に重なるように形成するトランジスタ形成部をさらに備える
請求項11に記載の製造装置。 - 前記読み出しトランジスタおよび前記フローティングディフュージョンが形成される第1のチップとは異なるチップとして、前記画素を構成する、増幅用のトランジスタ、選択用のトランジスタ、およびリセット用のトランジスタが形成される第2のチップを製造する製造部と、
前記製造部により製造された前記第2のチップを、前記第1のチップに重畳し結合する結合部と
をさらに備える請求項11に記載の製造装置。 - 前記結合部は、前記第1のチップの前記画素内の配線と、前記第2のチップの配線を、画素毎若しくは、複数画素毎に対応する回路に対して張り合わせることにより、前記第1のチップと前記第2のチップとを結合する
請求項15に記載の製造装置。 - 前記画素の入力系や出力系のトランジスタを含む論理回路が形成される第3のチップを製造する第3のチップ製造部と、
前記第3のチップ製造部により製造された前記第3のチップを、前記結合部により前記第1のチップと結合された前記第2のチップに結合する第3のチップ結合部と
をさらに備える請求項15に記載の製造装置。 - 撮像素子を製造する製造装置の製造方法であって、
チャネル形成部が、前記撮像素子の画素を構成する読み出しトランジスタのチャネル部を形成し、
フローティングディフュージョン形成部が、形成された前記チャネル部に対して、フローティングディフュージョンを、少なくとも互いの一部が重畳するように形成する
製造方法。 - 画素を構成する読み出しトランジスタのチャネル部およびフローティングディフュージョンが、少なくとも互いの一部が重畳するように形成される撮像素子と、
前記撮像素子において得られた被写体の画像を画像処理する画像処理部と
を備える撮像装置。 - 前記撮像素子の前記チャネル部および前記フローティングディフュージョンは、前記画素を構成するフォトダイオードの表面に柱状に形成される
請求項19に記載の撮像装置。
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CN201380007928.6A CN104094406A (zh) | 2012-02-10 | 2013-02-01 | 图像拾取元件、制造装置和方法以及图像拾取装置 |
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JPWO2017057277A1 (ja) * | 2015-09-30 | 2018-07-26 | 株式会社ニコン | 撮像素子および撮像装置 |
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WO2023249016A1 (ja) * | 2022-06-24 | 2023-12-28 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子および撮像装置 |
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Also Published As
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JPWO2013118646A1 (ja) | 2015-05-11 |
KR20140133814A (ko) | 2014-11-20 |
US20150029374A1 (en) | 2015-01-29 |
CN104094406A (zh) | 2014-10-08 |
TW201334169A (zh) | 2013-08-16 |
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