WO2013112336A3 - Adaptive programming and erasure schemes for analog memory cells - Google Patents

Adaptive programming and erasure schemes for analog memory cells Download PDF

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Publication number
WO2013112336A3
WO2013112336A3 PCT/US2013/021756 US2013021756W WO2013112336A3 WO 2013112336 A3 WO2013112336 A3 WO 2013112336A3 US 2013021756 W US2013021756 W US 2013021756W WO 2013112336 A3 WO2013112336 A3 WO 2013112336A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cells
analog memory
adaptive programming
erasure
schemes
Prior art date
Application number
PCT/US2013/021756
Other languages
French (fr)
Other versions
WO2013112336A2 (en
Inventor
Eyal Gurgi
Yoava KASORLA
Ofir Shalvi
Original Assignee
Apple Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/356,694 external-priority patent/US9009547B2/en
Priority claimed from US13/471,484 external-priority patent/US9293194B2/en
Application filed by Apple Inc. filed Critical Apple Inc.
Priority to JP2014554739A priority Critical patent/JP6001093B2/en
Priority to EP13701345.4A priority patent/EP2807650A2/en
Priority to KR1020147023284A priority patent/KR101635695B1/en
Priority to CN201380006438.4A priority patent/CN104067348B/en
Publication of WO2013112336A2 publication Critical patent/WO2013112336A2/en
Publication of WO2013112336A3 publication Critical patent/WO2013112336A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of the memory cells in accordance with the set parameter.
PCT/US2013/021756 2012-01-24 2013-01-16 Programming and erasure schemes for analog memory cells WO2013112336A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2014554739A JP6001093B2 (en) 2012-01-24 2013-01-16 Analog memory cell programming and erasing methods
EP13701345.4A EP2807650A2 (en) 2012-01-24 2013-01-16 Programming and erasure schemes for analog memory cells
KR1020147023284A KR101635695B1 (en) 2012-01-24 2013-01-16 Adaptive programming and erasure schemes for analog memory cells
CN201380006438.4A CN104067348B (en) 2012-01-24 2013-01-16 Programming and erasing scheme for analog memory unit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/356,694 US9009547B2 (en) 2011-01-27 2012-01-24 Advanced programming verification schemes for analog memory cells
US13/356,694 2012-01-24
US13/471,484 2012-05-15
US13/471,484 US9293194B2 (en) 2011-01-27 2012-05-15 Programming and erasure schemes for analog memory cells

Publications (2)

Publication Number Publication Date
WO2013112336A2 WO2013112336A2 (en) 2013-08-01
WO2013112336A3 true WO2013112336A3 (en) 2013-09-26

Family

ID=48874052

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/021756 WO2013112336A2 (en) 2012-01-24 2013-01-16 Programming and erasure schemes for analog memory cells

Country Status (6)

Country Link
EP (1) EP2807650A2 (en)
JP (1) JP6001093B2 (en)
KR (1) KR101635695B1 (en)
CN (1) CN104067348B (en)
TW (1) TWI523011B (en)
WO (1) WO2013112336A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9135975B2 (en) * 2013-10-28 2015-09-15 Qualcomm Incorporated Write pulse width scheme in a resistive memory
IT201600121618A1 (en) * 2016-11-30 2018-05-30 St Microelectronics Srl METHOD OF REDUCING THE DURATION OF A MEMORY OPERATION IN A NON-VOLATILE MEMORY DEVICE AND ITS RELATIVE NON-VOLATILE MEMORY DEVICE
KR102533072B1 (en) * 2018-08-13 2023-05-17 에스케이하이닉스 주식회사 Memory system and operation method for determining availability based on block status

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060158940A1 (en) * 2005-01-19 2006-07-20 Saifun Semiconductors, Ltd. Partial erase verify
US7656710B1 (en) * 2005-07-14 2010-02-02 Sau Ching Wong Adaptive operations for nonvolatile memories

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10199263A (en) * 1996-12-30 1998-07-31 Sony Corp Non-volatile semiconductor memory device
JP2001093287A (en) 1999-09-24 2001-04-06 Sony Corp Nonvolatile semiconductor memory
US20050128807A1 (en) * 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
KR100719368B1 (en) * 2005-06-27 2007-05-17 삼성전자주식회사 Apparatus and Method for Adaptive Incremental Step Pulse Programming in Flash Memory Device
CN102005244B (en) 2007-02-20 2015-10-21 桑迪士克科技公司 The variable program of non-volatile memories
KR100843037B1 (en) * 2007-03-27 2008-07-01 주식회사 하이닉스반도체 Flash memory apparatus and method of erasing thereof
US8085586B2 (en) * 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
JP2010027165A (en) * 2008-07-22 2010-02-04 Toshiba Corp Nonvolatile semiconductor storage device and its data writing method
JP2010123210A (en) * 2008-11-20 2010-06-03 Toshiba Corp Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060158940A1 (en) * 2005-01-19 2006-07-20 Saifun Semiconductors, Ltd. Partial erase verify
US7656710B1 (en) * 2005-07-14 2010-02-02 Sau Ching Wong Adaptive operations for nonvolatile memories

Also Published As

Publication number Publication date
JP2015510653A (en) 2015-04-09
WO2013112336A2 (en) 2013-08-01
EP2807650A2 (en) 2014-12-03
CN104067348B (en) 2017-04-05
CN104067348A (en) 2014-09-24
TWI523011B (en) 2016-02-21
TW201346909A (en) 2013-11-16
JP6001093B2 (en) 2016-10-05
KR20140117583A (en) 2014-10-07
KR101635695B1 (en) 2016-07-01

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