JP2001093287A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a nonvolatile semiconductor memory in which threshold voltage after erasion can be controlled highly accurately by predicting an erasion characteristic based on a write-in characteristic, and performing memory erasion conforming to erasion conditions set in accordance with the above. SOLUTION: An erasion characteristic predicting means predicts an erasion characteristic in accordance with correlation between a write-in characteristic previously obtained and an erasion characteristic based on a write-in characteristic of a memory cell, and stores obtained erasion characteristic information in a storage means. At the time of erasion operation, erasion conditions, for example, the number of times of applying erasing pulse until reaching the prescribed threshold voltage is set by an erasion means in accordance with stored erasion characteristic information, as erasion operation is performed conforming the above, threshold voltage of a memory cell after erasion can be controlled to near the previously set erasion target value, threshold voltage of a memory cell after erasion can be controlled highly accurately without performing erasion verifying.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, in particular, a memory device having a floating gate type memory cell having a floating gate as a charge storage layer, which is estimated based on the write characteristics of each memory cell. The present invention relates to a nonvolatile semiconductor memory device for erasing a memory cell under an erasing condition.

[0002]

2. Description of the Related Art As a nonvolatile memory capable of holding write data almost semi-permanently, there is a NAND nonvolatile memory having a floating gate type memory cell as a storage element. In the NAND type nonvolatile memory, a large number of memory strings formed by connecting a plurality of memory cells in series are arranged on a substrate to form a memory cell array.
By controlling the amount of charge injected into the floating gate of each memory cell, it is possible to realize a so-called multi-level memory in which the threshold voltage of the memory cell can be set to a plurality of different levels, which is suitable for increasing the capacity. .
In such a multi-level memory device, a feature that a plurality of bits of data can be stored in one memory cell and a large capacity can be realized without increasing the number of memory cells has been attracting attention.
Research on AND-type non-volatile memories has been actively conducted.

In a floating gate type non-volatile memory cell, a control gate is maintained at a low voltage, for example, 0 V during erasing, a bit line and a source line connected to both ends of a memory string are floated, and By applying a positive high voltage (hereinafter referred to as an erase voltage) to each of the memory cells, a high electric field is generated from the floating gate to the channel formation region across the gate insulating film,
Since the FN tunneling phenomenon occurs in which charges (electrons) in the floating gate pass through the gate insulating film and are discharged to the channel formation region, accumulated charges in the floating gate are drawn out to the substrate side, and the threshold voltage of the memory cell decreases. It is kept at a low level, for example, a negative level like a depletion type transistor. By writing
Since the word line voltage connected to the control gate of each memory cell is set according to the write data,
The threshold voltage of each memory cell is controlled according to the write data. Therefore, the threshold voltage can be determined by detecting the read current flowing through the selected memory cell while changing the voltage of the word line connected to the control gate of the selected memory cell step by step in reading. The data stored in the selected memory cell can be read.

[0004] One feature of the NAND type nonvolatile memory is the simultaneous erasure of a plurality of memory cells. That is, the erasing operation is performed collectively for each memory cell array or for each memory block including a plurality of memory cells. For this reason, the NAND nonvolatile memory is usually called a NAND flash memory.

Conventionally, a threshold voltage is set to a negative level of 0 V or less by erasing, and it is made to correspond to, for example, data "1", and a threshold voltage is made to 0 V or more by writing to make it correspond to data "0". In the binary nonvolatile memory, a sufficient margin is provided between the threshold voltage distributions corresponding to the data "1" and "0", and the negative threshold voltage distribution is used for the write or read operation. Since there is no particular effect, the erase is performed by sufficiently applying a pulse signal having the amplitude of the erase voltage to the substrate side without verifying the threshold voltage during the erase operation.

In the case of a multi-level memory, a plurality of voltages corresponding to write data are applied to bit lines to write multi-level data simultaneously to a plurality of memory cells in order to speed up writing. Further, in the case of a multi-valued memory, a plurality of threshold voltage distributions are set in one memory cell in accordance with stored data, so that a margin between distribution ranges of each threshold voltage is smaller than that of a binary memory. In addition, it is necessary to take measures to prevent malfunction due to disturb at the time of writing. As a technique for realizing this, there is a local self-boost disclosed in Japanese Patent Application Laid-Open No. 8-279297.

When writing is performed using the local self-boost method, a high write voltage V is applied to the selected word line.
_{Apply pgm} to the first word line adjacent to the selected word line.
_Is applied, and the second pass voltage _Vpass2 is applied to all the word lines other than the selected word line and its adjacent word line. The first pass voltage V _pass1 is
By setting the voltage lower than the second pass voltage V _pass2 , the memory cell connected to the word line adjacent to the selected word line is kept in a non-conductive state. The voltage of each forming region is locally boosted by capacitive coupling. As a result, the voltage difference between the control gate of the selected memory cell and the channel formation region is suppressed to a value equal to or less than the voltage difference required for the occurrence of FN tunneling, and the fluctuation of the threshold voltage can be effectively prevented.

[0008]

By the way, multi-valued NAN
When parallel writing is performed using local self-boost in a D-type flash memory, the operation is subject to the following restrictions. First, it is necessary to determine the upper limit of the threshold voltage of the erased cell, and it is necessary to determine the lower limit of the threshold voltage of the erased memory cell in order to improve the disturbance resistance. That is, it is necessary to control so that the threshold voltage of the erased memory cell is distributed within a predetermined voltage range.

In order to realize these, it is necessary to verify after applying an erase pulse at the time of erasing to determine whether the threshold voltage of the memory cell has reached a target value. Verification is performed using, for example, a reference current generation circuit used for write verification.
This reference current is usually set to about 1 μA or less in order to eliminate the influence of AGL which causes a malfunction in reading. However, the reference current needs to be set to about 2.8 μA in order to obtain a necessary erase threshold voltage in order to realize parallel writing. For this reason, in the conventional NAND flash memory, there is a large difference between the determination currents for the write verify and the erase verify, and it is necessary to improve the erase verify in order to correctly perform the erase verify.

The present invention has been made in view of the above circumstances, and has as its object to predict the erasing characteristics of a memory cell and perform erasing under erasing conditions set accordingly.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of controlling a threshold voltage of a memory cell at the time of erasing with high accuracy.

[0011]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention controls the amount of charge stored in a floating gate as a charge storage layer by writing and erasing, Is set to at least two different levels, and has a memory cell for storing information according to the threshold voltage, wherein the erasing of the memory cell is performed in accordance with the write characteristics of the memory cell. Erasing characteristic estimating means for estimating the characteristic; characteristic storing means for storing the erasing characteristic information estimated by the erasing characteristic estimating means; and erasing characteristic information stored in the characteristic storing means at the time of erasing. Erasing means for determining an erasing condition and performing an erasing operation on the memory cell according to the erasing condition.

Further, the non-volatile semiconductor memory device of the present invention is, for example, a NAND type non-volatile memory, in which a plurality of memory strings formed by connecting a plurality of memory cells in series are arranged. In a memory cell array connected to a bit line and a source line via a memory cell, the control gates of a plurality of memory cells arranged in each memory cell row are connected to a plurality of word lines, respectively. A nonvolatile semiconductor memory device that controls the amount of charge stored in a floating gate, sets a threshold voltage to at least two different levels, and stores information according to the threshold voltage in each memory cell. An erase characteristic estimating method for estimating the erase characteristic of the memory cell according to the write characteristic of the memory cell. A characteristic storage unit for storing erasure characteristic information estimated by the erasure characteristic estimation unit; and an erasure condition for the memory cell determined according to the erasure characteristic information stored in the characteristic storage unit during erasure. Erasing means for performing an erasing operation on the memory cell according to a condition.

In the present invention, preferably, any one of the plurality of word lines is selected as a selected word line,
A write pulse having a write voltage as an amplitude is applied to the selected word line, a reference voltage is applied to a word line adjacent to the selected word line, and all the word lines except the selected word line and the adjacent word line are applied to the selected word line. A word line drive circuit for applying a pass voltage set between the write voltage and the reference voltage; and a bit line drive circuit for applying a voltage corresponding to write data to the bit line.

In the present invention, preferably, the erasing characteristic estimating means is configured to apply the program voltage applied to the control gate of the memory cell until the threshold voltage of the memory cell reaches a predetermined programming target value. The number of pulses is input as the write characteristic.

In the present invention, preferably, the erasing means holds the control gate of the memory cell at a reference potential, and applies an erasing pulse having a predetermined amplitude to a channel forming region of the memory cell. The charge is extracted from the floating gate. The erasing means determines the number of times of the erasing pulse applied to the channel forming region of the memory cell as the erasing condition until the threshold voltage of the memory cell reaches a predetermined erasing target value.

In the present invention, preferably, the erase characteristic estimating means estimates the erase characteristic of the memory cell based on a correlation between the write characteristic and the erase characteristic of the memory cell.

Further, in the present invention, preferably, the erasing characteristic estimation by the erasing characteristic estimating means is performed for each word line, for each memory block as an erasing unit, or for each memory chip. In response, the characteristic storage means stores the estimated erasure characteristic information for each word line, for each memory block, or for each memory chip.

According to the present invention, in the nonvolatile semiconductor memory device, the write characteristics,
For example, during a write operation, until the threshold voltage of the memory cell reaches a predetermined write reference value, erasing is performed based on the number of write pulses applied to the selected word line, based on the correlation between the previously obtained write characteristics and erase characteristics. The characteristics are estimated, and the obtained erasure characteristic information is stored in the storage means. At the time of the erasing operation, the erasing means sets erasing conditions, for example, the number of erasing pulses applied to the memory cells, according to the erasing characteristic information stored in the storage means, and the erasing operation is performed in accordance therewith. As a result, it is possible to control the threshold voltage of the erased memory cell to be close to a preset erase target value. That is, in the nonvolatile semiconductor memory device according to the present invention, the memory cell is erased according to the erasing condition set based on the erasing characteristic estimated from the writing characteristic instead of the erase verify at the time of the erasing operation. Can be controlled with high precision.

[0019]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. As shown, the nonvolatile semiconductor memory device according to the present embodiment includes a memory cell array 10, a column decoder & sense amplifier & data latch 20, a row decoder 30, a control circuit 40, a booster circuit 50, an erase characteristic estimating circuit 60, and a characteristic storage circuit. 70.

The memory cell array 10 is composed of a plurality of nonvolatile memory cells arranged in a matrix. Here, each memory cell is, for example, a floating gate type memory cell having a floating gate serving as a charge storage layer, and a control gate of each memory cell arranged in the same row is connected to the same word line, Selects the memory cells for each row. Write data is supplied to each memory cell arranged in the same column through the same bit line, and stored data is read from the same bit line. Each word line is connected to a row decoder 30, and each bit line is connected to a column decoder.

The column decoder selects one or a plurality of bit lines according to the input column address. At the time of reading, the selected bit line is connected to the sense amplifier, and the sense amplifier reads the stored data of the selected memory cell connected to the selected bit line.At the time of writing, the selected bit line is connected to the data latch, The voltage of the selected bit line is set according to the write data latched by the latch, and the write data is stored in the selected memory cell.

The sense amplifier operates at the time of reading and verifying, detects the potential of the selected bit line, and reads data stored in the selected memory cell according to the detected potential. The data latch operates at the time of writing, holds write data, and sets the selected bit line to a predetermined potential accordingly.

The row decoder 30 selects one or a plurality of word lines according to an input row address.
At the time of write, read or erase operation, a predetermined voltage is applied to each selected word line.

The control circuit 40 controls the operation of each partial circuit of the memory device according to a control signal input from the outside, and controls the writing, reading and erasing operations of the entire device.

The booster circuit 50 generates a necessary high voltage from the power supply voltage under the control of the control circuit 40 and supplies the generated high voltage to the row decoder 30 or another partial circuit. During the write, read and erase operations, the booster circuit 50 generates different voltages and supplies them to the selected word line or substrate.

The components described above have substantially the same configuration and function as the respective partial circuits of the conventional nonvolatile semiconductor memory device. Therefore, in the present invention, a detailed description of a partial circuit that can be configured by a known technique is omitted.

Erasure characteristic estimation circuit 60 and characteristic storage circuit 70
Are components proposed by the present invention. Hereinafter, each of these will be described. Erasing characteristic estimation circuit 60
Inputs the characteristic data at the time of writing to the memory cell from the control circuit 40, and estimates the erasing characteristic of the memory cell accordingly. Here, the write characteristic data refers to, for example, the number N of application of a write pulse until the threshold voltage of the memory cell reaches a predetermined target value in a write operation. In the nonvolatile memory and the NAND flash memory with characteristics, writing and erasing are both performed by injecting charges into or extracting charges from the floating gate of the memory cell by the FN tunneling current. That is, writing and erasing can be realized by generating a FN tunneling current passing through the gate oxide film by applying a high voltage to the same gate insulating film. Therefore, there is a certain relationship between the writing characteristics and the erasing characteristics. The present invention
Paying attention to the relationship between the writing and the erasing characteristics, the erasing characteristics are estimated in accordance with the writing characteristics, and the erasing conditions such as the voltage amplitude of the erasing pulse applied at the time of erasing and the number of times the erasing pulse is applied are estimated based on the erasing characteristics. Since the erasing operation is performed according to the estimation condition, the threshold voltage of the memory cell after erasing is guaranteed instead of the verifying operation after erasing.

Specifically, the erase characteristic estimating circuit 60 estimates the erase characteristic according to the write characteristic data input from the control circuit 40. Note that the write characteristic data is acquired by the control circuit 40 in, for example, writing performed during product inspection. Then, the erasing condition is set according to the estimated erasing characteristic, and the erasing condition is provided to the control circuit 40. Therefore, the control circuit 40 outputs an operation instruction to each of the partial circuits involved in the erasing operation according to the erasing condition. Then, the respective partial circuits operate accordingly, and the erasing operation is performed.

The characteristic storage circuit 70 stores characteristic data indicating a write characteristic or an erase characteristic of a memory cell. For example, when write characteristic data is input from the control circuit 40 in a write operation, the characteristic storage circuit 70
Stores the characteristic data and provides the characteristic data to the erasure characteristic estimation circuit 60 when necessary. Instead of the write characteristic data, for example, erase data indicating the erase characteristic estimated by the erase characteristic estimating circuit 60 can be stored. In this case, for example, the erase characteristic estimating circuit 6 during the write operation
From 0, the erasure characteristic data is output according to the estimation result, and stored by the characteristic storage circuit 70. Then, when performing the erasing operation, the erasing characteristic data is read by the control circuit 40, and the erasing condition is set accordingly.

As described above, in the nonvolatile semiconductor memory device of the present embodiment, the erasing characteristic estimating circuit 60 and the characteristic storing circuit 70 are provided in the conventional configuration, and the erasing characteristic estimating circuit 60 reduces the write characteristic of the memory cell. Erasing characteristics are estimated. At the time of erasing operation, erasing conditions are set based on the estimated erasing characteristics, and the erasing operation is performed in accordance therewith. Therefore, instead of erasing verify in a conventional nonvolatile memory, the threshold voltage of a memory cell after erasing is changed. Is guaranteed.

FIG. 2 is a circuit diagram showing one configuration example of the memory cell array 10. As shown in FIG. Here, for example, the configuration of a memory cell array will be described using a NAND flash memory as an example. As shown, the memory cell array 10 includes 16 rows × 4 columns of memory cells MC ₁₁ and MC arranged in a matrix.
_{12, MC 13, MC 14,} MC 21, MC 22, MC 23, M
C ₂₄ , ..., MC ₁₅₁ , MC ₁₅₂ , MC ₁₅₃ , MC ₁₅₄ ,
MC ₁₆₁ , MC ₁₆₂ , MC ₁₆₃ , MC ₁₆₄ .

In the memory cell array 10, each column has one
Six memory cells are connected in series to form a memory string. One end of each memory string is connected to the bit line side select transistor ST ₁₁ , ST ₁₂ , S
Through T _13, ST _14, the bit lines BL1, BL2, BL
3, is connected to BL4, the other end is connected to a common source line CSL via the source selection side selection transistors _{GT 11, GT 12, GT 13} , GT 14. The gates of the bit line side select transistors ST _{11 to} ST ₁₄ are connected to the select signal line DSG, and the source line side select transistors GT _{11 to} GT ₁₄
Are connected to the selection signal line SSG. The control gates of the memory cells arranged in each row are connected to word lines WL1, WL2,..., WL15, WL16, respectively. Here, the common source line CSL is, for example,
The word lines WL1 to WL16 are formed in a metal wiring layer, and are formed in a p-well region formed on the substrate.

The word lines WL1 to WL16 and the selection signal lines DSG and SSG are respectively connected to a row decoder 30. When writing, reading or erasing, the row decoder 30 applies predetermined voltage signals to these word lines and signal lines. Is applied. Bit lines BL1 to BL4
Are connected to a sense amplifier or a data latch circuit via a selection gate. ON / OFF of the select gate is controlled by a column decoder.

FIG. 3 shows an example of the distribution of the threshold voltage of the memory cell of this embodiment. As shown in the figure, the threshold voltages of the memory cells correspond to the storage data Data0 to Data7.
Are controlled so as to be distributed in eight different regions, respectively. Here, for example, the erase operation is controlled so that the threshold voltage _{Vth of the} memory cell is distributed in a negative region of 0 V or less. When the threshold voltage V _th is distributed in this region, the data stored in the memory cell is referred to as “Data
7 ".

By the write operation, the threshold voltage _Vth of the memory cell is set to a different distribution region according to the write data. For example, when the write data is “Data0”, as shown in FIG. 3, the threshold voltage _Vth of the memory cell is set to a distribution region equal to or higher than the voltage _Vg0 .

At the time of reading, data stored therein is read according to the threshold voltage _Vth of each memory cell. In a read operation, for example, a read voltage applied to a selected word line is scanned,
When each read voltage is applied, the read current flowing through the selected memory cell is detected by the sense amplifier, and the data stored in the selected memory cell is determined accordingly. For example, when a voltage V _g2 is applied to the selected word line,
When the read current is not detected by the sense amplifier and the voltage V _g3 is applied, and when the read current is detected by the sense amplifier, the threshold voltage V
_It can be seen that _th is distributed between the voltage V _g3 and the voltage V _g2, and the stored data can be determined to be Data3.

Hereinafter, data read, erase, and write operations in the nonvolatile semiconductor memory device according to the present embodiment will be described in more detail with reference to FIG. FIG.
In the figure, for example, the operating conditions at the time of reading, erasing, and writing operations for a selected memory cell connected to the word line WL6 as a selected word line are shown.

First, at the time of reading, for example, the bit lines BL1 to BL1 are supplied by a precharge circuit (not shown).
4 is set to a precharge voltage of about 1.5V. By the row decoder 30, the select signal line DSG, the voltage of each SSG 6V is applied, the bit line side select transistors ST ₁₁ ~ST ₁₄ and source line-side selection transistors GT ₁₁ ~GT ₁₄ are all turned on. Further, a voltage of 6 V is applied to other word lines except the selected word line WL6. Here, when the threshold voltage V _th of the memory cell is the highest, for example, the data “Dat” shown in FIG.
Assuming that the threshold voltage _Vth corresponding to a0 "is 5 V, when a voltage of 6 V is applied to the word line, all the memory cells connected thereto are turned on.
The common source line CSL is held at 0 V, and the p-well (Pw
ell) is also maintained at 0V.

A read voltage divided into a plurality of stages from 0 V to 6 V is sequentially applied to the selected word line WL6. For example, as shown in FIG. 3, a voltage of 0 V is applied to the selected word line WL6 in the order of V _g5 , V _g4 ,..., V _g0 . When the read voltage applied to the selected word line WL6 is lower than the threshold voltage _{Vth of} the selected memory cell, the selected memory cell is turned off and the read current does not flow, so that the bit line voltage remains almost at the precharge voltage. Become. On the other hand, when the read voltage is higher than the threshold voltage _{Vth of} the selected memory cell, the selected memory cell is turned on and a current path is formed from the bit line to the common source line CSL. The line potential drops and falls below the precharge voltage. Therefore, at the time of reading, the sense amplifier connected to the bit line
By detecting the bit line potential, data stored in the selected memory cell can be read.

Next, the erasing operation will be described. As shown in FIG. 3, during the erasing operation, the bit lines BL1 to BL4 are held in a floating state, and the selection signal DS
G, SSG and the common source line CSL are also held in a floating state. All word lines WL1 to WL16
Is maintained at 0 V, and an erase voltage of, for example, about 20 V is applied to the p-well.

Under such a bias condition, in each memory cell, the control gate is maintained at 0 V, the source and the drain are in a floating state, and the channel forming region is biased at a high erase voltage. Electrons flow from the floating gate toward the channel formation region, and the threshold voltage V _th of the memory cell decreases. For example, as shown in FIG.
The distribution area is set to a distribution area corresponding to “ata7 ″.

In this embodiment, the operating condition at the time of erasing is controlled according to the erasing characteristic estimated by the erasing characteristic estimating circuit 60. For example, it is assumed here that a pulse-like erase voltage is applied to the p-well during the erase operation. According to the estimated erase characteristics, the amplitude of the pulse signal, the pulse width, the number of times of application of the pulse, and the like are respectively set, so that after the erase operation, the threshold voltage _Vth of the memory cell falls within a certain distribution range. Converge. That is, in the present embodiment, verification after erasing is not performed, and instead, all the conditions of the erasing operation are accurately controlled based on the estimated erasing characteristics. _th can be controlled within a certain distribution range.

Next, the write operation will be described. In the present embodiment, writing is performed on the selected memory cell based on the local self-boost method. FIG.
As shown in FIG.
4 is applied with a voltage corresponding to the write data. For example, if the write data is the same as the data corresponding to the threshold voltage after erasing ("Data7" in FIG. 3), it is not necessary to change the threshold voltage of the memory cell, and the write disturb is not required. It is required to prevent a change in the threshold voltage. In this case, a bit line connected to the memory cell is set as a non-selected bit line, and a voltage corresponding to the power supply voltage V _CC is applied to the bit line.
On the other hand, a voltage of 0 to 1.4 V is applied to bit lines other than the non-selected bit lines according to the respective write data.

The row decoder 30 causes the selection signal line D
The power supply voltage V _CC is applied to SG, and 0 is applied to the selection signal line SSG.
Since the voltage of V is applied, the bit line side select transistors ST ₁₁ ~ST ₁₄ is turned on, the source line side select transistors GT ₁₁ ~GT ₁₄ is turned off. Further, the selected word line W
A high voltage of, for example, about 18 V (hereinafter, referred to as a program voltage V _pgm ) is applied to L6, and a voltage of 0 V is applied to a word line adjacent to the selected word line, in this case, word lines WL5 and WL7 on both sides of word line WL6. is, other word lines WL1 to WL4, about half of the pass voltage V _pass of the program voltage V _pgm to WL8～WL16, for example, 10
A voltage of around V is applied. At the time of writing, both the common source line CSL and the p-well are kept at 0V.

Hereinafter, the write operation in the local self-boost method will be described in more detail with reference to FIGS. FIG. 5 shows one row of memory cells. Hereinafter, for convenience of explanation, the bit line connected to the memory cell column is BLi (i is a natural number), the bit line side selection transistor is STi, the source line side selection transistor is GTi, and the memory cells are MC _1i , MC _2i,. …, M
C _6i ,..., MC _15i and MC _16i . Here, the memory cell _MC6i is a selected memory cell.

As shown in FIG. 5, a program voltage V _pgm is applied to a selected word line WL6, a voltage of 0 V is applied to word lines WL5 and WL7 adjacent thereto, and a pass voltage V _pass is applied to other word lines. Applied. Further, since the power supply voltage V _CC is applied to the selection signal line DSG, the bit line side selection transistor STi is turned on. Since a voltage of 0 V is applied to the selection signal line SSG, the source line side selection transistor GTi is turned off.

According to FIG. 4, the selected word line WL6
Program V _pgm applied to, for example, is about 18V, the pass voltage V _pass is applied to the selected word line and the word lines other than the neighboring word line of it, for example, 10V
It is about. When the selected memory cell MC _6i holds data corresponding to the threshold voltage distribution in the erased state, for example, data “Data7” shown in FIG. 3, the power supply voltage V _CC is applied to the bit line BLi. Cell MC _6i
When data “Data7” is written to bit line B
For example, 0 to 1.4 according to the write data.
A write voltage V _BL set between V is applied.

For writing, a voltage of 0 V is applied to the word lines WL5 and WL7 adjacent to the selected word line WL6, and a pass voltage V _pass is applied to the other word lines WL1 to WL4 and WL8 to WL16. This is performed in the procedure of applying the program voltage V _pgm to WL6. During a write, the bit line BLi, the write voltage V _BL corresponding to the write data is applied.

As described above, when the threshold voltage of the selected memory cell MC _6i is kept in the erased state, the power supply voltage V _CC is applied to the bit line BLi as the write voltage V _BL . Therefore, the source of the selection transistor STi is held in (V _CC -V _th1). Here, V _th1 is the threshold voltage of the selection transistor STi. Memory cells MC _{1i to} M 1 to which a pass voltage V _pass is applied to the control gate
C _4i turns on. Therefore, the pass voltage V _pass is when applied to the word line WL1 to WL4, the drain of the memory cell MC _5i is held in at least (V _CC -V _th1).
Then, when the program voltage V _pgm is applied to the selected word line WL6, the selected memory cell MC _6i is capacitively coupled to the selected memory cell MC _6i .
_Since the drain, source and channel formation regions of _6i are boosted to a high voltage, the adjacent memory cells MC _5i and MC _7i connected to both sides of the selected memory cell MC _6i are all turned off.

When the memory cells MC _5i and MC _7i on both sides of the selected memory cell MC _6i are turned off, boosting (self-boost) by capacitive coupling is performed only in the selected memory cell MC _6i , so-called local self-boost occurs. Therefore, the drain of the selected memory cell MC _6i ,
Since the source and the channel formation region are boosted to a voltage higher than the normal capacitance coupling, and the voltage difference between the control gate and the channel formation region is kept at a low level at which FN tunneling does not easily occur, the selected memory cell MC _6i A change in threshold voltage can be prevented.

Next, when the threshold voltage of the selected memory cell _MC6i is set to a level different from the threshold voltage after erasing according to the write data, as described above, the write operation is performed on the bit line BLi. set the write voltage V _BL between 0~1.4V is applied in accordance with the data. In this case, the selection transistor STi and the memory cells _{MC1i to} MC1M
When C _4i is turned on and the threshold voltage of the memory cell MC _5i adjacent to the selected memory cell MC _6i is set to the threshold voltage in the erased state, that is, 0 V or less, 0 is applied to the word line WL5.
Even when the voltage V is applied, the memory cell _MC5i is turned on. Therefore, the write voltage V _BL applied to the bit line BLi via the selection transistor STi and the memory cells MC _1i to MC _5i, it is transmitted to the channel formation region of the selected memory cell MC _6i. Accordingly, the channel voltage of the selected memory cell MC _6i is set according to the write voltage V _BL applied to the bit line BL. Therefore, when the program voltage V _pgm is applied to the selected word line WL6, According to the voltage difference between the control gate of the MC _6i and the channel formation region, the threshold voltage is controlled to a level corresponding to the write data by FN tunneling.

At the time of writing, a program voltage V _pgm which is a pulse signal is applied to the selected word line, and thereafter, it is determined by write verification whether or not the threshold voltage of the selected memory cell to be written has reached the target value. . The write pulse is repeatedly applied to the selected word line until the threshold voltage of the selected memory cell reaches the target value. In the write verify, for example, when a verify voltage based on a target threshold voltage value is applied to a selected word line, a current flowing through the selected memory cell is detected, and the detected current and a reference current (reference current) are determined. To determine whether or not the threshold voltage of the selected memory cell has reached the target value.

As described above, when writing is performed by the local self-boost method, in order to correctly control the threshold voltage of the selected memory cell in accordance with the write data, the threshold voltage V of the memory cell in the erased state is set. _th must be set below a certain level. That is, the threshold voltage V of the memory cell set by the erase operation
_th has an upper limit. Usually, in order to guarantee the upper limit value of the threshold voltage, erase verify is performed at the time of the erase operation, and the erase operation is performed while confirming whether the threshold voltage of the memory cell is equal to or lower than the upper limit value. Is repeated. Erasure verification can be performed using the reference current used in write verification. However, since the memory cell current in erase verification is significantly different from the memory cell current in write verification, sufficient accuracy cannot be obtained in the erase verification. .

FIG. 6 is a graph for comparing the erase verify current and the write verify current. As shown, the target threshold voltage V _th in the erased state is, for example, −
When the voltage is set to 1.5 V, the erase verify determination current corresponding thereto is 2.8 μA. On the other hand, in the write verification, for example, the threshold voltage V _th is determined by a reference current corresponding to −0.8 V, for example, 1 μA, and thus these determination reference currents have a large difference. That is,
The accuracy of the erase verify cannot be sufficiently guaranteed by the reference current of the read verify.

Therefore, in the present invention, instead of the erase verify, the erase characteristic of the memory cell is estimated from the write characteristic obtained in the write, for example, the write performed in the product inspection stage, and based on the estimated erase characteristic. By setting an erasing condition and performing an erasing operation in accordance therewith, the threshold voltage _Vth of the memory cell after erasing is set to a predetermined target value.

FIG. 7 is a graph showing a method for estimating the erase characteristic based on the write characteristic. FIG. 7 shows the ISPP
FIG. 9 shows a result obtained by simulation of an example of a writing operation using the (Incremental Step Pulse Programming) method. In the ISPP method, a write pulse is applied to a selected word line a plurality of times during writing. The voltage level of the write pulse is changed with an increase in the number of times of writing, and is set, for example, gradually higher. The ISPP method has an advantage that writing can be speeded up, and is currently widely used for writing in a nonvolatile memory.

As shown in FIG. 7, the number of applied pulses until the threshold voltage _Vth reaches a predetermined write target value _VthW differs depending on the variation of the memory cell. For example, if the threshold voltage initial value at the start of writing is V _th0 , the threshold voltage of a certain memory cell reaches the write target value V _thW by applying N1 pulses. The threshold voltage reaches the target value V _thW by applying N2 and N3 pulses to the other memory cells, respectively.

Since both erasing and writing of a memory cell can be realized by changing the threshold voltage by movement of electrons by FN tunneling, there is a strong correlation between operating conditions for writing and erasing. That is, when erasing is performed on a certain memory cell based on the number N of application of the write pulse at the time of writing, the erase pulse necessary to reach the threshold voltage after erasing to a certain reference value is obtained. Is uniquely determined.

For this reason, in the present invention, for example, the erase characteristic is estimated by the erase characteristic estimating circuit 60 shown in FIG. 1 based on the write characteristic of the memory cell. Specifically,
For example, the correlation between the write and erase operations obtained in advance is input to the erase characteristic estimating circuit 60, and the erase characteristic estimating circuit 60
Is the write characteristic obtained during the write operation, for example,
From the number of application of the write pulse, an erasing characteristic, for example, the number of application of the erasing pulse is estimated based on the correlation inputted in advance. The characteristic storage circuit 7 shown in FIG.
At the time of erasing operation, the control circuit 40 sets erasing conditions based on the stored data and executes the erasing operation. As a result, the threshold voltage of the erased memory cell is controlled so as to be substantially distributed within a predetermined target range.

For example, as shown in FIG. 7B, the erasing characteristic estimating circuit 60 obtains an estimation result of the number N1 'of application of the erase pulse corresponding to the number N1 of application of the write pulse. Similarly, the number of application of the write pulse N2 and N3
For each, the number of times N2 'and N
3 ′ are estimated respectively. The estimated number of times of application of the erase pulse is stored in the characteristic storage circuit 70, and the erase condition is set according to the stored data at the time of erase. Therefore, as shown in FIG. On the other hand, after applying the erasing pulse at the estimated number of times of erasing, each threshold voltage V _th is set to a target distribution range, for example, between the erasing upper limit value and the erasing lower limit value, and in the vicinity of the erasing target value V _thE . Controlled to be distributed.

FIG. 7 shows the result of simulation of writing by the ISPP method. However, the present invention is not limited to the writing method by the ISPP method. The erasing characteristic can be estimated by a method of controlling the erasing time.

The estimation of the erasing characteristic by the writing characteristic is performed by calculating the erasing characteristic by the writing characteristic based on, for example, an equation reflecting the FN tunneling characteristic, in addition to the above-described estimation method based on the correlation between the writing and the erasing. A method, or a method in which a database is created based on the writing characteristics and the erasing characteristics, and the erasing characteristics are estimated with reference to the database may be used.

Generally, non-volatile memory cells formed on the same chip have almost the same characteristics. For this reason, in the present invention, the erasure characteristic estimation circuit 60 estimates the erasure characteristic based on the write characteristic for each erasure of the nonvolatile memory cell, for example, for each memory block, and stores the erasure characteristic data according to the estimation result in the characteristic storage. It is held by the circuit 70. At the time of the erase operation, the erase condition is set based on the erase characteristic data stored in the characteristic storage circuit 70. That is, in a flash memory that performs batch erasure for each block, all memory cells are erased under the same erasure condition in the same erasure unit. Note that the present invention is not limited to this. For example, assuming that all memory cells on the same chip have the same characteristics, the erasing condition can be estimated and stored for each chip. Further, in order to improve the accuracy of the threshold voltage after erasing, it is also possible to subdivide an erasing unit, for example, a memory cell block into a plurality of groups, estimate erasing characteristics for each group, and set erasing conditions. it can. Thereby, the characteristic storage circuit 7
Although the storage capacity of 0 increases, the threshold voltage after erasing can be controlled with high accuracy.

The characteristic storage circuit 70 can be constituted by using a nonvolatile memory, but other storage means, for example,
It can also be constituted by an element such as a fuse. In this case, at the time of product inspection, the erasing characteristic is estimated according to the writing characteristic, the fuse is cut by, for example, a laser beam according to the obtained erasing characteristic data, and the erasing characteristic data is determined according to the cutting state of the fuse. Is stored.

In the above description, the NAND type nonvolatile memory has been described as an embodiment.
The present invention is not limited to the ND type nonvolatile memory. If there is some correspondence between the writing characteristic and the erasing characteristic, other nonvolatile memories, for example, NOR type, AN
The present invention can be applied to a nonvolatile memory such as a D-type memory. In each nonvolatile memory, for example, if the correlation between the write characteristics and the erase characteristics of the memory cells is obtained in advance, the erase characteristics and the erase conditions can be uniquely estimated based on the write characteristics. Then, by performing memory erasing according to the obtained erasing condition instead of the erase verify, the threshold voltage of the memory cell after erasing can be controlled with high accuracy.

[0066]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the erasing characteristic is estimated from the writing characteristic of the memory cell, and the erasing characteristic is estimated based on the erasing characteristic estimated at the time of erasing. Since the erase conditions are set according to the erase conditions set in place of erase verify, the threshold voltage of the memory cell after erasure can be set within the target range, and the erase threshold voltage can be controlled with high accuracy. ,
There is an advantage that the influence of write disturbance can be suppressed and a highly reliable multi-valued memory can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory cell array.

FIG. 3 is a distribution diagram of a threshold voltage of the multilevel memory.

FIG. 4 is a diagram showing read, erase, and write operation conditions of a memory;

FIG. 5 is a circuit diagram showing a write operation by local self-boost.

FIG. 6 is a graph showing an erase threshold voltage and a memory cell current of a memory cell.

FIG. 7 is a graph showing estimation of an erase characteristic based on a write characteristic.

[Explanation of symbols]

10 ... memory cell array, 20 ... column decoder & sense amplifier & data latch, 30 ... row decoder, 40 ...
Control circuit, 50 booster circuit, 60 erase characteristic estimating circuit, 70 characteristic storage circuit, WL1, WL2, WL
3,..., WL15, WL16... Word lines, BL1, BL
2, BL3, BL4 ... bit lines, CSL ... common source _{line, ST 11, ST 12, ST} 13, ST 14 ... bit line side select _{transistors, GT 11, GT 12, GT} 13, GT 14 ... source line side select transistor, V _CC ... the power supply voltage, GND ... ground potential.

Claims (19)

[Claims] 1. A method for controlling the amount of charge stored in a floating gate as a charge storage layer by writing and erasing, setting a threshold voltage to at least two different levels, and storing information according to the threshold voltage. A non-volatile semiconductor storage device having a memory cell to be erased, comprising: an erase characteristic estimating means for estimating an erase characteristic of the memory cell according to a write characteristic of the memory cell; and erase characteristic information estimated by the erase characteristic estimating means. Erasing conditions for the memory cells are determined according to the erasing characteristic information stored in the erasing characteristics at the time of erasing, and an erasing operation is performed on the memory cells in accordance with the erasing conditions. Nonvolatile semiconductor memory device having means. And a writing means for holding a channel forming region of the memory cell at a reference voltage, applying a write pulse having a predetermined amplitude to a control gate, and injecting a charge into the floating gate. 2. The nonvolatile semiconductor memory device according to claim 1, comprising: 3. The erasure characteristic estimating means sets a threshold voltage of the memory cell until a predetermined write target value is reached.
3. The nonvolatile semiconductor memory device according to claim 2, wherein the number of times of said write pulse applied to a control gate of said memory cell is inputted as said write characteristic. 4. The erasing means according to claim 1, wherein said erasing means holds a control gate of said memory cell at a reference potential, applies an erasing pulse having a predetermined amplitude to a channel forming region of said memory cell, and extracts electric charges from said floating gate. Item 3. The nonvolatile semiconductor memory device according to Item 1. 5. The erasing characteristic estimating means determines the number of erasing pulses applied to a channel forming region of the memory cell until the threshold voltage of the memory cell reaches a predetermined erasing target value. The nonvolatile semiconductor memory device according to claim 4, wherein the condition is determined. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said erase characteristic estimating means estimates an erase characteristic of said memory cell based on a correlation between a write characteristic and an erase characteristic of said memory cell. 7. In a memory cell array in which a plurality of memory strings formed by connecting a plurality of memory cells in series and each memory string is connected to a bit line and a source line via a selection transistor are provided in each memory cell row. The control gates of the plurality of memory cells arranged are connected to a plurality of word lines, respectively, and the amount of charge stored in the floating gate of each memory cell is controlled by writing and erasing, and the threshold voltage is set to at least two different levels. And storing information corresponding to the threshold voltage in each of the memory cells, wherein an erasing characteristic for estimating an erasing characteristic of the memory cell according to a writing characteristic of the memory cell. Estimating means; and characteristic storing means for storing erasing characteristic information estimated by the erasing characteristic estimating means. A nonvolatile semiconductor memory having an erasing means for determining an erasing condition of the memory cell according to the erasing characteristic information stored in the characteristic storing means at the time of erasing and performing an erasing operation on the memory cell in accordance with the erasing condition apparatus. 8. A method for selecting one of the plurality of word lines as a selected word line, applying a write pulse having an amplitude of a write voltage to the selected word line, and applying a write pulse to a word line adjacent to the selected word line. A word line drive circuit for applying a reference voltage and applying a pass voltage set between the write voltage and the reference voltage to all the word lines other than the selected word line and the word line adjacent thereto; 8. The non-volatile semiconductor memory device according to claim 7, further comprising: a bit line driving circuit for applying a voltage according to write data to the line. 9. The erasing characteristic estimating means until the threshold voltage of the memory cell reaches a predetermined write target value.
9. The nonvolatile semiconductor memory device according to claim 8, wherein the number of times of said write pulse applied to a control gate of said memory cell is inputted as said write characteristic. 10. The erasing means, wherein a control gate of the memory cell is held at a reference potential, an erasing pulse having a predetermined amplitude is applied to a channel forming region of the memory cell, and charges are extracted from the floating gate. Item 7. The nonvolatile semiconductor memory device according to item 7. 11. The erasing means sets the number of times of the erasing pulse applied to a channel forming region of the memory cell as the erasing condition until the threshold voltage of the memory cell reaches a predetermined erasing target value. The nonvolatile semiconductor memory device according to claim 10, wherein the determination is made. 12. The nonvolatile semiconductor memory device according to claim 7, wherein said erase characteristic estimating means estimates an erase characteristic of said memory cell based on a correlation between a write characteristic and an erase characteristic of said memory cell. 13. The nonvolatile semiconductor memory device according to claim 7, wherein said erase characteristic estimating means estimates said erase characteristic for each of said word lines. 14. The nonvolatile semiconductor memory device according to claim 13, wherein said characteristic storage means stores said erase characteristic information estimated for each of said word lines. 15. The erasing means, as a memory block erasing unit composed of memory cells connected to a plurality of word lines, performs erasing collectively for each erasing unit.
14. The nonvolatile semiconductor memory device according to claim 1. 16. The nonvolatile semiconductor memory device according to claim 15, wherein said erase characteristic estimating means estimates said erase characteristic for each of said memory blocks. 17. The nonvolatile semiconductor memory device according to claim 16, wherein said characteristic storage means stores said erase characteristic information estimated for each of said memory cell blocks. 18. The nonvolatile semiconductor memory device according to claim 15, wherein said erase characteristic estimating means estimates said erase characteristic for each memory chip. 19. The characteristic storage means stores the erase characteristic information estimated for each of the memory chips.
14. The nonvolatile semiconductor memory device according to claim 1.