KR101635695B1 - Adaptive programming and erasure schemes for analog memory cells - Google Patents

Abstract

In a memory including a plurality of analog memory cells, a method for data storage includes setting parameters of an iterative process applied to a group of memory cells based on one or more data values stored in at least one memory cell of the memory cells . The iterative process is performed in the group of memory cells according to the set parameters.

Description

[0001] ADAPTIVE PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS [0002]

The present invention relates generally to data storage, and more particularly to methods and systems for post-pulse cell threshold voltages for programming and erasing analog memory cells.

Various types of memory devices, such as flash memories, use arrays of analog memory cells to store data. Each analog memory cell maintains a predetermined level of a given physical amount, such as charge or voltage, that represents the data stored in the cell. These levels of physical quantity are also referred to as stored values or analog values. In flash memories, for example, each analog memory cell holds a predetermined amount of charge. The range of possible analog values is typically divided into regions, where each region corresponds to a programming state representing one or more data bit values. Data is written to the analog memory cell by writing a nominal analog value corresponding to the desired bit or bits.

Some memory devices, often referred to as single-level cell (SLC) devices, store a single bit of information in each memory cell, that is, each memory cell is capable of estimating two possible memory states Can be programmed. High-density devices, often referred to as Multi-Level Cell (MLC) devices, can store more than two bits per memory cell, i.e., can be programmed to estimate two or more possible memory states.

Flash memory devices are described in, for example, Bez et al., "Introduction to Flash Memory," Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489- 502]. Multi-level flash cells and devices are described in, for example, Eitan et al., &Quot; Multilevel Flash Cells and their Trade-Offs, "Proceedings of the IEEE International Electron Devices Meeting (IEDM), New York, New York, pages 169-172. This document compares several types of multilevel flash cells, such as common ground, DINOR, AND, NOR, and NAND cells.

Et al., "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?", Incorporated herein by reference. (NROM) in the Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 21-24, 1999, pages 522-524. An analog memory cell will be described. NROM cells are also described in Maayan et al., "A 512 Mb NROM Flash Data Storage Memory with 8 MB / s Data Rate ", Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, California, February 3-7, 2002, pages 100-101. Other exemplary types of analog memory cells may include Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, MRAM cells, Charge Trap Flash (CTF) (PRAM, also referred to as phase change memory-PCM) cells. The FRAM, MRAM, and PRAM cells may be fabricated using the techniques described in Kim and Koh, "Future Memory Technology including Emerging New Memories," Proceedings of the 24 ^th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384.

Various methods for programming and erasing analog memory cells are known in the art. Some memory devices use an iterative programming and verification (P & V) process to apply a sequence of pulses to a group of memory cells and verify the programmed values during the sequence.

The embodiments of the invention described herein provide a method for data storage. The method includes setting a group of analog memory cells to respective analog values by performing an iterative process of applying a sequence of pulses to memory cells in a group of analog memory cells. During the iterative process, the progress of the iterative process is evaluated, and the parameters of the iterative process are modified in response to the evaluated progress. The iterative process continues according to the modified parameters.

In some embodiments, performing the iterative process includes programming the memory cells in the group according to the data. In other embodiments, performing an iterative process includes erasing a group of memory cells.

In an embodiment, evaluating the progress includes evaluating whether the number of memory cells in the group that reached each intended analog value as a result of the pulses exceeds a predefined number. Modifying the parameters includes modifying the amplitude or duration increments between consecutive pulses in the sequence. In another embodiment, evaluating the progress includes evaluating whether the number of pulses applied to the memory cells in the group exceeds a predefined number.

In the disclosed embodiment, the step of modifying the parameters may comprise an increment of amplitude or duration between consecutive pulses in the sequence, an amplitude or duration of the initial pulse in the sequence, a programming word line voltage applied to a group of memory cells word line voltage, an unselected word line voltage applied to another group of memory cells, a programming bit line voltage applied to memory cells in the group intended to receive subsequent pulses, And / or modifying an inhibiting bit line voltage applied to the memory cells in the group intended to be inhibited from receiving subsequent pulses.

The step of modifying the parameters may include programming a bit line voltage applied to the memory cells in the group intended to receive subsequent pulses, a programming word line voltage applied to the group of memory cells, Depending on the inhibited bit line voltage applied to the memory cells in the group intended to be inhibited from receiving the voltage, or the subsequent pulses.

According to an embodiment of the present invention, there is additionally provided an apparatus for data storage comprising a memory and a storage circuit. The memory includes a plurality of analog memory cells. The storage circuitry sets the group of analog memory cells to respective analog values by performing an iterative process of applying a sequence of pulses to the memory cells in the group of analog memory cells, evaluating the progress of the iterative process, Modify the parameters of the iterative process in response, and proceed to perform the iterative process according to the modified parameters.

According to an embodiment of the present invention, a method for data storage in a memory including a plurality of analog memory cells is also provided. The method includes setting a parameter of an iterative process applied to a group of memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of memory cells according to the set parameters.

In an embodiment, performing the iterative process includes programming the memory cells in the group according to the data. In another embodiment, performing an iterative process includes erasing a group of memory cells. In an embodiment, the step of setting parameters includes copying data values from at least one of the memory cells to an alternative storage location, and setting parameters based on the copied data values.

In another embodiment, the step of setting the parameters may comprise the step of increasing the amplitude or duration between successive pulses in the iterative process, the amplitude or duration of the initial pulse in the iterative process, the programming wordline voltage A non-selected word line voltage applied to another group of memory cells, a programming bit line voltage applied to memory cells in a group intended to receive subsequent pulses, and / or a memory within the group intended to be prohibited from receiving subsequent pulses And setting a forbidden bit line voltage applied to the cells.

According to an embodiment of the present invention, there is further provided an apparatus for data storage comprising a memory and a storage circuit. The memory includes a plurality of analog memory cells. The storage circuit is configured to set the parameters of the iterative process applied to the group of memory cells based on the one or more data values stored in at least one of the memory cells in the memory and to perform the iterative process in the group of memory cells according to the set parameters .

According to an embodiment of the present invention, a method for storing data in a memory including a plurality of analog memory cells is additionally provided. The method includes programming one or more of the memory cells according to data by performing a programming operation. A performance measure of the programming operation performed on the programmed memory cells is evaluated. After performing the programming operation, the erase operation is configured based on the performance measurements of the programming operation, and the group of memory cells in the memory is erased by performing a configured erase operation.

In some embodiments, evaluating the performance measure includes measuring the duration of the programming operation. In an embodiment, the step of configuring the erase operation may include an increment of amplitude or duration between successive erase pulses in the erase operation, an amplitude or duration of the initial pulse in the erase operation, a word line voltage applied during the erase operation, And / or setting an applied bit line voltage during an erase operation.

In an embodiment, estimating the performance measure includes determining the number of programming and erasing cycles applied to the programmed memory cells, and wherein configuring the erasing operation includes erasing based on a determined number of programming and erasing cycles And configuring the operation.

According to an embodiment of the present invention, there is also provided an apparatus for data storage comprising a memory and a storage circuit. The memory includes a plurality of analog memory cells. The storage circuit may program one or more of the memory cells according to the data by performing a programming operation, evaluate a performance measure of the programming operation performed on the programmed memory cells, perform a programming operation, And erase the group of memory cells in the memory by performing a configured erase operation.

According to an embodiment of the present invention, a method for storing data in a memory including a plurality of analog memory cells is further provided. The method includes applying to the group of memory cells an operation of setting memory cells in the group to respective analog values. The performance measure of the operation applied to the group of memory cells is evaluated. The health status of the memory blocks in the memory containing the group is evaluated based on the evaluated performance measures of the operation.

Applying the operation may include programming the memory cells in the group according to the data. Alternatively, applying the operation may comprise erasing the group of memory cells. In an embodiment, evaluating the performance measure comprises measuring the duration of the operation. In another embodiment, evaluating the health state includes marking the memory block as bad when the performance measurement deviates from a predefined range. In another embodiment, evaluating the health state includes marking the memory block as an object of additional evaluation when the performance measurement deviates from a predefined range. In yet another embodiment, evaluating the health state includes setting a storage configuration for subsequent data storage in the memory block, depending on performance measurements.

According to an embodiment of the present invention, there is additionally provided an apparatus for data storage comprising a memory and a storage circuit. The memory includes a plurality of analog memory cells. The storage circuit is configured to apply the operation of setting the memory cells in the group to respective analog values in a group of memory cells, to evaluate a performance measure of the operation applied to the group of memory cells, and based on the evaluated performance measure of operation, And to evaluate the health state of the memory block in the memory including the group.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be more fully understood from the following detailed description of embodiments thereof taken in conjunction with the drawings, in which: Fig.

≪ 1 >
1 is a block diagram schematically illustrating a memory system, in accordance with an embodiment of the present invention.
2,
Figure 2 is a circuit diagram that schematically illustrates an array of analog memory cells, in accordance with an embodiment of the present invention.
3A,
Figure 3A is a diagram schematically illustrating a process for programming a group of analog memory cells, in accordance with an embodiment of the present invention.
3b,
Figure 3B is a diagram schematically illustrating a process for erasing a group of analog memory cells, in accordance with an embodiment of the present invention.
<Fig. 4>
4 is a flow diagram schematically illustrating a method for programming or erasing a group of analog memory cells, in accordance with an embodiment of the present invention.
5,
5 is a flow diagram schematically illustrating a method for programming a group of analog memory cells, in accordance with an embodiment of the present invention.
6,
6 is a flow diagram schematically illustrating a method for erasing a group of analog memory cells, in accordance with an embodiment of the present invention.
7,
7 is a flow diagram schematically illustrating a method for evaluating a health level of a group of analog memory cells, in accordance with an embodiment of the present invention.

summary

In memory devices such as flash memory, data is typically stored in analog memory cells by programming memory cells with respective analog values representing stored bit values. Each bit value corresponds to a respective programming level or programming state, which is represented by a predetermined region of analog values.

In some memory devices, a group of analog memory cells is programmed in a repetitive programming and verification (P & V) process, which applies a sequence of programming pulses to memory cells in the group. The analog values of the memory cells are verified during the sequence by comparing each analog value to a respective verification threshold corresponding to the intended programming state of the memory cell being programmed. Programming continues only for memory cells whose analog values are still below their respective verification thresholds. Other memory cells are presumed to be correctly programmed, and it is prohibited to receive subsequent programming pulses. The block of flash memory cells is typically erased using a recursive erase process, which applies a sequence of erase pulses to the memory cells in the block. The analog values of the memory cells are verified during the sequence by comparing them to the erase threshold.

The embodiments of the invention described below provide improved methods and systems for programming and erasing analog memory cells such as flash cells. Compared to conventional programming and erasing techniques, the disclosed techniques achieve lower programming and erase times as well as higher programming and erase reliability.

In some embodiments, a storage circuit (e.g., a read / write circuit coupled to memory cells or a memory controller) evaluates the progress of the iterative programming or erase process and, based on the evaluated progress, Modify it. The progress can be evaluated, for example, for the percentage of memory cells that have reached their intended analog values, or for the number of programming or erase pulses applied to the memory cells.

The various programming or erasing parameters may be modified based on various word lines or bit line voltages applied during the progress, e. G., Continuous programming or increment of amplitude or duration between erase pulses, initial pulse amplitude, .

In alternative embodiments, the storage circuit sets one or more parameters of a programming or erasing process based on data stored in one or more of the memory cells. In other embodiments, the storage circuit configures one or more parameters of the erase operation based on the performance of the programming operation. For example, the storage circuit may measure an average programming time for pages in a given memory block, and may configure an erase operation for the block depending on the measured programming time.

In still other embodiments, the storage circuit evaluates the health state of the memory block based on (e.g., based on programming or erase time) the performance measure of the programming or erasing operation performed in the block.

System Description

1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. The system 20 may be any of a variety of devices, such as computing devices, cellular phones or other communication terminals, removable memory modules (sometimes referred to as "USB flash drives"), solid state disks May be used in various host systems and devices, such as other media players and / or any other system or device in which data is stored and retrieved.

The system 20 includes a memory device 24 that stores data in a memory cell array 28. The memory array includes a plurality of memory blocks (34). Each memory block 34 includes a plurality of analog memory cells 32. In the context of the present patent application and in the claims, the term "analog memory cell" is used to describe any memory cell that maintains a continuous analog value of a physical parameter, such as voltage or charge. The array 28 may include, for example, NAND, NOR and charge trap flash (CTF) flash cells, phase change RAM (PRAM, also referred to as phase change memory-PCM), nitride read only memory (NROM), ferroelectric RAM Such as FRAM, magnetic RAM (MRAM), and / or dynamic RAM (DRAM) cells.

The charge levels stored in the cells and / or the analog voltages or currents written to and read from the cells are collectively referred to herein as analog values, analog stored values or stored values. The stored values may include, for example, threshold voltages or any other suitable type of stored values. System 20 stores data in analog memory cells by programming the cells to estimate respective programming states, also referred to as programming levels. Programming states are selected from a finite set of possible states, with each programming state corresponding to a predetermined nominal storage value. For example, a 3 bit / cell MLC can be programmed to estimate one of eight possible programming states by writing one of eight possible nominal storage values to the cell.

The memory device 24 includes a read / write (R / W) unit 36 which converts the data for storage in the memory device into analog storage values and writes them to the memory cells 32. In alternate embodiments, the R / W unit does not perform the conversion, but is provided with storage values for storing the voltage samples, i. E., In the cells. When reading data from the array 28, the R / W unit 36 converts the stored values of the memory cells 32 into digital samples with resolution of one or more bits. The data is typically written to and read from the memory cells in groups referred to as pages. In some embodiments, the R / W unit may erase a group of cells 32 by applying one or more negative erase pulses to the cells. Erasing is typically performed on the entire memory blocks.

The storage and retrieval of data at and at the memory device 24 is performed by the memory controller 40. [ The memory controller includes an interface 44 for communicating with the memory device 24, and a processor 48 that performs various memory management functions. The memory controller 40 communicates with the host 52 to receive data for storage in the memory device and to output the retrieved data from the memory device. The memory controller 40, and in particular the processor 48, may be implemented in hardware. Alternatively, the memory controller may comprise suitable software or a microprocessor that drives a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown for conceptual clarity only. Any other suitable memory system configuration may also be used. Elements not required for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits, and debugging circuits have been omitted from the drawings for clarity.

Although the example of Figure 1 illustrates a single memory device 24, the system 20 may include a plurality of memory devices controlled by the memory controller 40. In the exemplary system configuration shown in FIG. 1, the memory device 24 and the memory controller 40 are implemented as two separate integrated circuits (ICs). However, in alternate embodiments, the memory device and the memory controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or a System on Chip (SoC) And can be interconnected via an internal bus. Additionally or alternatively, some or all of the memory controller circuitry may be on the same die on which the memory array is disposed. Additionally or alternatively, some or all of the functionality of the memory controller 40 may be implemented in software, and may be performed by a processor or other element of the host system. In some embodiments, the host 52 and the memory controller 40 may be fabricated on the same die or on separate dies in the same device package.

In some embodiments, the memory controller 40 includes a general purpose processor, which is programmed with software to perform the functions described herein. The software may be downloaded to the processor in electronic form, for example over a network, or it may alternatively or additionally be a non-transitory tangible media, such as magnetic, optical, or electronic memory, And / or &lt; / RTI &gt;

In an exemplary configuration of array 28, memory cells 32 are arranged in a plurality of rows and columns, each memory cell including a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. A memory array is typically divided into a plurality of pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes subdivided into sectors. In some embodiments, each page includes an entire row of the array. In alternative embodiments, each row (word line) may be divided into two or more pages. For example, in some devices each row is divided into two pages, one containing odd-order cells and the other containing even-order cells.

Typically, the memory controller 40 programs the data in page units, but erases the entire memory blocks 34. Typically, though not necessarily, the memory block is approximately 10 ⁶ memory cells, while the page is approximately 10 ³ to 10 ⁴ memory cells.

The following discussion illustrates several exemplary techniques for programming and erasing the memory cells 32 of the array 28. The disclosed techniques may be performed by the memory controller 40 and / or by the R / W unit 36. For clarity, the following description shows the programming and erasing processes as being performed by the R / W unit 36 in the memory device. However, in general, the various tasks that make up the disclosed programming and erasing techniques may be partitioned between the memory controller and the R / W circuit in any suitable manner, or may be performed by any one of these elements. Thus, in the context of the present patent application, and in the claims, the memory controller 40 and / or the R / W circuit 36 are collectively represented as a storage circuit that performs the disclosed techniques.

Figure 2 is a circuit diagram that schematically illustrates an array of analog memory cells that may be used to implement array 28, in accordance with an embodiment of the invention. In this embodiment, the array includes a plurality of flash memory cells (shown in the figure as floating-gate transistors) connected by word lines 64 and bit lines 68.

In some embodiments, the R / W unit 36 uses a repetitive programming and verification (P & V) process to write a group of memory cells (e.g., all memory cells , Odd-numbered cells, or even-numbered cells). In this process, the unit 36 applies a sequence of programming pulses to a group of cells, and verifies the threshold voltages of the cells in the group after each pulse. The unit 36 prohibits subsequent programming of cells that have reached their intended threshold voltages so that subsequent pulses are selectively applied only to those cells that have not yet reached the intended threshold voltages.

During the P & V process, the unit 36 biases the various word lines 64 and bit lines 68 in accordance with the appropriate voltages. The example of Figure 2 shows three word lines 64, and its intermediate word lines are programmed. This example illustrates a particular instance during the P & V process where memory cell 72 is programmed (because it has not yet reached its intended threshold voltage). At the same time, the memory cell 80 in the same word line is inhibited from being programmed because it has already reached its intended threshold voltage. Memory cells in other word lines, such as memory cell 80, are not programmed.

To program the appropriate memory cells, the R / W unit 36 biases the intermediate word line according to the programming voltage indicated by Vpgm and the other word lines in the block according to the pass voltage indicated by Vpass_pgm. Unit 36 biases the bit lines to be programmed according to the bit line programming voltage indicated by Vbitline_pgm and the bit lines to be programmed according to the bit line inhibition voltage indicated by Vbitline_inhibit.

3A is a diagram schematically illustrating a process of programming a group of analog memory cells 28, in accordance with an embodiment of the present invention. This example illustrates a group of 2 bits / cell memory cells (e.g., all memory cells, odd-numbered cells, or even-numbered cells in a word line) programmed according to the data. Each cell is programmable to one of four possible programming levels (also referred to as programming states) corresponding to four threshold voltage distributions 84A ... 84D. Each programming level corresponds to a respective 2-bit data value. The programming level 84A corresponding to negative threshold voltages also acts as an erase level. Before programming is started, all the memory cells in the group are set to the erase level.

In some embodiments, the R / W unit 36 programs the memory cells in the group using a recursive P & V process, as described above. Upon verifying the cell threshold voltages after a given programming pulse, the unit 36 compares the cell threshold voltages to one or more verification thresholds. In the preset example, the unit 36 uses three verification thresholds 88A ... 88C, which correspond to the programming levels 84B ... 84D, respectively. When a threshold voltage of a given memory cell intended to be programmed at a predetermined programming level exceeds a verification threshold of the programming level, the memory cell is inhibited from receiving subsequent programming pulses. The inhibition is typically performed by changing the bit line voltage of the cell from Vbitlie_pgm to Vbitline_inhibit.

(This example illustrates a programming process that concurrently programs all four programming levels for clarity.) In some embodiments, the unit 36 includes a group of memory cells according to two pages in two phases - one phase programs the first page using two programming levels and the second phase all uses the four programming levels to program the second page.

Figure 3B is a diagram schematically illustrating a process for erasing a group of analog memory cells 28, in accordance with an embodiment of the present invention. The erase process is typically applied to the entire block 34 simultaneously. In the erase process, the unit 36 applies the sequence or erase pulses to the memory cells and verifies the cell threshold voltages by comparing them to the erase threshold 92. The erase procedure continues until all the memory cells in the block (or a predefined controlled number of cells in some embodiments) have threshold voltages that are lower than the threshold value 92.

The embodiments of Figures 3A and 3B illustrate the programming and erasing of two bits / cell memory cells. However, the disclosed techniques are applicable to any other suitable type of memory cells having programming levels of any desired number and arrangement.

Programming / erasing based on programming / erasing progression Adaptive  Modified

In some embodiments, when programming or erasing a group of analog memory cells, the R / W unit 36 evaluates the progress of the iterative programming or erase process. When the progress meets certain switching conditions, the unit 36 modifies one or more of the parameters of the process.

Unit 36 can evaluate progress in various ways, i.e. define and evaluate various types of switching conditions. For example, the unit 36 may determine whether the predefined ratios of memory cells in the group have reached their intended threshold voltages (e. G., Exceeding the appropriate verification threshold for programming operation or under an erase threshold for erase operation) Or whether it has fallen to the bottom of the screen. In the erase operation, the unit 36 may evaluate the number of cells that are erased sufficiently after the first erase pulse or after two erase pulses. In alternate embodiments, the unit 36 may combine cell counts from two or more different verification steps of the iterative process.

When using this kind of condition, the R / W unit 36 can assume that the data is scrambled or otherwise equally distributed among the programming levels. In alternate embodiments, the R / W circuitry may determine the number of cells at each programming level or acquire this information in any other suitable manner before initiating the programming operation.

Another exemplary switching condition is to modify the programming or erasing parameters after performing a predefined number of iterations, i. E., Applying a predefined number of programming or erasing pulses. As a further alternative, the R / W unit can evaluate switching conditions by determining the absolute value of some of the parameters associated with programming or erasing.

In various embodiments, the R / W unit may modify any suitable parameters of the iterative programming or erasing process when the switching condition is met. The parameters may include, for example, an amplitude or duration increment (sometimes referred to as an incremental step pulse programming-ISPP) between consecutive programming / erase pulses in the sequence, and / or an amplitude or duration . &Lt; / RTI &gt;

Additionally or alternatively, in a programming operation, the modified parameters may include a pass voltage (Vpass_pgm) applied to the unselected word lines, a word line voltage (Vpgm) applied to the selected word line, a bit applied to the programmed cells The line voltage Vbitline_pgm, the bit line voltage applied to the forbidden cells Vbitline_inhibit, and / or any other suitable parameter. Additionally or alternatively, in an erase operation, the modified parameter may include, for example, the word line voltage and / or the bit line voltage applied in the erased block.

In an exemplary embodiment, the unit 36 evaluates the number of memory cells in the group that reached their intended programming level. When the ratio exceeds a predefined value, the unit 36 changes the amplitude increment between successive pulses.

In another exemplary embodiment, the unit 36 starts the erase process in accordance with the large erase pulse voltage. When the ratio of successfully-erased memory cells reaches a predetermined predefined value, the unit 36 reduces the erase pulse voltage for subsequent pulses.

In another embodiment, the R / W unit 36 modifies one or more of the biasing voltages (e.g., Vbitline_pgm, Vbitline_inhibit, Vpass_pgm) as a function of Vpgm. This type of programming allows the unit 36 to optimize the word line and / or bit line voltages and to efficiently program the memory cells.

Voltage optimization may be performed, for example, to minimize program disturb from adjacent memory cells (on adjacent word lines and / or adjacent bit lines). In some embodiments, optimization is performed as a function of the absolute value of Vpgm.

4 is a flow diagram that schematically illustrates a method for programming or erasing a group of analog memory cells 32, in accordance with an embodiment of the present invention. The method begins in an initialization step 96 with an R / W unit 36 that initiates a repetitive programming or erase process in a group of memory cells.

At some point during the programming or erasing process, the unit 36 evaluates the progress of the process, in the progress evaluation stage 100. Unit 36 checks whether the process has been completed in completion check step 104. [ The unit 36 may, for example, check whether all of the cells have reached their intended threshold voltages. If the process is complete, the method ends at an end step 108.

Otherwise, the unit 36 checks in the switching condition evaluation step 112 whether a predefined switching condition (based on the progress evaluated in step 100) is satisfied. If the progress of the iterative process satisfies the switching condition, the unit 36 modifies one or more of the parameters of the iterative process in the parameter modification step 116. [ The method then returns to step 100 where the unit 36 continues to track the progress of the iterative process.

Programming the process parameters based on the data Adaptive  Set

In some embodiments, the R / W unit 36 sets one or more parameters of the iterative programming or erase process based on data stored in one or more of the current memory cells. Any suitable programming or erasing process parameters may be set in this manner, such as the above listed parameters (e.g., ISPP, amplitude or duration of the initial pulse in the sequence, and / or any word line or bit line voltage) .

For example, when programming a group of memory cells (e.g., pages), the unit 36 may be programmed based on data stored in the same word line as the programmed group and / or on one or more other ) &Lt; / RTI &gt; word lines. For example, unit 36 may set Vbitline_pgm to less than or greater than the wordline of the programmed group based on data (or threshold voltages) in corresponding cells in adjacent word lines. In some embodiments, the unit 36 may first read the data used to set the programming parameters and store the data at an alternative location prior to programming.

As another example, when erasing a block, the unit 36 may set one or more parameters of the erase process based on data stored in the block. For example, the unit 36 may set the parameters of the erase process as a function of the number of word lines programmed in the block prior to erasure. In an exemplary embodiment, unit 36 sets one erase voltage (Verase) if all of the word lines in the block are programmed, and a different erase voltage if only a part of the word lines are programmed. In some embodiments, an indication of the number of programmed word lines is provided to the unit 36 by the memory controller 40. In other embodiments, the unit 36 determines the number of programmed word lines regardless of the memory controller. In some embodiments, the unit 36 alters one or more parameters of the programming process based on the number of programmed word lines in the block.

As another example, if the block includes a plurality of memory cells programmed with high threshold voltages, the unit 36 can set the initial amplitude of the erase pulses to a high value, and vice versa.

5 is a flow diagram that schematically illustrates a method for programming a group of analog memory cells 32, in accordance with an embodiment of the invention. Although the description of Figure 5 shows the programming process in a group of memory cells, a similar method may also be used in the erase process.

The method begins with a unit 36 for reading data from one or more memory cells in a readout step 120. Read memory cells may or may not belong to a group of memory cells to be programmed. Based on the data read in step 120, the unit 36 sets one or more parameters of the programming process in the parameter setting step 124. Unit 36 then stores the data in a group of memory cells using a repetitive programming process with the set parameters in a programming step 128.

Setting of erase process parameters based on the performance of the programming process

In some embodiments, the unit 36 configures an erase operation to be applied to a group of memory cells, based on the performance of the programming operation applied to the memory. Typically, though not necessarily, an erase operation on a given group of cells (e.g., a block) is configured based on the performance of the programming operation applied to one or more memory cells in the group (e.g., on pages in the block) .

This technique is based on the fact that the responsiveness of the memory cells to the programming operation (typically with the application of positive-voltage programming pulses) represents the responsiveness of the memory cells to the erase operation (typically with the application of negative-voltage programming pulses) . The unit 36 may evaluate the performance measurements of any suitable type of programming operation and may configure the erase operation in any suitable manner based on the evaluated performance measurements.

For example, unit 36 may measure the programming time (duration) of a programming operation, e.g., the time elapsing between the start and completion of an operation, or the number of P & V iterations performed in a programming operation. The unit 36 may then configure the erase operation based on the measured programming time. In an exemplary embodiment, the unit 36 may measure the number or percentage of cells that have reached their intended programming level as a function of the number of iterations. In other words, the unit 36 can evaluate the cumulative distribution function (CDF) of the number of successfully-programmed cells.

The unit 36 may perform any suitable erase operation based on the performance of the programming operation, such as the initial size or duration of erase pulses, the increment between successive erase pulses, and / or any bit line or word line voltage applied during erase By setting the parameter, the erase operation can be configured.

6 is a flow diagram that schematically illustrates a method for erasing a group of analog memory cells 32, in accordance with an embodiment of the present invention. The description of Figure 6 shows programming and erasing of the same group of memory cells. However, in general, the disclosed technique can be used to erase a certain group of memory cells based on the ability to program other groups. The two groups may or may not have memory cells in common.

The method begins with the unit 36 programming a group of memory cells according to the data by performing a programming operation (e.g., a P & V process) at a programming step 132. Unit 36 estimates the performance measure of the programming operation in performance estimation step 136. [ For example, the unit 36 may estimate the programming time (programming duration), or any other suitable performance measure.

Based on the estimated performance measure of the programming operation, the unit 36 constructs an erase operation to be applied to the group of memory cells in an erase configuration step 140. [ Unit 36 erases the group of memory cells using the erase operation configured in the erase step 144. [

In some embodiments, the unit 36 or the memory controller 40 may perform an erase operation on a predetermined memory block based on other performance measures, such as based on the number of programming and erase (P / E) The operation can be configured. In one embodiment, after programming, unit 36 or memory controller 40 may record some indications of the life of the block and may retrieve such an indication prior to erasure to configure the erase operation.

Health level evaluation based on programming or erasing performance

In some embodiments, the unit 36 measures the performance of an iterative programming or erasing process applied to a group of memory cells and evaluates the health state of the memory cells based on the measured performance. The following description refers to measuring the duration of a programming or erasing process, although the disclosed technique may be used with other suitable performance measures.

In an embodiment, unit 36 measures the programming or erase time of different groups of memory cells. A programming or erasure time that deviates from a predefined range (e.g., below a certain lower threshold and / or above a certain upper threshold) may indicate that the memory cells are in a vulnerable health state and may be unreliable or fail soon.

In some embodiments, the memory controller 40 marks a given memory block as bad or suspicious if the programming or erase time of the block (or groups of memory cells in the block) is outside the predefined range . Bad blocks are typically taken to be out of service. The suspicious block is typically subject to additional evaluation before marking it as bad. The memory controller may mark the block as bad or suspicious based on the average programming or erase time for the block, the maximum or minimum programming or erase time for the block, or any other suitable measure of programming or erase time associated with the block .

In an embodiment, the memory controller may measure the number or percentage of cells that reached their intended programming level as a function of the number of iterations or the number of successfully-programmed cells as the CDF, Evaluation can be used.

In some embodiments, the memory controller marks the block as bad based on programming time criteria, even if the P & V processes in the block are successfully completed. In some embodiments, the memory controller applies P & V verification techniques only for blocks whose programming time deviates from a predefined range. Examples of P & V-post verification techniques that may be used for this purpose are given in the above-cited U.S. Patent Application No. 13 / 356,694.

In an erase operation, the unit 36 or the memory controller 40 may take various actions based on the evaluated health state of the block. For example, the R / W unit or memory controller may set the storage configuration (e.g., error correction code and / or number of bits per cell) of subsequent programming instructions in the block based on the estimated health state of the block.

7 is a flow diagram schematically illustrating a method for evaluating a health level of a group of analog memory cells, in accordance with an embodiment of the present invention. The method begins with the R / W unit 36 or the memory controller 40 applying a programming or erasing operation to the group of memory cells in an operational step 148. Unit 36 or memory controller 40 estimates the performance measure of the programming or erasing operation in a performance estimation step 152. [ The performance measure may include, for example, the duration of the programming or erasing operation. Unit 36 or controller 40 evaluates the health state of the group of memory cells based on the performance measure,

It is to be understood that the above-described embodiments are cited by way of example and the present invention is not limited to what has been particularly shown and described herein. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications that will occur to those skilled in the art upon reading the foregoing description and which are not described in the prior art . The documents incorporated by reference into this patent application are hereby incorporated by reference in their entirety for all purposes to the extent that any term is defined in such incorporated documents in a manner inconsistent with the definitions explicitly or implicitly made herein, , And only the definitions in this specification should be considered.

Claims (20)

CLAIMS 1. A method for data storage,
The method comprising: in a memory including a plurality of analog memory cells, setting parameters of an iterative process applied to a group of memory cells based on one or more data values stored in at least one of the memory cells in the memory;
Performing the iterative process on the group of memory cells according to the set parameters;
Determining a duration of the iterative process; And
Evaluating a health status of the group of memory cells in dependence upon comparing the duration of the iterative process to an upper threshold and a lower threshold of a predefined range for the duration of the iterative process
/ RTI &gt; 2. The method of claim 1, wherein performing the iterative process comprises programming the memory cells in the group according to data. 2. The method of claim 1, wherein performing the iterative process comprises erasing the group of memory cells. 2. The method of claim 1, wherein setting the parameter comprises: copying the data values from the at least one memory cell of the memory cells to an alternative storage location; and setting the parameter based on the copied data values. &Lt; / RTI &gt; 2. The method of claim 1, wherein setting the parameter comprises: incrementing an amplitude or duration between successive pulses in the iterative process, an amplitude or duration of an initial pulse in the iterative process, An applied programming word line voltage, an unselected word line voltage applied to another group of the memory cells, a voltage applied to the memory cells in the group intended to receive subsequent pulses A programming bit line voltage, and an inhibiting bit line voltage applied to the memory cells in the group intended to be inhibited from receiving the subsequent pulses. Set up one parameter type &Lt; / RTI &gt; An apparatus for data storage,
A memory including a plurality of analog memory cells; And
Storage circuit
Lt; / RTI &gt;
The storage circuit comprising:
Setting a parameter of an iterative process applied to the group of memory cells based on one or more data values stored in at least one of the memory cells in the memory;
Perform the repetitive process in the group of memory cells according to the set parameters;
Determine a duration of the iterative process;
And evaluating a health state of the group of memory cells depending on comparing the duration of the iterative process to an upper threshold and a lower threshold of a predefined range for the duration of the iterative process
Lt; / RTI &gt; 7. The apparatus of claim 6, wherein the iterative process comprises a programming process for programming the memory cells in the group according to data. 7. The apparatus of claim 6, wherein the iterative process comprises an erase process to erase the group of memory cells. 7. The apparatus of claim 6, wherein the storage circuit is configured to copy the data values from the at least one memory cell of the memory cells to an alternative storage location and to set the parameter based on the copied data values. . 7. The method of claim 6, wherein the storage circuit further comprises: an increment of amplitude or duration between successive pulses in the iterative process, an amplitude or duration of an initial pulse in the iterative process, A word line voltage, a non-selected word line voltage applied to another group of the memory cells, a programming bit line voltage applied to the memory cells in the group intended to receive subsequent pulses, And to set at least one parameter type selected from the group of types consisting of the inhibited bit line voltage applied to the memory cells in the group intended. CLAIMS 1. A method for data storage,
In a memory comprising a plurality of analog memory cells, applying to the group of memory cells an operation of setting the memory cells in the group to respective analog values;
Determining a duration of the operation applied to the group of memory cells; And
Evaluating a health state of a memory block in the memory that includes the group based on comparing the duration of the operation to an upper threshold and a lower threshold of a predefined range for the duration of the operation , Way. 12. The method of claim 11, wherein applying the operation comprises programming the memory cells in the group according to data. 12. The method of claim 11, wherein applying the operation comprises erasing the group of memory cells. 12. The method of claim 11, wherein evaluating the health state comprises marking the memory block as bad in response to a determination that the duration of the operation is less than the lower threshold. 12. The method of claim 11, wherein evaluating the health state comprises marking the memory block as bad in response to a determination that the duration of the operation exceeds the upper threshold. 12. The method of claim 11, wherein evaluating the health state comprises marking the memory block as an object of further evaluation in response to a determination that the duration of the operation is less than the lower threshold. 12. The method of claim 11, wherein evaluating the health state comprises setting a storage configuration for subsequent data storage in the memory block depending on the duration of the operation. An apparatus for data storage,
A memory including a plurality of analog memory cells; And
Storage circuit
Lt; / RTI &gt;
The storage circuit comprising:
Applying to the group of memory cells an operation of setting the memory cells in the group to respective analog values;
Determine a duration of the operation applied to the group of memory cells;
Evaluating a health state of a memory block in the memory that includes the group based on comparing the duration of the operation with an upper threshold and a lower threshold of a predefined range for the duration of the operation
Lt; / RTI &gt; 19. The apparatus of claim 18, wherein the operation comprises a programming process for programming the memory cells in the group according to data. 19. The apparatus of claim 18, wherein the operation includes an erase operation to erase the group of memory cells.

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