WO2011103379A3 - Step soft program for reversible resistivity-switching elements - Google Patents

Step soft program for reversible resistivity-switching elements Download PDF

Info

Publication number
WO2011103379A3
WO2011103379A3 PCT/US2011/025367 US2011025367W WO2011103379A3 WO 2011103379 A3 WO2011103379 A3 WO 2011103379A3 US 2011025367 W US2011025367 W US 2011025367W WO 2011103379 A3 WO2011103379 A3 WO 2011103379A3
Authority
WO
WIPO (PCT)
Prior art keywords
programming
resistance
switching elements
reversible resistivity
memory cell
Prior art date
Application number
PCT/US2011/025367
Other languages
French (fr)
Other versions
WO2011103379A2 (en
Inventor
Xiying Chen Costa
Roy Scheuerlein
Abhijit Bandyopadhyay
Brian Le
Xiao Li
Tao Du
Chandrasekhar R. Gorla
Original Assignee
Sandisk 3D Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/949,146 external-priority patent/US8848430B2/en
Application filed by Sandisk 3D Llc filed Critical Sandisk 3D Llc
Priority to KR1020127024277A priority Critical patent/KR20130001725A/en
Priority to CN2011800196806A priority patent/CN102893338A/en
Priority to JP2012554047A priority patent/JP2013520761A/en
Publication of WO2011103379A2 publication Critical patent/WO2011103379A2/en
Publication of WO2011103379A3 publication Critical patent/WO2011103379A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.
PCT/US2011/025367 2010-02-18 2011-02-18 Step soft program for reversible resistivity-switching elements WO2011103379A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020127024277A KR20130001725A (en) 2010-02-18 2011-02-18 Step soft program for reversible resistivity-switching elements
CN2011800196806A CN102893338A (en) 2010-02-18 2011-02-18 Step soft program for reversible resistivity-switching elements
JP2012554047A JP2013520761A (en) 2010-02-18 2011-02-18 Step software program for reversible resistive switching devices

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US30586810P 2010-02-18 2010-02-18
US61/305,868 2010-02-18
US30724510P 2010-02-23 2010-02-23
US61/307,245 2010-02-23
US12/949,146 2010-11-18
US12/949,146 US8848430B2 (en) 2010-02-23 2010-11-18 Step soft program for reversible resistivity-switching elements

Publications (2)

Publication Number Publication Date
WO2011103379A2 WO2011103379A2 (en) 2011-08-25
WO2011103379A3 true WO2011103379A3 (en) 2011-11-24

Family

ID=44015320

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/025367 WO2011103379A2 (en) 2010-02-18 2011-02-18 Step soft program for reversible resistivity-switching elements

Country Status (5)

Country Link
JP (1) JP2013520761A (en)
KR (1) KR20130001725A (en)
CN (1) CN102893338A (en)
TW (1) TW201135731A (en)
WO (1) WO2011103379A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5665717B2 (en) * 2011-10-11 2015-02-04 株式会社東芝 Nonvolatile semiconductor memory device
WO2013061191A1 (en) 2011-10-28 2013-05-02 International Business Machines Corporation Conditioning phase change memory cells
WO2014208049A1 (en) * 2013-06-24 2014-12-31 日本電気株式会社 Method for programming switching elements
US9224469B2 (en) * 2013-10-30 2015-12-29 Kabushiki Kaisha Toshiba Semiconductor memory device and memory system
US9224465B2 (en) * 2014-03-21 2015-12-29 Intel Corporation Cross-point memory bias scheme
KR102298604B1 (en) * 2014-11-28 2021-09-06 삼성전자주식회사 Method for controlling resistive memory device
TWI560714B (en) * 2014-12-24 2016-12-01 Winbond Electronics Corp Resistance random access memory
US9443587B1 (en) * 2015-07-21 2016-09-13 Winbond Electronics Corp. Resistive memory apparatus and writing method thereof
FR3066309B1 (en) * 2017-05-09 2020-10-16 Commissariat Energie Atomique METHOD FOR MANAGING THE ENDURANCE OF A NON-VOLATILE RE-WRITING MEMORY AND DEVICE FOR PROGRAMMING SUCH A MEMORY
US11837285B2 (en) 2021-08-22 2023-12-05 Applied Materials, Inc. Bias temperature instability correction in memory arrays

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060126380A1 (en) * 2004-11-26 2006-06-15 Renesas Technology Corp. Semiconductor device
WO2007103220A2 (en) * 2006-03-03 2007-09-13 Marvell World Trade Ltd. Calibration system for writing and reading multiple states into phase change memory
US20080123389A1 (en) * 2006-11-29 2008-05-29 Samsung Electronics Co., Ltd. Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device
WO2009011221A1 (en) * 2007-07-18 2009-01-22 Kabushiki Kaisha Toshiba A resistance change memory device and programming method thereof
US20090059652A1 (en) * 2006-04-27 2009-03-05 Masao Taguchi Resistive memory cell array with common plate
US20090109737A1 (en) * 2007-10-31 2009-04-30 Ovonyx, Inc Method of restoring variable resistance memory device
US20090147563A1 (en) * 2007-12-07 2009-06-11 Thomas Happ Integrated circuit for programming a memory element
WO2009114200A1 (en) * 2008-03-14 2009-09-17 Micron Technology, Inc. Phase change memory adaptive programming
WO2009150608A1 (en) * 2008-06-11 2009-12-17 Nxp B.V. Phase change memory device and control method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6034882A (en) 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6420215B1 (en) 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US7081377B2 (en) 2002-06-27 2006-07-25 Sandisk 3D Llc Three-dimensional memory
US6952043B2 (en) 2002-06-27 2005-10-04 Matrix Semiconductor, Inc. Electrically isolated pillars in active devices
AU2003296988A1 (en) 2002-12-19 2004-07-29 Matrix Semiconductor, Inc An improved method for making high-density nonvolatile memory
US6951780B1 (en) 2003-12-18 2005-10-04 Matrix Semiconductor, Inc. Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays
US20060250836A1 (en) 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. Rewriteable memory cell comprising a diode and a resistance-switching material
US7542370B2 (en) 2006-12-31 2009-06-02 Sandisk 3D Llc Reversible polarity decoder circuit
US8233308B2 (en) 2007-06-29 2012-07-31 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060126380A1 (en) * 2004-11-26 2006-06-15 Renesas Technology Corp. Semiconductor device
WO2007103220A2 (en) * 2006-03-03 2007-09-13 Marvell World Trade Ltd. Calibration system for writing and reading multiple states into phase change memory
US20090059652A1 (en) * 2006-04-27 2009-03-05 Masao Taguchi Resistive memory cell array with common plate
US20080123389A1 (en) * 2006-11-29 2008-05-29 Samsung Electronics Co., Ltd. Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device
WO2009011221A1 (en) * 2007-07-18 2009-01-22 Kabushiki Kaisha Toshiba A resistance change memory device and programming method thereof
US20090109737A1 (en) * 2007-10-31 2009-04-30 Ovonyx, Inc Method of restoring variable resistance memory device
US20090147563A1 (en) * 2007-12-07 2009-06-11 Thomas Happ Integrated circuit for programming a memory element
WO2009114200A1 (en) * 2008-03-14 2009-09-17 Micron Technology, Inc. Phase change memory adaptive programming
WO2009150608A1 (en) * 2008-06-11 2009-12-17 Nxp B.V. Phase change memory device and control method

Also Published As

Publication number Publication date
TW201135731A (en) 2011-10-16
CN102893338A (en) 2013-01-23
KR20130001725A (en) 2013-01-04
WO2011103379A2 (en) 2011-08-25
JP2013520761A (en) 2013-06-06

Similar Documents

Publication Publication Date Title
WO2011103379A3 (en) Step soft program for reversible resistivity-switching elements
WO2011159705A3 (en) Write and erase scheme for resistive memory device
WO2010147809A3 (en) Programming reversible resistance switching elements
WO2014153174A3 (en) Non-volatile memory program algorithm device and method
WO2011037703A3 (en) Methods of reading and using memory cells
IL287286A (en) Modified stem cell memory t cells, methods of making and methods of using same
EP3497700A4 (en) Apparatuses including multi-level memory cells and methods of operation of same
EP3345185A4 (en) Methods of operating ferroelectric memory cells, and related ferroelectric memory cells
EP2279523A4 (en) Memory cells, memory cell constructions and memory cell programming methods
WO2006107796A3 (en) Faster programming of higher level states in multi-level cell flash memory
TWI410973B (en) Memory device program window adjustment
EP3293756A4 (en) Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device
WO2014150791A3 (en) Reading a memory cell using a reference cell and a common sensing path
WO2015047814A3 (en) System and method to trim reference levels in a resistive memory
EP2243138A4 (en) Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
TW200737211A (en) An programmable non-volatile memory device of lowing program margin needed for user program operation and method for testing the same
WO2009139567A3 (en) Memory device and memory programming method
SG184371A1 (en) Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
WO2010141650A3 (en) Reference voltage optimization for flash memory
EP2728948A4 (en) Method, device, terminal, computer program and storage medium for adjusting wake-up period of terminal
WO2010033975A3 (en) Programming a memory device to increase data reliability
EP3046031A4 (en) Power storage cell system, method for updating power storage cell system, and program
EP3046199A4 (en) Power storage control device, management system, power storage control method, power storage control program, and memory medium
WO2011112354A3 (en) Sensing operations in a memory device
WO2014066462A4 (en) Apparatus and method for reforming resistive memory cells

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180019680.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11707952

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2012554047

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127024277

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 11707952

Country of ref document: EP

Kind code of ref document: A2