WO2013097308A1

WO2013097308A1 - Multi-channel asymmetrical doherty power amplifier

Info

Publication number: WO2013097308A1
Application number: PCT/CN2012/070446
Authority: WO
Inventors: 孟庆南
Original assignee: 武汉正维电子技术有限公司
Priority date: 2011-12-29
Filing date: 2012-01-17
Publication date: 2013-07-04
Also published as: CN102545788A

Abstract

A multi-channel asymmetrical Doherty power amplifier comprises a multi-channel power distribution network circuit, a carrier amplifier, at least two peak amplifiers, and an output power synthesis and impedance transformer network circuit. The inputs of the carrier amplifier and the peak amplifiers are respectively connected with the multi-channel power distribution network circuit, and the outputs of the carrier amplifier and the peak amplifiers are respectively connected with the power synthesis and impedance transformer network circuit. The power of a first peak amplifier of the at least two peak amplifiers is 0.7 - 1.3 times as large as the power of the carrier amplifier. The power of the other peak amplifier is doubled step by step, and the doubling coefficient is 1.5 - 2.5. Under the condition of outputting a GSM multi-carrier signal of peak-to-average ratio of 7 dB when using a three-channel Doherty power amplifier circuit of the power amplifier to back off by 7 dB, the efficiency reaches more than 56%. With the increase of peak amplifier series, higher peak-to-average ratio and efficiency requirements can be satisfied.

Description

A multi-channel asymmetric Doherty amplifier

Technical field

The invention belongs to the technical field of base station power amplifiers, and in particular relates to a multi-channel asymmetric Doherty amplifier structure used in a multi-carrier base station system.

Background technique

The RF power amplifier is a key component of the wireless communication base station system. Most of the energy consumption of the base station system is consumed by the RF power amplifier. With the emphasis on green environmental protection, the efficiency of the RF power amplifier is becoming higher and higher in the wireless communication field.

Doherty amplifier is the most widely used high-efficiency technology in current wireless communication systems. The principle of the traditional Doherty amplifier circuit is shown in Figure 1. It is composed of input power divider 1, carrier amplifier 3, and peak amplifier. The /impedance conversion network circuit 5 is composed, and the input power splitter 1 is connected to the load 2. At the small signal level input, the peaking amplifier 4 is in the off state, and the output of the carrier amplifier 3 is pulled to a certain load by the power combining/impedance converting network circuit 5, so that the carrier amplifier 3 operates in a high efficiency state, with the input signal being electrically With the flat increase, the peak amplifier 4 is gradually turned on by the off state, and the output load of the carrier amplifier 3 and the peak amplifier 4 varies with the output power. When the input signal level reaches the maximum value, both the carrier amplifier 3 and the peak amplifier 4 are changed. It reaches saturation and works in a high efficiency state.

At present, the traditional Doherty amplifier circuit can achieve the best efficiency of about 50% when the signal peak-to-average ratio is 5-7dB. After being applied to the RF power amplifier, the efficiency is only about 43%. It is difficult to further improve. However, with the further development of wireless broadband networks, the bandwidth requirements of signals are becoming wider and wider, and the peak-to-average ratio of signals is getting higher and higher, which requires higher efficiency of power amplifiers. Therefore, how to further effectively improve the efficiency of the RF power amplifier, especially under peak-to-average ratio conditions, is a subject worthy of in-depth study in the field of RF power amplifiers.

technical problem

The technical problem to be solved by the present invention is to provide a multi-channel asymmetric Doherty amplifier capable of improving efficiency in the case of peak-to-average ratio back-off.

Technical solution

The technical solution adopted by the present invention to solve the above technical problem is: a multi-channel asymmetric Doherty amplifier, which is characterized in that it comprises a multi-channel power distribution network circuit, a carrier amplifier, at least two peak amplifiers, and output power. a synthesis and impedance transformation network circuit; an input end of the carrier amplifier and the peak amplifier are respectively connected to the multiple power distribution network circuit, and an output end of the carrier amplifier and the peak amplifier are respectively connected to the output power synthesis and impedance conversion network circuit;

In the at least two peak amplifiers, the power of the first peak amplifier is 0.7 to 1.3 times the power of the carrier amplifier, and the power of the remaining peak amplifiers is doubled step by step, and the doubling coefficient is 1.5 to 2.5, and the definition is as described. The power of the carrier amplifier is P _c , and the power of the peak amplifier is P _p1 , P _p2 ... P _p(n-1) , P _pn , then P _p1 = (0.7 ~ 1.3) P _c , P _p2 = ( 1.5 to 2.5) P _p1 , ..., P _pn = (1.5 to 2.5) P _p(n-1) , where n is the number of peak amplifiers.

According to the above scheme, the multi-channel power distribution network circuit is composed of one or more components of a hybrid coupler, a microstrip line splitter, a strip line splitter, and a coaxial cable splitter, and is used for The input signal is distributed into at least three powers.

According to the above scheme, the power synthesis and impedance transformation network circuit is composed of one or more of a separate coupling, a microstrip line, a strip line, a coaxial cable, and a microwave capacitor, and is used for all peak amplifiers and carriers. The RF signal output by the amplifier is output after power synthesis and impedance transformation.

According to the above scheme, each of the carrier amplifier and the peak amplifier are respectively connected in series with a delay phase shifting amplitude modulation network circuit for introducing group delay, insertion phase and insertion loss, so that the amplification path is in the working frequency band. The delay, insertion phase, and gain parameter characteristics are consistent.

According to the above aspect, the delay phase shift amplitude modulation network circuit comprises an element of at least one of a microstrip line, a strip line, a surface mount component, and a coaxial cable.

According to the above scheme, the amplifier is composed of independent components, or a plurality of amplifier tubes and corresponding auxiliary components are integrated into a single chip by a semiconductor fabrication process to form a single-chip integrated circuit.

Beneficial effect

The principle of operation of the present invention is that the design of the RF amplifier circuit employs at least three asymmetric topologies. A peak-to-average ratio signal is input at the input end. When the input signal is a signal below the mean and the mean, the peak amplifier is turned off, and the output of the carrier amplifier is pulled by the power synthesis and impedance conversion network circuit to a certain load, so that the carrier amplifier works. In the high efficiency state; as the input signal level increases, the peak amplifier is gradually turned on by the off state, and the output load of the carrier amplifier and the peak amplifier varies with the output power; when the input signal level reaches the maximum peak, the carrier The amplifier's peak amplifiers are saturated and operate in a high efficiency state.

The beneficial effects of the invention are:

1. Experiments show that the efficiency of the GSM multi-carrier signal with 7dB peak-to-average ratio can be more than 56% when the three-way asymmetric Doherty amplifier circuit implemented by the asymmetric Doherty amplifier is back-off 7dB. The asymmetric Doherty amplifier The circuit is applied to the power amplifier with driver stage and output isolator. The efficiency of the power amplifier back-off 7dB can reach 48%-50%, output GSM 6-carrier intermodulation suppression can be achieved ≤-63dBc, output GSM Intermodulation suppression of 4 carriers can achieve ≤ -65dBc. The four-way asymmetric Doherty amplifier circuit implemented by the asymmetric Doherty amplifier is applied to a power amplifier with a driver stage and an output isolator. The efficiency of the power amplifier back-off 7dB can reach 50%-52%. As the number of peak amplifier stages increases, higher peak-to-average ratios and efficiency requirements can be met.

2. This design adopts multi-channel asymmetric Doherty topology structure, which has higher efficiency in the case of amplification peak-to-average ratio signal, and can achieve better linearity when combined with additional DPD (digital pre-distortion) compensation circuit; It can also achieve lower cost and reliable and stable work.

3. Introduce a simple delay phase shift amplitude modulation network circuit in front of each amplifier to cancel the difference between the group delay, insertion phase, gain and other parameters between different amplifiers, so that the amplification path is within the working frequency band. The parameters such as delay, insertion phase, and gain are consistent, so that the power synthesis of the output RF signal reaches a maximum value, so that high efficiency can be achieved, and the peak-to-average ratio can be satisfied.

DRAWINGS

Figure 1 is a block diagram of the circuit of a conventional Doherty amplifier.

2 is a block diagram of a circuit according to an embodiment of the present invention.

FIG. 3 is an example of an application of an embodiment of the present invention.

4 is a block diagram of a circuit according to still another embodiment of the present invention.

In order to make the objects, the technical solutions, the working principles and the advantages of the present invention more clearly, the present invention will be described in detail below with reference to the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

2 is a circuit block diagram of an embodiment of the present invention, which includes a multi-channel power distribution network circuit, a carrier amplifier C1, at least two peak amplifiers P1-Pn, and an output power synthesis and impedance transformation network circuit; a carrier amplifier and The input terminals of the peak amplifier are respectively connected to the multiple power distribution network circuits, and the output terminals of the carrier amplifier and the peak amplifier are respectively connected to the output power synthesis and impedance conversion network circuit.

The multi-channel power distribution network circuit performs multi-channel power distribution on the input signal; the power synthesis and impedance transformation network circuit performs power synthesis and impedance transformation on the RF signals output by all the amplifier circuits, and outputs the signals. This multi-channel asymmetric Doherty amplifier structure uses the above-mentioned ratio of peak amplifiers to meet the high signal peak-to-average ratio requirements and achieve high efficiency. Among them, a suitable peak amplifier is selected according to the doubling coefficient.

Wherein, the multi-channel power distribution network circuit may be composed of one or more components of a hybrid coupler, a microstrip line splitter, a strip line splitter, and a coaxial cable splitter, and the implementation thereof inputs The signal is distributed into at least three channels of power.

Wherein, the power synthesis and impedance transformation network circuit can be composed of one or more of separate coupling, microstrip line, strip line, coaxial cable, microwave capacitor, etc., to realize multi-channel signal Combine the road.

FIG. 3 is an example of application of an embodiment of the present invention. In this embodiment, two peak amplifiers P1 and P2 are selected.

The multi-channel power distribution network circuit includes a first coupler 101, a second coupler 103, a first absorption load 102, and a second absorption load 104. The isolation port of the first coupler 101 is grounded by connecting the first absorption load 102 through a microstrip line; the -90° port of the first coupler 101 is connected to the input end of the second coupler 103 through a microstrip line; the second coupling The isolation port of the device 103 is connected to the second absorption load 104 through the microstrip line and grounded; the -90° output port of the second coupler 103 is connected to the input end of the carrier amplifier C1 through the microstrip line; 0° of the second coupler 103 The output port is connected to the input terminal of the first peaking amplifier P1 through the microstrip line; the 0° output port of the first coupler 101 is connected to the input port of the second peaking amplifier P2 through the microstrip line. The function of the multiple power distribution network circuit is to perform one-way three-way power distribution, the first coupler 101 can select a general 3dB coupler or a 5dB coupler, and the second coupler 104 can select a common 3dB coupler or 5dB coupling. Device. The positions of the carrier amplifier, the first peak amplifier, and the second peak amplifier are not limited, and the position can be arbitrarily changed according to actual needs, as long as the power ratio is ensured.

The power synthesis and impedance transformation network circuit is coupled with the output terminals of the carrier amplifier C1 and the peak amplifiers P1 and P2, and the output signal of the amplifier circuit is internally subjected to power synthesis and impedance transformation, and the carrier amplifier and the peak amplifier operate in the operating frequency band. . The power synthesis and impedance transformation network circuit includes a first microstrip line 201, a second microstrip line 202, a third microstrip line 203, and a fourth microstrip line 204; an output end of the first peak amplifier and the first microstrip The line 201 is connected; the output of the carrier amplifier is connected to the second microstrip line 202; the output of the second peaking amplifier is connected to the third microstrip line 203. The characteristic impedance of the first microstrip line 201, the second microstrip line 202, the third microstrip line 203, and the fourth microstrip line 204 is a value between 10 Ω and 200 Ω, and the first, second, third, and fourth micro The impedance of the strip lines is not necessarily the same, and the electrical lengths are not necessarily the same.

Input a signal with a peak-to-average ratio at the input. When the input signal is a signal below the mean and the mean, the first peak amplifier and the second peak amplifier are in a closed state, and the output of the carrier amplifier is integrated in the power synthesis and impedance conversion network circuit. The four microstrip lines 204 and the second microstrip line 202 are pulled to a certain load, so that the carrier amplifier operates in a high efficiency state; as the input signal level increases, the first peak amplifier and the second peak amplifier are gradually turned on from the off state. The output load of the carrier amplifier and the peak amplifier varies with the output power; when the input signal level reaches the maximum peak, the carrier amplifier, the first peak amplifier, and the second peak amplifier are saturated and operate at high efficiency. status.

The invention can be widely applied to a multi-carrier, high-efficiency power amplifier in a wireless communication system, and FIG. 3 shows an example of a power amplifier of the present invention.

The technical requirements of a GSM power amplifier are as follows: operating frequency 925-960MHZ, output power 110W, input signal peak-to-average ratio 7dB, gain 58dB, efficiency 46%, multi-carrier intermodulation suppression less than or equal to -63dBc.

The application of the present invention to complete the development of the power amplifier includes the following steps:

Step 1, considering the above technical specifications and the existing device conditions, it is decided to adopt a four-stage amplifying circuit, wherein the final amplifying circuit adopts a three-way asymmetric Doherty amplifier structure, as shown in FIG.

Step 2: Select each amplifier model. According to the link gain and power and efficiency index requirements, the first small signal amplifier 302 selects the MMG3014NT1 of Freescale, and the second small signal amplifier 304 selects the BGA7027 of the NXP company, and the driver stage amplifier 305. Freescale's 40W power amplifier tube MRF8P9040N was selected. Carrier amplifier C1 selected Freescale's 120W power amplifier tube MRF8S9120N. The first peak amplifier P1 selected Freescale's 120W power amplifier tube MRF8S9120N, and the second peak amplifier P2 selected Freescale. The 200W power amplifier tube MRF8S9200N, so that the power of the first peak amplifier is the same as the power of the carrier amplifier, and the power of the second peak amplifier is 1.7 times that of the first peak amplifier, which satisfies the design requirements.

Step 3: Select the other components such as the temperature compensation attenuator, the interstage attenuation network, the isolator, and the power supply circuit according to the requirements of the indicator.

Step 4: Determine the impedance and electrical length of the four microstrip lines of the power synthesis/impedance conversion network according to the output matching impedance and the open circuit characteristic of the final stage carrier amplifier and the peak amplifier.

Step 5. Design a suitable multi-channel power distribution network circuit, which is implemented using two hybrid couplers.

Step 6. Complete the schematic diagram, PCB, and structural design of the entire power amplifier.

Step 7. Complete the debugging test of the entire power amplifier.

The amplifier includes: input RF connector Q1, small signal amplifier circuit, driver stage amplifier, final stage amplifier circuit, 5.6V to 5V and temperature sensor circuit, output isolator 306, output RF connector Q2, temperature reporting and amplifier Can interface D1, 30V/5.6V power supply interface D2. The final amplifier circuit is the amplifier of the present invention.

The small signal amplifying circuit comprises a temperature-compensated attenuator 301, a first small signal amplifier 302, a 衰减-type attenuator 303 and a second small-signal amplifier 304, and the output of the second small-signal amplifier 304 is connected to the driving stage amplifier 305. The input end of the driver stage amplifier 305 is connected to the input end of the first coupler 101 in the final stage amplifier circuit, the output of the final stage amplifier circuit is connected to the input end of the output isolator 306, and the output end of the output isolator 306 is connected to the output. RF connector Q2. The output power is coupled to the forward power coupling output port Q3 through the forward coupling circuit, and the reflection port of the output isolator 306 is connected to the reverse power coupling output port Q4. The 30V power input to the power amplifier is connected to the power amplifier through the 30V/5.6V power supply interface D2. The 5.6V conversion circuit converts the input 5.6V voltage into 5V voltage to supply power to the small signal amplifier, the driver stage amplifier and the last three-stage amplifier. The amplifier is enabled. The signal controls the output of 5V by controlling the 5.6V to 5V voltage converter. When it is high, there is no 5V output. When it is low or when it is floating, it outputs 5V normally. The temperature sensor reports the temperature value to the system through the IIC interface.

The GSM power amplifier designed and implemented by the invention can fully meet the technical index requirements and has a certain margin, and is suitable for mass production. The amplifier is composed of independent components, or a plurality of amplifier tubes and corresponding auxiliary components are integrated into a single chip by a semiconductor fabrication process to form a single-chip integrated circuit.

Embodiments of the invention

The present embodiment is substantially the same as the first embodiment, as shown in FIG. 4. The difference is that a delay phase shift amplitude modulation network circuit is connected in series before each carrier amplifier and peak amplifier for introducing a group delay. The insertion phase and the insertion loss are such that the group delay, the insertion phase, and the gain parameter characteristics of the amplification path in the operating band are consistent. The time delay phase shifting network circuit comprises an element of at least one of a microstrip line, a strip line, a surface mount component, and a coaxial cable.

The delay phase shifting amplitude modulation network circuit introduces parameter features such as delay, insertion phase, insertion loss or gain, and works in combination with the carrier amplifier and the peak amplifier, and cooperates with the power distribution network circuit, power synthesis and impedance change network circuit. The parameter characteristics such as delay, insertion phase, insertion loss or gain of the plurality of amplification paths in the working frequency band are consistent, so that the power synthesis of the multi-path signals reaches a maximum value. In this way, higher efficiency can be achieved, and the peak-to-average ratio can be met.

The foregoing is only an example of a preferred embodiment of the present invention. The scope of the present invention is not limited to the embodiments described herein. Any person skilled in the art can easily use the technology disclosed in the present invention. Alterations or modifications are contemplated as being within the scope of the appended claims.

Claims

A multi-channel asymmetric Doherty amplifier characterized in that it comprises a multi-channel power distribution network circuit, a carrier amplifier, at least two peak amplifiers, and an output power synthesis and impedance transformation network circuit; a carrier amplifier and a peak amplifier The input ends are respectively connected to the multiple power distribution network circuits, and the output ends of the carrier amplifier and the peak amplifier are respectively connected to the output power synthesis and impedance conversion network circuit;

2. The multi-channel asymmetric Doherty amplifier according to claim 1, wherein said multi-channel power distribution network circuit comprises a hybrid coupler, a microstrip line splitter, a strip line splitter, and a coaxial cable. One or more components of the power divider are configured to distribute the input signal into at least three powers.

3. The multiplexed asymmetric Doherty amplifier of claim 1 wherein said power combining and impedance transforming network circuit is comprised of separate coupling, microstrip lines, strip lines, coaxial cables, microwave capacitors. One or more components for performing power synthesis and impedance transformation on the RF signals output by all the peak amplifiers and the carrier amplifiers.

The multi-channel asymmetric Doherty amplifier according to any one of claims 1 to 3, characterized in that: each of the carrier amplifier and the peak amplifier are respectively connected in series with a delay phase shift amplitude modulation network circuit for The group delay, the insertion phase, and the insertion loss are introduced such that the group delay, the insertion phase, and the gain parameter characteristics of the amplification path in the operating band are consistent.

5. The multiplexed asymmetric Doherty amplifier of claim 4, wherein said delay phase shifting amplitude modulation network circuit comprises at least one of a microstrip line, a strip line, a surface mount component, and a coaxial cable. A component.

6. A multiplexed asymmetric Doherty amplifier according to any one of claims 1 to 3, wherein the amplifier is formed by a separate component or by a plurality of amplifier tubes and corresponding auxiliary components using a semiconductor fabrication process Integrated in a single chip to form a single-chip integrated circuit.