CN115037253A - Doherty power amplifier with optimized matching - Google Patents
Doherty power amplifier with optimized matching Download PDFInfo
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- CN115037253A CN115037253A CN202210688208.1A CN202210688208A CN115037253A CN 115037253 A CN115037253 A CN 115037253A CN 202210688208 A CN202210688208 A CN 202210688208A CN 115037253 A CN115037253 A CN 115037253A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention provides a Doherty power amplifier with optimized matching, which comprises an input matching circuit, a first-stage driving amplifier, an interstage matching circuit I, a second-stage driving amplifier, an interstage matching circuit II, a power divider, an interstage matching circuit III, a main circuit PA, an on-chip blocking capacitor, an 1/4 wavelength transmission line I, an auxiliary circuit PA, an output matching network, offset and a 1/4 wavelength transmission line II. The radio frequency signal flow direction is that the leftmost radio frequency signal input (RFin) is subjected to first-stage amplification through the input matching circuit, the first-stage driving amplifier (DA1) and the interstage matching circuit I, and then is subjected to second-stage amplification through the second-stage driving amplifier (DA2) and the interstage matching circuit II. The invention optimizes the output matching network of the main path PA, so that the main path PA obtains the optimal load impedance in the two states of power backspacing and saturated output, and the output power and efficiency of the PA in the two states are improved.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a Doherty power amplifier with optimized matching.
Background
The traditional Doherty power amplifier consists of a main power amplifier and an auxiliary power amplifier, signals are distributed to the main power amplifier and the auxiliary power amplifier through power dividers, power synthesis is finally carried out after amplification, and active load modulation is realized through an output matching network and a transmission line, so that higher PAE is realized during power back-off. However, since the impedances at the two ends of the conventional LC matching network are not in a proportional change relationship, the main path PA cannot obtain the corresponding load impedance values in a proportional relationship in the saturated output state and the power back-off state at the same time, so that the main path PA can obtain the optimal load impedance only in one of the two states.
Firstly, if the main path PA is matched in a power backspacing state, the saturated output power and PAE of a saturated output power point are reduced;
② if the matching is in a saturated output state, it will result in a decrease in the power backoff point PAE.
The matching optimization structure provided by the invention can ensure that the main path PA obtains the optimal load impedance in two states, and simultaneously eliminates the deterioration of the insertion loss of the matching network on the output power and the efficiency, thereby improving the output power and the efficiency of the main path PA in the two states.
In a radio frequency wireless transmission front-end system, a power amplifier is used as a core module in the radio frequency wireless transmission front-end system, and directly determines indexes such as gain, linearity and output power of the whole system, which is always a design difficulty in the radio frequency wireless communication front-end system. The development of modern communication systems is towards large bandwidth, high data transmission rate and low power consumption, and increasing the frequency band utilization rate is always the key and difficult point of communication system research. In order to have a larger channel capacity and a higher data transmission rate in a limited frequency resource, a more complex modulation mode is adopted in a present communication system, such as a multi-carrier technology and an orthogonal frequency division multiple access technology, and these modulation signals are non-constant envelope modulation signals, have a higher peak-to-average ratio, and place a very high requirement on the linearity of a radio frequency front-end power amplifier, while the radio frequency power amplifier generally works at an average power, so the power amplifier generally works in a state of 6-10dB power back-off, resulting in extremely low efficiency of the power amplifier and serious waste of energy consumption. The Doherty structure can achieve higher efficiency also at power back-off by active load modulation.
As shown in fig. 1, in a conventional Doherty structure, a signal is distributed to a main amplifier and a sub amplifier through a power splitter, and is finally power-synthesized and output through an input offset line, an input matching, a PA, an output matching, and a transmission line, and active load modulation is realized through a quarter-wavelength transmission line, so that a higher PAE is also realized during power back-off. However, the output matching at the rear of the main path is generally realized by the LC network, and the impedances at the two ends of the LC matching network are not in a proportional change relationship, so that the main path PA cannot obtain the corresponding load impedance values in a proportional relationship in a saturated output state and a power back-off state at the same time, which causes the main path PA to obtain the optimal load impedance only in one of the two states, and further deteriorates the output power and efficiency of the Doherty PA.
In the conventional Doherty structure proposed above, there are mainly two typical operating states — a power back-off state and a saturated output state.
(1) Power back-off state: since the auxiliary PA is normally biased in class C, when the input power is relatively small, the auxiliary PA is not turned on, and Zp approaches infinity, Zm3 is Zload, and Zm2 is Z0 according to the impedance transformation principle of the quarter-wavelength transmission line 2 and/Zm 3, transforming Zm2 to Zm1 through the output matching network, where Zm1 is the load impedance value seen by the transistor.
(2) A saturated output state: when the input power increases to turn on the auxiliary PA, the auxiliary outputs a current i p Will create an impedance pull on Zm3, assuming i p =i m Then Zm3 becomes 2 × Zload, that is, Zm3 becomes 2 times of the original, Zm2 becomes 1/2 according to the impedance transformation principle of the quarter-wave transmission line, the output matching network converts Zm2 at this time into Zm1, and Zm1 is a load impedance value seen by the transistor in the saturation output state.
The traditional symmetrical Doherty structure generally designs the tube-to-eye load impedance at the time of power back-off as 2 × Zopt, so that the voltage swing of a main path PA reaches the full swing in advance, the peak value PAE at the time of power back-off occurs, and the efficiency at the time of power back-off is improved; the load impedance seen by the transistor during saturated output is designed to be the optimal load impedance Zopt so as to obtain higher saturated output power and efficiency. According to the above analysis, the conventional Doherty structure can change Zm2 to original 1/2 in the saturated output state, but since the output matching network cannot proportionally transform the impedances at both ends, that is, when the impedance Zm2 at the right end of the matching network becomes original 1/2, it cannot be guaranteed that the impedance Zm1 at the left end also becomes original 1/2, that is, it cannot be guaranteed that the load impedance becomes the optimal load impedance Zopt in the saturated output state, which leads to the aforementioned problems: the saturated output power of the PA and the PAE at the saturated output power point decrease.
Similarly, if the apparent load impedance at saturation output is designed to be 1/2 × Zopt, it should theoretically be Zopt in the power back-off state for high power back-off efficiency. However, when Zm2 becomes 2 times the original value, Zm1 cannot be guaranteed to become 2 times the original value, that is, the observed load impedance becomes the optimal load impedance Zopt during power back-off, which causes the aforementioned problem of (2): the power backoff point PAE of the PA decreases.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a Doherty power amplifier with optimized matching.
The matching optimization structure provided by the invention can enable the main path PA to obtain the optimal load impedance in two states, and simultaneously eliminate the deterioration of the insertion loss of the matching network on the output power and the efficiency, thereby improving the output power and the efficiency of the main path PA in the two states.
The invention adopts the following technical scheme:
a Doherty power amplifier with optimized matching comprises an input matching circuit, a first-stage drive amplifier, an interstage matching circuit I, a second-stage drive amplifier, an interstage matching circuit II, a power divider, an interstage matching circuit III, a main circuit PA, an on-chip DC blocking capacitor, an 1/4 wavelength transmission line I, an auxiliary circuit PA, an output matching network, an Offset line and a 1/4 wavelength transmission line II;
the radio frequency signal flow direction is that the leftmost radio frequency signal input (RFin) is subjected to first-stage amplification through the input matching circuit, the first-stage driving amplifier (DA1) and the interstage matching circuit I, and then is subjected to second-stage amplification through the second-stage driving amplifier (DA2) and the interstage matching circuit II.
The third stage is a Doherty power stage, a signal is divided into two paths through a power divider and enters a main circuit and an auxiliary circuit through an interstage matching circuit II, the signal directly jumps to an 1/4 wavelength transmission line outside a chip through a gold wire after passing through a main circuit PA and an on-chip blocking capacitor, the signal passing through the auxiliary circuit PA is synthesized with the signal output by the main circuit PA after passing through an output matching network and an offset line, and finally the amplified signal is output (RFout) after passing through a last section of 1/4 wavelength transmission line II.
1/4 wavelength transmission line I, 1/4 wavelength transmission line II, and offset line are all implemented on a PCB.
VCC is connected with the on-chip element through a choke inductor, and the choke inductor is realized by adopting an off-chip discrete element. For isolating the ac signal from the power supply.
The driving stage and the Doherty main circuit are biased by adopting self-adaptive biasing circuits, and the Doherty auxiliary circuit is directly biased in through an off-chip pad.
The VCC and RF output pad are added to the ESD circuit for electrostatic protection.
The invention has the beneficial effects that:
(1) compared with the traditional Doherty structure, the output matching circuit and the 1/4 wavelength transmission line behind the Doherty main circuit are optimized into a single 1/4 wavelength transmission line, so that the main circuit PA obtains optimal load impedance in two states of power back-off and saturation output, and the output power and the efficiency of the PA in the two states are improved.
(2) The invention eliminates the deterioration of the matching network insertion loss on the output power and the efficiency, thereby improving the output power and the efficiency of the PA.
(3) The invention optimizes the output matching network of the main circuit PA, simplifies the circuit complexity and reduces the layout area.
Drawings
FIG. 1 is a block diagram of a conventional Doherty architecture;
FIG. 2 is a block diagram of the Doherty structure of the invention in comparison with a block diagram of a conventional Doherty structure;
FIG. 3 is a Doherty PA with matching optimization proposed by the present invention;
FIGS. 4(a), 4(b), and 4(c) are adaptive bias circuit diagrams;
FIG. 5 is a graph of the variation of load impedance seen by the main transistor with output power;
fig. 6 is a graph showing the change in PAE with output power of the circuit as a whole in fig. 5.
In the figure: the circuit comprises a 1-input matching circuit, a 2-first stage driving amplifier, a 3-interstage matching circuit I, a 4-second stage driving amplifier, a 5-interstage matching circuit II, a 6-power divider, a 7-interstage matching circuit III, an 8-main circuit PA, a 9-on-chip DC blocking capacitor, a 10-1/4 wavelength transmission line I, an 11-auxiliary circuit PA, a 12-output matching network, a 13-Offset line, a 14-1/4 wavelength transmission line II and a 15-choke inductor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention are described below clearly and completely, and it is obvious that the described embodiments are some, not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
PA: power amplifier
Doherty power amplifier: amplifier structure for improving power back-off efficiency proposed by doherty.w.h
PAE: efficiency of power addition
D, DA: drive amplifier
ESD: the purpose of the electrostatic protection circuit is to protect the transistor from breakdown when the transistor is subjected to static electricity.
And Die: chip and method for manufacturing the same
The matching optimization mechanism provided by the invention can enable the main path PA to obtain the optimal load impedance in two states, and simultaneously eliminate the deterioration of the insertion loss of the matching network on the output power and the efficiency, thereby improving the output power and the efficiency of the main path PA in the two states.
As shown in fig. 2, the difference between the conventional Doherty structure and the conventional Doherty structure of the present invention is that the output matching circuit and the 1/4 wavelength transmission line behind the Doherty main circuit are replaced by a single 1/4 wavelength transmission line, and at this time, Zm3 directly changes from 1/4 wavelength transmission line to Zm1, and does not need to change from Zm2 to Zm1 through the output matching network, so that the main circuit PA can obtain the optimal load impedance in both states due to the inverse ratio of the impedances at both ends of the 1/4 wavelength transmission line, and simultaneously, the deterioration of the matching network insertion loss on the output power and efficiency is eliminated, thereby improving the output power and efficiency of the main circuit PA in both states.
As shown in fig. 3, a matching optimized Doherty power amplifier comprises an input matching circuit 1, a first-stage driving amplifier 2, an interstage matching circuit i 3, a second-stage driving amplifier 4, an interstage matching circuit ii 5, a power divider 6, an interstage matching circuit iii 7, a main circuit PA8, an on-chip dc blocking capacitor 9, a 1/4 wavelength transmission line i 10, an auxiliary circuit PA11, an output matching network 12, an Offset line13, and a 1/4 wavelength transmission line ii 14;
the radio frequency signal flows in the direction of flow, the leftmost radio frequency signal input (RFin) is subjected to first-stage amplification through the input matching circuit 1, the first-stage drive amplifier (DA1)2 and the interstage matching circuit i 3, and then to second-stage amplification through the second-stage drive amplifier (DA2)4 and the interstage matching circuit ii 5.
The third stage is a Doherty power stage, a signal is divided into two paths through a power divider 6 and enters a main circuit and an auxiliary circuit through an interstage matching circuit II 5 respectively, the signal directly jumps to a 1/4 wavelength transmission line 10 outside a chip through a gold wire after passing through a main circuit PA8 and an on-chip DC blocking capacitor 9, the signal passing through the auxiliary circuit PA is synthesized with a signal output by a main circuit PA8 after passing through an output matching network and an offset 13, and finally the amplified signal is output (RFout) after passing through a last section 1/4 wavelength transmission line II 14.
The invention is composed of three-stage amplifying circuit, the first two stages are driving stages, which are traditional PA biased in AB class, the third stage adopts two asymmetric Doherty structures, the output of the main circuit transistor directly jumps to the quarter-wave transmission line outside the chip after passing through a DC blocking capacitor, 1/4-wave transmission line and offset line are realized on PCB, the choke inductor is realized by discrete elements outside the chip, the driving stage and the Doherty main circuit bias are both self-adaptive bias circuits, as shown in fig. 4(a) -4 (c), the Doherty auxiliary circuit is directly biased in through the outside of the chip, and VCC and RF output pad are both added with ESD circuit for electrostatic protection.
As shown in fig. 6, it can be seen that since the desirable transformation of the main circuit impedance from the back-off state to the saturation state is realized in fig. 5, the PA has a PAE peak value in both the power back-off state and the saturation output state, and the PAE can be kept high in both the power back-off state and the saturation output state.
Compared with the traditional Doherty structure, the output matching circuit and the 1/4 wavelength transmission line behind the Doherty main circuit are replaced by a single 1/4 wavelength transmission line, the output of the main circuit transistor directly jumps to the quarter-wavelength transmission line outside the chip after passing through a DC blocking capacitor, and the impedance at two ends of the quarter-wavelength transmission line can realize proportional change, so that the main circuit PA can obtain the optimal load impedance in two states, and the deterioration of the output power and efficiency caused by the insertion loss of the matching network is eliminated, thereby improving the output power and efficiency of the main circuit PA in the two states.
Meanwhile, the invention optimizes the output matching network of the main path PA, so that the main path PA obtains the optimal load impedance in the two states of power backoff and saturation output, and the output power and efficiency of the PA in the two states are improved.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A Doherty power amplifier with optimized matching is characterized by comprising an input matching circuit, a first-stage driving amplifier, an interstage matching circuit I, a second-stage driving amplifier, an interstage matching circuit II, a power divider, an interstage matching circuit III, a main circuit PA, an on-chip DC blocking capacitor, an 1/4 wavelength transmission line I, an auxiliary circuit PA, an output matching network, an Offset line and a 1/4 wavelength transmission line II;
the radio frequency signal is input through a radio frequency signal, is subjected to first-stage amplification through an input matching circuit, a first-stage driving amplifier and an interstage matching circuit I, and is subjected to second-stage amplification through a second-stage driving amplifier and an interstage matching circuit II;
the third stage is a Doherty power stage, a signal is divided into two paths through a power divider and enters a main circuit and an auxiliary circuit through an interstage matching circuit II, the signal directly jumps to an 1/4 wavelength transmission line outside a chip through a gold wire after passing through a main circuit PA and an on-chip DC blocking capacitor, the signal passing through the auxiliary circuit PA is synthesized with the signal output by the main circuit PA after passing through an output matching network and offset, and finally the amplified signal is output after passing through a last section of 1/4 wavelength transmission line II.
2. The matching optimized Doherty power amplifier of claim 1, wherein the 1/4 wavelength transmission line i, the 1/4 wavelength transmission line ii, the offset line are all implemented on a PCB.
3. The match optimized Doherty power amplifier of claim 1, wherein VCC is connected to on-chip components through a choke inductor, the choke inductor being implemented as off-chip discrete components.
4. The matching optimized Doherty power amplifier of claim 1, wherein the first stage driver amplifier, the second stage driver amplifier and the main PA bias all adopt adaptive bias circuits, and the auxiliary PA is directly biased in through an off-chip pad.
5. The matching optimized Doherty power amplifier of claim 1, wherein VCC and RF output pad are both added to ESD circuits for electrostatic protection.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN115567012A (en) * | 2022-11-22 | 2023-01-03 | 成都明夷电子科技有限公司 | Self-adaptive broadband Doherty power amplifier |
CN117674747A (en) * | 2024-01-31 | 2024-03-08 | 苏州悉芯射频微电子有限公司 | High-linearity high-efficiency non-pair Doherty power amplifier |
WO2024067226A1 (en) * | 2022-09-30 | 2024-04-04 | 唯捷创芯(天津)电子技术股份有限公司 | Balanced radio frequency power amplifier, radio frequency front-end module, and electronic device |
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2022
- 2022-06-17 CN CN202210688208.1A patent/CN115037253A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2024067226A1 (en) * | 2022-09-30 | 2024-04-04 | 唯捷创芯(天津)电子技术股份有限公司 | Balanced radio frequency power amplifier, radio frequency front-end module, and electronic device |
CN115567012A (en) * | 2022-11-22 | 2023-01-03 | 成都明夷电子科技有限公司 | Self-adaptive broadband Doherty power amplifier |
CN115567012B (en) * | 2022-11-22 | 2023-03-10 | 成都明夷电子科技有限公司 | Self-adaptive broadband Doherty power amplifier |
CN117674747A (en) * | 2024-01-31 | 2024-03-08 | 苏州悉芯射频微电子有限公司 | High-linearity high-efficiency non-pair Doherty power amplifier |
CN117674747B (en) * | 2024-01-31 | 2024-04-12 | 苏州悉芯射频微电子有限公司 | High-linearity high-efficiency non-pair Doherty power amplifier |
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