WO2013091448A1 - Method for preparing polysilicon gate electrode of mos transistor - Google Patents

Abstract

A method for preparing a polysilicon gate electrode of a metal-oxide semiconductor (MOS) transistor comprises the steps of: providing a semiconductor substrate for preparing an MOS transistor and compositing to form a gate dielectric layer thereon (S21); depositing an amorphous silicon layer on the gate dielectric layer (S22); performing ion implantation on the amorphous silicon layer so as to implement doping (S23); and performing annealing to activate the doping and converting the amorphous silicon layer into a polycrystalline silicon layer at the same time (S24). The leakage current of a gate dielectric layer of an MOS transistor prepared by the method is small.

Description

Method for preparing polysilicon gate electrode of MOS transistor

[Technical Field]

 The invention belongs to the technical field of preparation of MOS transistors, and relates to a method for preparing a polysilicon gate electrode of a MOS transistor.

【Background technique】

In a MOS transistor, it includes a source terminal (S), a drain terminal (D), and a gate terminal (G), wherein the gate terminal generally further includes a gate dielectric layer and a gate electrode formed over the gate dielectric layer. Generally, the gate electrode uses polysilicon of low resistivity (poly Silicon) The formation of a pattern has a small electrical resistance.

FIG. 1 is a schematic view showing the preparation of a polysilicon gate electrode in a MOS transistor of the prior art. As shown in FIG. 1, a MOS transistor is formed on the semiconductor substrate 100, and a gate dielectric layer 110 having a certain thickness is formed between the source terminal S and the drain terminal D (S and D may not be doped to form), in the gate dielectric layer. At 110, the pattern deposition is performed to form the polysilicon layer 130. In order to make the polysilicon layer 130 have a lower resistivity, an ion implantation step as shown in FIG. 1 is required to dope the polysilicon layer 130, and it is required to be fast after ion implantation. Thermal annealing The (Rapid Thermal Annealing, RTA) step is to activate doping (the temperature of the RTA is typically set at 720 ° C to 750 ° C) to form a low resistivity polysilicon gate electrode.

In the prior art method of forming a polysilicon layer, re-ion implantation doping, and then rapid thermal annealing to prepare a polysilicon gate electrode, since a crystal grain size in the polysilicon layer 130 is large, at a certain implantation energy, The distribution of the depth of the ion implantation is large, and some places cause the implanted ions to bombard the gate dielectric layer 110 due to the grain boundary factor, thereby easily causing defects in the gate dielectric layer 110, etc.; The leakage current of the large gate dielectric layer seriously affects the performance (such as power consumption) of the MOS transistor.

In view of this, it is necessary to propose a novel method for preparing a polysilicon gate electrode.

[Summary of the Invention]

One of the objects of the present invention is to reduce the leakage current of the gate dielectric layer of a MOS transistor.

To achieve the above object or other objects, the present invention provides a method for preparing a polysilicon gate electrode of a MOS transistor, comprising the following steps:

Providing a semiconductor substrate for preparing a MOS transistor and patterning thereon to form a gate dielectric layer;

Depositing an amorphous silicon layer on the gate dielectric layer;

Performing ion implantation on the amorphous silicon layer to perform doping;

Annealing activates the doping while simultaneously converting the amorphous silicon layer into a polysilicon layer.

According to a production method of an embodiment of the present invention, the depositing the amorphous silicon layer is performed at a low temperature range of 550 ° C to 570 ° C.

A production method according to an embodiment of the present invention, wherein the annealing is performed at a high temperature of 1000 ° C or higher.

Preferably, the annealing is performed using a rapid thermal annealing process.

Preferably, the time of the rapid thermal annealing is set in the range of 30 seconds to 45 seconds.

Preferably, during the ion implantation, the implanted dose ranges from 5 × 10 ¹⁵ /cm ² to 1 × 10 ¹⁶ /cm ² , the injected energy ranges from 25 keV to 35 keV, and the implanted element is phosphorus.

Preferably, the polysilicon layer has a sheet resistance ranging from 40 ohms/□ to 60 ohms/square.

Preferably, the total area of the polysilicon gate electrode of the MOS transistor is greater than 0.001 square inches.

Preferably, the preparation process is performed in a 0.35 μm or 0.5 μm CMOS process technology.

The technical effect of the present invention is that when a polysilicon gate electrode is formed by first forming an amorphous silicon layer, re-ion implantation, and re-annealing to form polycrystalline silicon, damage to the gate dielectric layer under the amorphous silicon layer is small during ion implantation. The quality of the gate dielectric layer can be ensured, and the leakage current of the gate dielectric layer of the MOS transistor can be greatly reduced.

[Description of the Drawings]

The above and other objects and advantages of the present invention will be more fully understood from the aspects of the appended claims.

1 is a schematic view showing the preparation of a polysilicon gate electrode in a prior art MOS transistor.

2 is a flow chart showing a method of fabricating a polysilicon gate electrode in accordance with an embodiment of the present invention.

3 to FIG. 6 are schematic diagrams showing changes in the structure of the gate electrode corresponding to the flow of the method shown in FIG.

 【detailed description】

The following is a description of some of the various possible embodiments of the invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention or the scope of the invention. It is to be understood that, in accordance with the technical aspects of the present invention, those skilled in the art can suggest other alternatives that are interchangeable without departing from the spirit of the invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the embodiments of the invention, and are not intended to

In the drawings, the thickness of layers and regions are exaggerated for clarity, and the shape features such as rounding due to etching are not illustrated in the drawings.

2 is a schematic flow chart of a method for preparing a polysilicon gate electrode according to an embodiment of the present invention; and FIGS. 3 to 6 are schematic diagrams showing changes in a gate electrode structure corresponding to the flow of the method shown in FIG. 2. The preparation method of this embodiment will be described in detail below with reference to FIGS. 2 to 6.

First, in step S21, a semiconductor substrate for preparing a MOS transistor is provided and patterned thereon to form a gate dielectric layer.

As shown in FIG. 3, the semiconductor substrate 200 may be a conventional silicon (Si) substrate. In an embodiment, the gate dielectric layer 210 may be a thermal oxidation-generated silicon dioxide. Of course, it may be, but not limited to, other high. k dielectric layer. Generally, in order to ensure the performance of the MOS transistor, the gate dielectric layer 210 is required to have a dense and anti-leakage performance, and therefore, it is generally prepared by a fine and excellent process. It should be understood that the specific material types, preparation methods, thicknesses and the like of the gate dielectric layer 210 are not limited by the illustrated embodiment; and, before the step of forming the gate dielectric layer, it may be performed to prepare the MOS transistor. Other process steps known to those skilled in the art are not described herein.

Further, in step S22, an amorphous silicon layer is deposited on the gate dielectric layer at a low temperature.

As shown in FIG. 4, an amorphous silicon layer 221 is formed over the gate dielectric layer 210, which is ultimately used to form a low resistivity polysilicon gate electrode. In this embodiment, the amorphous silicon layer 221 is preferably prepared in a low temperature process, which can prevent the amorphous silicon from being partially converted into polycrystalline silicon during the preparation process. Specifically, the low temperature deposition process may be LPCVD (Low Temperature Chemical Vapor Deposition) or the like, and the deposition temperature ranges from 550 ° C to 570 ° C.

Further, in step S23, ion implantation is performed on the amorphous silicon layer.

As shown in FIG. 5, in order to achieve doping, the amorphous silicon layer 221 is ion-implanted. Since the grain boundary of the amorphous silicon layer 221 is not obvious with respect to the polysilicon, the dispersion of the depth of the ion implantation is relatively small at the time of ion implantation, and therefore, high energy ions are generally not in the process of implantation. The energy bombarded to the gate dielectric layer 210, or the ions bombarded to the gate dielectric layer 210, is relatively small, thereby not causing an increase in defects in the gate dielectric layer 210.

Preferably, in this embodiment, during the ion implantation, the implanted element is phosphorus, and the ion implantation dose ranges from 5×10 ¹⁵ /cm ² to 1×10 ¹⁶ /cm ² , and the injected energy range It is 25keV~35keV (kiloelectron volts).

Further, in step S24, the high temperature annealing activates doping and simultaneously converts the amorphous silicon layer into a polysilicon layer.

As shown in FIG. 6, after the annealing process, the amorphous silicon layer 221 is crystallized into a polysilicon layer 223, and the ion-implanted impurities are activated during high-temperature annealing to form a P-type or N-type semiconductor doping, a polysilicon layer. The resistivity of 223 is greatly reduced. Under high temperature conditions, the conversion of polycrystalline silicon is facilitated, and the resistivity is also favored. The annealing temperature is preferably, but not limited to, above 1050 °C. In this embodiment, the annealing process preferably employs an RTA process with an annealing time of 30 seconds to 45 seconds. The sheet resistance of the prepared polysilicon layer 223 ranges from 40 ohms/□ to 60 ohms/□ by setting parameters such as time and temperature during the RTA process. Therefore, the polysilicon layer 223 can be used as a polysilicon gate electrode of a MOS transistor.

At this point, the preparation of the polysilicon gate electrode is substantially completed, and further processes of the MOS transistor can be further performed, which are completely achievable by those skilled in the art, and will not be further described herein.

It should be understood that, in a subsequent process, it may be further included to deposit a metal layer on the polysilicon layer 223, further form a salicide on the polysilicon layer 223 by self-alignment by an RTA process, or a polysilicon layer. 223 is all used to convert to form a metal silicide. Regardless of what low resistivity material the polysilicon layer 223 is used to form during the subsequent process, it is defined herein as a polysilicon gate electrode.

In addition, the inventors have found that since the problems described in the background art are more prominent when the area of the gate electrode is large, for example, when the total area of the polysilicon gate electrode is greater than or equal to 0.001 square inch (inch^2), ion implantation causes The leakage current problem is more prominent. Therefore, when the total area of the polysilicon gate electrode of the MOS transistor is more than 0.001 square inch, the above preparation method process can more significantly highlight the effect of reducing leakage current. Moreover, the above preparation method process is preferably carried out under the 0.35 μm, 0.5 μm CMOS process technology.

The inventors have found through testing that the formed MOS transistor is prepared by the method of the embodiment shown in FIG. 2, and the polysilicon gate electrode is formed in comparison with the conventional technology, and the leakage current of the gate dielectric layer can be reduced by about 2-4 orders of magnitude.

The above examples mainly illustrate the preparation method of the polysilicon gate electrode of the present invention. Although only a few of the embodiments of the present invention have been described, it will be understood by those skilled in the art that the invention may be practiced in many other forms without departing from the spirit and scope of the invention. Accordingly, the present invention is to be construed as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims With replacement.

Claims (9)

1. A method for preparing a polysilicon gate electrode of a MOS transistor, comprising the steps of:

   Providing a semiconductor substrate for preparing a MOS transistor and patterning thereon to form a gate dielectric layer;

   Depositing an amorphous silicon layer on the gate dielectric layer;

   Performing ion implantation on the amorphous silicon layer to perform doping;

   Annealing activates the doping while simultaneously converting the amorphous silicon layer into a polysilicon layer.
2. The method according to claim 1, wherein the depositing the amorphous silicon layer is performed at a low temperature range of 550 ° C to 570 ° C.
3. The production method according to claim 1 or 2, wherein the annealing is performed at a high temperature of 1050 ° C or higher.
4. The preparation method according to claim 1 or 2, wherein the annealing is performed by a rapid thermal annealing process.
5. The method according to claim 4, wherein the time of the rapid thermal annealing is set in the range of 30 seconds to 45 seconds.
6. The preparation method according to claim 1, wherein during the ion implantation, the implanting element is phosphorus, and the dose is in the range of 5 × 10 ¹⁵ /cm ² to 1 × 10 ¹⁶ /cm ^{2 .} The injected energy ranges from 25 keV to 35 keV.
7. The method according to claim 1, wherein the polysilicon layer has a sheet resistance ranging from 40 ohm/□ to 60 ohm/□.
8. The method according to claim 1, wherein the total area of the polysilicon gate electrode of the MOS transistor is greater than 0.001 square inch.
9. The preparation method according to claim 1, wherein the preparation method is 0.35 μm or 0.5 μm CMOS process technology is completed.

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