TWI785545B - Manufacturing Method of Transparent Thin Film Transistor with Simplified Process - Google Patents

Abstract

A method for manufacturing a transparent thin film transistor with simplified procedures, comprising: (a) sputtering a patterned gate circuit layer on a transparent substrate; (b) sputtering a gate dielectric layer on the patterned gate circuit layer to fully cover Patterning the gate circuit layer; (c) sputtering a patterned channel layer of indium gallium zinc oxide doped with carriers on the gate dielectric layer; (d) sputtering and connecting the patterned channel layer on the patterned channel layer Layer patterned source, drain line layer; (e) sputtering passivation layer on the patterned source, drain line layer to fully cover each layer of steps (a) to (d); (f) on the passivation layer Forming a plurality of through holes with the gate dielectric layer, some of the through holes expose the patterned gate wiring layer, and the remaining through holes expose one of the patterned source wiring layer and the patterned drain wiring layer; 1. A second patterned transparent circuit layer to fill the through holes.

Description

Manufacturing Method of Transparent Thin Film Transistor with Simplified Process

The invention relates to a method for manufacturing a thin film transistor, in particular to a method for manufacturing a transparent thin film transistor with simplified procedures.

Thin film transistor (thin film transistor, hereinafter referred to as TFT) is a common metal oxide semiconductor field effect transistor (MOSFET), which can be made of various semiconductor materials; among them, the most common one is silicon (Si), such as , amorphous silicon (a-Si) or polycrystalline silicon (poly-Si). When the external signal line (data line) based on the source (source) and drain (drain) of the TFT is made of a transparent semiconductor or a transparent electrode (such as ITO), the TFT can be completely transparent; therefore, the TFT is also Has been used in active display. As is well known to researchers in the field of TFT-related technologies, the manufacturing process for forming a TFT device is quite cumbersome. Due to the many steps in the manufacturing process, many photolithography processes are required to be executed in the overall manufacturing process, and therefore a large number of photomasks are required to be used.

For example, Low-Temperature Polysiliscon oxide Thin-Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 VV ^-1 published by Duk Young Jeong et al. in Adv. Eng. Mater. 2020, 22, 1901497 (hereinafter referred to as In the previous application 1), a method for manufacturing a conventional coplanar complementary metal-oxide-semiconductor (CMOS) TFT device 1 (see FIG. 4 ) is disclosed.

The manufacturing method of the CMOS TFT device 1 disclosed in the previous application 1 includes the steps described in the following paragraphs.

Refer to a step (A), a step (B) and a step (C) of the method for making the previous case 1 shown in FIG. 1 . The step (A) is to deposit a patterned low-temperature polysilicon (hereinafter referred to as LTPS) layer 1110 on a surface of a transparent glass substrate 10 by plasma-assisted chemical vapor deposition (hereinafter referred to as PECVD), as shown in FIG. A p-type channel layer 111 of a p-type TFT unit 11 of a CMOS TFT device 1 is shown. In detail, the step (A) is to sequentially deposit a 400 nm _SiO2 buffer layer and a 100 nm hydrogenated amorphous silicon (a-Si:H) layer on the surface of the transparent glass substrate 10 by PECVD, And under the condition of 450 °C, the hydrogenated amorphous silicon layer was subjected to dehydrogenation treatment and blue femtosecond laser annealing (BLA) treatment for 1 hour in sequence, so that the hydrogenated amorphous silicon layer was crystallized into an LTPS layer and then, patterning the LTPS layer through wet etching (wet etching) to obtain the patterned LTPS layer 1110 . The step (B) is to use PECVD to deposit a 100 nm SiO ₂ on the patterned LTPS layer 1110 as a high temperature gate dielectric insulation of the COMS TFT device 1 shown in FIG. 4 . ; Hereinafter referred to as HT-GI) layer 13. In this step (C), a 25 nm patterned amorphous indium gallium zinc oxide (hereinafter referred to as a-IGZO) layer 1210 is sputtered on the HT-GI layer 13 by a dc sputtering method, so that It is an n-type channel layer 121 of an n-type TFT unit 12 of a COMS TFT device 1 as shown in FIG. 4; wherein, the patterned a-IGZO layer 1210 is a patterned a-IGZO layer by dry etching get.

Referring to a step (D), a step (E) and a step (F) of the method for making the previous case 1 shown in FIG. 2 . The step (D) is to use PECVD to deposit a 100 nm SiO ₂ on the HT-GI layer 13 and the patterned a-IGZO layer 1210, as a low temperature for the COMS TFT device 1 shown in FIG. 4 Gate insulating (hereinafter referred to as LT-GI) layer 14 . This step (E) is to use the sputtering method in conjunction with the use of yellow light lithography and etching procedures between the p-type channel layer 111 and the n-type TFT unit 12 of the p-type TFT unit 11 of the TFT device 1 of COMS as shown in FIG. 4 A 150 nm patterned Mo layer 15 is respectively deposited on the LT-GI layer 14 on the n-type channel layer 121, thereby defining the n-type TFT unit on the LT-GI layer 14 on the n-type channel layer 121 An n-type gate layer 122 of 12, and the opposite sides of the n-type channel layer 121 (that is, the opposite sides of the patterned a-IGZO layer 1210) are exposed from the corresponding LT-GI layer 14 come out. The step (F) is to dope the opposite sides of the patterned a-IGZO layer 1210 with high-concentration n-type carriers using a self-alignment process, so that the exposed pattern The two sides of the Fa-IGZO layer 1210 form an n-type source contact region 1211 and an n-type drain contact region 1212 of the n-type channel layer 121 respectively.

Referring to a step (G), a step (H) and a step (I) of the method for making the previous case 1 shown in FIG. 3 . This step (G) is to cover a patterned photoresist (PR) layer ( (not shown), wet etching and dry etching are applied to the patterned Mo layer 15 exposed outside the patterned photoresist layer, and the HT-GI layer 13 and LT-GI layer 14 laminated layers respectively in sequence, thereby according to Sequentially define a p-type gate layer 112 of the p-type TFT unit 11 of the TFT device 1 of COMS as shown in FIG. opposite sides) are exposed from the corresponding lamination of the HT-GI layer 13 and the LT-GI layer 14. The step (H) is to apply a self-alignment process on the opposite sides of the patterned LTPS layer 1110 via an ion implantation system to dope p-type carriers, so that the exposed patterned LTPS layer 1110 The two sides respectively form a p-type source contact region 1111 and a p-type drain contact region 1112 of the p-type channel layer 111 . The step (I) is to sequentially stack SiO ₂ and SiNx on the p-type gate layer 112 and the n-type gate layer 122 under the condition of 300 °C to form an intermediate layer 16 covering the transparent glass substrate 10 .

Referring to a step (J), a step (K) and a step (L) of the method for making the previous case 1 shown in FIG. 4 . This step (J) is to apply a patterning process to the intermediate layer 16 by dry etching, so that the p-type source contact region 1111, the p-type drain contact region 1112, the n-type source contact region 1211 and the n-type A via hole 160 is correspondingly formed in the drain contact region 1212 and the like. The step (K) is sputtering a Mo layer 17 on the patterned intermediate layer 16 to fill the through holes 160 . The step (L) is to pattern the Mo layer 17 of the step (K), so that the p-type source contact region 1111, the p-type drain contact region 1112, the n-type source contact region 1211 and the n-type drain contact region 1111 are patterned. A p-type source 113 and a p-type drain 114 of the p-type TFT unit 11, and an n-type source 123 and an n-type drain of the n-type TFT unit 12 are respectively defined at the pole contact region 1212 and the like. electrode 124, and make the CMOS TFT device 1.

It can be known from the above paragraphs that the manufacturing method of the previous case 1 can complete the CMOS TFT device 1 in six patterning procedures (that is, only six photomasks are used). However, in the method of the previous document 1, monosilane (SiH ₄ ) is required to be used as a reactive gas source for depositing SiO ₂ or SiNx when performing various PECVD processes to deposit SiO ₂ or SiNx. SiH ₄ is a flammable gas, which is highly explosive in air, as long as 1% SiH ₄ is mixed with pure nitrogen (N ₂ ) to cause an explosion. Therefore, the aforementioned SiH ₄ undoubtedly poses a certain risk to the overall process of the method of the previous case 1. Furthermore, the manufacturing method of the previous case 1 also needs to perform an ion implantation procedure of p-type carriers and n-type carriers on the p-type channel layer 111 and the n-type channel layer 121, respectively, so as to complete the corresponding p-type channels. The source contact region 1111 and the p-type drain contact region 1112 and the n-type source contact region 1211 and the n-type drain contact region 1212 can respectively correspond to the p-type source 113 and the p-type drain 114 and the n-type The source electrode 123 and the n-type drain electrode 124 complete the ohmic contact, and the manufacturing process is very complicated.

From the above description, it can be seen that reducing the risk in the TFT device manufacturing process and simplifying the tedious steps in its manufacturing method is a subject to be improved by those skilled in the art.

Therefore, the object of the present invention is to provide a transparent thin film transistor manufacturing method which avoids the use of flammable gas and solves the problem of cumbersome manufacturing process.

Then, the preparation method of the transparent thin film transistor of the present invention process simplification, it comprises the following steps: a step (a), a step (b), a step (c), a step (d), a step (f), and a step (g).

The step (a) is sputtering a patterned gate circuit layer on a transparent substrate.

The step (b) is sputtering a gate dielectric layer on the patterned gate circuit layer to fully cover the patterned gate circuit layer.

The step (c) is sputtering a patterned channel layer made of carrier-doped InGaZnO on the gate dielectric layer.

The step (d) is sputtering a patterned source line layer and a patterned drain line layer connecting the patterned channel layer on the patterned channel layer.

The step (e) is sputtering a passivation layer on the patterned source wiring layer and the patterned drain wiring layer, so as to completely cover each layer of the step (a) to the step (d).

The step (f) is to form a plurality of through holes in the passivation layer and the gate dielectric layer, part of the through holes expose the patterned gate wiring layer, and the rest of the through holes expose the patterned One of the source wiring layer and the patterned drain wiring layer.

The step (g) is sputtering a first patterned transparent circuit layer and a second patterned transparent circuit layer which are separated from each other to fill the through holes.

The effect of the present invention is that: the gate dielectric layer, the patterned channel layer and the passivation layer are all completed by sputtering, which is safe because no flammable gas is used in the overall manufacturing process, and the patterned channel layer It is made of InGaZnO doped with carriers, so there is no need for additional ion implantation procedures, and the overall manufacturing process is simplified.

Referring to Fig. 5 and Fig. 6, an embodiment of the manufacturing method of the transparent thin film transistor of the present invention process simplification, it is made up of following steps substantially: a step (a), a step (b), a step (c) , a step (d), a step (f), and a step (g).

As shown in FIG. 5 , the step (a) is sputtering a patterned gate circuit layer 3 on a transparent substrate 2 . Specifically, the step (a) of this embodiment of the present invention is implemented using a direct current sputtering system (not shown), which is to first place the transparent substrate 2 in a reaction chamber of the sputtering system on the stage, and horizontally arrange a photomask having the pattern outline of the patterned gate circuit layer 3 on the transparent substrate 2, and then control a base pressure of the reaction chamber to ~1×10 ^-6 torr and when the stage temperature reached 300°C, argon (Ar) was introduced into the reaction chamber at a rate of 10 sccm, and a diameter in the reaction chamber was 2 inches and a working distance between the transparent substrate 2 was The 7.5 cm Mo target provides a power of 70 W, so that the working pressure in the reaction chamber of the sputtering system is maintained at 9×10 ^-3 torr, and the Mo target is bombarded after the dissociation of Ar The material lasted for 15 minutes, so that a patterned gate circuit layer 3 with a thickness of 200 nm to 220 nm was sputtered on the transparent substrate 2 . It should be noted that, although the patterned gate circuit layer 3 in step (a) of this embodiment of the present invention is implemented by using a photomask at the same time during the sputtering process; It can also be achieved without using the photomask, and after the film is formed, processes such as lithography and etching are used.

The step (b) is sputtering a gate dielectric layer 4 on the patterned gate circuit layer 3 to completely cover the patterned gate circuit layer 3 (see FIG. 5 ). The process conditions of the step (b) of this embodiment of the present invention are substantially the same as the step (a), the difference is that the step (b) is implemented by using a radio frequency magnetron (rf magnetron) sputtering system . In detail, an Al ₂ O ₃ target of the RF magnetron sputtering system in step (b) is formed by hot pressing and sintering 58 at% Al ₂ O ₃ powder and 42 at% Al powder, And the argon and oxygen flow rates in step (b) are both 5 sccm, the power provided to the Al ₂ O ₃ target is 80 W, and the sputtering time is 50 minutes, the film formation of the gate dielectric layer 4 The thickness is about 40 nm to 50 nm. It can be seen from the foregoing description that the gate dielectric layer 4 in this embodiment of the present invention is made of aluminum oxide.

Referring to FIG. 5 again, the step (c) is sputtering a patterned channel layer 5 made of carrier-doped indium gallium zinc oxide (IGZO) on the gate dielectric layer 4 . Preferably, the carrier-doped InGaZnO is doped with a plurality of p-type carriers. More preferably, the p-type carriers are selected from N ³⁺ or Sb ³⁺ . In this embodiment of the invention, the p-type carriers are N ³⁺ . In detail, the implementation conditions of the step (c) of this embodiment of the present invention are substantially the same as the step (b), the difference is that a photomask used when implementing the step (c) has the pattern The pattern outline of the channel layer 5, and a carrier-doped indium gallium zinc oxide (IGZO) target material of the radio frequency magnetron sputtering system of the step (c) is made of 21 at% In ₂ O ₃ powder, 10 at% In powder, 12 at% Ga powder, 35 at% GaN powder, 6 at% Zn powder and 7 at% Sn powder are hot pressed and sintered, and the argon gas in step (c) The oxygen flow rate is 10 sccm, the sputtering time is 15 minutes, and the film thickness of the patterned channel layer 5 is about 50 nm to 65 nm.

Referring also to FIG. 5 , the step (d) is sputtering a patterned source line layer 61 and a patterned drain line layer 62 connected to the patterned channel layer 5 on the patterned channel layer 5 . The implementation conditions of the step (d) of this embodiment of the present invention are substantially the same as the step (a), the difference is that a photomask used when implementing the step (d) has the patterned source circuit Layer 61 and the pattern profile of the patterned drain line layer 62 .

Referring to FIG. 6, the step (e) is sputtering a passivation layer 7 on the patterned source wiring layer 61 and the patterned drain wiring layer 62, so as to fully cover each layer of the step (a) to the step (d) 3, 4, 5, 61, 62. The implementation conditions of the step (e) of this embodiment of the present invention are substantially the same as the step (b), and the difference is that the sputtering time of the step (e) is 55 minutes to 60 minutes, and the passivation layer 7 The film thickness is about 200 nm. Likewise, it can be seen from the foregoing description that the passivation layer 7 in this embodiment of the present invention is also made of aluminum oxide.

The step (f) is to form a plurality of through holes 70 in the passivation layer 7 and the gate dielectric layer 4, and part of the through holes 70 in the through holes 70 expose the patterned gate circuit layer 3 (please refer to the through holes 70 on the right side of FIG. 6 . ), and the remaining through holes 70 of the through holes 70 expose one of the patterned source wiring layer 61 and the patterned drain wiring layer 62 (see the left through hole 70 in FIG. 6 ). In this embodiment of the present invention, the through-holes 70 are formed by known procedures such as lithography and etching, and the remaining through-holes 70 are exposed to the patterned drain circuit layer 62 as shown in FIG. 6 .

Referring to FIG. 6 again, the step (g) is sputtering a first patterned transparent wiring layer 81 and a second patterned transparent wiring layer 82 separated from each other to fill the through holes 70 . The implementation conditions of the step (g) of this embodiment of the present invention are substantially the same as the step (c), the difference is that a photomask used in the implementation of the step (g) has the first patterned transparent The pattern profile of the circuit layer 81 and the second patterned transparent circuit layer 82, and the indium tin oxide (ITO) target of the RF magnetron sputtering system in step (g) is made of 90 at% In ₂ O ₃ The powder and 10 at% SnO ₂ powder are hot-pressed and sintered, the sputtering time is 20 minutes to 25 minutes, and the film thickness of the patterned transparent circuit layers 81 and 82 is about 40 nm to 50 nm.

It can be seen from the detailed description of the manufacturing method of this embodiment of the present invention that this embodiment of the present invention is a transparent thin film transistor with a p-type MOS structure. Although only five photomasks are used in the overall manufacturing process, it is essentially composed of the aforementioned steps ( a), step (b), step (c), step (d), step (f), and step (g); however, it can be known that if the relevant research and development personnel in the technical field want to make For CMOSFETs with p-type MOS structure and n-type MOS structure at the same time, only one more photomask and one sputtering step (that is, sputtering a patterned channel layer made of IGZO doped with n-type carriers ), the transparent thin film transistor of CMOSFET can be completed under six masks. What needs to be explained here is that in the overall manufacturing process of the transparent thin film transistor of the present invention, the gate dielectric layer 4 , the patterned channel layer 5 and the passivation layer 7 do not need to use flammable gas (SiH ₄ ), Compared with the previous case 1 mentioned in the prior art, it is safer, and the carrier-doped indium gallium zinc oxide (IGZO) target used in sputtering the patterned channel layer 5 is based on its own GaN is already mixed, so that the patterned channel layer 5 is essentially doped with p-type carriers, and there is no need to perform an additional ion implantation procedure as in the previous case 1, and the overall manufacturing process is more simplified compared with the previous case 1.

To sum up, the manufacturing method of the transparent thin film transistor with simplified process of the present invention is not only safe because no flammable gas is used in the overall manufacturing process, but also does not require additional ion implantation procedures, so the purpose of the present invention can indeed be achieved .

But the above-mentioned ones are only embodiments of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

2 Transparent substrate 3 Patterned gate line layer 4 Gate dielectric layer 5 patterned channel layer 61 Patterned source line layer 62 patterned drain line layer 7 passivation layer 81 The first patterned transparent circuit layer 82 Second patterned transparent circuit layer

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: 1 is a schematic front view of an element manufacturing process, illustrating a step (A), a step (B) and a step (C) of a conventional coplanar complementary metal-oxide-semiconductor (COMS) TFT device manufacturing method; FIG. 2 is a schematic front view of a component manufacturing process, illustrating a step (D), a step (E) and a step (F) of the conventional TFT device manufacturing method; Fig. 3 is a schematic front view of an element manufacturing process, illustrating a step (G), a step (H) and a step (I) of the manufacturing method of the existing TFT device; FIG. 4 is a schematic front view of an element manufacturing process, illustrating a step (J), a step (K) and a step (L) of the conventional TFT device manufacturing method; Fig. 5 is a schematic front view of an element manufacturing process, illustrating a step (a), a step (b), a step (c), and a step of an embodiment of a transparent thin film transistor manufacturing method with simplified procedures of the present invention (d); and Fig. 6 is a schematic front view of a device manufacturing process, illustrating a step (e), a step (f), and a step (g) of the method of the embodiment of the present invention.

2 Transparent substrate 3 Patterned gate line layer 4 Gate dielectric layer 5 patterned channel layer 61 Patterned source line layer 62 patterned drain line layer 7 passivation layer 81 The first patterned transparent circuit layer 82 Second patterned transparent circuit layer

Claims (4)

A method for preparing a transparent thin film transistor with simplified procedures, comprising the following steps: A step (a), sputtering a patterned gate circuit layer on a transparent substrate; A step (b), sputtering a gate dielectric layer on the patterned gate wiring layer to completely cover the patterned gate wiring layer; A step (c), sputtering a patterned channel layer made of carrier-doped indium gallium zinc oxide on the gate dielectric layer; A step (d), sputtering a patterned source line layer and a patterned drain line layer connecting the patterned channel layer on the patterned channel layer; A step (e), sputtering a passivation layer on the patterned source wiring layer and the patterned drain wiring layer to fully cover each layer of the step (a) to the step (d); A step (f), forming a plurality of through holes in the passivation layer and the gate dielectric layer, part of the through holes expose the patterned gate circuit layer, and the remaining through holes in the through holes expose the patterned one of a source wiring layer and the patterned drain wiring layer; and A step (g), sputtering a first patterned transparent circuit layer and a second patterned transparent circuit layer separated from each other to fill the through holes. The process-simplified method for manufacturing a transparent thin film transistor as claimed in Claim 1, wherein the carrier-doped InGaZnO is doped with a plurality of p-type carriers. The manufacturing method of the transparent thin film transistor with simplified process as claimed in item 2, wherein the p-type carriers are selected from N ³⁺ or Sb ³⁺ . The manufacturing method of the transparent thin film transistor with simplified process as claimed in claim 1, wherein the gate dielectric layer and the passivation layer are made of aluminum oxide.

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