WO2013086902A1 - 一种改进soi结构抗辐照性能的方法 - Google Patents

一种改进soi结构抗辐照性能的方法 Download PDF

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WO2013086902A1
WO2013086902A1 PCT/CN2012/083474 CN2012083474W WO2013086902A1 WO 2013086902 A1 WO2013086902 A1 WO 2013086902A1 CN 2012083474 W CN2012083474 W CN 2012083474W WO 2013086902 A1 WO2013086902 A1 WO 2013086902A1
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oxide layer
buried oxide
irradiation
soi structure
soi
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French (fr)
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吕荫学
毕津顺
罗家俊
韩郑生
叶甜春
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a method of improving the radiation resistance of a SOI structure. Background technique
  • Silicon-on-insulator (SOI) technology is an all-media isolation technique in which a buried oxide layer is present between the top silicon film and the substrate to isolate the active device film from the substrate. .
  • a semiconductor device fabricated based on the S0I technology is referred to as an S0I device.
  • FIG. 1 is a schematic cross-sectional view showing a typical SOI CMOS structure in the prior art. Since the buried oxide layer achieves good isolation, and the active area of the SOI device is also small, has a lower leakage current than the bulk silicon, and has no latch-up effect, the SOI device has an anti-irradiation performance of the device. The superiority of other devices is unmatched.
  • the first way is to implant positive ions such as boron into the silicon substrate of the SOI structure.
  • the back gate threshold voltage is increased to improve the anti-irradiation capability of the S0 I device.
  • the second way is to introduce a deep electron trap or a recombination center into the buried oxide layer to prevent the electrons generated by the irradiation from migrating out of the buried oxide layer, maintaining the electrical neutrality of the buried oxide layer, thereby improving the anti-radiation of the buried oxide layer.
  • Photo ability The ions implanted into the buried oxide layer should be easily combined with the electrons generated by the irradiation, and are not easily separated, and are not redistributed in the buried oxide layer.
  • Deep electron traps or recombination centers are typically introduced into the buried oxide layer by ion implantation of the buried oxide layer (e.g., S i , N, A 1 , etc.).
  • the implanted S i forms an electron trap in the buried oxide layer.
  • these electron traps compensate for the trap positive charge and reduce the net positive charge in the buried oxide layer.
  • N into the buried oxide layer for a typical S0 I device, holes in the electron-hole pair generated by irradiation in the entire buried oxide layer due to the presence of a high concentration of hole traps in the buried oxide layer It is captured almost in situ, while electrons are captured by shallow-level electron traps and quickly excited by heat, and then most of the thermally excited electrons are swept out of the buried oxide layer by the electric field.
  • the buried oxide layer is positively charged macroscopically, which will affect the normal performance of the S0 I device.
  • the implantation of N ions can generate a large number of electron traps in the buried oxide layer, and after annealing, the N ions combine with S i to form a larger S i -N bond, replacing some of the weak bonds.
  • the weak bond is replaced to reduce the electron-hole pair generated by the buried oxide layer in ionizing radiation, thereby improving the radiation resistance of the SOI device; and in ionizing radiation, these electron traps can be used as a recombination center after trapping electrons.
  • the disadvantage of the first method is that the improvement of the anti-irradiation ability of the S0 I structure is limited.
  • the disadvantage of the second method is that in the process of ion implantation into the buried oxide layer of the S0 I structure, a certain implantation damage is inevitably caused to the top silicon film, although such damage can be basically performed by annealing after implantation. It is eliminated, but some defects left after annealing still have a certain impact on the performance of the S0 I device.
  • ion implantation can effectively improve the internal microstructure of the buried oxide layer while effectively improving the radiation resistance of the buried oxide layer.
  • the macroscopic performance is the change of the electrical characteristics of the buried oxide layer, and such changes may in turn be reversed. It affects the anti-irradiation improvement effect of ion implantation on the S0 I structure. For example, the injection of high-dose nitrogen ions has an effect on the structure of the buried oxide layer, causing the dense Si 2 2 atom network to relax, and the S i-0-S i bond angle becomes larger, which causes more holes. Capturing in the buried oxide layer is not conducive to the radiation resistance of the SOI device, and the nitrogen injection also reduces and increases the back gate threshold voltage of the MOSFET and the PMOS.
  • An object of the present invention is to provide a method for improving the anti-irradiation performance of a SOI structure, which uses a high-energy neutron, proton, and ray to irradiate a SOI material with a high-energy particle, thereby introducing a displacement damage into the SOI buried oxide layer to form a defect.
  • the electron-hole pair generated by the irradiation is reduced, thereby improving the anti-irradiation performance of the buried oxide layer of the S0I structure back-grid, thereby improving the anti-irradiation performance of the SOI device.
  • the present invention provides a method for improving the radiation resistance of a SOI structure, including:
  • the buried oxide layer of the SOI structure is subjected to high energy particle implantation, and an annealing operation is performed.
  • the present invention has the following advantages: by introducing high-energy neutrons, protons, rays, etc. by an accelerator to introduce displacement damage into the buried oxide layer to form defects, which are like the composite center, so that the current carrying The lifetime of the sub-member is reduced, so that a large number of electron-hole pairs generated during the irradiation process are recombined by the recombination center, so that the number of holes trapped by the hole trap in the buried oxygen layer is greatly reduced.
  • FIG. 1 is a schematic cross-sectional view showing a SOI CMOS structure in the prior art
  • FIG. 2 is a flow chart of a method for improving the anti-irradiation performance of a SOI structure in accordance with the present invention
  • FIG. 3 and FIG. 4 are schematic cross-sectional views showing various stages of improving the anti-irradiation performance of the SOI structure according to the flow shown in FIG. 2 according to an embodiment of the present invention
  • FIG. 5 is a graph showing the relationship between the back gate threshold voltage and the total radiation absorption dose after the improved and unmodified SOI wafer irradiation.
  • the S0I structure generally includes a substrate 100, a buried oxide layer 110 over the substrate, and a silicon layer 120 over the buried oxide layer 110.
  • the SOI structure includes a substrate 100, a buried oxide layer 110, and a silicon layer 120, wherein the buried oxide layer 110 is located above the substrate 100, and the silicon layer 120 Located above the buried oxide layer 110.
  • the material of the substrate 100 is single crystal silicon.
  • the thickness of the bottom 100 can be about, but not limited to, a few hundred meters, such as a thickness ranging from 0.5 mm to 1.5 mm.
  • the material of the buried oxide layer 110 is SiO 2 , and typically, the buried oxide layer 110 has a thickness ranging from 200 nm to 400 nm.
  • the material of the silicon layer 120 is single crystal silicon, and its thickness ranges from 200 legs to 300 nm.
  • the buried oxide layer 110 of the SOI structure is irradiated, and an annealing operation is performed on the SOI structure.
  • the SOI wafer is irradiated under an accelerator, high energy particles are injected into the buried oxide layer 110, and introduced into the buried oxide layer 110. Displacement damage forms defects.
  • the irradiated high energy particles may be protons, neutrons, or gamma rays.
  • the proton implantation is performed with a dose ranging from 5 X 10 16 cm - 2 to 5 X 10 17 cm - 2 , and the proton implantation energy ranges from 30 MeV to 50 MeV, and the proton is at this energy.
  • the silicon layer 120 can be stably penetrated into the buried oxide layer 110, and the subsequent annealing process does not have a large influence on it. It should be understood by those skilled in the art that the dose and energy of the proton implantation should be determined according to the specific conditions of the SOI structure. For example, when the thickness of the silicon layer 120 is different, in order to ensure that protons can be implanted into the buried oxide layer 110. The amount of proton implantation energy will also vary accordingly, so the dose and energy range of the proton implantation described above should not be construed as limiting the invention.
  • the S0I structure is annealed to eliminate implant damage caused by proton implantation on the silicon layer 120. Since the high temperature annealing introduces more defects into the buried oxide layer 110, the present invention anneals the SOI structure by means of low temperature annealing. By controlling the temperature of the annealing and the annealing time, the defects in the buried oxide layer 110 due to the annealing are reduced as much as possible. Among them, the low temperature annealing is preferably carried out in the range of 800 °C to 900 °C.
  • the damage caused by the proton implantation on the silicon layer 120 is reduced by using multiple implantations and multiple annealings, that is, after performing proton implantation on the buried oxide layer 110 and performing an annealing operation, according to Specifically, the above steps of proton implantation and annealing are repeated a plurality of times. Multiple proton implantation plus annealing can be used to make the defects formed by the implant damage in the silicon layer.
  • the distribution in 120 is more uniform, while reducing the damage of the top silicon film on the front side of the SOI device by irradiation, thereby reducing the effect of irradiation on the performance of the S0 I device.
  • the method provided by the invention has the following advantages: introducing displacement damage into the buried oxide layer by irradiating high energy particles such as protons, neutrons, etc., forming defects, like the composite center, The lifetime of the carriers is reduced, so that a large number of electron-hole pairs generated during the irradiation process are recombined by the recombination center, so that the number of holes trapped by the hole traps in the buried oxide layer is greatly reduced.
  • proton implantation introduces only displacement damage to the buried oxide layer.
  • the prior art method of introducing deep electron traps or recombination centers in the buried oxide layer by ion implantation the electron neutral characteristics of the proton implantation on the SOI device.
  • FIG. 5 is a graph showing the relationship between the threshold voltage of the back gate and the total dose of radiation absorption after the improved and unmodified S 01 wafer irradiation, and the abscissa in FIG. 5 indicates the total irradiation dose, vertical
  • the coordinates represent the back gate threshold voltage of the S0 I wafer.
  • the commercial standard Smar tCut SOI wafer is used, the thickness of which is 370 legs, and the thickness of the silicon layer is 300 legs.
  • the initial wafer for making this type of S0 I structure is the [100] crystal orientation of the p-type S i , which The resistivity is between 10 ⁇ ⁇ cm and 20 ⁇ ⁇ cm.
  • the resistivity is between 10 ⁇ ⁇ cm and 20 ⁇ ⁇ cm.
  • 5 X 10 16 cm - 2 to 5 X 10 17 cm - 2 protons were implanted into the buried oxide layer, and the implantation energy was 30 MeV to 50 MeV at 850 °.
  • Annealing was carried out at a temperature of about C.
  • the above-described proton implantation and multiple annealing operations are performed on the SOI wafer a plurality of times.
  • the modified S0I wafer and the unmodified SOI wafer were placed under a cobalt 60 irradiation source for total dose irradiation. It is apparent from Fig. 5 that the same irradiation total dose is received.
  • the back gate threshold voltage drift is much smaller than the back gate threshold voltage after the unmodified SOI wafer irradiation, that is, the method provided by the present invention is improved.
  • the post-S0 I wafer has a much higher anti-irradiation capability than the unmodified S0 I wafer.

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Abstract

一种改进SOI结构抗辐照性能的方法，该方法包括以下步骤：对所述SOI结构进行质子、中子和γ射线等高能粒子注入，并执行退火操作。本发明通过利用高能粒子注入在埋氧层中引入位移损伤，以此来提高SOI结构抗辐照的性能。

Description

一种改进 SOI结构抗辐照性能的方法
[0001] 本申请要求了 2011年 12月 14 日提交的、 申请号为
201110418276.8、 发明名称为 "一种改进 S0I结构抗辐照性能的方法" 的中 国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002] 本发明涉及半导体制造技术， 尤其涉及一种改进 S0I结构抗辐 照性能的方法。 背景技术
[0003] 绝缘体上硅（Silicon_On_Insulator, SOI)技术是一种全介质隔 离技术， 即在顶层硅膜与衬底之间存在一层埋氧层， 用于把有源器件薄 膜去与衬底进行隔离。 基于 S0I技术所制造的半导体器件被称为 S0I 器 件。 请参考图 1, 图 1为现有技术中典型的 SOI CMOS结构的剖面示意图。 由于埋氧层实现了良好的隔离， 而 S0I 器件有源区的体积也较小， 相对 于体硅具有更低的泄漏电流， 且无闩锁效应， 因此 S0I 器件在器件抗辐 照性能方面有着其它器件不可比拟的优越性。 但是， 也正是由于埋氧层 的存在， 其内部存在大量的空穴陷阱， 当 S0I 器件持续工作在电离辐照 环境中时， 电离辐照会在埋氧层中激发电子-空穴对， 电子会很快迁移出 埋氧层， 而空穴会被空穴陷阱俘获， 成为固定空间正电荷， 造成正电荷 的积累。 这些固定空间正电荷主要集中在顶层硅膜和埋氧层的界面附近。 当埋氧层中的正电荷积累到一定程度时， SOI 沟道晶体管的背栅界面将 会反型， 致使器件漏电电流增加、 电特性参数漂移， 并最终失效。 因此， 如何提高 S0I器件的抗总剂量性能成为目前研究的焦点。
[0004] 在现有技术中， 主要采用以下两种方式提高 S0I结构的抗辐照 能力， 进而提升 S0I器件的抗总剂量辐照水平。
[0005] 第一种方式是向 S0I结构的硅衬底中注入硼等正离子， 以此来 提高背栅阈值电压， 从而提高 S0 I器件的抗辐照能力。
[0006] 第二种方式是向埋氧层中引入深电子陷阱或者复合中心， 防止 辐照产生的电子迁移出埋氧层， 保持埋氧层的电中性， 从而提高埋氧层 的抗辐照能力。 注入到埋氧层内的离子应该能够很容易地和辐照产生的 电子结合， 且不容易分离， 在埋氧层中也不会重新分配。 通常采用对埋 氧层进行离子注入（例如 S i、 N、 A 1 等）的方式， 向埋氧层中引入深电子 陷阱或者复合中心。 以向埋氧层中注入 S i 为例， 注入的 S i在埋氧层中 形成电子陷阱， 当这些电子陷阱被填充后， 它们会补偿陷阱正电荷， 减 少埋氧层中的净正电荷。 以向埋氧层中注入 N为例， 对于典型的 S0 I 器 件， 由于埋氧层内存在高浓度的空穴陷阱， 整个埋氧层内辐照所产生的 电子-空穴对中的空穴几乎在原位被俘获， 而电子则被浅能级电子陷阱俘 获并很快就被热激发， 随后大多数热激发的电子被电场扫出埋氧层。 在 这种情况下， 埋氧层宏观上带正电， 会影响 S0 I器件的正常使用性能。 N 离子的注入能在埋氧层中产生大量的电子陷阱， 并且在退火后， N离子与 S i结合形成键能较大的 S i -N键， 替代了部分弱键。 弱键被替代能够减低 埋氧层在电离辐照中产生的电子一空穴对， 从而提高 S0 I 器件的抗辐照 性能； 而且在电离辐照中， 这些电子陷阱俘获电子后既可以作为复合中 心吸引辐照产生的空穴， 又可以补偿被空穴陷阱俘获的空穴， 有助于达 到宏观电中性； 此外， 这些电子陷阱还影响了埋氧层内的电场， 有利于 辐照后产生的电子一空穴对的复合。
[0007] 但是， 上述两种方式均存在一定的缺点。 其中， 第一种方式的 缺点在于对 S0 I 结构抗辐照能力的提升有限。 第二种方式的缺点在于： 在向 S0 I 结构的埋氧层中进行离子注入的过程中， 不可避免地会对顶层 硅膜造成一定的注入损伤， 尽管这样的损伤可以通过注入后的退火基本 予以消除， 但退火后遗留的部分缺陷仍会对 S0 I 器件的性能产生一定的 影响。 此外， 离子注入在有效改善埋氧层抗辐照性能的同时， 会影响到 埋氧层的内部微观结构， 宏观上的表现则为埋氧层电特性的变化， 而这 样的变化又可能反过来影响到离子注入对 S0 I 结构的抗辐照改进效果。 例如， 高剂量氮离子的注入对埋氧层的结构会产生影响， 使致密的 S i02 原子网络松弛， S i-0-S i键角变得更大， 这会使更多的空穴俘获在埋氧层 内，不利于 S0 I器件的抗辐照性能，而且，注氮还会使 M0SFET和 PM0SFET 的背栅阈值电压分别降低和提高。
[0008] 因此， 亟需提出一种可以解决上述问题的改进 S0 I结构抗辐照 性能的方法。 发明内容
[0009] 本发明的目的是提供一种改进 S0I 结构抗辐照性能的方法， 利用 高能中子、 质子和 射线等高能粒子辐照 S0I材料的方式在 S0I埋氧层中引 入位移损伤， 形成缺陷如同复合中心， 减小辐照产生的电子一空穴对， 以此 来提高 S0I结构背栅隐埋氧化层的抗辐照性能， 进而提升 S0I器件的抗辐照 性能。
[0010] 本发明提供了一种改进 S0I结构抗辐照性能的方法， 包括：
[0011] 对所述 S0I结构的埋氧层进行高能粒子注入， 并执行退火操作。
[0012] 与现有技术相比， 本发明具有以下优点： 通过加速器辐照高能中 子、 质子、 射线等方式在埋氧层中引入位移损伤形成缺陷， 这些缺陷如同 复合中心一样， 使载流子的寿命减小， 这样在辐照过程中所产生的大量电 子-空穴对会被复合中心所复合， 使得埋氧层中空穴陷阱所俘获的空穴数量 大大减小。 此外， 辐照质子、 中子和;射线等对于埋氧层仅仅是引入了位移 损伤， 与现有技术中通过离子注入在埋氧层中引入深电子陷阱或复合中心 的方式相比， 对 S0I器件的电中性特性并不会产生影响， 所以不会造成 S0I 器件背栅阈值电压漂移等改变埋氧层电学特性的影响， 因此可以有效地提 高 S0I 结构背栅隐埋氧化层的抗辐照性能， 进而提升 S0I 器件的抗辐照性
附图说明
[0013] 通过阅读参照以下附图所作的对非限制性实施例所作的详细描 述， 本发明的其它特征、 目的和优点将会变得更明显：
[0014] 图 1为现有技术中 SOI CMOS结构的剖面示意图；
[0015] 图 2为根据本发明的改进 S0I结构抗辐照性能的方法流程图；
[0016] 图 3和图 4为根据本发明一个具体实施例按照图 2所示流程改 进 S0I结构抗辐照性能的各个阶段的剖面示意图； 以及
[0017] 图 5为改进与未改进 S0I晶圓辐照后背栅阈值电压与辐照吸收 总剂量之间的关系曲线图。
具体实施方式
[0018] 下面详细描述本发明的实施例， 所述实施例的示例在附图中示 出。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0019] 下文的公开提供了许多不同的实施例或例子用来实现本发明的 不同结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进 行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒 化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了各种特定的工艺和材料的例子， 但是本领域技 术人员可以意识到其他工艺的可应用于性和 /或其他材料的使用。 应当 注意， 在附图中所图示的部件不一定按比例绘制。 本发明省略了对公知 组件和处理技术及工艺的描述以避免不必要地限制本发明。
[0020] 下面， 请结合图 3和图 4通过本发明的一个实施例对图 2中改 进 S0I结构抗辐照性能的方法进行具体地描述。
[0021] S0I结构一般包括衬底 100、位于所述衬底之上的埋氧层 110以 及位于所述埋氧层 110之上的硅层 120。
[0022] 具体地， 如图 3所示， S0I结构包括衬底 100、 埋氧层 110以及 硅层 120, 其中， 所述埋氧层 110位于所述衬底 100之上， 所述硅层 120 位于所述埋氧层 110之上。 [0023] 在本实施例中， 所述衬底 100的材料为单晶硅。 典型地， 所述 ^"底 100 的厚度可以约为但不限于几百 米， 例如从 0.5mm-l.5mm的厚 度范围。
[0024] 所述埋氧层 110的材料为 Si02, 典型地， 所述埋氧层 110的厚 度范围为 200nm-400nm。
[0025] 所述硅层 120的材料为单晶硅， 其厚度范围为 200腿- 300nm。
[0026] 如图 2中步骤 S101所示， 根据本发明的一个实施例， 对 S0I结 构的埋氧层 110进行辐照， 并对所述 S0I结构执行退火操作。
[0027] 具体地， 首先， 如图 4所示， 将所述 S0I晶圓放在加速器下对 其进行辐照， 将高能粒子注入所述埋氧层 110, 在所述埋氧层 110中引入 位移损伤形成缺陷。 其中， 所述辐照的高能粒子可以是质子、 中子， 还 可以是 γ射线。 在本实施例中， 所述采用质子注入， 注入的剂量范围为 5 X 1016cm— 2至 5 X 1017cm— 2, 所述质子注入的能量范围为 30MeV至 50MeV, 在 这个能量下质子能够稳定地穿透硅层 120注入到埋氧层 110 中， 并且后 续的退火过程不会对其产生较大的影响。 本领域的技术人员应该可以理 解， 所述质子注入的剂量和能量的大小应该根据 S0I 结构的具体情况而 决定， 例如， 当硅层 120 的厚度不同时， 为了保证质子可以注入到埋氧 层 110 中， 质子注入能量的大小也会相应有所不同， 所以上述所述质子 注入的剂量和能量范围不应作为对本发明的限制。
[0028] 接着， 对所述 S0I结构进行退火操作， 以消除质子注入对硅层 120所造成的注入损伤。由于高温退火会在埋氧层 110中引入较多的缺陷， 所以本发明采用低温退火的方式对所述 S0I 结构进行退火。 通过控制退 火的温度以及退火的时间使埋氧层 110 中由于退火所产生的缺陷尽可能 地减小。 其中， 所述低温退火优选在 800°C至 900°C的范围内进行。
[0029] 优选地， 采用多次注入以及多次退火的方式减小由于质子注入 对硅层 120所造成的损伤， 即， 在对所述埋氧层 110进行质子注入并执 行退火操作后， 根据具体情况， 多次重复上述质子注入以及退火的步骤。 采用多次质子注入加退火的方式， 可以使注入损伤所形成的缺陷在硅层 120中的分布更加均匀， 同时降低辐照对 S0I器件正面顶层硅膜的损伤从 而减小辐照对 S0 I器件性能的影响。
[0030] 与现有技术相比， 本发明所提供的方法具有以下优点： 通过辐 照高能粒子例如质子、 中子等方式在埋氧层中引入位移损伤形成缺陷， 这些缺陷如同复合中心一样， 使载流子的寿命减小， 这样在辐照过程中 所产生的大量电子-空穴对会被复合中心所复合， 使得埋氧层中空穴陷阱 所俘获的空穴数量大大减小。 此外， 质子注入对于埋氧层仅仅是引入了 位移损伤， 与现有技术中通过离子注入在埋氧层中引入深电子陷阱或复 合中心的方式相比， 质子注入对 S0I器件的电中性特性并不会产生影响， 所以不会造成 S0I器件背栅阈值电压漂移等改变埋氧层电学特性的影响， 因此可以有效地提高 S0I 结构的抗辐照性能， 进而提升 S0I 器件的抗辐 照性能。
[0031] 下面， 基于实验结果， 对使用本发明所提供的方法进行改进后 的 S0 I晶圓与未改进的 S0I晶圓的抗辐照能力进行比较。 请参考图 5 , 图 5为改进后与未改进 S 01晶圓辐照后背栅阈值电压与辐照吸收总剂量之间 的关系曲线图， 图 5 中的横坐标表示辐照总剂量， 纵坐标表示 S0 I 晶圓 的背栅阈值电压。 实验中采用商业化标准的 Smar tCut SOI晶圓， 其厚度 为 370腿， 硅层的厚度为 300腿， 制作该类 S0 I 结构的初始晶圓为 [100] 晶向的 ρ型 S i , 其电阻率在 10 Ω · cm至 20 Ω · cm之间。 其中， 在对 S0I 晶圓改进的过程中，向其埋氧层中注入了 5 X 1016cm— 2至 5 X 1017cm— 2的质子， 注入能量为 30 MeV至 50MeV , 并在 850 °C左右温度下进行了退火。 此外， 为了减小质子注入对硅层所造成的损伤， 对该 S0 I 晶圓执行了多次上述 质子注入和多次退火的操作。 在辐照实验中， 将改进后的 S0I 晶圓和未 改进的 S0I晶圓放在钴 60辐照源下进行总剂量辐照， 从图 5中可以明显 看出， 在接受相同辐照总剂量的情况下， 改进后的 S0I 晶圓辐照后的背 栅阈值电压的漂移量远远小于未改进的 S0I晶圓辐照后的背栅阈值电压， 也就是说， 采用本发明提供的方法改进后的 S0 I 晶圓的抗辐照能力远远 高于未改进的 S0 I晶圓。 [ 0032] 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱 离本发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些 实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术 人员应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可 以变化。
[ 0033] 此外， 本发明的应用范围不局限于说明书中描述的特定实施例 的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开 内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者 以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体 相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利 要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含 在其保护范围内。

Claims

权 利 要 求
1. 一种改进 S0I结构抗辐照性能的方法， 该方法包括以下步骤： a) 对所述 SOI结构进行高能粒子注入， 并执行退火操作。
2. 根据权利要求 1 所述的方法， 其中， 所述高能粒子注入在所述 S0I 结构的埋氧层（110) 中引入位移损伤。
3. 根据权利要求 1或 2所述的方法， 其中， 所述对所述埋氧层（110)进 行高能粒子注入的步骤包括：
利用对所述 S0I 结构进行辐照的方式， 对所述埋氧层（110)进行高能粒 子辐照注入。
4. 根据权利要求 3所述的方法， 其中：
所述辐照的高能粒子是质子、 中子或 γ射线中的一种或其组合。
5. 根据权利要求 3所述的方法， 其中：
所述高能粒子注入的剂量范围为 5 X 1016cm— 2至 5 X 1017cm-2 , 所述高能粒 子注入的能量范围为 30MeV至 50MeV。
6. 根据权利要求 3所述的方法， 其中， 所述退火操作在 800 °C至 900 °C 的范围内进行。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111863608A (zh) * 2020-07-28 2020-10-30 哈尔滨工业大学 一种抗单粒子烧毁的大功率晶体管及其制作方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522362B (zh) 2011-12-14 2015-06-24 中国科学院微电子研究所 一种改进soi结构抗辐照性能的方法
CN104217925B (zh) * 2013-06-05 2017-07-18 中国科学院微电子研究所 一种降低绝缘体上硅材料埋氧层中正电荷密度的方法
CN105679658B (zh) * 2016-01-29 2018-06-26 西北核技术研究所 一种cmos器件抗单粒子闭锁的加固方法
CN108054089A (zh) * 2017-12-20 2018-05-18 中国工程物理研究院电子工程研究所 一种基于位错减少辐照损伤的方法
CN108346565B (zh) * 2018-02-09 2020-06-09 哈尔滨工业大学 一种基于电离辐照诱导位移缺陷退火的方法
CN111693838B (zh) * 2020-05-14 2022-08-02 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） 纳米场效应晶体管的总剂量辐射试验方法及装置
CN111739838B (zh) * 2020-06-23 2023-10-31 中国科学院上海微系统与信息技术研究所 一种抗辐射的soi材料的制备方法
CN112230448A (zh) * 2020-10-15 2021-01-15 中国科学院上海微系统与信息技术研究所 微环电光调制器及其制备方法
CN113120857B (zh) * 2021-04-14 2024-07-02 中国科学院上海微系统与信息技术研究所 一种光学微纳结构的制备方法
CN114597251B (zh) * 2022-03-03 2023-05-26 电子科技大学 一种抗总剂量辐射加固的屏蔽栅vdmos

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222436A1 (en) * 2003-05-09 2004-11-11 International Business Machines Corporation Bicmos technology on soi substrates
KR20100096480A (ko) * 2009-02-24 2010-09-02 주식회사 나노아이에프 게르마늄 온 인슐레이터 구조의 제조 방법과 이 방법에 의해 제조된 게르마늄 온 인슐레이터 구조 및 이를 이용한 트랜지스터
CN102437087A (zh) * 2011-12-14 2012-05-02 中国科学院微电子研究所 抗辐照加固的soi结构及其制作方法
CN102522362A (zh) * 2011-12-14 2012-06-27 中国科学院微电子研究所 一种改进soi结构抗辐照性能的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289552A (ja) * 2001-03-28 2002-10-04 Nippon Steel Corp Ｓｉｍｏｘ基板の製造方法およびｓｉｍｏｘ基板
US20100112780A1 (en) * 2005-07-12 2010-05-06 The Arizona Board Of Regents, A Body Corporate Acting On Behalf Of Arizona State University Microwave-Induced Ion Cleaving and Patternless Transfer of Semiconductor Films
WO2011074599A1 (ja) * 2009-12-16 2011-06-23 独立行政法人産業技術総合研究所 モザイク状ダイヤモンドの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222436A1 (en) * 2003-05-09 2004-11-11 International Business Machines Corporation Bicmos technology on soi substrates
KR20100096480A (ko) * 2009-02-24 2010-09-02 주식회사 나노아이에프 게르마늄 온 인슐레이터 구조의 제조 방법과 이 방법에 의해 제조된 게르마늄 온 인슐레이터 구조 및 이를 이용한 트랜지스터
CN102437087A (zh) * 2011-12-14 2012-05-02 中国科学院微电子研究所 抗辐照加固的soi结构及其制作方法
CN102522362A (zh) * 2011-12-14 2012-06-27 中国科学院微电子研究所 一种改进soi结构抗辐照性能的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111863608A (zh) * 2020-07-28 2020-10-30 哈尔滨工业大学 一种抗单粒子烧毁的大功率晶体管及其制作方法
CN111863608B (zh) * 2020-07-28 2023-05-19 哈尔滨工业大学 一种抗单粒子烧毁的大功率晶体管及其制作方法

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