WO2013065212A1 - Radiation detector - Google Patents

Radiation detector Download PDF

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Publication number
WO2013065212A1
WO2013065212A1 PCT/JP2012/004366 JP2012004366W WO2013065212A1 WO 2013065212 A1 WO2013065212 A1 WO 2013065212A1 JP 2012004366 W JP2012004366 W JP 2012004366W WO 2013065212 A1 WO2013065212 A1 WO 2013065212A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
electrode
layer
ground layer
semiconductor layer
Prior art date
Application number
PCT/JP2012/004366
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French (fr)
Japanese (ja)
Inventor
貴弘 土岐
敏 徳田
弘之 岸原
正知 貝野
聖菜 吉松
吉牟田　利典
晃一 田邊
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株式会社島津製作所
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Publication of WO2013065212A1 publication Critical patent/WO2013065212A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/24—Measuring radiation intensity with semiconductor detectors
    • G01T1/247—Detector read-out circuitry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H01L27/14659—Direct radiation imagers structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H01L27/14661—X-ray, gamma-ray or corpuscular radiation imagers of the hybrid type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/32—Transforming X-rays

Definitions

  • the present invention relates to a radiation detector for detecting radiation (X-rays, ⁇ -rays, etc.) used for medical (diagnosis) and industrial purposes such as foreign body inspection.
  • FPD flat panel X-ray detector
  • the FPD includes an indirect conversion method and a direct conversion method (see, for example, Patent Documents 1 and 2).
  • An indirect conversion FPD is a phosphor layer such as CsI (cesium iodide) that converts X-rays to light, and a photoelectric conversion element (matrix shape) that is arranged immediately below the phosphor layer to convert light into charges.
  • Photodiode a capacitor for accumulating the charge converted by the photoelectric conversion element
  • TFT thin film transistor
  • Each pixel is composed of one photoelectric conversion element, a capacitor, and a TFT.
  • the FPD 101 of the direct conversion method is arranged in a matrix form immediately below the conversion layer 102 that is sensitive to X-rays and directly converts charges according to the incident dose, and is converted by the conversion layer 102.
  • the capacitor 111 for storing the generated charge and the TFT 112 as a switching element for reading the charge stored in the capacitor 111 are provided.
  • One pixel is composed of one capacitor 111 and one TFT 112, respectively.
  • a high-resistance semiconductor of a-Se (amorphous selenium), CdTe (cadmium telluride) or CdZnTe (cadmium zinc telluride) is used for the conversion layer 102.
  • the pixel electrode 125 is electrically connected to the capacitor electrode 127.
  • the capacitor 111 includes a capacitive electrode 127 and a ground layer 131.
  • a bias voltage is applied to the common electrode 106, and the charges converted by the X-ray incidence are sequentially transferred from the conversion layer 102 to the hole injection blocking layer 108, the counter electrode 109, the bump electrode 141, the pixel electrode 125, and the through hole.
  • 133 is stored in the capacitor 111.
  • the electric charge accumulated in the capacitor 111 is read from the capacitor 111 by the operation of the TFT 112.
  • such a conventional example has the following problems. That is, when the conversion layer 102 is made of CdTe or CdZnTe, the conversion layer 102 has high sensitivity. Thereby, for example, more charges are converted by X-ray incidence than the conversion layer 102 such as a-Se. In addition to the charges converted by the incidence of X-rays, more charges are generated due to leakage current when X-rays are not irradiated than the conversion layer 102 such as a-Se. That is, more charge is converted into the capacitor 111 due to X-ray incidence than the conversion layer 102 such as a-Se. For this reason, the capacity of the conventional capacitor 111 overflows during long-time shooting.
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a radiation detector capable of accumulating a large amount of charge even when a highly sensitive conversion layer is employed.
  • the film thickness must be uniform. Further, the area S is affected by the pixel pitch, and its size is limited.
  • the radiation detector according to the present invention includes a semiconductor layer of a polycrystalline film of CdTe or CdZnTe that generates charges in response to incident radiation, and the semiconductor individually provided in a plurality of pixels configured in a matrix.
  • the semiconductor layer of the polycrystalline film of CdTe or CdZnTe generates charges in response to incident radiation, and the capacitor stores the charges generated in the semiconductor layer.
  • the switching element reads the electric charge accumulated in the capacitor.
  • the capacitor and the switching element are individually provided for a plurality of pixels configured in a matrix.
  • condenser is comprised by the capacity
  • a semiconductor layer of a polycrystalline film of CdTe or CdZnTe generates a lot of charges upon incidence of radiation and generates a lot of charges due to a leak current. Those charges can be stored in the capacitor.
  • the reset noise increases as the capacitance of the capacitor increases.
  • the influence on the S / N ratio can be suppressed by reducing the reset noise relative to the X-ray quantum noise that is relatively larger than the reset noise.
  • the capacitor includes a plurality of capacitor electrodes electrically connected to each other, a ground layer provided between the capacitor electrodes, and the capacitor electrode. And an inter-electrode insulating film provided between the first electrode and the ground layer.
  • the ground layer is provided by laminating a plurality of ground layers, and the plurality of ground layers are electrically connected to each other between the plurality of ground layers.
  • any one of the plurality of capacitive electrodes is provided.
  • it can be set as the laminated structure by which the some capacitive electrode and the some ground layer were arrange
  • the interelectrode insulating film of the capacitor is preferably composed of any one of Ta 2 O 5 , Al 2 O 3 , (Ba, Sr) TiO 2 , and SrTiO 3. .
  • the capacitance of the capacitor can be increased.
  • the semiconductor layer of the polycrystalline film of CdTe or CdZnTe generates charges in response to incident radiation, and the capacitor stores the charges generated in the semiconductor layer.
  • the switching element reads the electric charge accumulated in the capacitor.
  • the capacitor and the switching element are individually provided for a plurality of pixels configured in a matrix.
  • condenser is comprised by the capacity
  • a semiconductor layer of a polycrystalline film of CdTe or CdZnTe generates a lot of charges upon incidence of radiation and generates a lot of charges due to a leak current. Those charges can be stored in the capacitor.
  • the reset noise increases as the capacitance of the capacitor increases.
  • the influence on the S / N ratio can be suppressed by reducing the reset noise relative to the X-ray quantum noise that is relatively larger than the reset noise.
  • FIG. 1 is a longitudinal sectional view illustrating a configuration of a flat panel X-ray detector (FPD) according to Embodiment 1.
  • FIG. It is a longitudinal cross-sectional view which shows the structure of the opposing board
  • (A) to (c) are partial plan views showing an example of a first ground layer, a capacitor electrode, and first and second through holes as viewed from the direction A in FIG. It is the figure which compared the sensitivity and the amount of leak current of the flat panel type X-ray detector (FPD) using CdZnTe and a-Se for a semiconductor layer. It is a block diagram which shows the structure of a flat panel type X-ray detector (FPD).
  • FIG. It is a longitudinal cross-sectional view which shows the structure of the flat panel type
  • FIG. It is a longitudinal cross-sectional view which shows the structure of the flat panel type
  • FIG. 1 is a longitudinal sectional view showing the configuration of a flat panel X-ray detector (FPD) according to the first embodiment.
  • FIG. 2 is a longitudinal sectional view showing the configuration of the counter substrate of the flat panel X-ray detector (FPD).
  • FIGS. 3A to 3C are partial plan views showing examples of the first ground layer, the capacitor electrode, and the first and second through holes as viewed from the direction A in FIG. FIG.
  • FIG. 4 is a diagram comparing the sensitivity and the amount of leakage current of a flat panel X-ray detector (FPD) using CdZnTe and a-Se for the semiconductor layer.
  • FIG. 5 is a block diagram showing a configuration of a flat panel X-ray detector (FPD).
  • a flat panel X-ray detector (FPD) 1 includes a counter substrate (also referred to as a detection substrate) 3 having a semiconductor layer 2 that generates charges (electron-hole pair carriers) in response to incident X-rays, and a generation And an active matrix substrate 4 for reading out the accumulated charges.
  • the counter substrate 3 is formed in order from the X-ray incident direction (symbol x in FIGS. 1 and 2), and a support substrate 5 that is the basis of the semiconductor layer 2 and a bias voltage application formed on the lower surface of the support substrate 5.
  • Common electrode 6 electron injection blocking layer 7 for blocking charge (electron) injection into semiconductor layer 2, semiconductor layer 2, and hole injection blocking for blocking charge (hole) injection into semiconductor layer 2
  • the layer 8 and the counter electrode 9 for collecting charges are stacked.
  • the support substrate 5 preferably has a small X-ray absorption coefficient.
  • graphite, ceramic (Al 2 O 3 , AlN), silicon, or the like is used.
  • the common electrode 6 is made of a conductive material such as ITO (indium tin oxide), Au (gold), or Pt (platinum), and is formed on the support substrate 5 by vapor deposition or sputtering. When a conductive material such as graphite is used for the support substrate 5, the common electrode 6 may be omitted.
  • the electron injection blocking layer 7 is made of a p-type semiconductor such as ZnTe, Sb 2 S 3 , or Sb 2 Te 3 , and is formed on the common electrode 6 by a sublimation method, vapor deposition or sputtering, chemical deposition method, or electrodeposition method. It is formed.
  • the semiconductor layer 2 is made of a compound semiconductor such as CdTe or CdZnTe, and CdTe or CdZnTe is composed of a polycrystalline film.
  • the semiconductor layer 2 of CdTe or CdZnTe is formed by proximity sublimation. That is, in the semiconductor layer 2 of CdTe or CdZnTe, the support substrate 5 on which the common electrode 6 and the electron injection blocking layer 7 are formed is disposed close to the sintered body or the mixed sintered body and heated under reduced pressure. Formed by sublimation.
  • the sintered body or the mixed sintered body (also referred to as a source) is, for example, a sintered body of a CdTe powder material, a mixed sintered body of a CdTe powder material and a ZnTe powder material, or a CdZnTe powder material.
  • the sintered body is used.
  • the semiconductor layer 2 is formed to 600 to 700 ⁇ m by the proximity sublimation method and polished to a thickness of about 500 ⁇ m.
  • the hole injection blocking layer 8 is made of an n-type semiconductor such as CdS (cadmium sulfide), ZnS (zinc sulfide), ZnO (zinc oxide), or Sb 2 S 3 (antimony sulfide). It is formed by sputtering, chemical precipitation, or electrodeposition. The hole injection blocking layer 8 is formed separately for each pixel by patterning as necessary. However, if the hole injection blocking layer 8 has a high resistance and there is no harmful effect such as a decrease in spatial resolution due to adjacent pixel leakage, it may not be formed separately.
  • CdS cadmium sulfide
  • ZnS zinc sulfide
  • ZnO zinc oxide
  • Sb 2 S 3 antimony sulfide
  • the arrangement of the electron injection blocking layer 7 and the hole injection blocking layer 8 may be exchanged, and either the electron injection blocking layer 7 or the hole injection blocking layer 8 or It is good also as a structure which does not form both.
  • the counter electrode 9 is made of a conductive material such as ITO, Au, or Pt, like the common electrode 6, and is formed on the hole injection blocking layer 8 by vapor deposition or sputtering. In addition, it is good also as a structure which does not form the counter electrode 9 as needed.
  • the active matrix substrate 4 includes a capacitor 11 that stores the generated charge, a thin film transistor (TFT) 12 that reads the charge stored in the capacitor 11, and the like.
  • the capacitor 11, the TFT 12, etc. are formed on the insulating substrate 13.
  • the TFT 12 includes a first capacitor electrode 27 and an insulating film 15, which will be described later, a data line 17, a gate channel 19, and a gate line 21.
  • the insulating film 23 is formed as a protective film.
  • the TFT 12 corresponds to the switching element of the present invention.
  • the capacitor 11 includes a pixel electrode 25, a first capacitor electrode 27, a first ground layer 29, and a second ground layer 31 that are stacked in the thickness direction 24.
  • the pixel electrode 25 and the first capacitor electrode 27 are electrically connected to each other through the first through hole 33.
  • the first ground layer 29 and the second ground layer 31 are electrically connected to each other through the second through hole 35.
  • the first ground layer 29 and the second ground layer 31 are grounded or a predetermined voltage set in advance is applied.
  • an insulating film 37 is provided between the pixel electrode 25 and the first ground layer 29.
  • an insulating film 39 is provided between the first ground layer 29 and the first capacitor electrode 27, and an insulating film 15 is provided between the first capacitor electrode 27 and the second ground layer 31. ing.
  • FIG. 3 is a partial plan view as seen from the direction A in FIG. 1 (a) to (c).
  • the first through hole 33 is formed at a position where it does not overlap (does not connect) with the first ground layer 29, and the second through hole 35 also does not overlap with the first capacitor electrode 27. Is formed.
  • the first through hole 33 is inside the first ground layer 29 and is not connected to the first ground layer 29 as shown in FIG. 3B. It may be provided.
  • the first through hole 33 and the second through hole 35 may be provided at positions facing each other in plan view.
  • the capacitor 11 includes a pixel electrode 25, a first capacitor electrode 27, a first ground layer 29, a second ground layer 31, a first through hole 33, a second through hole 35, and insulating films 15, 37, and 39. Yes.
  • the pixel electrode 25 and the first capacitor electrode 27 correspond to the capacitor electrode of the present invention, and the first ground layer 29 and the second ground layer 31 correspond to the ground layer of the present invention.
  • the insulating films 15, 37 and 39 correspond to the interelectrode insulating film of the present invention.
  • the gate channel 19 is composed of, for example, an n + layer formed by depositing a-Si (amorphous silicon) or p-Si (polysilicon) by vapor deposition and diffusing impurities.
  • the data line 17, the gate line 21, the pixel electrode 25, the first capacitor electrode 27, the first ground layer 29, the second ground layer 31, the first through hole 33, and the second through hole 35 are Ta (tantalum), Al (Aluminum), Mo (molybdenum), Ti (titanium), etc. are comprised. These metal films are formed by vapor deposition or sputtering.
  • the insulating films 15, 23, 35 and 37 are made of Ta 2 O 5 (tantalum oxide), Al 2 O 3 (aluminum oxide), TiO 2 (titanium oxide), (Ba, Sr) TiO 2 (BST: barium strontium titanate). ), And SrTiO 3 (STO: strontium titanate). These high dielectric materials are formed by CVD or sputtering.
  • the insulating films 15, 23, 35, and 37 may be made of SiNx or SiOx. In this case, the insulating films 15, 23, 35, and 37 are formed by vapor deposition or the like. Further, the insulating films 15, 23, 35, and 37 may be made of acrylic or polyimide in addition to the inorganic film.
  • FIG. 4 is a diagram comparing FPD sensitivity and leakage current amount using CdZnTe and a-Se for the semiconductor layer 2.
  • the sensitivity is represented by a value indicating the number of electrons generated (converted) with respect to the X-ray irradiation dose per pixel.
  • a CdZnTe film has a sensitivity about 4 to 7 times that of an a-Se film.
  • the leakage current amount is about 100 times that of the a-Se film. Therefore, during long-time imaging, the capacitance of the capacitor 11 must be set in consideration of not only the charge generated (converted) by the X-ray incidence in the semiconductor layer 2 but also the charge due to the leak current.
  • the capacitance C of the capacitor 11 is preferably 5 pF or more.
  • the reset noise due to the on-resistance of the TFT 12 increases as the capacitance of the capacitor 11 increases.
  • the reset noise is noise that appears after the TFT 12 is turned off.
  • Reset noise is a random noise is irregular fluctuation component, of the random noise, it is less desirable than the larger X-ray quantum noise n x.
  • S / N ratio is deteriorated.
  • the reset noise is obtained by the equation (2), and the capacitance C s of the capacitor 11 is set so as to have a relationship as in the equation (3).
  • the reset noise n r and X-ray quantum noise n x is represented by the noise electron number.
  • n r ⁇ (2 ⁇ k ⁇ T ⁇ C s / q 2 ) (2) n r ⁇ n x (3)
  • the capacitor 11 is preferably configured with a capacitance of 5 pF to 30 pF.
  • the counter substrate 3 and the active matrix substrate 4 are bonded together by bonding the counter electrode 9 of the counter substrate 3 and the pixel electrode 25 of the active matrix substrate 4 with a bump electrode 41.
  • the bump electrode 41 is made of a conductive paste.
  • a conductive paste For example, an organic material is gradually volatilized and cured by leaving it at room temperature with a conductive material mainly composed of carbon on a base material mainly composed of rubber. Or a blend of a binder resin that cures by condensation with moisture in the air.
  • the electroconductive material contained in this electroconductive paste as long as it has electroconductivity, you may select a material suitably.
  • the main component of the base material is exemplified as rubber, but other polymer materials may be used.
  • binder resin it is not necessarily limited to resin, The mixture of the raw material which has adhesiveness and sclerosis
  • the conductive paste includes, for example, a material such as a binder resin that is cured by allowing the organic substance to volatilize gradually when left at room temperature, or to cure by condensation with moisture in the air.
  • a material such as a binder resin that is cured by allowing the organic substance to volatilize gradually when left at room temperature, or to cure by condensation with moisture in the air.
  • cures by giving a temperature change (to about 100 degreeC) may be contained.
  • the counter electrode 9 of the counter substrate 3 and the bump electrode 41 formed on the pixel electrode 25 of the active matrix substrate 4 are joined. Thereby, the counter substrate 3 and the active matrix substrate 4 are bonded together. Joining is performed by leaving at room temperature or applying heat as necessary while applying a predetermined pressure set in advance. Further, besides the bump electrode 41, an anisotropic conductive film (ACF) may be used for bonding (connection).
  • ACF anisotropic conductive film
  • FIG. 1 shows one X-ray detection element, and detection by the X-ray detection element corresponds to one pixel.
  • the X-ray detection elements DU are arranged in a two-dimensional matrix, and are composed of, for example, about 1500 ⁇ 1500 (about 230 ⁇ 230 mm).
  • the X-ray detection elements DU are composed of 3 ⁇ 3 for convenience of illustration. That is, the capacitor 11 and the TFT 12 are individually provided in a 3 ⁇ 3 X-ray detection element DU (pixel) configured in a matrix.
  • the gate line 21 is configured to be commonly connected by the X-ray detection elements DU in the row (X) direction, and the data line 17 is shared by the X-ray detection elements DU in the column (Y) direction. Configured to connect to.
  • the gate line 21 is connected to the gate drive unit 43, and the data line 17 is connected to the charge voltage conversion amplifier 45 and the multiplexer 47 in order.
  • the gate drive unit 43, the charge voltage conversion amplifier 45, and the multiplexer 47 are controlled by a drive control unit 49, and are driven by a signal from an external device (not shown), for example.
  • X-rays are irradiated from the X-ray tube toward the subject (both the X-ray tube and the subject are not shown), and the X-rays that have passed through the subject enter the FPD 1.
  • the semiconductor layer 2 electric charges are generated in the semiconductor layer 2 due to the photoconductive effect.
  • the capacitor 11 and the semiconductor layer 2 are connected in series by the hole injection blocking layer 8, the counter electrode 9 and the bump electrode 41. For this reason, when a bias voltage (Vh) is applied to the common electrode 6, charges generated in the semiconductor layer 2 move. The generated charges are collected by the counter electrode 9 and accumulated in the capacitor 11.
  • Vh bias voltage
  • the charge accumulated in the capacitor 11 is read out by the TFT 12.
  • the gate drive unit 43 applies a voltage sequentially from the upper gate line 21 of FIG. 5 one by one to transmit a signal, thereby turning the TFT 12 into a connected (ON) state, and the charge accumulated in the capacitor 11. Is read from the data line 17.
  • the charge-voltage conversion amplifier 45 converts the charge taken out through the data line 17 into a voltage and outputs it as a voltage signal.
  • the multiplexer 47 selects and outputs one voltage signal from the plurality of voltage signals. An X-ray image is acquired based on the voltage signal output in this way.
  • the CdTe or CdZnTe polycrystalline semiconductor layer 2 generates charges in response to incident X-rays, and the capacitor 11 generates charges generated in the semiconductor layer 2. accumulate.
  • the TFT 12 reads out the electric charge accumulated in the capacitor 11.
  • the capacitor 11 and the TFT 12 are individually provided in a plurality of pixels configured in a matrix.
  • condenser 11 is comprised by the capacity
  • the capacitor 11 includes a pixel electrode 25 and a first capacitor electrode 27 which are provided in a stacked manner and are electrically connected to each other, and a first ground layer 29 provided between the pixel electrode 25 and the first capacitor electrode 27. Insulating films 37 and 39 provided between the pixel electrode 25 and the first ground layer 29 and between the first ground layer 29 and the first capacitor electrode 27. As a result, the number of combinations of the capacitance electrode and the ground layer facing each other with the insulating films 37 and 39 interposed therebetween increases, and the area for forming the capacitance of the capacitor 11 (between the pixel electrode 25 and the first ground layer 29 and (Between the first ground layer 29 and the first capacitance electrode 27) can be increased, and the capacitance of the capacitor 11 can be increased. Therefore, even when the highly sensitive semiconductor layer 2 is employed, a large amount of charges can be accumulated, and the capacity of the capacitor 11 can be prevented from overflowing.
  • the first ground layer 29 and the second ground layer 31 are provided in a stacked manner, and the first ground layer 29 and the second ground layer 31 are electrically connected to each other.
  • a first capacitance electrode 27 is provided between the first ground layer 29 and the second ground layer 31.
  • the insulating films 15, 37, and 39 are made of any one of Ta 2 O 5 , Al 2 O 3 , (Ba, Sr) TiO 2 , and SrTiO 3 .
  • the capacitance of the capacitor 11 can be increased.
  • FIG. 6 is a longitudinal sectional view illustrating the configuration of a flat panel X-ray detector (FPD) according to the second embodiment.
  • FPD flat panel X-ray detector
  • description of the part which overlaps with each Example is abbreviate
  • the capacitor 61 of the second embodiment is formed by stacking more capacity electrodes and ground layers than the first embodiment.
  • the capacitor 61 of the FPD 60 includes a second capacitor electrode 63 and a third ground layer 65 between the second ground layer 31 and the insulating substrate 13.
  • the first capacitor electrode 27 and the second capacitor electrode 63 are electrically connected to each other through a third through hole 67.
  • the second ground layer 31 and the third ground layer 65 are electrically connected to each other through the fourth through hole 69.
  • An insulating film 71 is provided between the second ground layer 31 and the second capacitor electrode 63, and an insulating film 73 is provided between the second capacitor electrode 63 and the third ground layer 65. Yes.
  • the capacitor 61 includes the second capacitor electrode 63, the third ground layer 65, the third through hole 67, the fourth through hole 69, and the insulating films 71 and 73 in addition to the configuration of the capacitor 11 of the first embodiment.
  • the second capacitor electrode 63 corresponds to the capacitor electrode of the present invention
  • the third ground layer 65 corresponds to the ground layer of the present invention.
  • the insulating films 71 and 73 correspond to the interelectrode insulating film of the present invention.
  • the pixel electrode 25, the first capacitor electrode 27, the second capacitor electrode 63, the first through hole 33, and the third through hole 67 are the first to third ground layers 29, 31, 65, the second through hole 35, and the second through hole 35, respectively.
  • the 4-through hole 69 is not electrically connected.
  • the second capacitor electrode 63, the third ground layer 65, the third through hole 67, and the fourth through hole 69 are composed of a metal film such as Ta, Al, Mo, and Ti. . These metal films are formed by vapor deposition or sputtering.
  • the insulating films 71 and 73 are made of any one high dielectric material such as Ta 2 O 5 , Al 2 O 3 , TiO 2 , (Ba, Sr) TiO 2 , and SrTiO 3 . These high dielectric materials are formed by CVD or sputtering.
  • the TFT 12 is formed in the layers of the insulating films 15 and 39 so as to read out the electric charge accumulated in the capacitor 61 from the first capacitance electrode 27.
  • the TFT 12 may be formed in the layers of the insulating films 71 and 73 so as to read out the electric charge accumulated in the capacitor 61 from the second capacitance electrode 63.
  • the area for forming the capacitance of the capacitor 61 (further, between the second ground layer 31 and the second capacitor electrode 63, the second capacitor electrode 63 and the second capacitor electrode 63 3 ground layers 65) can be further increased. Therefore, the capacity of the capacitor 61 can be increased.
  • the present invention is not limited to the above embodiment, and can be modified as follows.
  • the capacitor electrode electrically connected to the second capacitor electrode 63 through the through hole between the third ground layer 65 and the insulating substrate 13, and the third ground layer 65 and the through-hole.
  • a ground layer electrically connected by a hole and an insulating film provided between the capacitor electrode and the ground layer may be provided.
  • the capacitor 11 (61) is composed of the same number of layers as the capacitance electrode and the ground layer.
  • the capacitor 81 includes three layers of the pixel electrode 25, the first capacitor electrode 27, and the second capacitor electrode 63 as the capacitor electrodes, and the first ground layer 29 and the first layers as the ground layers. Two layers of two ground layers 31 may be provided.
  • the capacitor 83 includes the pixel electrode 25, the first ground layer 29, the first through hole 33, and the second through hole in the capacitor 61 of FIG.
  • the hole 35 and the insulating films 37 and 39 may be omitted.
  • the first capacitor electrode 27 functions as the pixel electrode 25.
  • the semiconductor layer 2 is composed of a polycrystalline film of CdTe or CdZnTe, but is not limited thereto.
  • the semiconductor layer 2 can be applied as long as it is a highly sensitive material as compared with, for example, a-Se.
  • the semiconductor layer 2 that directly generates charges in response to incident X-rays is employed as the conversion layer.
  • the conversion layer may include a phosphor layer such as CsI (cesium iodide) that converts X-rays into light, and a photoelectric conversion element (photodiode) that converts light into charges.
  • the FPD 1 arranges the X-ray detection elements DU (pixels) in a two-dimensional matrix (array) form. It is configured to acquire an X-ray image. However, it may be configured to acquire a one-dimensional X-ray image.
  • the capacitor 111 in FIG. 9 may be used instead of the capacitor 11.
  • the insulating layer (interelectrode insulating film) 115 provided between the capacitor electrode 127 and the ground layer 131 includes Ta 2 O 5 , Al 2 O 3 , TiO 2 , (Ba, Sr) TiO 2 , and It is made of any one high dielectric material such as SrTiO 3 .

Abstract

An FPD1 capacitor (11) is configured having a capacity of equal to or greater than 5 pF but equal to or less than 30 pF. Using a semiconductor layer (2) of either a CdTe or a CdZnTe polycrystalline film, a large number of electrical charges is created by an incident X-ray, and a large number of electrical charges is generated by a leakage current. These electrical charges can be accumulated in the capacitor (11). Specifically, a large number of electrical charges can be accumulated even when a high-sensitivity semiconductor layer (conversion layer) (2) is used, and the capacity of the capacitor (11) can be prevented from overflowing. When the capacity of the capacitor (11) is increased, reset noise increases. However, decreasing the reset noise with respect to an X-ray quanta noise that is relatively larger than the reset noise makes it possible to curb the impact on the S/N ratio.

Description

放射線検出器Radiation detector
　本発明は、医用（診断用）および異物検査等の産業用に用いられる放射線（Ｘ線、γ線等）を検出する放射線検出器に関する。 The present invention relates to a radiation detector for detecting radiation (X-rays, γ-rays, etc.) used for medical (diagnosis) and industrial purposes such as foreign body inspection.
　従来の放射線検出器として、例えば、被検体等を透過したＸ線を検出して２次元のＸ線画像を得るためのフラットパネル型Ｘ線検出器（以下適宜、「ＦＰＤ」と略する）が挙げられる。ＦＰＤは、間接変換方式のものと、直接変換方式のものとがある（例えば、特許文献１および２参照）。 As a conventional radiation detector, for example, there is a flat panel X-ray detector (hereinafter abbreviated as “FPD” as appropriate) for detecting a X-ray transmitted through a subject or the like to obtain a two-dimensional X-ray image. Can be mentioned. The FPD includes an indirect conversion method and a direct conversion method (see, for example, Patent Documents 1 and 2).
　間接変換方式のＦＰＤは、Ｘ線を光に変換するＣｓＩ（ヨウ化セシウム）等の蛍光体層と、その直下に行列状（マトリクス状）に配置され、光を電荷に変換する光電変換素子（フォトダイオード）と、光電変換素子で変換された電荷を蓄積するコンデンサと、コンデンサに蓄積された電荷を読み出すスイッチング素子としての薄膜トランジスタ（以下適宜、「ＴＦＴ」と略する）と、を備えている。１画素は、それぞれ１つの光電変換素子、コンデンサおよびＴＦＴで構成されている。 An indirect conversion FPD is a phosphor layer such as CsI (cesium iodide) that converts X-rays to light, and a photoelectric conversion element (matrix shape) that is arranged immediately below the phosphor layer to convert light into charges. Photodiode), a capacitor for accumulating the charge converted by the photoelectric conversion element, and a thin film transistor (hereinafter abbreviated as “TFT” as appropriate) as a switching element for reading out the electric charge accumulated in the capacitor. Each pixel is composed of one photoelectric conversion element, a capacitor, and a TFT.
　一方、直接変換方式のＦＰＤ１０１は、図９に示すように、Ｘ線に感応し入射線量に応じた電荷を直接変換する変換層１０２と、その直下に行列状に配置され、変換層１０２で変換された電荷を蓄積するコンデンサ１１１と、コンデンサ１１１に蓄積された電荷を読み出すスイッチング素子としてのＴＦＴ１１２と、を備えている。１画素は、それぞれ１つのコンデンサ１１１およびＴＦＴ１１２で構成されている。なお、変換層１０２には、ａ－Ｓｅ（アモルファスセレン）、ＣｄＴｅ（テルル化カドミウム）またはＣｄＺｎＴｅ（テルル化カドミウム亜鉛）の高抵抗半導体が用いられる。 On the other hand, as shown in FIG. 9, the FPD 101 of the direct conversion method is arranged in a matrix form immediately below the conversion layer 102 that is sensitive to X-rays and directly converts charges according to the incident dose, and is converted by the conversion layer 102. The capacitor 111 for storing the generated charge and the TFT 112 as a switching element for reading the charge stored in the capacitor 111 are provided. One pixel is composed of one capacitor 111 and one TFT 112, respectively. For the conversion layer 102, a high-resistance semiconductor of a-Se (amorphous selenium), CdTe (cadmium telluride) or CdZnTe (cadmium zinc telluride) is used.
　画素電極１２５は、容量電極１２７と電気的に接続されている。コンデンサ１１１は、容量電極１２７とグランド層１３１とを有する。共通電極１０６にはバイアス電圧が印加されており、Ｘ線入射により変換された電荷は、変換層１０２から順番に正孔注入阻止層１０８、対向電極１０９、バンプ電極１４１、画素電極１２５、スルーホール１３３を通過して、コンデンサ１１１に蓄積される。コンデンサ１１１に蓄積された電荷は、ＴＦＴ１１２の動作によりコンデンサ１１１から読み出される。 The pixel electrode 125 is electrically connected to the capacitor electrode 127. The capacitor 111 includes a capacitive electrode 127 and a ground layer 131. A bias voltage is applied to the common electrode 106, and the charges converted by the X-ray incidence are sequentially transferred from the conversion layer 102 to the hole injection blocking layer 108, the counter electrode 109, the bump electrode 141, the pixel electrode 125, and the through hole. 133 is stored in the capacitor 111. The electric charge accumulated in the capacitor 111 is read from the capacitor 111 by the operation of the TFT 112.
特開２０００－３４９２６９号公報JP 2000-349269 A 特開２００６－２１１６９３号公報JP 2006-211163 A
　しかしながら、このような従来例の場合には、次のような問題がある。すなわち、変換層１０２が、ＣｄＴｅまたはＣｄＺｎＴｅで構成される場合は、変換層１０２が高感度となる。これにより、例えばａ－Ｓｅ等の変換層１０２に比べ、Ｘ線入射により多くの電荷が変換される。また、Ｘ線入射により変換された電荷の他にも、ａ－Ｓｅ等の変換層１０２に比べ、Ｘ線が照射されていないときのリーク電流による電荷も多く発生する。すなわち、Ｘ線入射により変換された電荷とリーク電流による電荷とがａ－Ｓｅ等の変換層１０２よりも多くコンデンサ１１１に蓄積される。そのため、従来のコンデンサ１１１では、長時間の撮影時にその容量がオーバーフローしてしまう。 However, such a conventional example has the following problems. That is, when the conversion layer 102 is made of CdTe or CdZnTe, the conversion layer 102 has high sensitivity. Thereby, for example, more charges are converted by X-ray incidence than the conversion layer 102 such as a-Se. In addition to the charges converted by the incidence of X-rays, more charges are generated due to leakage current when X-rays are not irradiated than the conversion layer 102 such as a-Se. That is, more charge is converted into the capacitor 111 due to X-ray incidence than the conversion layer 102 such as a-Se. For this reason, the capacity of the conventional capacitor 111 overflows during long-time shooting.
　本発明は、このような事情に鑑みてなされたものであって、高感度の変換層を採用した場合でも多くの電荷を蓄積することが可能な放射線検出器を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a radiation detector capable of accumulating a large amount of charge even when a highly sensitive conversion layer is employed.
　本発明者は、上記の問題を解決するために鋭意研究した結果、次のような知見を得た。コンデンサの容量Ｃは、Ｃ＝ε×（Ｓ／ｄ）の式に示すように、εは誘電率、Ｓは面積、ｄは電極間距離によって設定される。そのため、コンデンサの容量Ｃを増やすためには、誘電率εを大きくする、面積Ｓを広くする、電極間距離ｄを短く（薄く）することの少なくともいずれかを行って容量Ｃを設定すればよい。しかしながら、電極間の絶縁膜を薄く形成するには、膜厚を均一しなければならない問題がある。また、面積Ｓは、画素ピッチに影響され、その大きさに制限がある。 As a result of intensive studies to solve the above problems, the present inventor has obtained the following knowledge. The capacitance C of the capacitor is set according to the dielectric constant, S is the area, and d is the distance between the electrodes, as shown in the equation C = ε × (S / d). Therefore, in order to increase the capacitance C of the capacitor, the capacitance C may be set by at least one of increasing the dielectric constant ε, increasing the area S, and shortening (thinning) the interelectrode distance d. . However, in order to form a thin insulating film between the electrodes, there is a problem that the film thickness must be uniform. Further, the area S is affected by the pixel pitch, and its size is limited.
　このような知見に基づく本発明は、次のような構成をとる。すなわち、本発明に係る放射線検出器は、入射した放射線に感応して電荷を生成するＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層と、マトリクス状に構成された複数の画素に個別に設けられる前記半導体層で生成された電荷を蓄積するコンデンサと、マトリクス状に構成された複数の画素に個別に設けられる前記コンデンサに蓄積された電荷を読み出すスイッチング素子と、を備え、前記コンデンサは、５ｐＦ以上３０ｐＦ以下の容量で構成されることを特徴とするものである。 The present invention based on such knowledge has the following configuration. That is, the radiation detector according to the present invention includes a semiconductor layer of a polycrystalline film of CdTe or CdZnTe that generates charges in response to incident radiation, and the semiconductor individually provided in a plurality of pixels configured in a matrix. A capacitor for accumulating the charge generated in the layer, and a switching element for reading out the electric charge accumulated in the capacitor individually provided in a plurality of pixels arranged in a matrix, wherein the capacitor is 5 pF or more and 30 pF or less It is comprised by the capacity | capacitance of.
　本発明に係る放射線検出器によれば、ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層は、入射した放射線に感応して電荷を生成し、コンデンサは半導体層で生成された電荷を蓄積する。スイッチング素子はコンデンサに蓄積された電荷を読み出す。コンデンサおよびスイッチング素子は、マトリクス状に構成された複数の画素に個別に設けられている。そして、コンデンサは、５ｐＦ以上３０ｐＦ以下の容量で構成されている。ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層によって、放射線の入射で多くの電荷が生成され、また、リーク電流による多くの電荷が発生する。それらの電荷をコンデンサに蓄積することができる。すなわち、高感度の変換層を採用した場合でも多くの電荷を蓄積することができ、コンデンサの容量がオーバーフローすることを防止することができる。また、コンデンサの容量の大きくするとリセットノイズが大きくなる。しかしながら、リセットノイズよりも比較的に大きなＸ線量子ノイズに対し、リセットノイズを小さくすることで、Ｓ／Ｎ比に与える影響を抑えることができる。 According to the radiation detector according to the present invention, the semiconductor layer of the polycrystalline film of CdTe or CdZnTe generates charges in response to incident radiation, and the capacitor stores the charges generated in the semiconductor layer. The switching element reads the electric charge accumulated in the capacitor. The capacitor and the switching element are individually provided for a plurality of pixels configured in a matrix. And the capacitor | condenser is comprised by the capacity | capacitance of 5 pF or more and 30 pF or less. A semiconductor layer of a polycrystalline film of CdTe or CdZnTe generates a lot of charges upon incidence of radiation and generates a lot of charges due to a leak current. Those charges can be stored in the capacitor. That is, even when a high-sensitivity conversion layer is employed, a large amount of charge can be accumulated, and the capacitance of the capacitor can be prevented from overflowing. In addition, the reset noise increases as the capacitance of the capacitor increases. However, the influence on the S / N ratio can be suppressed by reducing the reset noise relative to the X-ray quantum noise that is relatively larger than the reset noise.
　また、本発明に係る放射線検出器において、前記コンデンサは、積層して設けられる互いに電気的に接続された複数の容量電極と、前記複数の容量電極の間に設けられるグランド層と、前記容量電極と前記グランド層との間に設けられる電極間絶縁膜とを有することが好ましい。これにより、電極間絶縁膜を挟んで対向する容量電極とグランド層との組合せが増えることになり、コンデンサの容量を形成する面積を増やすことができ、コンデンサの容量を大きくすることができる。そのため、高感度の変換層を採用した場合でも多くの電荷を蓄積することができ、コンデンサの容量がオーバーフローすることを防止することができる。 In the radiation detector according to the present invention, the capacitor includes a plurality of capacitor electrodes electrically connected to each other, a ground layer provided between the capacitor electrodes, and the capacitor electrode. And an inter-electrode insulating film provided between the first electrode and the ground layer. As a result, the number of combinations of the capacitor electrode and the ground layer facing each other with the interelectrode insulating film interposed therebetween is increased, the area for forming the capacitor can be increased, and the capacitance of the capacitor can be increased. Therefore, even when a high-sensitivity conversion layer is employed, a large amount of charge can be accumulated, and the capacitance of the capacitor can be prevented from overflowing.
　また、本発明に係る放射線検出器において、前記グランド層は、複数のグランド層が積層して設けられ、前記複数のグランド層は、互いに電気的に接続され、前記複数のグランド層の間には、前記複数の容量電極のいずれか１つが設けられることが好ましい。これにより、複数の容量電極と複数のグランド層とが交互に配置された積層構造とすることができる。そのため、コンデンサの容量を形成する面積を増やすことができる。 Further, in the radiation detector according to the present invention, the ground layer is provided by laminating a plurality of ground layers, and the plurality of ground layers are electrically connected to each other between the plurality of ground layers. Preferably, any one of the plurality of capacitive electrodes is provided. Thereby, it can be set as the laminated structure by which the some capacitive electrode and the some ground layer were arrange | positioned alternately. Therefore, the area for forming the capacitance of the capacitor can be increased.
　また、本発明に係る放射線検出器において、前記コンデンサの電極間絶縁膜は、Ｔａ２Ｏ５、Ａｌ２Ｏ３、（Ｂａ，Ｓｒ）ＴｉＯ２、ＳｒＴｉＯ３のいずれかで構成されることが好ましい。コンデンサの電極間絶縁膜に、高誘電体材料が用いられることにより、コンデンサの容量を大きくすることができる。 In the radiation detector according to the present invention, the interelectrode insulating film of the capacitor is preferably composed of any one of Ta 2 O 5 , Al 2 O 3 , (Ba, Sr) TiO 2 , and SrTiO 3. . By using a high dielectric material for the interelectrode insulating film of the capacitor, the capacitance of the capacitor can be increased.
　本発明に係る放射線検出器によれば、ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層は、入射した放射線に感応して電荷を生成し、コンデンサは半導体層で生成された電荷を蓄積する。スイッチング素子はコンデンサに蓄積された電荷を読み出す。コンデンサおよびスイッチング素子は、マトリクス状に構成された複数の画素に個別に設けられている。そして、コンデンサは、５ｐＦ以上３０ｐＦ以下の容量で構成されている。ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層によって、放射線の入射で多くの電荷が生成され、また、リーク電流による多くの電荷が発生する。それらの電荷をコンデンサに蓄積することができる。すなわち、高感度の変換層を採用した場合でも多くの電荷を蓄積することができ、コンデンサの容量がオーバーフローすることを防止することができる。また、コンデンサの容量の大きくするとリセットノイズが大きくなる。しかしながら、リセットノイズよりも比較的に大きなＸ線量子ノイズに対し、リセットノイズを小さくすることで、Ｓ／Ｎ比に与える影響を抑えることができる。 According to the radiation detector according to the present invention, the semiconductor layer of the polycrystalline film of CdTe or CdZnTe generates charges in response to incident radiation, and the capacitor stores the charges generated in the semiconductor layer. The switching element reads the electric charge accumulated in the capacitor. The capacitor and the switching element are individually provided for a plurality of pixels configured in a matrix. And the capacitor | condenser is comprised by the capacity | capacitance of 5 pF or more and 30 pF or less. A semiconductor layer of a polycrystalline film of CdTe or CdZnTe generates a lot of charges upon incidence of radiation and generates a lot of charges due to a leak current. Those charges can be stored in the capacitor. That is, even when a high-sensitivity conversion layer is employed, a large amount of charge can be accumulated, and the capacitance of the capacitor can be prevented from overflowing. In addition, the reset noise increases as the capacitance of the capacitor increases. However, the influence on the S / N ratio can be suppressed by reducing the reset noise relative to the X-ray quantum noise that is relatively larger than the reset noise.
実施例１に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。1 is a longitudinal sectional view illustrating a configuration of a flat panel X-ray detector (FPD) according to Embodiment 1. FIG. フラットパネル型Ｘ線検出器（ＦＰＤ）の対向基板の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the opposing board | substrate of a flat panel type X-ray detector (FPD). （ａ）～（ｃ）は、図１中のＡ方向から見た、第１グランド層、容量電極および第１，第２スルーホールの一例を示す部分平面図である。(A) to (c) are partial plan views showing an example of a first ground layer, a capacitor electrode, and first and second through holes as viewed from the direction A in FIG. 半導体層にＣｄＺｎＴｅとａ－Ｓｅを用いたフラットパネル型Ｘ線検出器（ＦＰＤ）の感度およびリーク電流量を比較した図である。It is the figure which compared the sensitivity and the amount of leak current of the flat panel type X-ray detector (FPD) using CdZnTe and a-Se for a semiconductor layer. フラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示すブロック図である。It is a block diagram which shows the structure of a flat panel type X-ray detector (FPD). 実施例２に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the flat panel type | mold X-ray detector (FPD) which concerns on Example 2. FIG. 変形例に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the flat panel type | mold X-ray detector (FPD) which concerns on a modification. 変形例に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the flat panel type | mold X-ray detector (FPD) which concerns on a modification. 従来のフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the conventional flat panel type | mold X-ray detector (FPD).
　以下、図面を参照して本発明の実施例１を説明する。本実施例では、フラットパネル型Ｘ線検出器（ＦＰＤ）を放射線検出器の一例として説明する。なお、図１は、実施例１に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。図２は、フラットパネル型Ｘ線検出器（ＦＰＤ）の対向基板の構成を示す縦断面図である。図３は、（ａ）～（ｃ）は、図１中のＡ方向から見た、第１グランド層、容量電極および第１，第２スルーホールの一例を示す部分平面図である。図４は、半導体層にＣｄＺｎＴｅとａ－Ｓｅを用いたフラットパネル型Ｘ線検出器（ＦＰＤ）の感度およびリーク電流量を比較した図である。図５は、フラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示すブロック図である。 Embodiment 1 of the present invention will be described below with reference to the drawings. In this embodiment, a flat panel X-ray detector (FPD) will be described as an example of a radiation detector. FIG. 1 is a longitudinal sectional view showing the configuration of a flat panel X-ray detector (FPD) according to the first embodiment. FIG. 2 is a longitudinal sectional view showing the configuration of the counter substrate of the flat panel X-ray detector (FPD). FIGS. 3A to 3C are partial plan views showing examples of the first ground layer, the capacitor electrode, and the first and second through holes as viewed from the direction A in FIG. FIG. 4 is a diagram comparing the sensitivity and the amount of leakage current of a flat panel X-ray detector (FPD) using CdZnTe and a-Se for the semiconductor layer. FIG. 5 is a block diagram showing a configuration of a flat panel X-ray detector (FPD).
　図１および図２を参照する。フラットパネル型Ｘ線検出器（ＦＰＤ）１は、入射したＸ線に感応して電荷（電子－正孔対キャリア）を生成する半導体層２を有する対向基板（検出基板ともいう）３と、生成された電荷を蓄積するとともに蓄積された電荷を読み出すアクティブマトリクス基板４とを備えている。 Refer to FIG. 1 and FIG. A flat panel X-ray detector (FPD) 1 includes a counter substrate (also referred to as a detection substrate) 3 having a semiconductor layer 2 that generates charges (electron-hole pair carriers) in response to incident X-rays, and a generation And an active matrix substrate 4 for reading out the accumulated charges.
　＜対向基板＞
　対向基板３は、Ｘ線入射方向（図１および図２中の符号ｘ）から順番に、半導体層２の基礎となる支持基板５と、支持基板５の下面に形成されるバイアス電圧印加用の共通電極６と、半導体層２への電荷（電子）の注入を阻止する電子注入阻止層７と、半導体層２と、半導体層２への電荷（正孔）の注入を阻止する正孔注入阻止層８と、電荷収集用の対向電極９と、が積層形成された構成となっている。 <Counter substrate>
The counter substrate 3 is formed in order from the X-ray incident direction (symbol x in FIGS. 1 and 2), and a support substrate 5 that is the basis of the semiconductor layer 2 and a bias voltage application formed on the lower surface of the support substrate 5. Common electrode 6, electron injection blocking layer 7 for blocking charge (electron) injection into semiconductor layer 2, semiconductor layer 2, and hole injection blocking for blocking charge (hole) injection into semiconductor layer 2 The layer 8 and the counter electrode 9 for collecting charges are stacked.
　支持基板５は、Ｘ線の吸収係数が小さなものが好ましく、例えば、グラファイトや、セラミック（Ａｌ２Ｏ３、ＡｌＮ）、シリコン等が用いられる。共通電極６は、ＩＴＯ（酸化インジウムスズ）や、Ａｕ（金）、Ｐｔ（白金）などの導電材料から構成され、支持基板５上に蒸着法やスパッタリング等で形成される。支持基板５にグラファイトのような導電性材料を用いる場合は、共通電極６を省略してもよい。 The support substrate 5 preferably has a small X-ray absorption coefficient. For example, graphite, ceramic (Al 2 O 3 , AlN), silicon, or the like is used. The common electrode 6 is made of a conductive material such as ITO (indium tin oxide), Au (gold), or Pt (platinum), and is formed on the support substrate 5 by vapor deposition or sputtering. When a conductive material such as graphite is used for the support substrate 5, the common electrode 6 may be omitted.
　電子注入阻止層７は、ＺｎＴｅ、Ｓｂ２Ｓ３、またはＳｂ２Ｔｅ３等のｐ型半導体で構成され、共通電極６上に昇華法、蒸着もしくはスパッタリング、化学析出法、または電析法等によって形成される。 The electron injection blocking layer 7 is made of a p-type semiconductor such as ZnTe, Sb 2 S 3 , or Sb 2 Te 3 , and is formed on the common electrode 6 by a sublimation method, vapor deposition or sputtering, chemical deposition method, or electrodeposition method. It is formed.
　半導体層２は、ＣｄＴｅまたはＣｄＺｎＴｅといった化合物半導体が用いられ、ＣｄＴｅまたはＣｄＺｎＴｅは、多結晶膜で構成される。ＣｄＴｅまたはＣｄＺｎＴｅの半導体層２は、近接昇華法により形成される。すなわち、ＣｄＴｅまたはＣｄＺｎＴｅの半導体層２は、共通電極６および電子注入阻止層７が形成された支持基板５を、焼結体または混合焼結体に対向して近接配置し、減圧下で加熱して昇華させることにより形成される。焼結体または混合焼結体（これらをソースとも言う）は、例えば、ＣｄＴｅの粉末材料の焼結体や、ＣｄＴｅの粉末材料とＺｎＴｅの粉末材料との混合焼結体や、ＣｄＺｎＴｅの粉末材料の焼結体を用いる。半導体層２は、近接昇華法により６００～７００μｍに形成され、５００μｍ程の厚みに研磨される。 The semiconductor layer 2 is made of a compound semiconductor such as CdTe or CdZnTe, and CdTe or CdZnTe is composed of a polycrystalline film. The semiconductor layer 2 of CdTe or CdZnTe is formed by proximity sublimation. That is, in the semiconductor layer 2 of CdTe or CdZnTe, the support substrate 5 on which the common electrode 6 and the electron injection blocking layer 7 are formed is disposed close to the sintered body or the mixed sintered body and heated under reduced pressure. Formed by sublimation. The sintered body or the mixed sintered body (also referred to as a source) is, for example, a sintered body of a CdTe powder material, a mixed sintered body of a CdTe powder material and a ZnTe powder material, or a CdZnTe powder material. The sintered body is used. The semiconductor layer 2 is formed to 600 to 700 μm by the proximity sublimation method and polished to a thickness of about 500 μm.
　正孔注入阻止層８は、ＣｄＳ（硫化カドミウム）、ＺｎＳ（硫化亜鉛）、ＺｎＯ（酸化亜鉛）、またはＳｂ２Ｓ３（硫化アンチモン）等のｎ型半導体で構成され、昇華法、蒸着法、スパッタリング、化学析出法、または電析法等で形成される。正孔注入阻止層８は、必要に応じてパターニングして画素ごとに分離して形成する。但し、正孔注入阻止層８が高抵抗で隣接画素リークによる空間解像度低下などの弊害が無ければ、分離して形成しなくてもよい。 The hole injection blocking layer 8 is made of an n-type semiconductor such as CdS (cadmium sulfide), ZnS (zinc sulfide), ZnO (zinc oxide), or Sb 2 S 3 (antimony sulfide). It is formed by sputtering, chemical precipitation, or electrodeposition. The hole injection blocking layer 8 is formed separately for each pixel by patterning as necessary. However, if the hole injection blocking layer 8 has a high resistance and there is no harmful effect such as a decrease in spatial resolution due to adjacent pixel leakage, it may not be formed separately.
　なお、必要に応じて、電子注入阻止層７と正孔注入阻止層８との配置を交換した構成としてもよいし、また、電子注入阻止層７および正孔注入阻止層８のいずれか一方あるいは両方を形成しない構成としてもよい。 If necessary, the arrangement of the electron injection blocking layer 7 and the hole injection blocking layer 8 may be exchanged, and either the electron injection blocking layer 7 or the hole injection blocking layer 8 or It is good also as a structure which does not form both.
　対向電極９は、共通電極６と同様に、ＩＴＯや、Ａｕ、Ｐｔなどの導電材料から構成され、正孔注入阻止層８上に蒸着法やスパッタリング等で形成される。なお、必要に応じて、対向電極９を形成しない構成としてもよい。 The counter electrode 9 is made of a conductive material such as ITO, Au, or Pt, like the common electrode 6, and is formed on the hole injection blocking layer 8 by vapor deposition or sputtering. In addition, it is good also as a structure which does not form the counter electrode 9 as needed.
　＜アクティブマトリクス基板＞
　一方、アクティブマトリクス基板４は、生成された電荷を蓄積するコンデンサ１１と、コンデンサ１１に蓄積された電荷を読み出す薄膜トランジスタ（ＴＦＴ）１２などを備えている。コンデンサ１１とＴＦＴ１２等は、絶縁基板１３上に形成される。ＴＦＴ１２は、後述する第１容量電極２７および絶縁膜１５、データ線１７、ゲートチャネル１９、ゲート線２１で構成されている。なお、絶縁膜２３は保護膜として形成される。また、ＴＦＴ１２は、本発明のスイッチング素子に相当する。 <Active matrix substrate>
On the other hand, the active matrix substrate 4 includes a capacitor 11 that stores the generated charge, a thin film transistor (TFT) 12 that reads the charge stored in the capacitor 11, and the like. The capacitor 11, the TFT 12, etc. are formed on the insulating substrate 13. The TFT 12 includes a first capacitor electrode 27 and an insulating film 15, which will be described later, a data line 17, a gate channel 19, and a gate line 21. The insulating film 23 is formed as a protective film. The TFT 12 corresponds to the switching element of the present invention.
　コンデンサ１１は、厚み方向２４に積層して形成された、画素電極２５、第１容量電極２７、第１グランド層２９、および第２グランド層３１を有している。画素電極２５と第１容量電極２７は、第１スルーホール３３によって、互いに電気的に接続されている。また、第１グランド層２９と第２グランド層３１は、第２スルーホール３５によって、互いに電気的に接続されている。第１グランド層２９と第２グランド層３１は、アースされたり、予め設定された所定電圧が印加されていたりする。 The capacitor 11 includes a pixel electrode 25, a first capacitor electrode 27, a first ground layer 29, and a second ground layer 31 that are stacked in the thickness direction 24. The pixel electrode 25 and the first capacitor electrode 27 are electrically connected to each other through the first through hole 33. The first ground layer 29 and the second ground layer 31 are electrically connected to each other through the second through hole 35. The first ground layer 29 and the second ground layer 31 are grounded or a predetermined voltage set in advance is applied.
　また、画素電極２５と第１グランド層２９との間には、絶縁膜３７が設けられている。同様に、第１グランド層２９と第１容量電極２７との間には、絶縁膜３９が設けられ、第１容量電極２７と第２グランド層３１との間には、絶縁膜１５が設けられている。 Further, an insulating film 37 is provided between the pixel electrode 25 and the first ground layer 29. Similarly, an insulating film 39 is provided between the first ground layer 29 and the first capacitor electrode 27, and an insulating film 15 is provided between the first capacitor electrode 27 and the second ground layer 31. ing.
　また、図３は、（ａ）～（ｃ）は、図１中のＡ方向から見た部分平面図である。図３（ａ）に示すように、第１スルーホール３３は、第１グランド層２９と重ならない（接続しない）位置に形成され、第２スルーホール３５も第１容量電極２７と重ならない位置に形成されている。図３（ａ）に示す形態に限らず、図３（ｂ）に示すように、第１スルーホール３３は、第１グランド層２９の内側であって、第１グランド層２９と接続しないように設けてもよい。また、図３（ｃ）に示すように、平面視で対向する位置に第１スルーホール３３および第２スルーホール３５を設けてもよい。 FIG. 3 is a partial plan view as seen from the direction A in FIG. 1 (a) to (c). As shown in FIG. 3A, the first through hole 33 is formed at a position where it does not overlap (does not connect) with the first ground layer 29, and the second through hole 35 also does not overlap with the first capacitor electrode 27. Is formed. Not only the form shown in FIG. 3A but also the first through hole 33 is inside the first ground layer 29 and is not connected to the first ground layer 29 as shown in FIG. 3B. It may be provided. Further, as shown in FIG. 3C, the first through hole 33 and the second through hole 35 may be provided at positions facing each other in plan view.
　図１に戻る。コンデンサ１１は、画素電極２５、第１容量電極２７、第１グランド層２９、第２グランド層３１、第１スルーホール３３、第２スルーホール３５、および絶縁膜１５，３７，３９を有している。なお、画素電極２５および第１容量電極２７は本発明の容量電極に相当し、第１グランド層２９および第２グランド層３１は本発明のグランド層に相当する。絶縁膜１５，３７，３９が本発明の電極間絶縁膜に相当する。 Return to Figure 1. The capacitor 11 includes a pixel electrode 25, a first capacitor electrode 27, a first ground layer 29, a second ground layer 31, a first through hole 33, a second through hole 35, and insulating films 15, 37, and 39. Yes. The pixel electrode 25 and the first capacitor electrode 27 correspond to the capacitor electrode of the present invention, and the first ground layer 29 and the second ground layer 31 correspond to the ground layer of the present invention. The insulating films 15, 37 and 39 correspond to the interelectrode insulating film of the present invention.
　ゲートチャネル１９は、ａ－Ｓｉ（アモルファスシリコン）やｐ－Ｓｉ（ポリシリコン）を蒸着法で形成し、不純物を拡散させて例えばｎ＋層としたもので構成される。データ線１７、ゲート線２１、画素電極２５、第１容量電極２７、第１グランド層２９、第２グランド層３１、第１スルーホール３３、および第２スルーホール３５は、Ｔａ（タンタル）、Ａｌ（アルミニウム）、Ｍｏ（モリブデン）、Ｔｉ（チタン）等の金属膜で構成される。これらの金属膜は、蒸着法またはスパッタリング等で形成される。 The gate channel 19 is composed of, for example, an n + layer formed by depositing a-Si (amorphous silicon) or p-Si (polysilicon) by vapor deposition and diffusing impurities. The data line 17, the gate line 21, the pixel electrode 25, the first capacitor electrode 27, the first ground layer 29, the second ground layer 31, the first through hole 33, and the second through hole 35 are Ta (tantalum), Al (Aluminum), Mo (molybdenum), Ti (titanium), etc. are comprised. These metal films are formed by vapor deposition or sputtering.
　絶縁膜１５，２３，３５，３７は、Ｔａ２Ｏ５（酸化タンタル）、Ａｌ２Ｏ３（酸化アルミニウム）、ＴｉＯ２（酸化チタン）、（Ｂａ，Ｓｒ）ＴｉＯ２（ＢＳＴ：チタン酸バリウムストロンチウム）、およびＳｒＴｉＯ３（ＳＴＯ：チタン酸ストロンチウム）等のいずれか１つの高誘電体材料で構成される。これらの高誘電体材料は、ＣＶＤ法またはスパッタリング等で形成される。また、絶縁膜１５，２３，３５，３７は、ＳｉＮｘやＳｉＯｘで構成してもよい。この場合、絶縁膜１５，２３，３５，３７は蒸着法等で形成される。また、絶縁膜１５，２３，３５，３７は、無機膜の他にアクリルやポリイミド等で構成してもよい。 The insulating films 15, 23, 35 and 37 are made of Ta 2 O 5 (tantalum oxide), Al 2 O 3 (aluminum oxide), TiO 2 (titanium oxide), (Ba, Sr) TiO 2 (BST: barium strontium titanate). ), And SrTiO 3 (STO: strontium titanate). These high dielectric materials are formed by CVD or sputtering. The insulating films 15, 23, 35, and 37 may be made of SiNx or SiOx. In this case, the insulating films 15, 23, 35, and 37 are formed by vapor deposition or the like. Further, the insulating films 15, 23, 35, and 37 may be made of acrylic or polyimide in addition to the inorganic film.
　次に、コンデンサ１１の容量について説明する。図４は、半導体層２にＣｄＺｎＴｅとａ－Ｓｅを用いたＦＰＤの感度およびリーク電流量を比較した図である。なお、感度は、１画素当たりのＸ線照射線量に対する生成（変換）された電子数を示した値で表す。例えば、ＣｄＺｎＴｅ膜は、ａ－Ｓｅ膜に対し、４～７倍程度の感度を示す。さらに、ａ－Ｓｅ膜の１００倍程度のリーク電流量を示す。そのため、長時間撮影時には、半導体層２でＸ線入射により生成（変換）された電荷のみならず、リーク電流による電荷を考慮してコンデンサ１１の容量を設定しなければならない。 Next, the capacity of the capacitor 11 will be described. FIG. 4 is a diagram comparing FPD sensitivity and leakage current amount using CdZnTe and a-Se for the semiconductor layer 2. The sensitivity is represented by a value indicating the number of electrons generated (converted) with respect to the X-ray irradiation dose per pixel. For example, a CdZnTe film has a sensitivity about 4 to 7 times that of an a-Se film. Further, the leakage current amount is about 100 times that of the a-Se film. Therefore, during long-time imaging, the capacitance of the capacitor 11 must be set in consideration of not only the charge generated (converted) by the X-ray incidence in the semiconductor layer 2 but also the charge due to the leak current.
　コンデンサ１１の容量は、まず、一般撮影の条件（例えば、腰椎、側面）でＸ線照射を行い、コンデンサ１１に蓄積される電荷を求める。蓄積電荷Ｑは、半導体層２でＸ線入射により変換された電荷とリーク電流による電荷とを加算した電荷とで求められる。コンデンサ１１に加わる電圧Ｖは、ゲート線２１の入力電圧Ｖｇｌ（－１０Ｖ）の３～５分の１程度が好ましく、式（１）から求められる。この式（１）により、コンデンサ１１の容量Ｃは、５ｐＦ以上であることが好ましい。
　Ｑ／Ｃ＝Ｖ＜Ｖｇｌ／（３～５）　　　…（１） For the capacity of the capacitor 11, first, X-ray irradiation is performed under the general imaging conditions (for example, lumbar spine, side surface), and the charge accumulated in the capacitor 11 is obtained. The accumulated charge Q is obtained from the charge obtained by adding the charge converted by the X-ray incidence in the semiconductor layer 2 and the charge due to the leakage current. The voltage V applied to the capacitor 11 is preferably about 3 to 1/5 of the input voltage V gl (−10 V) of the gate line 21 and is obtained from the equation (1). According to this equation (1), the capacitance C of the capacitor 11 is preferably 5 pF or more.
Q / C = V <V gl / (3 to 5) (1)
　また、ＴＦＴ１２のオン抵抗によるリセットノイズは、コンデンサ１１の容量が大きいほど大きくなる。リセットノイズは、ＴＦＴ１２をＯＦＦにした後に現れるノイズである。リセットノイズは、不規則なゆらぎ成分であるランダムノイズであり、このランダムノイズのうち、比較的大きいＸ線量子ノイズｎｘよりも小さいことが望まれる。リセットノイズｎｒがＸ線量子ノイズｎｘよりも大きくなると、Ｓ／Ｎ比が悪くなる。リセットノイズは、式（２）により求められ、式（３）のような関係となるように、コンデンサ１１の容量Ｃｓが設定される。なお、リセットノイズｎｒおよびＸ線量子ノイズｎｘは、ノイズ電子数で表される。また、ｋはボルツマン定数、Ｔは絶対温度、Ｃｓは容量、ｑは電荷素量を示す。これら式（２）および式（３）により、コンデンサ１１の容量Ｃは、３０ｐＦ未満であることが好ましい。
　ｎｒ＝√（２×ｋ×Ｔ×Ｃｓ／ｑ２）　　　…（２）
　ｎｒ＜ｎｘ　　　…（３） The reset noise due to the on-resistance of the TFT 12 increases as the capacitance of the capacitor 11 increases. The reset noise is noise that appears after the TFT 12 is turned off. Reset noise is a random noise is irregular fluctuation component, of the random noise, it is less desirable than the larger X-ray quantum noise n x. When the reset noise n r is greater than X-ray quantum noise n x, S / N ratio is deteriorated. The reset noise is obtained by the equation (2), and the capacitance C s of the capacitor 11 is set so as to have a relationship as in the equation (3). The reset noise n r and X-ray quantum noise n x is represented by the noise electron number. Also, k is the Boltzmann constant, T is the absolute temperature, C s is the capacitance, q represents an elementary charge. According to these expressions (2) and (3), the capacitance C of the capacitor 11 is preferably less than 30 pF.
n r = √ (2 × k × T × C s / q 2 ) (2)
n r <n x (3)
　すなわち、コンデンサ１１は、５ｐＦ以上３０ｐＦ以下の容量で構成されることが好ましい。 That is, the capacitor 11 is preferably configured with a capacitance of 5 pF to 30 pF.
　次に、対向基板３とアクティブマトリクス基板４との貼り合わせ等について説明する。対向基板３とアクティブマトリクス基板４は、図１に示すように、対向基板３の対向電極９とアクティブマトリクス基板４の画素電極２５とがバンプ電極４１で接合されることにより、貼り合わされている。 Next, bonding of the counter substrate 3 and the active matrix substrate 4 will be described. As shown in FIG. 1, the counter substrate 3 and the active matrix substrate 4 are bonded together by bonding the counter electrode 9 of the counter substrate 3 and the pixel electrode 25 of the active matrix substrate 4 with a bump electrode 41.
　バンプ電極４１は、導電性ペーストで構成され、例えば、ゴムを主成分とした母材に、カーボンを主成分とした導電性材料と、常温で放置することにより有機物質が徐々に揮発して硬化する、あるいは空気中の水分と縮合反応して硬化するバインダー樹脂とを配合したもので構成される。この導電性ペーストに含まれる導電性材料については、導電性を有していれば、適宜材料を選択しても良い。また、例えば、母材の主成分をゴムと例示したが、その他の高分子材料でもよい。バインダー樹脂についても、必ずしも樹脂に限定されず、接着性および硬化性を有する素材の混合物であってもよい。 The bump electrode 41 is made of a conductive paste. For example, an organic material is gradually volatilized and cured by leaving it at room temperature with a conductive material mainly composed of carbon on a base material mainly composed of rubber. Or a blend of a binder resin that cures by condensation with moisture in the air. About the electroconductive material contained in this electroconductive paste, as long as it has electroconductivity, you may select a material suitably. For example, the main component of the base material is exemplified as rubber, but other polymer materials may be used. Also about binder resin, it is not necessarily limited to resin, The mixture of the raw material which has adhesiveness and sclerosis | hardenability may be sufficient.
　また、導電性ペーストには、例えば、バインダー樹脂のように常温で放置することにより有機物質が徐々に揮発して硬化する、あるいは空気中の水分と縮合反応して硬化する素材が含まれていることが好ましいが、温度変化（１００℃程度まで）を与えることにより硬化する物質が含まれていてもよい。 In addition, the conductive paste includes, for example, a material such as a binder resin that is cured by allowing the organic substance to volatilize gradually when left at room temperature, or to cure by condensation with moisture in the air. Although it is preferable, the substance which hardens | cures by giving a temperature change (to about 100 degreeC) may be contained.
　対向基板３の対向電極９とアクティブマトリクス基板４の画素電極２５上に形成されたバンプ電極４１とを接合する。これにより、対向基板３とアクティブマトリクス基板４とが貼り合われる。接合は、予め設定された所定の圧力を加えながら、常温放置、あるいは必要に応じて加熱することにより行われる。また、バンプ電極４１以外にも、異方導電性フィルム（ＡＣＦ）を用いて接合（接続）してもよい。 The counter electrode 9 of the counter substrate 3 and the bump electrode 41 formed on the pixel electrode 25 of the active matrix substrate 4 are joined. Thereby, the counter substrate 3 and the active matrix substrate 4 are bonded together. Joining is performed by leaving at room temperature or applying heat as necessary while applying a predetermined pressure set in advance. Further, besides the bump electrode 41, an anisotropic conductive film (ACF) may be used for bonding (connection).
　図１は、１つのＸ線検出素子を示しており、Ｘ線検出素子での検出が１画素に相当する。Ｘ線検出素子ＤＵは、図５に示すように、２次元マトリクス状に配置され、例えば１５００×１５００個程度（２３０×２３０ｍｍ程度）で構成される。Ｘ線検出素子ＤＵは、図示の便宜上３×３個で構成されている。すなわち、コンデンサ１１およびＴＦＴ１２は、マトリクス状に構成された３×３のＸ線検出素子ＤＵ（画素）に個別に設けられている。 FIG. 1 shows one X-ray detection element, and detection by the X-ray detection element corresponds to one pixel. As shown in FIG. 5, the X-ray detection elements DU are arranged in a two-dimensional matrix, and are composed of, for example, about 1500 × 1500 (about 230 × 230 mm). The X-ray detection elements DU are composed of 3 × 3 for convenience of illustration. That is, the capacitor 11 and the TFT 12 are individually provided in a 3 × 3 X-ray detection element DU (pixel) configured in a matrix.
　図５において、ゲート線２１は、行（Ｘ）方向のＸ線検出素子ＤＵで共通に接続するように構成されており、データ線１７は、列（Ｙ）方向のＸ線検出素子ＤＵで共通に接続するように構成されている。また、ゲート線２１は、ゲート駆動部４３と接続しており、データ線１７は、順番に電荷電圧変換アンプ４５、マルチプレクサ４７と接続している。ゲート駆動部４３、電荷電圧変換アンプ４５およびマルチプレクサ４７は、駆動制御部４９で制御されるようになっており、例えば図示しない外部装置からの信号で駆動される。 In FIG. 5, the gate line 21 is configured to be commonly connected by the X-ray detection elements DU in the row (X) direction, and the data line 17 is shared by the X-ray detection elements DU in the column (Y) direction. Configured to connect to. The gate line 21 is connected to the gate drive unit 43, and the data line 17 is connected to the charge voltage conversion amplifier 45 and the multiplexer 47 in order. The gate drive unit 43, the charge voltage conversion amplifier 45, and the multiplexer 47 are controlled by a drive control unit 49, and are driven by a signal from an external device (not shown), for example.
　次に、図１および図５を参照して、ＦＰＤ１の動作を簡単に説明をする。Ｘ線管から被検体に向けてＸ線が照射され（Ｘ線管と被検体は共に図示しない）、被検体を透過したＸ線はＦＰＤ１に入射する。半導体層２にＸ線が入射すると、光導電効果により半導体層２で電荷が生成される。このとき、コンデンサ１１と半導体層２は、正孔注入阻止層８、対向電極９およびバンプ電極４１により直列に接続された構成となっている。そのため、共通電極６にバイアス電圧（Ｖｈ）を印加しておくと、半導体層２内で生成された電荷が移動する。そして、生成された電荷は、対向電極９で収集されてコンデンサ１１に蓄積される。 Next, the operation of the FPD 1 will be briefly described with reference to FIG. 1 and FIG. X-rays are irradiated from the X-ray tube toward the subject (both the X-ray tube and the subject are not shown), and the X-rays that have passed through the subject enter the FPD 1. When X-rays enter the semiconductor layer 2, electric charges are generated in the semiconductor layer 2 due to the photoconductive effect. At this time, the capacitor 11 and the semiconductor layer 2 are connected in series by the hole injection blocking layer 8, the counter electrode 9 and the bump electrode 41. For this reason, when a bias voltage (Vh) is applied to the common electrode 6, charges generated in the semiconductor layer 2 move. The generated charges are collected by the counter electrode 9 and accumulated in the capacitor 11.
　コンデンサ１１に蓄積された電荷は、ＴＦＴ１２により読み出される。ゲート駆動部４３は、例えば図５の上側のゲート線２１から１行ずつ順番に電圧を印加して信号を送信することで、ＴＦＴ１２を接続（ＯＮ）の状態にし、コンデンサ１１に蓄積された電荷をデータ線１７から読み出す。電荷電圧変換アンプ４５は、データ線１７を通じて取り出された電荷を電圧に変換して電圧信号として出力する。マルチプレクサ４７は、複数の電圧信号から１つの電圧信号を選択して出力する。このようにして出力された電圧信号に基づいてＸ線画像が取得される。 The charge accumulated in the capacitor 11 is read out by the TFT 12. For example, the gate drive unit 43 applies a voltage sequentially from the upper gate line 21 of FIG. 5 one by one to transmit a signal, thereby turning the TFT 12 into a connected (ON) state, and the charge accumulated in the capacitor 11. Is read from the data line 17. The charge-voltage conversion amplifier 45 converts the charge taken out through the data line 17 into a voltage and outputs it as a voltage signal. The multiplexer 47 selects and outputs one voltage signal from the plurality of voltage signals. An X-ray image is acquired based on the voltage signal output in this way.
　上述した実施例１に係るＦＰＤ１によれば、ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層２は、入射したＸ線に感応して電荷を生成し、コンデンサ１１は半導体層２で生成された電荷を蓄積する。ＴＦＴ１２はコンデンサ１１に蓄積された電荷を読み出す。コンデンサ１１およびＴＦＴ１２は、マトリクス状に構成された複数の画素に個別に設けられている。そして、コンデンサ１１は、５ｐＦ以上３０ｐＦ以下の容量で構成されている。ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層２によって、Ｘ線の入射で多くの電荷が生成され、また、リーク電流による多くの電荷が発生する。しかしながら、それらの電荷をコンデンサ１１に蓄積することができる。すなわち、高感度の半導体層（変換層）２を採用した場合でも多くの電荷を蓄積することができ、コンデンサ１１の容量がオーバーフローすることを防止することができる。また、コンデンサ１１の容量の大きくするとリセットノイズが大きくなる。しかしながら、リセットノイズよりも比較的に大きなＸ線量子ノイズに対し、リセットノイズを小さくすることで、Ｓ／Ｎ比に与える影響を抑えることができる。 According to the FPD 1 according to Example 1 described above, the CdTe or CdZnTe polycrystalline semiconductor layer 2 generates charges in response to incident X-rays, and the capacitor 11 generates charges generated in the semiconductor layer 2. accumulate. The TFT 12 reads out the electric charge accumulated in the capacitor 11. The capacitor 11 and the TFT 12 are individually provided in a plurality of pixels configured in a matrix. And the capacitor | condenser 11 is comprised by the capacity | capacitance of 5 pF or more and 30 pF or less. By the semiconductor layer 2 of the polycrystalline film of CdTe or CdZnTe, a lot of charges are generated by the incidence of X-rays, and a lot of charges are generated due to a leak current. However, those charges can be stored in the capacitor 11. That is, even when the high-sensitivity semiconductor layer (conversion layer) 2 is employed, a large amount of charges can be accumulated, and the capacitance of the capacitor 11 can be prevented from overflowing. Further, when the capacitance of the capacitor 11 is increased, the reset noise is increased. However, the influence on the S / N ratio can be suppressed by reducing the reset noise relative to the X-ray quantum noise that is relatively larger than the reset noise.
　また、コンデンサ１１は、積層して設けられる互いに電気的に接続された画素電極２５および第１容量電極２７と、画素電極２５と第１容量電極２７との間に設けられる第１グランド層２９と、画素電極２５と第１グランド層２９との間、および第１グランド層２９と第１容量電極２７との間に設けられる絶縁膜３７，３９とを有している。これにより、絶縁膜３７，３９を挟んで対向する容量電極とグランド層との組合せが増えることになり、コンデンサ１１の容量を形成する面積（画素電極２５と第１グランド層２９との間、および第１グランド層２９と第１容量電極２７との間）を増やすことができ、コンデンサ１１の容量を大きくすることができる。そのため、高感度の半導体層２を採用した場合でも多くの電荷を蓄積することができ、コンデンサ１１の容量がオーバーフローすることを防止することができる。 The capacitor 11 includes a pixel electrode 25 and a first capacitor electrode 27 which are provided in a stacked manner and are electrically connected to each other, and a first ground layer 29 provided between the pixel electrode 25 and the first capacitor electrode 27. Insulating films 37 and 39 provided between the pixel electrode 25 and the first ground layer 29 and between the first ground layer 29 and the first capacitor electrode 27. As a result, the number of combinations of the capacitance electrode and the ground layer facing each other with the insulating films 37 and 39 interposed therebetween increases, and the area for forming the capacitance of the capacitor 11 (between the pixel electrode 25 and the first ground layer 29 and (Between the first ground layer 29 and the first capacitance electrode 27) can be increased, and the capacitance of the capacitor 11 can be increased. Therefore, even when the highly sensitive semiconductor layer 2 is employed, a large amount of charges can be accumulated, and the capacity of the capacitor 11 can be prevented from overflowing.
　また、第１グランド層２９および第２グランド層３１は積層して設けられ、第１グランド層２９および第２グランド層３１は互いに電気的に接続されている。第１グランド層２９と第２グランド層３１との間には、第１容量電極２７が設けられている。これにより、画素電極２５および第１容量電極２７と、第１グランド層２９および第２グランド層３１とが交互に配置された積層構造とすることができる。そのため、コンデンサ１１の容量を形成する面積（さらに第１容量電極２７と第２グランド層３１との間）を増やすことができる。 The first ground layer 29 and the second ground layer 31 are provided in a stacked manner, and the first ground layer 29 and the second ground layer 31 are electrically connected to each other. A first capacitance electrode 27 is provided between the first ground layer 29 and the second ground layer 31. Thereby, it can be set as the laminated structure by which the pixel electrode 25 and the 1st capacity | capacitance electrode 27, and the 1st ground layer 29 and the 2nd ground layer 31 are arrange | positioned alternately. Therefore, the area for forming the capacitance of the capacitor 11 (further, between the first capacitance electrode 27 and the second ground layer 31) can be increased.
　また、絶縁膜１５，３７，３９は、Ｔａ２Ｏ５、Ａｌ２Ｏ３、（Ｂａ，Ｓｒ）ＴｉＯ２、ＳｒＴｉＯ３のいずれかで構成されている。絶縁膜１５，３７，３９に、高誘電体材料が用いられることにより、コンデンサ１１の容量を大きくすることができる。 The insulating films 15, 37, and 39 are made of any one of Ta 2 O 5 , Al 2 O 3 , (Ba, Sr) TiO 2 , and SrTiO 3 . By using a high dielectric material for the insulating films 15, 37, and 39, the capacitance of the capacitor 11 can be increased.
　次に、図面を参照して本発明の実施例２を説明する。図６は、実施例２に係るフラットパネル型Ｘ線検出器（ＦＰＤ）の構成を示す縦断面図である。なお、各実施例と重複する部分の説明は省略する。実施例２のコンデンサ６１は、実施例１よりも多く容量電極およびグランド層が積層して形成されている。 Next, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a longitudinal sectional view illustrating the configuration of a flat panel X-ray detector (FPD) according to the second embodiment. In addition, description of the part which overlaps with each Example is abbreviate | omitted. The capacitor 61 of the second embodiment is formed by stacking more capacity electrodes and ground layers than the first embodiment.
　図６を参照する。ＦＰＤ６０のコンデンサ６１は、第２グランド層３１と絶縁基板１３との間に、第２容量電極６３および第３グランド層６５を備えている。第１容量電極２７と第２容量電極６３は、第３スルーホール６７によって、互いに電気的に接続されている。また、第２グランド層３１と第３グランド層６５は、第４スルーホール６９によって、互いに電気的に接続されている。また、第２グランド層３１と第２容量電極６３との間には、絶縁膜７１が設けられ、第２容量電極６３と第３グランド層６５との間には、絶縁膜７３が設けられている。 Refer to FIG. The capacitor 61 of the FPD 60 includes a second capacitor electrode 63 and a third ground layer 65 between the second ground layer 31 and the insulating substrate 13. The first capacitor electrode 27 and the second capacitor electrode 63 are electrically connected to each other through a third through hole 67. The second ground layer 31 and the third ground layer 65 are electrically connected to each other through the fourth through hole 69. An insulating film 71 is provided between the second ground layer 31 and the second capacitor electrode 63, and an insulating film 73 is provided between the second capacitor electrode 63 and the third ground layer 65. Yes.
　すなわち、コンデンサ６１は、実施例１のコンデンサ１１の構成に加え、第２容量電極６３、第３グランド層６５、第３スルーホール６７、第４スルーホール６９および絶縁膜７１，７３を有している。なお、第２容量電極６３は本発明の容量電極に相当し、第３グランド層６５は本発明のグランド層に相当する。絶縁膜７１，７３は本発明の電極間絶縁膜に相当する。 That is, the capacitor 61 includes the second capacitor electrode 63, the third ground layer 65, the third through hole 67, the fourth through hole 69, and the insulating films 71 and 73 in addition to the configuration of the capacitor 11 of the first embodiment. Yes. The second capacitor electrode 63 corresponds to the capacitor electrode of the present invention, and the third ground layer 65 corresponds to the ground layer of the present invention. The insulating films 71 and 73 correspond to the interelectrode insulating film of the present invention.
　画素電極２５、第１容量電極２７、第２容量電極６３、第１スルーホール３３、および第３スルーホール６７は、第１～第３グランド層２９，３１，６５、第２スルーホール３５および第４スルーホール６９と、電気的に接続していない。 The pixel electrode 25, the first capacitor electrode 27, the second capacitor electrode 63, the first through hole 33, and the third through hole 67 are the first to third ground layers 29, 31, 65, the second through hole 35, and the second through hole 35, respectively. The 4-through hole 69 is not electrically connected.
　また、実施例１と同様に、第２容量電極６３、第３グランド層６５、第３スルーホール６７、および第４スルーホール６９は、Ｔａ、Ａｌ、Ｍｏ、Ｔｉ等の金属膜で構成される。これらの金属膜は、蒸着法またはスパッタリング等で形成される。絶縁膜７１，７３は、Ｔａ２Ｏ５、Ａｌ２Ｏ３、ＴｉＯ２、（Ｂａ，Ｓｒ）ＴｉＯ２、およびＳｒＴｉＯ３等のいずれか１つの高誘電体材料で構成される。これらの高誘電体材料は、ＣＶＤ法またはスパッタリング等で形成される。 Similarly to the first embodiment, the second capacitor electrode 63, the third ground layer 65, the third through hole 67, and the fourth through hole 69 are composed of a metal film such as Ta, Al, Mo, and Ti. . These metal films are formed by vapor deposition or sputtering. The insulating films 71 and 73 are made of any one high dielectric material such as Ta 2 O 5 , Al 2 O 3 , TiO 2 , (Ba, Sr) TiO 2 , and SrTiO 3 . These high dielectric materials are formed by CVD or sputtering.
　なお、ＴＦＴ１２は、第１容量電極２７からコンデンサ６１に蓄積された電荷を読み出すように絶縁膜１５，３９の層に形成されている。しかしながら、ＴＦＴ１２は、第２容量電極６３からコンデンサ６１に蓄積された電荷を読み出すように絶縁膜７１，７３の層に形成されてもよい。 The TFT 12 is formed in the layers of the insulating films 15 and 39 so as to read out the electric charge accumulated in the capacitor 61 from the first capacitance electrode 27. However, the TFT 12 may be formed in the layers of the insulating films 71 and 73 so as to read out the electric charge accumulated in the capacitor 61 from the second capacitance electrode 63.
　上述した実施例２に係るＦＰＤ６０によれば、実施例１に対し、コンデンサ６１の容量を形成する面積（さらに第２グランド層３１と第２容量電極６３との間、第２容量電極６３と第３グランド層６５との間）をさらに増やすことができる。そのため、コンデンサ６１の容量を増やすことができる。 According to the FPD 60 according to the second embodiment described above, compared to the first embodiment, the area for forming the capacitance of the capacitor 61 (further, between the second ground layer 31 and the second capacitor electrode 63, the second capacitor electrode 63 and the second capacitor electrode 63 3 ground layers 65) can be further increased. Therefore, the capacity of the capacitor 61 can be increased.
　本発明は、上記実施形態に限られることはなく、下記のように変形実施することができる。 The present invention is not limited to the above embodiment, and can be modified as follows.
　（１）上述した実施例２において、第３グランド層６５と絶縁基板１３との間に、第２容量電極６３とスルーホールにより電気的に接続された容量電極と、第３グランド層６５とスルーホールにより電気的に接続されたグランド層と、容量電極とグランド層との間に設けられた絶縁膜とを設けてもよい。これにより、さらに容量電極とグランド層とを多くすることができ、コンデンサの容量を増やすことができる。 (1) In the above-described second embodiment, the capacitor electrode electrically connected to the second capacitor electrode 63 through the through hole between the third ground layer 65 and the insulating substrate 13, and the third ground layer 65 and the through-hole. A ground layer electrically connected by a hole and an insulating film provided between the capacitor electrode and the ground layer may be provided. Thereby, the capacity electrode and the ground layer can be further increased, and the capacity of the capacitor can be increased.
　（２）上述した各実施例および変形例（１）において、コンデンサ１１（６１）は、容量電極とグランド層とが同数の層で構成されている。しかしながら、例えば、図７に示すように、コンデンサ８１は、容量電極として、画素電極２５、第１容量電極２７および第２容量電極６３の３層と、グランド層として、第１グランド層２９および第２グランド層３１の２層とを有するようにしてもよい。 (2) In each of the above-described embodiments and modification (1), the capacitor 11 (61) is composed of the same number of layers as the capacitance electrode and the ground layer. However, for example, as shown in FIG. 7, the capacitor 81 includes three layers of the pixel electrode 25, the first capacitor electrode 27, and the second capacitor electrode 63 as the capacitor electrodes, and the first ground layer 29 and the first layers as the ground layers. Two layers of two ground layers 31 may be provided.
　（３）上述した各実施例および各変形例において、図８に示すように、コンデンサ８３は、図６のコンデンサ６１における画素電極２５、第１グランド層２９、第１スルーホール３３、第２スルーホール３５、および絶縁膜３７，３９を省略する構成としてもよい。この場合、第１容量電極２７が画素電極２５として機能する。 (3) In each of the above-described embodiments and modifications, as shown in FIG. 8, the capacitor 83 includes the pixel electrode 25, the first ground layer 29, the first through hole 33, and the second through hole in the capacitor 61 of FIG. The hole 35 and the insulating films 37 and 39 may be omitted. In this case, the first capacitor electrode 27 functions as the pixel electrode 25.
　（４）上述した各実施例および各変形例において、半導体層２は、ＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜で構成されるが、これに限定されない。半導体層２は、例えばａ－Ｓｅと比較して高感度な材料であれば適応可能である。 (4) In each example and each modification described above, the semiconductor layer 2 is composed of a polycrystalline film of CdTe or CdZnTe, but is not limited thereto. The semiconductor layer 2 can be applied as long as it is a highly sensitive material as compared with, for example, a-Se.
　（５）上述した各実施例および各変形例において、入射したＸ線に感応して直接電荷を生成する半導体層２を変換層として採用している。しかしながら、変換層は、Ｘ線を光に変換するＣｓＩ（ヨウ化セシウム）等の蛍光体層と、光を電荷に変換する光電変換素子（フォトダイオード）と、を備えるものでもよい。 (5) In each of the above-described embodiments and modifications, the semiconductor layer 2 that directly generates charges in response to incident X-rays is employed as the conversion layer. However, the conversion layer may include a phosphor layer such as CsI (cesium iodide) that converts X-rays into light, and a photoelectric conversion element (photodiode) that converts light into charges.
　（６）上述した各実施例および各変形例において、図５に示すように、ＦＰＤ１（６０）は、Ｘ線検出素子ＤＵ（画素）を２次元マトリクス（アレイ）状に配置し、２次元のＸ線画像を取得するように構成される。しかしながら、１次元のＸ線画像を取得するように構成してもよい。 (6) In each of the above-described embodiments and modifications, as shown in FIG. 5, the FPD 1 (60) arranges the X-ray detection elements DU (pixels) in a two-dimensional matrix (array) form. It is configured to acquire an X-ray image. However, it may be configured to acquire a one-dimensional X-ray image.
　（７）上述した各実施例および各変形例において、コンデンサ１１に代えて、図９のコンデンサ１１１を用いてもよい。この場合、容量電極１２７とグランド層１３１との間に設けられた絶縁層（電極間絶縁膜）１１５は、Ｔａ２Ｏ５、Ａｌ２Ｏ３、ＴｉＯ２、（Ｂａ，Ｓｒ）ＴｉＯ２、およびＳｒＴｉＯ３等のいずれか１つの高誘電体材料で構成される。 (7) In each embodiment and each modification described above, the capacitor 111 in FIG. 9 may be used instead of the capacitor 11. In this case, the insulating layer (interelectrode insulating film) 115 provided between the capacitor electrode 127 and the ground layer 131 includes Ta 2 O 5 , Al 2 O 3 , TiO 2 , (Ba, Sr) TiO 2 , and It is made of any one high dielectric material such as SrTiO 3 .
　１，６０　…　フラットパネル型Ｘ線検出器（ＦＰＤ）
　２　　…　半導体層
　１１，６１，８１，８３　…　コンデンサ
　１２　…　薄膜トランジスタ（ＴＦＴ）
　１５，２３，３７，３９，７１，７３　…　絶縁膜
　２５　…　画素電極
　２７　…　第１容量電極
　２９　…　第１グランド層
　３１　…　第２グランド層
　３３　…　第１スルーホール
　３５　…　第２スルーホール
　６３　…　第２容量電極
　６５　…　第３グランド層
　６７　…　第３スルーホール
　６９　…　第４スルーホール 1,60 ... Flat panel X-ray detector (FPD)
2 ... Semiconductor layer 11, 61, 81, 83 ... Capacitor 12 ... Thin film transistor (TFT)
15, 23, 37, 39, 71, 73 ... Insulating film 25 ... Pixel electrode 27 ... First capacitor electrode 29 ... First ground layer 31 ... Second ground layer 33 ... First through hole 35 ... Second through hole 63 ... Second capacitance electrode 65 ... Third ground layer 67 ... Third through hole 69 ... Fourth through hole

Claims (4)

  1. 　入射した放射線に感応して電荷を生成するＣｄＴｅまたはＣｄＺｎＴｅの多結晶膜の半導体層と、
    　マトリクス状に構成された複数の画素に個別に設けられる前記半導体層で生成された電荷を蓄積するコンデンサと、
    　マトリクス状に構成された複数の画素に個別に設けられる前記コンデンサに蓄積された電荷を読み出すスイッチング素子と、を備え、
    　前記コンデンサは、５ｐＦ以上３０ｐＦ以下の容量で構成されることを特徴とする放射線検出器。     A CdTe or CdZnTe polycrystalline semiconductor layer that generates charge in response to incident radiation;
    A capacitor for accumulating charges generated in the semiconductor layer individually provided in a plurality of pixels configured in a matrix;
    A switching element that reads out the electric charge accumulated in the capacitor individually provided in a plurality of pixels configured in a matrix, and
    The radiation detector is configured with a capacitance of 5 pF to 30 pF.
  2. 　請求項１に記載の放射線検出器において、
    　前記コンデンサは、積層して設けられる互いに電気的に接続された複数の容量電極と、前記複数の容量電極の間に設けられるグランド層と、前記容量電極と前記グランド層との間に設けられる電極間絶縁膜とを有することを特徴とする放射線検出器。     The radiation detector according to claim 1.
    The capacitor includes a plurality of capacitor electrodes electrically connected to each other, a ground layer provided between the capacitor electrodes, and an electrode provided between the capacitor electrode and the ground layer. A radiation detector comprising an inter-layer insulating film.
  3. 　請求項２に記載の放射線検出器において、
    　前記グランド層は、複数のグランド層が積層して設けられ、
    　前記複数のグランド層は、互いに電気的に接続され、
    　前記複数のグランド層の間には、前記複数の容量電極のいずれか１つが設けられることを特徴とする放射線検出器。     The radiation detector according to claim 2, wherein
    The ground layer is provided by laminating a plurality of ground layers,
    The plurality of ground layers are electrically connected to each other;
    One of the plurality of capacitive electrodes is provided between the plurality of ground layers.
  4. 　請求項１から３のいずれかに記載の放射線検出器において、
    　前記コンデンサの電極間絶縁膜は、Ｔａ２Ｏ５、Ａｌ２Ｏ３、（Ｂａ，Ｓｒ）ＴｉＯ２、ＳｒＴｉＯ３のいずれかで構成されることを特徴とする放射線検出器。     The radiation detector according to any one of claims 1 to 3,
    The radiation detector is characterized in that the inter-electrode insulating film of the capacitor is composed of any one of Ta 2 O 5 , Al 2 O 3 , (Ba, Sr) TiO 2 , and SrTiO 3 .
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2858113A1 (en) * 2013-10-02 2015-04-08 Rayence Co., Ltd. X-ray sensor and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04255269A (en) * 1991-02-07 1992-09-10 Hitachi Ltd Photodetective device
JPH1187679A (en) * 1997-09-01 1999-03-30 Nec Corp Solid state image sensor with on-chip source follower amplifier
JP2001345440A (en) * 2000-03-31 2001-12-14 Canon Inc Electro-magnetic wave detection device
JP2004209117A (en) * 2003-01-08 2004-07-29 Hitachi Medical Corp Radiation detecting instrument, and its production method
JP2007170908A (en) * 2005-12-20 2007-07-05 Shimadzu Corp Radiation detector and imaging device using the same
JP2010219339A (en) * 2009-03-17 2010-09-30 Sony Corp Solid-state imaging device, method of manufacturing solid-state imaging device, method of driving solid-state imaging device, and electronic apparatus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308365A (en) * 1987-06-10 1988-12-15 Toshiba Corp Manufacture of capacitor in integrated circuit
JP2696860B2 (en) * 1987-11-11 1998-01-14 株式会社日立製作所 Radiation detection element
JP2686263B2 (en) * 1987-11-19 1997-12-08 株式会社日立製作所 Radiation detection element
JP2006345330A (en) * 2005-06-10 2006-12-21 Hitachi Medical Corp Imaging apparatus
JP4352057B2 (en) * 2006-02-13 2009-10-28 キヤノン株式会社 Imaging device
JP2008243931A (en) * 2007-03-26 2008-10-09 Taiyo Yuden Co Ltd Manufacturing method for laminated type thin-film capacitor and laminated type thin-film capacitor
JP2010182764A (en) * 2009-02-04 2010-08-19 Sony Corp Semiconductor element, method of manufacturing the same, and electronic apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04255269A (en) * 1991-02-07 1992-09-10 Hitachi Ltd Photodetective device
JPH1187679A (en) * 1997-09-01 1999-03-30 Nec Corp Solid state image sensor with on-chip source follower amplifier
JP2001345440A (en) * 2000-03-31 2001-12-14 Canon Inc Electro-magnetic wave detection device
JP2004209117A (en) * 2003-01-08 2004-07-29 Hitachi Medical Corp Radiation detecting instrument, and its production method
JP2007170908A (en) * 2005-12-20 2007-07-05 Shimadzu Corp Radiation detector and imaging device using the same
JP2010219339A (en) * 2009-03-17 2010-09-30 Sony Corp Solid-state imaging device, method of manufacturing solid-state imaging device, method of driving solid-state imaging device, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2858113A1 (en) * 2013-10-02 2015-04-08 Rayence Co., Ltd. X-ray sensor and method of manufacturing the same
US10163969B2 (en) 2013-10-02 2018-12-25 Rayence Co., Ltd. X-ray sensor and method of manufacturing the same

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