WO2013061183A1 - Boîtier électriquement isolant pour composants à semi-conducteur ou modules en technique de moulage et procédé de fabrication - Google Patents

Boîtier électriquement isolant pour composants à semi-conducteur ou modules en technique de moulage et procédé de fabrication Download PDF

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Publication number
WO2013061183A1
WO2013061183A1 PCT/IB2012/055168 IB2012055168W WO2013061183A1 WO 2013061183 A1 WO2013061183 A1 WO 2013061183A1 IB 2012055168 W IB2012055168 W IB 2012055168W WO 2013061183 A1 WO2013061183 A1 WO 2013061183A1
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WO
WIPO (PCT)
Prior art keywords
materials
layer
tool
circuit carrier
transfer molding
Prior art date
Application number
PCT/IB2012/055168
Other languages
German (de)
English (en)
Inventor
Rupprecht Gabriel
Original Assignee
Rupprecht Gabriel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rupprecht Gabriel filed Critical Rupprecht Gabriel
Priority to DE112012004032.5T priority Critical patent/DE112012004032A5/de
Publication of WO2013061183A1 publication Critical patent/WO2013061183A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Definitions

  • the invention relates to a method according to claim 10 and an assembly according to claim 1 is claimed (thermoactive assembly), as a product by process claim.
  • IPMs Integrated Power Modules
  • the principle is applicable and advantageous for all requirements in which electrical insulation as well as good heat conduction are required.
  • Transfermolding also called RTM (Resin Transfer Molding)
  • RTM Resin Transfer Molding
  • a tool chamber is filled from a reservoir with initially solid or liquid molding compound under pressure and heat via injection channels as a liquid mass.
  • the molding compound is cured with heat.
  • the transfermolding is known and includes many
  • Chip size package housing for miniaturized semiconductors Today, both small and large semiconductors are manufactured in RTM housings, also referred to as plastic housings. While thermoplastic housings have become increasingly popular in many other applications, the RTM process has remained the state of the art in the semiconductor industry.
  • thermoplastic spraying The advantage of transfer molding compared to thermoplastic spraying is the low viscosity of the molding compositions during injection compared with non-reactive thermoplastic spraying processes. In contrast, so far with significantly higher
  • the molding compositions consist of a thermosetting reactive curing material which z. B. epoxy.
  • silicone or compound materials are also used as molding compounds, especially in LEDs. The material is often filled to the
  • thermosets have very good insulation properties, but only very limited thermal conductivities. Typical for optimized materials are thermal conductivities of 2W / mK achieved. Comparing this with aluminum and copper, the difference is immediately noticeable (thermal conductivity of copper is about 300W / mK).
  • insulators also have good thermal conductivities. Examples are aluminum oxide, aluminum nitride and especially diamond (2300W / mK). The very good properties have also stimulated many researches in the field of carbon nanoparticles.
  • the degree of filling of such masses can be increased to> 90% and the resin content (binder) are kept low.
  • Transfermoldings are the very good flow properties of the potting compounds, which is why electronic components can not yet be wrapped thermoplastic.
  • the rheology in the transfermolding achieves flow properties of the molding compounds which are in part better (lighter) than water. This ensures that the thin bonding wires are not torn and deformed when injecting the molding compound into the tool contained in the assembly and the circuit board (leadframe) do not bend much.
  • thermally highly conductive materials with a very high degree of filling of the conductive particles and the relatively large particle size of up to 300 ⁇ only with very poor flow properties (ie pasty or as a powder with a powdery in the initial state proportion of binder) can be produced. These materials can not be injected after heating and liquefaction like the usual materials.
  • the entire circuit carrier is often placed on an insulating and thermally highly conductive material. This substrate can then be in
  • the thermally conductive insulating material is z. B. as DCB (direct copper bonding) method by applying
  • Copper interconnects made on ceramic materials (eg, alumina). there the electrical conductor is connected in a thermal process with a thermally highly conductive ceramic in a sintering process, see. Michael Pecht, Handbook of Electronic Package Design, CRC Press, 1991. That is, the circuit carrier is no longer shrouded but the insulating side forms the outside of the housing.
  • ceramic materials eg, alumina
  • Substrates disseminated from the printed circuit board technology. These are created on a metal core by casting and screen printing technique with a highly filled mass. In both
  • IPM modules are manufactured by various manufacturers, and represent the known prior art.
  • the object of the claimed invention (s) is to reduce the number of process steps and to reduce the required use of materials.
  • Circuit carrier in a transfer molding process the process is extended so that a similar result is achieved cheaper and more reliable process (claim 1, 10).
  • the circuit carrier with the at least one component is preferably one
  • metallic leadframe (claim 8), as it is used today in almost all IC packages.
  • the leadframe has - since made of metal - a high thermal conductivity and is placed directly on the formed by screen printing or press-fitting first layer and adhesively bonded to this in the molding process.
  • the joint curing in a molding process under pressure and heat results in particularly good thermal conduction properties, which are in no way inferior to those of previously used techniques with injected ceramic substrates or IMS substrates, but cheaper and cheaper can be produced more reliable.
  • the second material forming the top layer may be transparent (claim 7, claim 17).
  • Possible materials for the first material are aluminum oxide powder or Keramit, AINi or diamonds.
  • the second material can come from the known transfer molding, z.
  • FIG. 1 shows an opening of a tool with upper tool half 5
  • thermally conductive compound 1 in viscous or viscous powder form by screen printing or dispensing and pressing shows the case of the screen printing method; Doctor blade 8 with a movement 8a in the arrow direction distributes the pasty or powdery material 1 with binder in the cavity 4a of the lower mold half 4 with a defined
  • Layer thickness d (outlined here in the screen printing process), where it forms a layer la with a defined layer thickness d by the screen printing process.
  • Figure 2a illustrates Fig. 2 from above with the doctor blade 8 in his
  • FIG. 3 shows the insertion of an assembly on a circuit carrier 6 (eg as
  • Figure 4 is a closing of the tool and injecting a low viscosity
  • Figure 5 is an opening of the tool 4,5 for removing the cured
  • Figures 6 illustrate the flow of Figure 2 in an upstream
  • FIGS. 7 illustrate the process with a stamp 13.
  • FIG. 8 illustrates an additional functional part 12.
  • the additional process step according to FIG. 2 allows thermally highly conductive masses, which preferably have the same chemical base for the reactive curing adhesive (resin) but can not be injected, with the proven method of FIG.
  • Another advantage is the easily controllable layer thickness d of the thermally conductive material 1 as layer la.
  • very low defined layer thicknesses 'd' can be achieved by screen printing or the defined dispensing and pressing.
  • the mass 1 in the introduced state la forms a buffer against the flow forces of the molding compound 2 and stabilizes the assembly against bending.
  • layer thicknesses of 0.1mm to 0.3mm or up to 500 ⁇ can be achieved to ensure sufficient electrical insulation.
  • controllable layer thickness d is possible.
  • process step 2 filling the lower cavity 4a of the tool 4 with thermally conductive compound
  • a "preform” eg of PTFE
  • circuit carrier lead frame with soldered semiconductors
  • the process is very advantageous in industrialization, since the molding machines are either additionally equipped with a small screen printing device (doctor blade 8 and a mask as in SMD soldering process), cf. Fig. 2, or the process step in an upstream machine in a z. B. deep-drawn shape can be done, see. Fig. 6.
  • a small screen printing device doctor blade 8 and a mask as in SMD soldering process
  • cf. Fig. 2 or the process step in an upstream machine in a z. B. deep-drawn shape can be done, see. Fig. 6.
  • the good thermally conductive and highly viscous mass 1 is introduced by screen printing in a recessed sheet 10 in a tool 4 as a layer la.
  • the mold is cured under pressure and heat in one process step.
  • the film carrier 10 also serves as a release agent to almost completely avoid tool wear. After hardening of the layers 2a, la, the leadframes are then punched out and the carrier foil 10 is peeled off.
  • the parting plane T of the mold 4.5 is shown, also with respect to the
  • Auxiliary level 10 ' The film 10 is inserted into the cavity 4a of the lower mold half 4 as a "recessed film". On the recessed in the cavity 4a film 10 is the first
  • Dispens and a mold (punch) are installed, which introduces the thermally conductive mass 1 in the tool-half 4.
  • the thermally conductive powder or the paste 1 is first pressed with a resin as a binder in a filled out by a film 10 form with the sketched on the left in Fig. 7 pressing tool 13.
  • the circuit carrier 6 is placed and both introduced together into the mold 4.5 and cured together under injection of the low-viscosity mass 2 under pressure and heat.
  • the pre ssvon (according to FIG. 7) is used, as well as viscous pasty masses with a liquid binder and powdery masses can be used.
  • the advantage of powdery materials is the high
  • the illustrated leadframe 6 as a circuit carrier can also be continuous or extend in size and extent beyond the dimension of the lower layer 1a.
  • the outer edge is then die-cut during the molding process or thereafter.
  • Components 7, 7 a which are applied to the one or more part carrier 6, are fastened to the circuit carrier by soldering or gluing.
  • One option is chip-on-chip mounting where the controls are mounted on the power semiconductor.
  • Part of the implementation examples is the introduction of one or more poorly flowing - so pasty or powdery - materials using a different method than in the molding process (RTM) is used.
  • RTM molding process
  • the injection of the mass 2 takes place in a liquid, low-viscous state.
  • Advantageous methods for introducing the first mass 1 are screen printing and pressing. This results in a hybrid process with two different methods for

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé de moulage par transfert, dans lequel deux matériaux (1, 2) différemment thermoconducteurs sont reliés au moyen de liants réactifs, le premier matériau (1) ne pouvant être injecté et, avant le processus de moulage par transfert, la couche ne pouvant être injectée étant introduite par sérigraphie ou injection dans un moule (4) avec une proportion de matière granuleuse thermiquement conductrice. Ensuite, le boîtier et le module électronique (6) sont remplis ensemble sous pression par moulage par transfert, et les deux matériaux (1, 2) sont durcis simultanément de manière réactive. Des boîtiers électriquement isolants et présentant une bonne conductivité thermique pour des modules de puissance et des modules à DEL de puissance, par exemple intégrés, sont ainsi possibles.
PCT/IB2012/055168 2011-09-27 2012-09-27 Boîtier électriquement isolant pour composants à semi-conducteur ou modules en technique de moulage et procédé de fabrication WO2013061183A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112012004032.5T DE112012004032A5 (de) 2011-09-27 2012-09-27 Elektrisch isolierendes Harz-Gehäuse für Halbleiterbauelemente oder Baugruppen und Herstellungsverfahren mit einem Mold-Prozess

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011053997.2 2011-09-27
DE102011053997 2011-09-27

Publications (1)

Publication Number Publication Date
WO2013061183A1 true WO2013061183A1 (fr) 2013-05-02

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Country Link
DE (1) DE112012004032A5 (fr)
WO (1) WO2013061183A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014111930A1 (de) 2014-08-20 2016-02-25 Rupprecht Gabriel Thermisch gut leitendes, elektrisch isolierendes Gehäuse mit elektronischen Bauelementen und Herstellverfahren
CN105990297A (zh) * 2015-01-28 2016-10-05 苏州普福斯信息科技有限公司 不对等模腔配合无下沉导线框的结构
CN107768362A (zh) * 2013-03-28 2018-03-06 东芝北斗电子株式会社 发光装置及其制造方法
CN113113315A (zh) * 2020-01-13 2021-07-13 珠海零边界集成电路有限公司 一种防止智能功率模块溢胶的方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825643A (en) * 1970-05-20 1974-07-23 Dowty Seals Ltd Production of shaped articles
JPS58138039A (ja) * 1982-02-10 1983-08-16 Nec Home Electronics Ltd 樹脂封止型半導体装置の製造方法
DE10024415A1 (de) * 2000-05-19 2001-11-22 Erich Schuermann Befüllvorrichtung
DE10213296A1 (de) * 2002-03-25 2003-10-23 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip
US20040089928A1 (en) * 2002-11-11 2004-05-13 Mitsubishi Denki Kabushiki Kaisha Mold resin-sealed power semiconductor device having insulating resin layer fixed on bottom surface of heat sink and metal layer on the resin layer
JP2007165426A (ja) 2005-12-12 2007-06-28 Mitsubishi Electric Corp 半導体装置
JP2010067851A (ja) * 2008-09-11 2010-03-25 Sanyo Electric Co Ltd 回路装置の製造方法
US20100197830A1 (en) * 2007-07-19 2010-08-05 Sekisui Chemical Co., Ltd. Adhesive for electronic component
US20100226095A1 (en) * 2007-09-26 2010-09-09 Mitsubishi Electric Corporation Heat conductive sheet and power module

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825643A (en) * 1970-05-20 1974-07-23 Dowty Seals Ltd Production of shaped articles
JPS58138039A (ja) * 1982-02-10 1983-08-16 Nec Home Electronics Ltd 樹脂封止型半導体装置の製造方法
DE10024415A1 (de) * 2000-05-19 2001-11-22 Erich Schuermann Befüllvorrichtung
DE10213296A1 (de) * 2002-03-25 2003-10-23 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip
US20040089928A1 (en) * 2002-11-11 2004-05-13 Mitsubishi Denki Kabushiki Kaisha Mold resin-sealed power semiconductor device having insulating resin layer fixed on bottom surface of heat sink and metal layer on the resin layer
JP2007165426A (ja) 2005-12-12 2007-06-28 Mitsubishi Electric Corp 半導体装置
US20100197830A1 (en) * 2007-07-19 2010-08-05 Sekisui Chemical Co., Ltd. Adhesive for electronic component
US20100226095A1 (en) * 2007-09-26 2010-09-09 Mitsubishi Electric Corporation Heat conductive sheet and power module
JP2010067851A (ja) * 2008-09-11 2010-03-25 Sanyo Electric Co Ltd 回路装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MICHAEL PECHT: "Handbook of Electronic Package Design", 1991, CRC PRESS

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768362A (zh) * 2013-03-28 2018-03-06 东芝北斗电子株式会社 发光装置及其制造方法
CN107768362B (zh) * 2013-03-28 2020-09-08 东芝北斗电子株式会社 发光装置及其制造方法
DE102014111930A1 (de) 2014-08-20 2016-02-25 Rupprecht Gabriel Thermisch gut leitendes, elektrisch isolierendes Gehäuse mit elektronischen Bauelementen und Herstellverfahren
CN105990297A (zh) * 2015-01-28 2016-10-05 苏州普福斯信息科技有限公司 不对等模腔配合无下沉导线框的结构
CN113113315A (zh) * 2020-01-13 2021-07-13 珠海零边界集成电路有限公司 一种防止智能功率模块溢胶的方法

Also Published As

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