WO2013040751A1 - Method for forming air gap interconnect structure - Google Patents

Method for forming air gap interconnect structure Download PDF

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Publication number
WO2013040751A1
WO2013040751A1 PCT/CN2011/079859 CN2011079859W WO2013040751A1 WO 2013040751 A1 WO2013040751 A1 WO 2013040751A1 CN 2011079859 W CN2011079859 W CN 2011079859W WO 2013040751 A1 WO2013040751 A1 WO 2013040751A1
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Prior art keywords
layer
dielectric layer
dielectric
copper
air gap
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PCT/CN2011/079859
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French (fr)
Inventor
Hui Wang
Jian Wang
Yinuo JIN
Zhaowei Jia
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ACM Research Shanghai Inc
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ACM Research Shanghai Inc
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Priority to KR1020147010406A priority Critical patent/KR101842903B1/en
Priority to PCT/CN2011/079859 priority patent/WO2013040751A1/en
Publication of WO2013040751A1 publication Critical patent/WO2013040751A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6924—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG

Definitions

  • the present invention relates to semiconductor manufacture. More specifically, the present invention relates to improvements to an air gap interconnect structure for applications in 65nm or smaller technology.
  • VLSI and ULSI typically have complex multilevel structures, tiny line width and line space which contain patterns of metal wiring layer and dielectric material to insulate the metal wire.
  • the performance of VLSI and ULSI are limited by the interconnect capacitance, especially in ultra tiny feature size integrated circuit.
  • the value of time constant is equal to the product of the circuit resistance and the circuit capacitance (RC)
  • the power consumption is equal to the product of the capacitance, square of the voltage and the frequency (CV 2 /). Therefore the resistance and capacitance determine the performance of the semiconductor devices.
  • Cu copper
  • Al aluminum
  • SiLK aromatics hydrocarbon thermosetting polymer
  • air gap interconnection structure is developed.
  • the permittivity of air is equal to 1, which is much lower than traditional dielectric material (Si0 2 ) at approximately 3.9, if air is formed between copper lines, the dielectric constant of the dielectric layer will be decreased significantly.
  • the air gap process can provide a relative low-k dielectric constant, the air gap combined with dielectric material can be consider as a porous material with permittivity depending on the volume of the air gap.
  • SFP stress-free-polishing
  • an improved damascene technique integrated with SFP technique uses copper as a main conductor layer and solves the following problems: [0008] 1) No hard mask is used.
  • the hard mask in order to protect the sacrificial polymer layer, commonly a hard mask is formed above the sacrificial polymer layer, the hard mask has a higher mechanical strength to resist the stress during the CMP process.
  • the method according to the present invention utilizes SFP instead of CMP to ! 3 ⁇ 4if ⁇
  • the method of the present invention simplifies the whole process and reduces the cost by removing the processes of the hard mask.
  • the air gaps can not be formed in narrow line space areas or only smaller air gaps can be formed in these areas. That is the reason why air gap interconnect structure is not applied to narrow interconnect structures, such as first metal layer (Ml layer) structures, even the permittivity has the most significant impact in this layer.
  • the method of the present invention may also remove the reserved dielectric materials since no stress will be applied by the SFP process. Therefore, the air gaps can be formed in narrow line spaces, such as the spaces having a scale less than 65nm.
  • a relatively larger air gap may be formed in the spaces between copper lines and the shape of the air gap is optimized.
  • the permittivity of dielectric will be significantly reduced, and the RC delay and the power consumption will be further reduced.
  • the tiny node VLSI and ULSI dissipation problem will be solved.
  • a method for forming air gap interconnect structure is provided.
  • Trench and via are selectively etched in an insulating structure composed by sacrificial material.
  • Conductive structures are formed in the trench and via, the conductive structures are separated by sacrificial material.
  • a scale of the conductive structures is lower than 65nm.
  • the conductive structures are plated by copper and the copper is polished by both Chemical Mechanical Polishing (CMP) and Stress-Free ElectroPolishing (SFP) in sequence.
  • CMP Chemical Mechanical Polishing
  • SFP Stress-Free ElectroPolishing
  • Dielectric material is non-conformally deposited over the conductive structure and in the recesses by Chemical vapor deposition (CVD) so as to form air gaps within the dielectric material in the recesses. No hard mask is deposited during the formation of the conductive structures.
  • CVD Chemical vapor deposition
  • a copper sealing layer is non-conformally deposited on the conductive structure after removing the sacrificial material and prior to non-conformally depositing dielectric material.
  • a sacrificial removal stop layer is formed on the substrate prior to forming conductive structure on the substrate.
  • FIG. 1 is a diagram illustrating the relation between copper line width and its mechanical strength.
  • FIG. 2 is a cross-sectional view of the initial structure of the substrate according to the method for forming an air gap interconnect structure of the present invention.
  • FIG. 3 is a cross-sectional view of the structure of the substrate after a pattern process according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 4 is a cross-sectional view of the structure of the substrate after recesses are formed according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 5 is a cross-sectional view of the structure of the substrate after a barrier layer and a main conductive copper layer is deposited according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 6 is a cross-sectional view of the structure of the substrate after the main conductive copper layer is smoothed by CMP according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 7 is a cross-sectional view of the structure of the substrate after the main conductive copper layer is polished by SFP according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 8 is a cross-sectional view of the structure of the substrate after etching the barrier layer according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 9 is a cross-sectional view of the structure of the substrate after removing the insulating film according to the method for forming air gap interconnect structure of the present invention.
  • FIG. 10 is a cross-sectional view of the structure of the air gap interconnect structure formed according to the method for forming air gap interconnect structure of the present invention.
  • a first dielectric layer 302 is deposited on substrate 301.
  • the first dielectric layer 302 may be one of SiCN, SiC, SiN and SiOC or their combination.
  • a second dielectric layer (sacrificial layer) 303 is deposited on the first dielectric layer 302.
  • the second dielectric layer 303 may be a low-k material or insulating film like an organic film such as a SiLK film.
  • a reflection preventive film 304 and a photo-resist film 305 is sequentially deposited on the second dielectric layer 303.
  • the photo-resist film 305 is patterned by exposure to form a photo-resist pattern 405 as shown in FIG. 3.
  • the reflection preventive film 304 is selectively removed by dry etching using the photo-resist pattern 405 as an etching mask and forms a patterned reflection preventive film 404.
  • the second dielectric layer 503 is selectively removed to form trenches by dry etching using the photo-resist pattern 405 as an etching mask. Thereafter, the photo-resist pattern 405 and the patterned reflection preventive film 404 are removed. Refer to FIG. 4, trenches 506 are formed within the second dielectric layer 503. [0026] A barrier layer of TaN/Ta 606a is deposited on entire main surface of substrate 301 by using sputtering. Then, the metal layer of copper 606b is deposited on the barrier layer of TaN/Ta 606a by using sputtering and plating in sequence. FIG. 5 shows the structure after the depositions of the barrier layer of TaN/Ta 606a and the metal layer of copper 606b.
  • the metal layer of copper 606b is polished to 100nm ⁇ 200nm of remaining copper film thickness by CMP for smoothing the surface topography, as shown in FIG 6.
  • the remaining copper film is numbered as 706b.
  • FIG.7 illustrates the structure after a stress-free electropolihsing (SFP) process.
  • the copper film 806b is polished back to the surface of non-recessed areas, such that metal layer within the recessed regions, i.e., the trenches and/or vias, is isolated from adjacent recessed regions.
  • SFP is a chemical-electrical process: the copper on the wafer substrate works as an anode and an electrolyte nozzle works as a cathode. The copper is dissolved and polished by contacted electrolyte when positive voltage is applied between the anode and the cathode.
  • SFP is a stress free and selective copper removal process.
  • WO2010/020092 discloses a detailed process of SFP.
  • the barrier layer of Ta/TaN 906a on the top surface of wafer is removed by XeF 2 gas phase etching.
  • the XeF 2 reacts spontaneously with Ta/TaN at a certain temperature and pressure.
  • XeF 2 is an isotropic selective etching method of Ta/TaN (the barrier layer of Ta/TaN 606a).
  • the XeF 2 gas has good selectivity to both copper 806b and the second dielectric layer 503, which is formed by dielectric materials such as Si0 2 , SiLK, or low k Si- C-O-H based materials.
  • the value k of the low k Si-C-O-H based materials varies from 1.2 to 4.2 and 1.3-2.4 is preferred.
  • the temperature of the substrate varies from 0°C to 300°C and 25°C ⁇ 200°C is preferred.
  • the pressure of XeF 2 gas during the process is between O. lTorr and 100 Torr and 0.5 Torr ⁇ 20 Torr is preferred.
  • FIG. 8 shows the above process.
  • the chemical reaction products of XeF 2 and Ta/TaN are in gas phase, such as Xe or volatiles with the processing pressure.
  • An example of the volatiles is tantalum fluoride.
  • the trenches 906 in the semiconductor device is electrically separated completely.
  • the copper layer or copper film 806b and the remaining barrier layer (of Ta/TaN) 906a are completely separated by the low k dielectric layer 503 (formed from the second dielectric layer 303).
  • the low k dielectric layer 503 (formed from the second dielectric layer 303) is removed by using reducing gas NH 3 , or H 2 /N 2 to form trench 1007, and first dielectric layer 302 serves as an etching stopper. The depth for removal becomes uniform. At the same time, the copper layer or copper film 806b and remaining barrier layer of TaN/Ta 906a does not get any damage.
  • the FIG. 9 shows the above process.
  • a third dielectric layer 1008 is deposited on entire surface of substrate, and serves as a sealing dielectric in FIG. 9.
  • the third dielectric layer 1008 maybe one of SiCN, SiC, SiN and SiOC or their combination.
  • a fourth dielectric layer 1109 is deposited on the third dielectric layer of SiCN 1008 by using non-conformally plasma enhance chemical vapor deposition (PECVD) or thermal chemical vapor deposition (TCVD). Tetraethyl Orthosillicate (TEOS) and Ozone (0 3 ) are applied in TCVD. Air gap structure are formed by TCVD with temperature from 300°C and 450°C, with best temperature 400°C. Air gaps 1110 are formed in trenches 1007. The trenches 1007 shall have a space between lOnm to 250nm.
  • the fourth dielectric layer 1109 may be one of SiOF, SiOC, Black Diamond (BD) and Black Diamond II (BDII) or their combination.

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Abstract

Embodiments of the present invention provide a method for forming air gap interconnect structure. A first step of the method is to form conductive structures on a substrate, the conductive structures are separated by sacrificial material. A scale of the conductive structures is lower than 65nm and the conductive structures are polished by both Chemical Mechanical Polishing (CMP) and Stress-Free ElectroPolishing (SFP). A second step of this method is to remove the sacrificial material to form recesses between the conductive structures. And a third step of this method is to non-conformally deposit dielectric material over the conductive structure and in the recesses, so as to form air gaps within the dielectric material in the recesses. No hard mask is deposited during the formation of the conductive structures.

Description

METHOD FOR FORMING AIR GAP INTERCONNECT STRUCTURE
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor manufacture. More specifically, the present invention relates to improvements to an air gap interconnect structure for applications in 65nm or smaller technology.
BACKGROUND
[0002] With the recent semiconductor development, very large scale integrated circuits (VLSI) and ultra large scale integration (ULSI) are widely required in the semiconductor industry. VLSI and ULSI typically have complex multilevel structures, tiny line width and line space which contain patterns of metal wiring layer and dielectric material to insulate the metal wire. The performance of VLSI and ULSI are limited by the interconnect capacitance, especially in ultra tiny feature size integrated circuit. In a RC circuit, the value of time constant is equal to the product of the circuit resistance and the circuit capacitance (RC), and the power consumption is equal to the product of the capacitance, square of the voltage and the frequency (CV2/). Therefore the resistance and capacitance determine the performance of the semiconductor devices. In order to reduce the resistance, copper (Cu) is used as an effectively conductive line to replace aluminum (Al) in VLSI and ULSI, and a low-k dielectric material, such as aromatics hydrocarbon thermosetting polymer (SiLK) is considered to replace the traditional dielectric material, such as silicon dioxide (Si02), which can effectively reduce the capacitance of VLSI and ULSI.
[0003] The mechanical property of low-k dielectric material restricts the developments of VLSI and ULSI, due to the low Young's modulus of low-k dielectric, as shown in TABLE 1. The mechanical strength of copper will weaken square with the copper line width decrement, as shown in FIG.1. With the purpose of removing the excess copper line, a planarizing polish process, such as a chemical mechanical planarization (CMP) is applied. Because of the mechanical weakness of low-k material and the huge young's modulus difference between the low-k dielectric material and copper, the conductive line will appear deformed during the CMP process and result in a short circuit or an open circuit of VLSI and ULSI. It would be very possible that the copper line may be destroyed by the CMP during the process. Therefore, low-k dielectric material can not become a main current dielectric material and replace the traditional dielectric material.
[0004] Table 1 Mechanical and electrical property of dielectric material
Figure imgf000003_0001
[0005] In order to overcome this issue, air gap interconnection structure is developed. The permittivity of air is equal to 1, which is much lower than traditional dielectric material (Si02) at approximately 3.9, if air is formed between copper lines, the dielectric constant of the dielectric layer will be decreased significantly. The air gap process can provide a relative low-k dielectric constant, the air gap combined with dielectric material can be consider as a porous material with permittivity depending on the volume of the air gap. US 7,501,347, US 7,629,268 and US 7,361,991 have provided some methods to form air-gap structures lager than 90-nm scale, however, when the feature size is decreased, the traditional damascene processes, especially the processes using CMP to planarize the copper line surfaces, are facing serious bottleneck. It would be a big problem on how to eliminate the stress on the copper lines.
[0006] Hence, the stress-free-polishing (SFP) is invented to overcome this bottleneck. SFP bases on the electrochemical mechanism to polish the excess copper line without erosion and mechanical stress. By using SFP, the copper line will not be damaged. The damascene technique integrated with SFP process can form an air-gap structure with a scale smaller than 65 nm.
SUMMARY
[0007] According to the present invention, an improved damascene technique integrated with SFP technique is provided. The technique uses copper as a main conductor layer and solves the following problems: [0008] 1) No hard mask is used. In prior art, in order to protect the sacrificial polymer layer, commonly a hard mask is formed above the sacrificial polymer layer, the hard mask has a higher mechanical strength to resist the stress during the CMP process. The method according to the present invention utilizes SFP instead of CMP to ! ¾if}|¾3 l ffi¾¾ o the excess copper, as a result the processes of depositing and removing the hard mark may be removed because the SFP process will not bring any stress to the copper lines. The method of the present invention simplifies the whole process and reduces the cost by removing the processes of the hard mask.
[0009] 2) In prior art, a part of the dielectric materials will be reserved to protect the flanks of copper lines so as to avoid potential damages to the copper lines caused by the polishing process. Therefore, the air gaps can not be formed in narrow line space areas or only smaller air gaps can be formed in these areas. That is the reason why air gap interconnect structure is not applied to narrow interconnect structures, such as first metal layer (Ml layer) structures, even the permittivity has the most significant impact in this layer. The method of the present invention may also remove the reserved dielectric materials since no stress will be applied by the SFP process. Therefore, the air gaps can be formed in narrow line spaces, such as the spaces having a scale less than 65nm. And a relatively larger air gap may be formed in the spaces between copper lines and the shape of the air gap is optimized. The permittivity of dielectric will be significantly reduced, and the RC delay and the power consumption will be further reduced. The tiny node VLSI and ULSI dissipation problem will be solved.
[0010] According to an embodiment of the present invention, a method for forming air gap interconnect structure is provided. Trench and via are selectively etched in an insulating structure composed by sacrificial material. Conductive structures are formed in the trench and via, the conductive structures are separated by sacrificial material. A scale of the conductive structures is lower than 65nm. Then deposit a barrier and remove the barrier by XeF2 selective thermal flow etching. The conductive structures are plated by copper and the copper is polished by both Chemical Mechanical Polishing (CMP) and Stress-Free ElectroPolishing (SFP) in sequence. The sacrificial material are removed by plasma etch to form recesses between the conductive structures. Then deposit a insulating film serving as a sealing dielectric on entire surface. Dielectric material is non-conformally deposited over the conductive structure and in the recesses by Chemical vapor deposition (CVD) so as to form air gaps within the dielectric material in the recesses. No hard mask is deposited during the formation of the conductive structures.
[0011] According to an embodiment of the present invention, a copper sealing layer is non-conformally deposited on the conductive structure after removing the sacrificial material and prior to non-conformally depositing dielectric material.
[0012] According to an embodiment of the present invention, a sacrificial removal stop layer is formed on the substrate prior to forming conductive structure on the substrate.
BRIFE DESCRIPTION OF THE DRAWING
[0013] FIG. 1 is a diagram illustrating the relation between copper line width and its mechanical strength.
[0014] FIG. 2 is a cross-sectional view of the initial structure of the substrate according to the method for forming an air gap interconnect structure of the present invention.
[0015] FIG. 3 is a cross-sectional view of the structure of the substrate after a pattern process according to the method for forming air gap interconnect structure of the present invention.
[0016] FIG. 4 is a cross-sectional view of the structure of the substrate after recesses are formed according to the method for forming air gap interconnect structure of the present invention.
[0017] FIG. 5 is a cross-sectional view of the structure of the substrate after a barrier layer and a main conductive copper layer is deposited according to the method for forming air gap interconnect structure of the present invention.
[0018] FIG. 6 is a cross-sectional view of the structure of the substrate after the main conductive copper layer is smoothed by CMP according to the method for forming air gap interconnect structure of the present invention. [0019] FIG. 7 is a cross-sectional view of the structure of the substrate after the main conductive copper layer is polished by SFP according to the method for forming air gap interconnect structure of the present invention.
[0020] FIG. 8 is a cross-sectional view of the structure of the substrate after etching the barrier layer according to the method for forming air gap interconnect structure of the present invention.
[0021] FIG. 9 is a cross-sectional view of the structure of the substrate after removing the insulating film according to the method for forming air gap interconnect structure of the present invention.
[0022] FIG. 10 is a cross-sectional view of the structure of the air gap interconnect structure formed according to the method for forming air gap interconnect structure of the present invention.
DEDETAIL DESCRIPTION OF EMBODIMENTS
[0023] As shown in FIG. 2, a first dielectric layer 302 is deposited on substrate 301. The first dielectric layer 302 may be one of SiCN, SiC, SiN and SiOC or their combination. A second dielectric layer (sacrificial layer) 303 is deposited on the first dielectric layer 302. The second dielectric layer 303 may be a low-k material or insulating film like an organic film such as a SiLK film. A reflection preventive film 304 and a photo-resist film 305 is sequentially deposited on the second dielectric layer 303.
[0024] The photo-resist film 305 is patterned by exposure to form a photo-resist pattern 405 as shown in FIG. 3. The reflection preventive film 304 is selectively removed by dry etching using the photo-resist pattern 405 as an etching mask and forms a patterned reflection preventive film 404.
[0025] As shown in FIG. 4, the second dielectric layer 503 is selectively removed to form trenches by dry etching using the photo-resist pattern 405 as an etching mask. Thereafter, the photo-resist pattern 405 and the patterned reflection preventive film 404 are removed. Refer to FIG. 4, trenches 506 are formed within the second dielectric layer 503. [0026] A barrier layer of TaN/Ta 606a is deposited on entire main surface of substrate 301 by using sputtering. Then, the metal layer of copper 606b is deposited on the barrier layer of TaN/Ta 606a by using sputtering and plating in sequence. FIG. 5 shows the structure after the depositions of the barrier layer of TaN/Ta 606a and the metal layer of copper 606b.
[0027] The metal layer of copper 606b is polished to 100nm~200nm of remaining copper film thickness by CMP for smoothing the surface topography, as shown in FIG 6. The remaining copper film is numbered as 706b.
[0028] A stress-free electropolishing (SFP) is performed on the remaining copper film 706b. FIG.7 illustrates the structure after a stress-free electropolihsing (SFP) process. After the SFP process, the copper film 806b is polished back to the surface of non-recessed areas, such that metal layer within the recessed regions, i.e., the trenches and/or vias, is isolated from adjacent recessed regions. SFP is a chemical-electrical process: the copper on the wafer substrate works as an anode and an electrolyte nozzle works as a cathode. The copper is dissolved and polished by contacted electrolyte when positive voltage is applied between the anode and the cathode. SFP is a stress free and selective copper removal process. WO2010/020092 discloses a detailed process of SFP.
[0029] The barrier layer of Ta/TaN 906a on the top surface of wafer is removed by XeF2 gas phase etching. The XeF2 reacts spontaneously with Ta/TaN at a certain temperature and pressure. XeF2 is an isotropic selective etching method of Ta/TaN (the barrier layer of Ta/TaN 606a). The XeF2 gas has good selectivity to both copper 806b and the second dielectric layer 503, which is formed by dielectric materials such as Si02, SiLK, or low k Si- C-O-H based materials. The value k of the low k Si-C-O-H based materials varies from 1.2 to 4.2 and 1.3-2.4 is preferred. During the whole process there is no mechanical stress applied to the barrier layer of Ta/TaN 906a or the second dielectric layer 503 directly, so there is no damage to copper 806b or the second dielectric layer 503 (the dielectric materials). According to an embodiment, the temperature of the substrate varies from 0°C to 300°C and 25°C~200°C is preferred. The pressure of XeF2 gas during the process is between O. lTorr and 100 Torr and 0.5 Torr~20 Torr is preferred. FIG. 8 shows the above process. [0030] The chemical reaction products of XeF2 and Ta/TaN are in gas phase, such as Xe or volatiles with the processing pressure. An example of the volatiles is tantalum fluoride. Thus, there is no residual on the surface of the wafer.
[0031] As shown in Fig. 8, when the barrier layer 906a exposed on the top surface is removed completely by XeF2 gas phase etching, the trenches 906 in the semiconductor device is electrically separated completely. The copper layer or copper film 806b and the remaining barrier layer (of Ta/TaN) 906a are completely separated by the low k dielectric layer 503 (formed from the second dielectric layer 303).
[0032] The low k dielectric layer 503 (formed from the second dielectric layer 303) is removed by using reducing gas NH3, or H2/N2 to form trench 1007, and first dielectric layer 302 serves as an etching stopper. The depth for removal becomes uniform. At the same time, the copper layer or copper film 806b and remaining barrier layer of TaN/Ta 906a does not get any damage. The FIG. 9 shows the above process.
[0033] A third dielectric layer 1008 is deposited on entire surface of substrate, and serves as a sealing dielectric in FIG. 9. The third dielectric layer 1008 maybe one of SiCN, SiC, SiN and SiOC or their combination.
[0034] As shown in FIG. 10, a fourth dielectric layer 1109 is deposited on the third dielectric layer of SiCN 1008 by using non-conformally plasma enhance chemical vapor deposition (PECVD) or thermal chemical vapor deposition (TCVD). Tetraethyl Orthosillicate (TEOS) and Ozone (03) are applied in TCVD. Air gap structure are formed by TCVD with temperature from 300°C and 450°C, with best temperature 400°C. Air gaps 1110 are formed in trenches 1007. The trenches 1007 shall have a space between lOnm to 250nm. The fourth dielectric layer 1109 may be one of SiOF, SiOC, Black Diamond (BD) and Black Diamond II (BDII) or their combination.

Claims

What is claimed is:
1. A method for forming air gap interconnect structure comprising,
depositing a first dielectric layer;
depositing a second dielectric layer (sacrificial layer);
putting photo mask, then selectively etching the second dielectric layer to form trenches and vias in the second dielectric layer;
depositing barrier layer and seed layer on the second dielectric layer with trench and via;
depositing a metal layer on the seed layer;
partially polishing the metal layer by using Chemical Mechanical Polishing (CMP); polishing the metal layer to barrier layer by using Stress-Free ElectroPolishing (SFP); etching the barrier layer;
removing the second dielectric layer by plasma etch to form recesses between the metal structures;
depositing a third dielectric layer serving as a sealing dielectric on entire surface; non-conformally depositing a fourth dielectric layer over the metal structure and in the recesses by Chemical vapor deposition (CVD) , so as to form air gap structure between the metal lines;
planarizing the top surface of the fourth dielectric layer CMP for smoothing the surface topography.
2. The method of claim 1, wherein the first dielectric layer is on of one of SiCN, SiC, SiN and SiOC or their combination.
3. The method of claim 1, wherein the second dielectric layer is organic material.
4. The method of claim 3, wherein the organic material is SiLK.
5. The method of claim 1, wherein the second dielectric layer is SiOF, SiOC.
6. The method of claim 1, wherein the barrier layer is Ta/TaN, Ti/TiN, or Ru.
7. The method of claim 6, wherein the barrier layer of TaN/Ta or TiN/Ti is deposited by sputtering.
8. The method of claim 1, wherein the seed layer is copper.
9. The method of claim 1, wherein the metal layer is copper.
10. The method of claim 9, wherein the metal layer is deposited by sputtering or Electrochemical plating (ECP).
11. The method of claim 1, wherein partially polishing the copper layer to 100nm~200nm of remaining thickness by Chemical Mechanical Polishing (CMP) for smoothing the surface topography.
12. The method of claim 1, wherein the rest of the metal layer in non-recessed areas is polished by Stress-Free ElectroPolishing (SFP) to isolate the barrier layer of within the recessed regions.
13. The method of claim 1, wherein the barrier layer comprising Ta/TaN or Ti/TiN is removed by XeF2 gas phase etching.
14. The method of claim 1, wherein the barrier layer comprising Ta/TaN or Ti/TiN is removed by plasma etching.
15. The method of claim 1, wherein the second dielectric layer comprising SiLK comprises is plasma etched by using NH3, or H2/N2 as a reducing gas, and using the first dielectric layer as an etching stopper.
16. The method of claim 1, wherein one of SiCN, SiC, SiN and SiOC or their combination is deposited as the third dielectric layer.
17. The method of claim 1, wherein SiOF, SiOC, Black Diamond (BD), or Black Diamond II (BDII) is non-conformally deposited as the fourth dielectric layer by using Chemical Vapor Deposition (CVD).
18. The method of claim 17, wherein CVD is Plasma Enhance Chemical Vapor Deposition (PECVD) or Thermal Chemical Vapor Deposition (TCVD).
19. The method of claim 18, wherein Tetraethyl Orthosillicate (TEOS) and Ozone (03) are applied in the TCVD.
20. The method of claim 18, wherein air gap structure formed by TCVD with temperature from 300°C and 450°C, with best temperature 400°C.
21. The method of claim 1, wherein air gaps are only formed on recesses with a space between lOnm to 250nm.
PCT/CN2011/079859 2011-09-20 2011-09-20 Method for forming air gap interconnect structure Ceased WO2013040751A1 (en)

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