WO2013029564A1 - Three-dimensional recorded memory - Google Patents

Three-dimensional recorded memory Download PDF

Info

Publication number
WO2013029564A1
WO2013029564A1 PCT/CN2012/080895 CN2012080895W WO2013029564A1 WO 2013029564 A1 WO2013029564 A1 WO 2013029564A1 CN 2012080895 W CN2012080895 W CN 2012080895W WO 2013029564 A1 WO2013029564 A1 WO 2013029564A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
mask
data entry
3d
Prior art date
Application number
PCT/CN2012/080895
Other languages
French (fr)
Chinese (zh)
Inventor
张国飙
Original Assignee
Zhang Guobiao
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US61/529,919 priority Critical
Priority to US201161529920P priority
Priority to US201161529919P priority
Priority to US201161529922P priority
Priority to US61/529,922 priority
Priority to US61/529,920 priority
Application filed by Zhang Guobiao filed Critical Zhang Guobiao
Publication of WO2013029564A1 publication Critical patent/WO2013029564A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11213ROM only
    • H01L27/1128ROM only with transistors on different levels, e.g. 3D ROM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11213ROM only
    • H01L27/1122ROM only with source and drain on the same level, e.g. lateral transistors
    • H01L27/11226Source or drain contact programmed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11213ROM only
    • H01L27/1122ROM only with source and drain on the same level, e.g. lateral transistors
    • H01L27/11253Doping programmed, e.g. mask ROM
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three-dimensional recorded memory. Same is an improved three-dimensional mask-programmable read-only memory and employs three means to reduce data capturing costs: 1) use of a shared data mask (18A) to reduce mask costs apportioned to each mass-volume publication; 2) use of an embossing method to imprint data, where a data template used in the embossing method is at a great discount compared to the data mask (18A); and 3) employment of an offset imprint method to reduce the quantity of the data mask (18A). Also provided in the present invention is a three-dimensional recordable memory.

Description

 3D imprint memory Technical field

 This invention relates to the field of integrated circuit memory and, more particularly, to a mask programming read only memory (mask-ROM).

Background technique

 Discs - including DVDs and Blu-ray Discs (BD) - are the main medium for mass publishing. The 'massive' in mass publication has a double meaning, and it refers to the massive release of massive publications. Here, each mass publication contains massive data, and the amount of data is GB. Magnitude, its content can be movies, video games, digital maps, music libraries, library or software. For example, the amount of data in a VCD format movie is ~0.5GB, and the amount of data in a DVD format movie is ~4GB, and the amount of data in a BD format movie is ~20GB. On the other hand, massive issuance means that the circulation is over 10,000 or even millions.

The disc is too large for mobile users. Because semiconductor memory is smaller in size, it is more suitable for mass publishing for mobile users. 3D mask programming read-only memory (3D-MPROM) ) is such a semiconductor memory. US Patents 5,835,396, 6,624,485, 6,794,253, 6,903,427 and 7,821,080 Several features of the 3D-MPROM are disclosed. Figures 1A and 1B show a 3D-MPROM. Fig. 1A is a cross-sectional view taken along line AA' of Fig. 1B. The The 3D-MPROM is a monolithic integrated circuit comprising a semiconductor substrate 0 and a three-dimensional stack 16 stacked on a substrate. The three-dimensional stack 16 contains M ( M ≥ 2 ) A stack of storage layers (such as 16A, 16B). The memory layers (eg, 16A, 16B) are coupled to substrate 0 through contact via holes (eg, 1av, 1 ' av ). On the substrate The substrate circuit 0X in 0 contains the peripheral circuit of the three-dimensional stack 16.

 Each storage layer (such as 16A) contains multiple top address lines (such as 2a-2d), bottom address lines (such as 1a), and storage elements (such as 5aa-5ad). The width of the address line is f . Each memory element (such as 5aa) stores n ( n ≥ 1) bits of data. Each memory cell also contains a diode 3d . A diode generally refers to any two-port device that has a resistance that is greater than the resistance at the read voltage when the magnitude of the voltage it receives is less than the read voltage, or the direction of the voltage it receives is different from the read voltage. Each storage layer (such as 16A ) Contain at least one layer of data entry film (eg 6A). The graphics in the data entry film are data graphics that represent the data it stores. In Fig. 1A, the data entry films 6A, 6B are all isolation dielectric films 3b. It blocks the current flow between the top address line and the bottom address line, and distinguishes the different states of the memory elements (such as 5aa) by the presence or absence of data openings (such as 6aa). In the figure, the data opening 6aa The size is the same as the width f of the address line. In other embodiments of the invention, the size of the data opening 6aa is in many cases greater than the width of the address line f (see U.S. Patent 6,903,427 This can help reduce the cost of data entry (see Figure 5, Figure 10A, and Figure 10B). In the present application, xMxn 3D-MPROM means one containing M ( M ≥ 2 a storage layer, and each storage element stores a 3D-MPROM of n (n ≥ 1) bits.

 Figure 1B is a top view of the storage layer 16A. The 3D-MPROM is a cross-point (cross-point) Array memory, which contains multiple top address lines (such as 2a-2d), bottom address lines (such as 1a-1d), and memory elements (such as 5aa-5dd) ) and distinguish the different states of the memory cells by the presence or absence of data openings (such as channel holes). For example, there is a data opening at the storage element 5aa, which represents '1'; there is no data opening at the storage element 5ab, which represents ' 0 '. This figure only shows the isolation dielectric film 3b (indicated by the cross pattern) near the data opening. In order to display the address lines and their relationship with the data openings, the isolation dielectric film 3b elsewhere Not drawn. The figure also does not show components such as diodes in the memory cell.

 In order to further increase the storage density, 3D-MPROM can adopt n ( n>1 ) bits, that is, each storage element stores n Bit data. A multi-bit 3D-MPROM is disclosed in U.S. Patent Application Serial No. 12/785,621. Figure 1C is a 2-bit 3D-MPROM Sectional view. Its memory elements (such as 5aa) store two digital bits: the 1st and 2nd digits. The figure shows only one storage layer 16C, which contains two data entry films 6C, 6D . The data entry film 6C determines whether a memory cell has an additional doping 3i according to the value of the first digital bit, and the data recording film 6D determines whether a memory cell has a resistive film according to the value of the second digital bit. . In the present application, the jth digital bit represents the jth bit stored in an n-bit (storage element storing n digital bits, n ≥ j ).

technical problem

 In the prior art, the graphics in the data entry film are obtained from the data mask by pattern conversion. Graphic conversion is also called printing (print ), that is, by 'printing' to enter data. The present invention refers to a mask that carries content data as a data mask. When the feature size of the integrated circuit is smaller than the optical wavelength of the lithography machine, the mask needs to adopt resolution enhancement technology ( Resolution enhancement techniques ( RET ), such as optical proximity correction Correction, ie OPC) and phase-shift mask. The introduction of these technologies led to the manufacture of 100 The amount of data that needs to be written when the mask is less than nanometer is greatly increased, and the manufacturing process is also increasingly complicated.

 Particularly bad is that the data pattern on the data mask is different from other mask patterns in the memory, such as address line graphics, storage columns ( Storage pillar ) ) Graphics, etc. The address line pattern, the memory column pattern, and the memory hole pattern have a strong micron-scale periodicity, that is, in a micron-sized area, the pattern is repeated in a certain period. Micron is important because it represents the diffraction range of the exposure light. The above graphics are more suitable OPC and phase-shift mask, etc. RET Technology. On the other hand, the data pattern in the data mask has no micro-scale periodicity at all, that is, in the micron-sized area, the data pattern is not repeated at all. Data graphics are not suitable for OPC, phase-shift The RET technology, such as mask, makes the fabrication of data masks very complicated. These factors have led to a sharp rise in data mask costs after 90 nm.

 In general, a data mask is required for each data entry film. Thus, an xMxn 3D-MPROM requires M×n Block data mask. For example, for an x8x2 3D-MPROM, it needs 16 (=8×2 ) Block data mask. So many data masks make the cost of high data masks even more unacceptable: the cost of these data masks at the 90nm node is about $800,000 at 22nm. The cost of the node rose to $4 million.

In the prior art, a data mask was only used for a large number of publications, and it was a dedicated data mask. As shown in Figure 2, the dedicated data mask 8A contains only mask patterns for the mass publication MC 0 . Note that a data mask version 8A can contain multiple copies of the MC 0 mask pattern (here 16 copies). For proprietary data masks, the high cost of masks falls on a single mass publication. Accordingly, the cost of storing the 3D-MPROM of the mass publication MC 0 also becomes high. Most professionals believe that the high data mask cost after 90nm will greatly limit the wide application of 3D-MPROM.

Technical solution

 The invention provides a three-dimensional printed memory (three-dimensional printed memory) , referred to as 3D-P). The name is called 'printing memory' in order to highlight the method of entering data by 'printing', that is, the printing method. In the present invention, 'printing' is another term for 'mask programming'.

 3D-P is an improved 3D-MPROM and uses three methods to reduce data entry costs: 1 Use a shared data mask; 2) use imprint-lithography (also known as nanoimprint lithography) , referred to as NIL for printing data; 3 Use offset-printing to reduce the number of data masks. In the present invention, unless otherwise specified (such as when the context is compared with a data template), the data mask refers to any data bearing device used in the printing process, including data templates.

In order to reduce the data entry cost, the 3D-P in the present invention uses a shared data mask to record data. A shared data mask contains mask patterns for a number of different mass publications, so the cost of high masks can be shared by multiple mass publications. The data mask cost allocated to each mass publication is the unit GB mask cost C GB (that is, the cost of the mask version corresponding to the data mask area occupied by GB data) and the mass publication The product of the amount of data (in GB). In the scale of semiconductor technology, CGB actually drops due to the increase in the amount of mask data (the amount of data carried on one mask) is faster than the increase in mask cost. He said example, from 90nm to 22nm, C GB reduced from ~ $ 5.4k / GB ~ $ 1.7k / GB (k = 1,000). Accordingly, the portion of the 3D-P cost from the data mask will gradually decrease as technology advances. After 45nm, the cost of 3D-P can be as low as the replacement of the disc. In the present invention, the amount of data contained in each of the mass publications is of the order of GB, preferably not less than 0.5 GB.

 In order to further reduce the data entry cost, the present invention also proposes an imprinted memory (imprinted memory). ), especially three-dimensional imprinted memory (3D-iP for short) ). It uses imprinting to record data: imprinting by applying pressure on the template to make the imprint resist Produce mechanical deformation to achieve graphics conversion. The main advantage of using imprinting to enter data is that its data template is much cheaper than the data mask in photolithography. Here, the data template is a template for converting data graphics to a data entry film. Templates are also known as masters ( Master ), stamp, mold, etc. In imprinting, since the graphics in the data entry film are 1 : 1 on the data template Copy, it does not have optical distortion problems in lithography, so data templates do not require OPC The amount of data that needs to be written during manufacturing is much smaller than the data mask. In addition, the imprint method does not have to worry about the diffraction effect, and the data template does not require the use of phase shifting technology, thereby avoiding the use of complex mask processes. More importantly, the imprint method makes the imprinted nanoscale (such as 1 nanometer to 100 Nano-) and data graphs that do not have microscale periodicity are possible. In general, because manufacturing data templates are easier than data masks, data templates are less expensive, so imprinted memories have lower data entry costs.

 In order to reduce the number of data masks, the present invention also proposes a three-dimensional offset printing memory (three-dimensional Offset-printed memory (3D-oP for short). 3D-oP enters data by offset printing. In order to achieve offset printing, corresponding to different storage layers / The mask pattern of the digital bits is merged into a multi-region data mask. The offset of the wafer relative to the multi-region data mask is different in different printing steps. Therefore, mask patterns from the same data mask are printed to different storage layers. / Digital data is entered into the film. In the same 3D-oP batch, all 3D-oP The chips are printed by the same data mask. Although there may be different digital array sequences between chips, all chips have the same set of digital arrays. In the present invention, the digital array is defined as follows: each layer of data entry film contains a plurality of locations, each location corresponding to a memory element, and the data pattern at each location represents a digital value, and the array of these digital values forms a digital Array. Accordingly, the digital array sequence refers to one All digital arrays in the 3D-oP chip (including all data entry films, ie all memory layers and all digital bits) in a sequence (eg according to the distance from the substrate); digital array set refers to the 3D-oP A collection of all digital arrays in the chip. By definition, a collection is only relevant to the elements it contains, regardless of the order.

 In order to be able to write customized data in 3D-P, the present invention also proposes a three-dimensional writable print memory ( Three-dimensional writable printed memory (3D-wP for short). It contains a printed storage array and a write storage array. The print storage array stores content data. Content data is publications (including movies, video games, maps, music libraries, library, software, etc.) The data is entered by the imprint method. The printing method is a parallel data entry method, which mainly includes photolithography and imprinting. Write storage array storage Custom data. Custom data includes custom information such as chip serial number, key, and so on. Custom data is entered by writing. The write method is a serial data entry method, which mainly includes direct writing photolithography, such as electron beam lithography, laser beam lithography or focused particle beam lithography. In the same batch In 3D-wP, all memories store the same content data, but can store different custom data. To ensure capacity, the total amount of data for custom data should be less than 1% of the total amount of data for the content data.

Beneficial effect

 As can be seen from the above scheme, the present invention has the following beneficial effects:

 Achieve low-cost mass publishing;

 Reduce data entry costs;

 Reduce the cost of data masks;

 Write custom data in the print memory.

DRAWINGS

 Figure 1A is a cross-sectional view of a 3D-MPROM; Figure 1B is a top view of the 3D-MPROM; Figure 1C It is a cross-sectional view of another 3D-MPROM.

 Figure 2 shows a dedicated data mask used in the prior art.

 Figure 3 shows a shared data mask proposed by the present invention.

 Figure 4 shows a printed field on a 3D-P wafer.

Figure 5 is a top view of an F- node data mask.

Figure 6 compares mask cost and unit GB mask cost (C GB ) in several generations of semiconductor technology.

 Figure 7 compares the cost structure of 3D-P over several generations of semiconductor technology at different throughputs (V).

8 shows generations of semiconductor technology, the cost of 3D-P reaches the disc replacement threshold cost (C th), a minimum circulation of 3D-P (V th).

 Figures 9A-9C show various steps for implementing the imprint method.

 Figures 10A and 10B are top views of two data templates.

 Figures 11A and 11B show two printing steps used in the offset printing method.

 Figure 12A is a simple example of a multi-region data mask; Figure 12B and Figure 12C The two data mask areas in the multi-area data mask represent the digital arrays m(1), m(2), respectively.

 Figure 13A and Figure 13B show two 3D-oP chips 18a in the same x2x1 3D-oP batch, Sectional view of 18b.

 Figure 14A and Figure 14B show two 3D-oP chips 18c in the same x1x2 3D-oP batch, Sectional view of 18d.

 Figure 15 shows a circuit block diagram of a 3D-oP.

 Figure 16A shows a circuit block diagram of x2x1 3D-oP; Figure 16B shows an x1x2 3D-oP Circuit block diagram.

 Figure 17 is a cross-sectional view of an x2x2 3D-oP.

 Figure 18 shows an x2x2 3D-oP The multi-area data mask used, as well as all the chips in an exposure field.

 Figure 19 lists the x2x2 3D-oP After each printing step, each data on each chip is entered into the digital array in the film.

 Figure 20 shows a circuit block diagram of an x2x2 3D-oP.

Figure 21 is a cross-sectional view of an x3x3x1 3D 2 -oP package.

Figure 22 shows a block diagram of a 3D 2- oP package.

Figure 23 shows a multi-region data mask used in a 3D 2- oP package with all the chips in an exposure field.

Figure 24 shows the digital array in each data entry film on each chip after each printing step in the 3D 2- oP package.

Figure 25 lists three 3D 2 -oP packages in a 3D 2 -oP batch.

 Figure 26A and Figure 26B are cross-sectional views of two chips in the same 3D-wP batch.

 Figures 27A-27D illustrate the data entry steps for implementing the embodiment of Figures 2A-2B.

 Figure 28 is a cross-sectional view of another 3D-wP chip.

 Figure 29 shows the data entry step for implementing the embodiment of Figure 4.

 Figure 30 is a block diagram of a 3D-wP with good data security.

It is noted that the drawings are only schematic and are not drawn to scale. In order to be conspicuous and convenient, some of the dimensions and structures in the figures may be enlarged or reduced. In the different embodiments, the same symbols generally indicate corresponding or similar structures.

Embodiments of the invention

 In order to reduce the data entry cost, the present invention proposes a three-dimensional imprinting memory (3D-P). It is an improvement 3D-MPROM uses three methods to reduce data entry costs: 1) use shared data mask; 2) use imprint method to print data; 3 Use offset printing to reduce the number of data masks. The name is called 'printing memory' in order to highlight the method of entering data by 'printing', that is, the printing method. In the present invention, 'printing' is another term for 'mask programming'.

 In most cases, this manual uses 3D-MPROM (that is, a mask-ROM in which memory cells are distributed in three-dimensional space). The specific embodiments are explained by way of example. The spirit of the present invention can be readily extended to conventional mask-ROMs (i.e., mask-ROMs in which memory elements are distributed on a two-dimensional plane). Mask-ROM The main method of data entry is the printing method. The printing method includes photolithography and imprinting. Correspondingly, unless otherwise specified (such as when the context is compared with the template), the 'mask version' in mask programming refers to any data-bearing device used in the printing process, which can be photolithography. The mask used in the method can also be the template used in the imprint method ( Template , also known as master , stamp , or mold ).

 Shared data mask

3D-P is an improved 3D-MPROM that uses a shared data mask to record data. Figure 3 shows a mask pattern on a shared data mask 18A. Unlike the dedicated data mask 8A in Figure 2, the shared data mask 18A contains mask patterns for 16 different mass publications (MC 1 -MC 16 ). In the present embodiment, all of these mass publications MC 1 -MC 16 are not repeated. Obviously, the cost of data mask 18A can be shared among the 16 massive publications. Specifically, the data mask cost of a large number of publications is the cost per unit GB mask (C GB , which is the cost of the mask version corresponding to the data mask area of the unit GB data) and the mass publication. The product of the amount of data (in GB). For those familiar with the profession, although the data mask 18A in Figure 3 only carries 16 mass publications, as the technology advances, a data mask can carry more massive publications. For example, a 45nm data mask can carry ~37GB of data, or ~70 movies.

Figure 4 shows a printing field 28 on the 3D of the 3D-P wafer. The print field 28 refers to a graphic area formed on a wafer after a single print in a step-and-repeat printing process. For photolithography, the print field is its exposure field. It is noted that wafer 0W contains a plurality of repeating print field regions 28. Since the printed record field region 28 is formed in Figure 4 by the data recorded in the mask plate 18A in FIG. 3, which stores publication data 16 different mass of MC 1 -MC 16. In this embodiment, the 16 mass publications MC 1 -MC 16 are not repeated.

After cutting 3W of 3D-P wafers, each chip can store only a single mass publication, or multiple mass publications. In Figure 4, each of the print field areas 28 is cut into four chips D1-D4, each of which stores data for a plurality of different mass publications: chip D1 stores MC 1 , MC 2 , MC 5 , MC 6 Data, chip D2 stores data of MC 3 , MC 4 , MC 7 , MC 8 , chip D3 stores data of MC 9 , MC 10 , MC 13 , MC 14 , and chip D4 stores MC 11 , MC 12 , MC 15 , MC 16 The data. In this embodiment, different chips in the same footprint area store non-repeating mass publication data.

Figure 5 shows an F- node data mask 18A which is used to print data into the data entry film 6A of Figure 1A. The data mask 18A contains a mask element array 'aa' - 'bd'. The brightness or darkness of the pattern at each mask element determines the presence or absence of a data opening at the corresponding memory element. In this embodiment, the mask patterns at the mask elements 'aa', 'ad', 'bb', and 'bc' form mask openings 8aa, 8ad, 8bx. In the present application, the size F of the data mask is represented by the size of the pattern it forms on the wafer, rather than its size on the data mask. For those skilled in the art, due to the reduction of the mask pattern by the lithography machine, the size on the reticle can be several times (for example, 4 times) the size of the pattern on the wafer.

On data mask 18A, the minimum feature size F of its data opening (eg, 8aa) can be greater than the minimum feature size f of 3D-P (such as the half-cycle of the address line), preferably twice the value of f (see US Patent 6,903,427). Accordingly, data mask 18A is also referred to as a xf (x>1, preferably ~2) mask. In fact, for almost all kinds of 3D-P (including 3D-P using an isolation dielectric film, a resistive film, an additional doped film, etc. as a data entry film), the data in the data entry film can pass x f A mask is printed. Using the xf mask can greatly reduce the cost of the data mask. For example, for a 45nm 3D-P, the 45nm data mask costs ~$140k; the 90nm data mask costs only ~$50k.

Figure 6 compares mask cost and unit GB mask cost (C GB ) in several generations of semiconductor technology. Simultaneously, the horizontal axis shows the data mask minimum feature size F (= 2 f) 3D-P and the minimum feature size f. When F is reduced from 90nm to 22nm, the cost of the data mask increases from ~$50k to ~$260k. On the other hand, the amount of mask data has also increased from ~9GB to ~155GB. In general, C GB has been reduced from ~$6.7k/GB to ~$1.7k/GB. Note that since the 90nm mask is in mass production, its C GB is lower.

 As an example, when a 2f mask is used for movie data, the cost of a mask for each DVD format movie (~4GB) is between Between ~$27k and ~$7k; the cost of masks for each BD format movie (~20GB) is between ~$135k and ~$34k Between. These figures are much less expensive than the film masks that most people think of. They are small compared to the cost of film production and can be ignored.

Figure 7 compares the cost structure of 3D-P over several generations of semiconductor technology at different throughputs (V). 3D-P costs include memory costs and data entry costs, regardless of royalties. Each f- node has two vertical bars, each f-node has two vertical bars, one corresponding to the case of a circulation of 200k and the other corresponding to a case of a circulation of 100k. The bottom of each bar represents the memory cost per unit GB (C storage ), the top represents the data entry cost per unit GB (C entry ), and the total height represents the 3D-P cost per unit GB (C 3D ). The individual data in the figure is calculated according to the following formula:

C 3D = C storage + C entry ,

 among them,

C storage = C wafer / D wafer ;

C entry = F print × C mask /V.

Here, the C wafer is the wafer cost, and the D wafer is the total amount of data on one wafer; the F printing represents the printing cost factor, that is, the printing cost (including mask, photoresist, etc.) The ratio of the depreciation of various printed assets to the cost of the mask; V is the circulation, that is, the yield of all chips that use the data mask to enter data.

As can be seen from Figure 7, as f decreases, the cost of 3D-P gradually decreases. This is different from popular ideas. When f is less than 45nm, the cost of 3D-P can be less than $0.25/GB. For example, when the circulation is 200k, the cost of 32nm 3D-P is ~$0.25/GB; when the circulation is 100k, the cost of 22nm 3D-P is ~$0.17/GB. In order to replace the disc, the cost of 3D-P needs to be lower than the disc replacement threshold cost C th . It is generally believed that C th ~$0.25/GB. This requires that the minimum feature size f of 3D-P be less than 45 nm.

8 shows generations of semiconductor technology, the cost of 3D-P reaches the disc replacement threshold cost (C th), a minimum circulation of 3D-P (V th). V th is an important parameter that determines the market positioning of different f- node 3D-P. As can be seen from the figure, for 32nm 3D-P, V th ~200k, it is only suitable for mass production. For 22nm, 16nm and 11nm 3D-P, Vth is 42k, 31k and 15k, respectively. They can be used for medium-volume publishing.

 It is noted that publications of medium or small amount of data can be distributed in the same 3D-P as a large number of publications. Overall, 3D-P The content stored in the file may be moving images (such as movies, television programs, video materials, video games, etc.), still images (such as photos, digital maps, etc.), audio materials (such as music, e-books, etc.), text materials (such as electronic Books), software (such as operating systems) and their databases (such as movie libraries, game libraries, photo libraries, map libraries, music libraries, library libraries, software libraries, etc.).

 Imprint memory

 In order to reduce the data entry cost, the present invention also proposes an imprinted memory (imprinted memory). ), especially 3D imprint memory (3D-iP). Imprint memory and mask-ROM for its final physical structure They are identical, they all use the data graphics in their data entry film to store data. The difference between imprinted memory and mask-ROM is that they use different data entry methods: mask-ROM Photo-lithography, imprint-lithography (also known as nano-imprint) Lithography, referred to as NIL). However, the data template used in the imprint method is much cheaper than the data mask used in photolithography.

 Embossing method by applying pressure on a template to make an imprint resist Produce mechanical deformation to achieve graphics conversion (see Chou et al. "Imprint-lithography with 25-nanometer resolution 》, Science Journal, 272, 5258, pp. 85-87). Examples of embossing methods include thermoplastic embossing (pigma) Nano-imprint lithography ), photo nano-imprint lithography, electrochemical imprinting Electro-chemical nano-imprint lithography ) and laser-assisted direct Imprint-lithography ). Imprinting can be performed on a full-wafer imprint on the entire wafer, or by step-and-repeat imprinting ( Step-and-repeat imprint ).

 Figures 9A-9C show various steps for implementing the imprint method. These figures are along the AA' in Figure 1. A cross-sectional view of the line. These steps are used to enter data for the memory in Figure 1. The imprint method is a hot plastic stamping method. The specific steps are as follows. First, a data entry film is formed on a base film (e.g., address line) 89. Then, an embossing adhesive (such as a thermoplastic polymer material) is formed thereon (Fig. 9A). Will be a template 81 (Also known as master, stamp, mold, etc.) and embossing adhesive 85 contact and apply pressure. Thereafter, the embossing paste 85 is heated to a temperature exceeding the glass transition temperature of the embossing adhesive, and the stencil 81 The upper pattern is pressed into the softened embossing paste 85. After cooling, the stencil 81 is separated from the wafer (Fig. 9B). Finally, the pattern in the embossing paste 85 is converted to the data entry film by an etching step. Medium (Figure 9C).

 The template 81 has a preset topology graphic. The template 81 in Figure 9A is used to imprint the memory layer in Figure 1A. 16A data entry film 6A. The stencil 81 has a plurality of projections 83. These projections 83 protrude from one surface of the stencil 81 and are between 1 nm and 100 nm in size. stencil The presence or absence of the protrusion 83 in 81 determines the state of the corresponding memory cell. For example, if there is a bump 83 at the template position corresponding to the storage element 5aa, the storage element 5aa contains the data opening. 6aa and in the '1' state. On the other hand, if there is no bump at the position of the template corresponding to the storage element 5ba, the storage element 5ba does not contain the data opening and is at '0'. 'Status. It is noted that the pattern in the embossing paste 85 is exactly the opposite of the pattern in the stencil 81 after the embossing step is completed.

 Figures 10A and 10B show two data templates 81 which can all be used to form the data pattern of Figure 1A. Figure The data template in 10A 81 applies the spirit of the xf ( x>1 , preferably ~2 ) mask in the data mask (see US Patent 6,903,427), ie the template 81 The minimum feature size F can be greater than the half-cycle (or width) f of the address line, preferably twice the value of f. Moreover, adjacent protrusions (such as positions 5bb, 5bc, 5cc) ) can also be merged together. Accordingly, the data template 81 is also referred to as an xf template. For example, a 90nm data template can be a 45nm The imprinted memory enters data. This can further reduce the cost of the data template. In this embodiment, the projections 83 have a rectangular shape.

 Figure 10B shows another data template 81. Its raised 83 (such as position 5aa Where) has a cylindrical shape. The cylindrical minimum feature size F can also be larger than the half cycle (or width) f of the address line. In addition to this, the protrusion 83 It may also have a conical shape, a pyramid shape, or the like. The cylindrical projections 83 are particularly suitable for forming by direct writing by electron beam. Obviously, the data template 81 It is also possible to apply the spirit of a shared data mask to a shared data template, ie a data template 81 carrying data from a number of different mass publications.

The main advantage of imprinting is that its data templates are very cheap. Since the printing method has no optical distortion problem of photolithography, the pattern in the data entry film is the pattern on the data template 1 : 1 Copy, so each protrusion on the data template can have the same shape, without the need for optical correction based on the distribution of the protrusions around it. For each data bit in the imprint memory, the data template requires only one bit of data to define the presence or absence of a bump. Compared with it, for Mask-ROM In one of the data bits, the data mask requires multiple bits of data to define the shape of the data opening. For the same amount of memory data, the amount of data written to make a data template is much smaller than the data mask. In addition, the imprint method does not have to worry about the diffraction effect, and does not require the use of phase shifting techniques, thereby avoiding the use of complex mask processes. More importantly, the data template enables the imprint to have a nanoscale (eg 1 nanometer to 100 Nano), and does not have periodic data patterns in the micrometer scale becomes possible. In general, because manufacturing data templates are easier than data masks and data templates are less expensive, imprinted memories can have lower data entry costs.

 Three-dimensional offset printing memory

 In order to reduce the number of data masks, the present invention proposes a three-dimensional offset printing memory (3D-oP) ). It enters data by offset-printing. The offset printing method is one of the printing methods. Figure 11A and Figure 11B Represents two printing steps used in offset printing. It uses a multi-region data mask 8 . In this embodiment, the multi-region data mask 8 contains two different memory layers 16A, 16B. Mask graphic. They are located in the data mask areas 8a, 8b, respectively.

The offset printing method includes the following two printing steps. In the first printing step (see Fig. 11A, if the photolithography step A of the first memory layer 16A is printed), the origin O 18a of the chip 18a is aligned with the origin O M of the data mask region 8a. At the exposure step E 1a , the data mask area 8a is printed into the data entry film 6A of the memory layer 16A in the chip 18a; at the exposure step E1b , the data mask area 8b is printed to the memory layer of the chip 18b. The data of 16A is entered in the film 6A.

At the second printing step (see Fig. 11B, if the photolithography step B of the second memory layer 16B is printed), the wafer 9 is offset by a distance S y with respect to its alignment position at the first printing step. . Here, d y is used to indicate the distance between the chip 18a and the chip 18b. If S y =d y , the origin O 18b of the chip 18b is aligned with the origin O M . At the time of exposure step E 2a , the data mask area 8a is printed in the data entry film 6B of the memory layer 16B in the chip 18b.

When exposing the next exposure field E 2b , as long as the step distance D y is twice d y , that is, D y = 2d y , the data mask area 8b will be printed on the chip 18a. The data of the storage layer 16B is recorded in the film 6B. Finally, after the above two photolithography steps A, B are completed, in the chip 18a, the data mask regions 8a, 8b are respectively printed into the data entry films 6A, 6B of the memory layers 16A, 16B; in the chip 18b, They are printed in the data entry films 6B, 6A of the memory layers 16B, 16A, respectively.

 Figure 12A is a simple example of a multi-region data mask 8. Each data mask area 8a, 8b Contains a mask element array 'aa ' - ' bd '. In the data mask region 8a, the mask pattern at the mask elements 'ac', 'bb', 'ba' forms a mask opening 8ac, 8bx. In the data mask area 8b, the mask patterns at the mask elements 'aa', 'ad', 'bb' form mask openings 8'aa, 8'ad, 8'bb. If the following definition is used: the dark mask pattern represents '0' and the bright mask pattern represents '1', then the digital value represented by each mask element in the data mask area 8a constitutes a digital array m(1) ( Figure 12B), the digital value represented by each mask element in the data mask area 8b constitutes another digital array m(2) (Fig. 12C).

Figures 13A and 13B show two 3D-oP chips 18a, 18b in the same x2x1 3D-oP batch. In a 3D-oP batch, all chips are made from the same set of masks, all of which contain the same 3D frame. Here, the three-dimensional framework includes all of the address lines in the three-dimensional stack, but does not contain a data entry film. In this embodiment, the data in chips 18a and 18b are both printed by the same data mask 8. Figure 8A shows an x2x1 three-dimensional stack 16a of chip 18a. The data entry film 6A of the memory layer 16A is printed by the data mask area 8a; the data entry film 6B of the memory layer 16B is printed by the data mask area 8b. In the 3D-oP chip 18a, the digital values stored by all the memory cells in the memory layer 16A constitute the digital array p 18a [1], and the digital values stored in all the memory cells in the memory layer 16B constitute the digital array p 18a [2]. If the following definition is used: no data opening represents '0' and a data opening represents '1', the digital array p 18a [1] is identical to the digital array m(1) in Figure 12B, ie p 18a [1]= m (1); The digital array p 18a [2] is identical to the digital array m(2) in Figure 12C, ie p 18a [2] = m(2) . On the other hand, Fig. 8B shows the x2x1 three-dimensional stack 16b of the chip 18b. In the chip 18b, the data entry film 6A of the memory layer 16A is printed by the data mask area 8b; the data entry film 6B of the memory layer 16B is printed by the data mask area 8a. Therefore, for chip 18b, p 18b [1] = m(2) ; p 18b [2] = m(1) .

 In this 3D-oP batch, each 3D-oP All digital arrays of the chip (including all data entry films, including all memory layers and all digital bits) are arranged in a certain order (in terms of distance from the substrate, from near to far) to form a digital array sequence. . The collection of digital arrays is called the digital array collection {S}. According to its definition, a collection is only related to its elements, regardless of the order in which the elements are arranged. For chip 18a and Figure 13A and Figure 13B For 18b, its digital array sequence can be expressed as:

S 18a = (p 18a [1], p 18a [2]) = (m(1), m(2));

S 18b = (p 18b [1], p 18b [2]) = (m(2), m(1));

Where {S 18a } = {S 18b } , but S 18a ≠ S 18b .

 It can be seen that the chip 18a and the chip 18b Have the same set of data arrays, but different sequences of data arrays. In order to read the same data, it is necessary to access different storage layers of chips 18a and 18b.

 Offset printing can also be applied to 3D-MPROM with n bits Medium. Similarly, mask patterns corresponding to different digital bits are merged into a multi-region data mask. The offset of the wafer relative to the multi-region data mask is different in different printing steps. Therefore, data patterns from the same data mask are printed into the data entry film of different digital bits. Figure 14A and Figure 14B Represents two 3D-oP chips 18c, 18d in the same x1x2 3D-oP batch.

Figure 14A shows an x1x2 three-dimensional stack 16c of chip 18c. Each memory element (such as 5aa) on storage layer 16C stores two digital bits: the 1st and 2nd digits. The first digital bit is stored by the first data entry film 6C, which is an additional doped film 3i; the second digital bit is stored by the second data entry film 6D, which is a resistive film 3r. The data entry film 6C of the first digital bit is printed by the data mask area 8a, and the data entry film 6D of the second digital bit is printed by the data mask area 8b. In the first memory layer 16C of the 3D-oP chip 18c, the digital value stored in the first digital bit constitutes the digital array p 18c [1, 1], and the digital value stored in the second digital bit constitutes the digital array p 18a [1,2]. Here, p 18c [i, j] refers to a digital array in which the j-th digital bit of the i-th storage layer in the chip 18c is stored. If the following definition is used: there is an additional doping for '0', no additional doping for '1'; a resistive film for '0', and a resistive film for '1', then the digital array p 18c [1,1] The digital array m(1) in Fig. 12B is reversed, that is, p 18c [1,1] = - m(1); the digital array p 18c [1, 2] is the same as the digital array m(2) in Fig. 12C, that is, p 18c [1,2] = m(2) . Here, the symbol ' - ' indicates the opposite, that is, ' 0 ' and ' 1 ' are interchanged. Since the binary values in a digital array can change with the definition of a binary value, the positive and negative of the digital array does not make much sense. In the present application, the two digital arrays are considered equivalent as long as all binary values in the two digital arrays are the same or opposite. On the other hand, Fig. 14B shows the x1x2 three-dimensional stack 16d of the chip 18d. In the first memory layer 16C of the chip 18d, the data entry film 6C of the first digital bit is printed by the data mask area 8b, and the data entry film 6D of the second digital bit is printed by the data mask area 8a. Therefore, for chip 18d, p 18d [1,1] = - m(2) ; p 18d [1,2] = -m(1) .

 Therefore, for chips 18c and 18d of Figures 14A and 14B In other words, its digital array sequence can be expressed as:

S 18c = (p 18c [1,1], p 18c [1,2]) = (-m(1), m(2)) ;

S 18d = (p 18d [1,1], p 18d [1,2]) = (-m(2), m(1)) ;

Where {S 18c } = {S 18d } , but S 18c ≠ S 18d .

 It can be seen that the chip 18c and the chip 18d Have the same set of data arrays, but different sequences of data arrays. For the same input address, the order of the output bits in the output needs to be swapped.

 Figure 15 shows a circuit block diagram of a 3D-oP. It contains an xMxn 3D heap 16 and a settable input / Output circuit 24 . The three-dimensional stack 16 contains M × n digital arrays. Wherein, the digital array of the jth digital digit in the i-th storage layer is p[i,j] (0≤i≤M, 0 ≤ j ≤ n ) indicates. The settable input/output circuit 24 also includes a sequence of memories 22 . The memory 22 is stored with the 3D-oP Information about the sequence of digital arrays in the chip. One piece of information related to the sequence of digital arrays is the chip serial number. The chip serial number is directly related to the position of the chip on the wafer, which can be used to extract the digital array sequence information of the chip. Sequence memory 22 is preferably an embedded non-volatile memory. For example, it can be directly written to memory, laser programming fuses and / Or electrically programming memory. For direct write to the memory memory, information related to the sequence of the digital array is written during production; for laser programming fuses, information related to the sequence of the digital array is written during or after the production process; For programming memory, information related to a sequence of digital arrays is written after the production process.

 The input/output circuit 24 can be set to change the external input/output according to information related to the digital array sequence. The input in the middle can also change the output of the internal input/output 26 so that the external input/output 28 is independent of the digital array sequence. In other words, all 3D-oP in the same batch Although they may have different digital array sequences, they have the same external input/output 28 for the user. Figure 16A- Figure 16B discloses 3D-oP More details of the circuit.

 Figure 16A shows an x2x1 3D-oP 18 in Figure 13A and Figure 13B. Circuit block diagram. The figure shows its input address decoder 20I. The memory layers 16A and 16B in the three-dimensional stack 16 store the digital arrays p[1] and p[2], respectively. . Here, since each memory cell stores only one digital bit, the representation of the digital array is simplified to p[i] ( 0 ≤ i ≤ M ). Input Address Decoder 20I for Internal Input Address 26 Decode. For example, if the highest bit of the internal input address 26 is '0', the digital array p[1] is accessed; otherwise, the digital array p[2] is accessed. Input/output circuits can be set up 24 The external input address can be changed according to the information associated with the digital array sequence. For chip 18a, internal input address 26 is the same as external input address 28; for chip 18b For example, the internal input address 26 and the highest bit of the external input address 28 are just the opposite.

 Figure 16B shows an x1x2 3D-oP 18 in Figures 14A and 14B. Circuit block diagram. The figure shows the output buffer 20O. The 3D stack 6 stores the digital arrays p[1,1] and p[1,2] corresponding to the 1st and 2nd digits. Output buffer 20O Contains multiple output groups 21, 21'... Each output group outputs all digits stored in the same bank. For example, output group 21 contains digital bits 21a, 21b. Where the output digital position 21a outputs the first digit stored in a bank, and the output digit 21b outputs the second digit stored in the same bank. Input/output circuits can be set up 24 The output digital bit order of each output group 21 in the output buffer 20O can be changed based on information related to the digital array sequence. For chip 18c, external output 28 and internal output 26 The same; for chip 18d, the output digits in each output group (such as 21) are in the reverse order.

 The method of offsetting the printing to different storage layers (Fig. 13A and Fig. 13B) can be used to offset the printing to different digital digits (Fig. 14A and Figure 14B )Combined. Specifically, mask patterns of different memory layers and different digital bits are combined onto a multi-region data mask. The offset of the wafer relative to the multi-region data mask is different in different printing steps. Therefore, from the same data mask Data graphics are printed into data entry films of different memory layers and different digital bits. Figure 17 discloses an example of this. The x2x2 3D-oP 18e contains two storage layers 16A, 16B And each memory element stores two digital bits: the 1st and 2nd digits. This embodiment contains four data entry films which respectively store the following digital array: the first digital bit storage in the storage layer 16A p[1,1] ; the second digit in the storage layer 16A stores p[1,2]; the first digit in the storage layer 16B stores p[2,1]; the second in the storage layer 16B The digital bit stores p[2,2].

The left-hand diagram in Figure 18 shows the multi-region data mask 8 used by the x2x2 3D-oP 18. It contains 4 data mask areas, the digital array of which is m(1)-m(4). The origin of the multi-region data mask 8 is O M . The graph on the right in Figure 18 shows all of the chips D[1]-D[4] in an exposure field E on a 3D-oP wafer 9. The origin of each of these chips is O 1 -O 4 . Since the chips D[1]-D[4] are offset by a data mask 8, they belong to the same 3D-oP batch.

Figure 19 shows the digital array stored on each data entry film on each chip after each print step of the x2x2 3D-oP 18. Column 3 of the table lists the chip origins at which O M is aligned at each printing step. The four data entry films of this embodiment require four printing steps. In the first printing step (forming p[1,1]), O M is aligned with the origin O 1 of chip D[1], and the digital array p[1,1] of chip D[1]-D[4] They are m(1)-m(4) respectively. At the second printing step (forming p[1, 2]), O M is aligned with the origin O 2 of the chip D[2]. As long as the step distance D y in the y direction is twice the distance d y of the chip D[1] and D[2], ie D y =2d y , the digital array p of the chip D[1]-D[4] [1,2] are m(2), m(1), m(4), m(3), respectively. At the third printing step (forming p[2, 1]), O M is aligned with the origin O 3 of the chip D[3]. As long as the stepping distance D x is the x-direction chip D [3], and D [1] 2 x times the distance D, i.e., D x = 2d x, the chip D [1] -D [4] The digital array p [2,1] are m(3), m(4), m(1), m(2), respectively. At the 4th printing step (forming p[2, 2]), O M is aligned with the origin O 4 of the chip D[4]. As long as D y = 2d y and D x = 2d x , the digital array p[2, 2] of the chip D[1]-D[4] is m(4), m(3), m(2), respectively. m(1).

 In summary, for the chip D[1]-D[4] in Figure 18, the digital array sequence can be expressed as:

S D[1] = (p D[1] [1,1], p D[1] [1,2], p D[1] [2,1], p D[1] [2,2] ) = (m(1), m(2), m(3), m(4));

S D[2] = (p D[2] [1,1], p D[2] [1,2], p D[2] [2,1], p D[2] [2,2] ) = (m(2), m(1), m(4), m(3));

S D[3] = (p D[3] [1,1], p D[3] [1,2], p D[3] [2,1], p D[3] [2,2] ) = (m(3), m(4), m(1), m(2));

S D[4] = (p D[4] [1,1], p D[4] [1,2], p D[4] [2,1], p D[4] [2,2] ) = (m(4), m(3), m(2), m(1));

As can be seen from these expressions, the 3D-oP chip D[1]-D[4] All have the same set of digital arrays, but can have different digital array sequences.

 Figure 20 shows the circuit block diagram of the x2x2 3D-oP 18. The figure shows the input address decoder 20I And output buffer 20O. They have the same function as the input address decoder 20I and the output buffer 20O in Figs. 16A and 16B. 3D heap 16 storage 4 digital arrays p[1,1]-p[2,2] . The input/output circuit can be set. 24 According to the information related to the sequence of the digital array, the external input address 28 can be changed, or the internal output can be changed. 26: For the chip For D[1], there is no change; for chip D[2], the output digital bit order of each output group (such as 21) in output buffer 20O is exchanged; for chip D[3] For example, the internal input address 26 is the opposite of the highest bit of the external input address 28; for chip D[4], the internal input address 26 and the external input address 28 The highest bit is reversed, and the output digits of each output group (such as 21) in the output buffer 20O are sequentially swapped.

The offset printing technology can be used not only in the data entry film of a single chip, but also in the data entry film of a plurality of chips. Accordingly, the present invention proposes a three-dimensional memory based on the 3D-oP package (3D-oP-based three- dimensional package, referred to as 3D 2 -oP). 3D 2- oP packages are typically distributed as a memory card. Similarly, mask patterns of multiple memory layers/digital bits in multiple chips are combined into a multi-region data mask. In different printing steps, the offset of the wafer relative to the multi-region data mask is different. Therefore, data patterns from the same data mask are printed into different memory layers/digital bits of different chips in the 3D 2- oP package.

Figure 21 shows an x3x3x1 3D 2 -oP package 38 . Here, the xKxMxn 3D 2 -oP package represents a memory package containing K stacked xMxn 3D-oP chips. Specifically, this embodiment contains three 3D-oP chips C 1 - C 3 . They are stacked vertically on a package substrate (e.g., interposer) 30 and form a 3D-oP stack 36. The lead 32 is C 1 -C 3 chip and the package substrate 30 is coupled. In order to improve its data security, it is preferable to fill the molding compound 34 in the 3D 2 -oP package 38.

Figure 22 is a circuit block diagram of the 3D 2- oP package 38. 3D-oP stack 36 which contains an array of digital 9, wherein each of the chips C 1 -C 3 contains three digital array p [1] -p [3] . It also contains a configurable input/output circuit 24 that functions similarly to that of Figure 20. The settable input/output circuitry 24 can be located in the 3D-oP chip and/or in the control chip.

The left-hand side of Figure 23 shows the multi-region data mask used in the 3D 2- oP package 38. It contains 9 data mask areas and represents the digital array m(1)-m(9), respectively. The origin of the multi-region data mask 8 is O M . The picture on the right in Figure 23 is all the chips D[1]-D[9] in an exposure field E in a 3D-oP wafer 9. Wherein, the origins of the chips D[1]-D[3] are respectively O 1 -O 3 .

Figure 24 shows the digital array in each data entry film on each chip after each printing step of the 3D 2- oP package 38. Column 3 of the table lists the chip origins at which O M is aligned at each printing step. The three data entry films of this embodiment require three printing steps. In the first printing step (forming p[1]), O M is aligned with the origin O 1 of the chip D[1], and the digital array p[1] of the chip D[1]-D[9] is m ( 1)-m(9). At the second printing step (forming p[2]), O M is aligned with the origin O 2 of the chip D[2]. As long as D y =3d y1 =3d y2 , the digital array p[2] of the chip D[1]-D[9] is m(3), m(1), m(2), m(6), respectively. m(4), m(5), m(9), m(7), m(8). At the third printing step (forming p[3]), O M is aligned with the origin O 3 of the chip D[3]. As long as D y = 3d y1 = 3d y2 , the digital array p[3] of the chip D[1]-D[9] is m(2), m(3), m(1), m(5), respectively. m(6), m(4), m(8), m(9), m(7).

Figure 25 lists three 3D 2 -oP packages M[1]-M[3] in a 3D 2- oP batch. The three 3D 2- oP packages M[1]-M[3] are composed of the nine chips in Figure 23: 3D 2 -oP package M[1] contains chips D[1], D[4], D [7] ; 3D 2 -oP package M[2] contains chips D[2], D[5], D[8] ; 3D 2 -oP package M[3] contains chips D[3], D[6] , D[9]. Because these 3D 2 -oP packages M[1]-M[3] are formed by the same data mask 8 offset printing, they belong to the same 3D 2 -oP batch.

In summary, for the 3D 2 -oP package M[1]-M[3] in Figure 20, the digital array sequence can be expressed as:

S M[1] = (S D[1] , S D[4] , S D[7] ) = (m(1), m(3), m(2); m(4), m(6 ), m(5); m(7), m(9), m(8));

S M[2] = (S D[2] , S D[5] , S D[8] ) = (m(2), m(1), m(3); m(5), m(4 ), m(6); m(8), m(7), m(9));

S M[3] = (S D[3] , S D[6] , S D[9] ) = (m(3), m(1), m(1); m(6), m(5 ), m(4); m(9), m(8), m(7));

Where {S M[1] } = {S M[2] } = {S M[3] } , but S M[1] ≠ S M[2] ≠ S M[3] .

As can be seen from these expressions, the 3D 2 -oP packages M[1]-M[3] all have the same set of digital arrays, but they can have different digital array sequences.

 3D writable print memory

 In order to be able to write custom data in 3D-P, the present invention also proposes a three-dimensional writable imprint memory (3D-wP). It contains a printed storage array and a write storage array. The print storage array stores content data. Content data is a publication (including movies, video games, maps, music libraries, library, software, etc.) The data is entered by the imprint method. The printing method is a parallel data entry method, which mainly includes photolithography and imprinting. Write storage array storage Custom data. Custom data includes custom information such as chip serial number and key. Custom data is entered by writing. The write method is a serial data entry method, which mainly includes direct writing photolithography, such as electron beam lithography, laser beam lithography or focused particle beam lithography. In the same batch In 3D-wP, all memories store the same content data, but can store different custom data.

 Figure 26A and Figure 26B show two chips 18f, 18g in the same 3D-wP batch. in a In the 3D-wP batch, all chips are made from the same mask. In this embodiment, chips 18f, 18g store the same content data, but store different custom data. Every 3D-wP The chip (e.g., 18f) contains a semiconductor substrate 0 and a three-dimensional stack (e.g., 16f) stacked on the substrate 0. The transistor on the substrate 0 and its interconnect lines constitute the substrate layer 0K. Three-dimensional heap 16f There are two storage layers 16A, 16B whose storage elements are generally based on diode 3d.

 Storage layer 16A contains a printed storage array 11A (including storage elements 5ac-5af) and a write storage array 13A (including storage elements 5aa, 5ab), storage layer 16B contains only one print storage array 11B. Wherein, the print storage array 11A, 11B stores content data . Content data is data for publications (including movies, video games, maps, music libraries, library, software, etc.) that are entered by imprinting. The printing method is a parallel data entry method, which is mainly It should include photolithography and imprinting.

 On the other hand, the write storage array 13A stores custom data. Custom data includes custom information such as chip serial number and key. Custom data Enter by means of writing. The write method is a serial data entry method, which mainly includes direct writing photolithography, such as electron beam lithography, laser beam lithography or focused particle beam lithography. Direct write lithography does not require a data mask.

For the chip 18f in Fig. 26A, the digital array P 18f [1] stored in the data recording film 6A in the memory layer 16A includes the print digital array p 18f [1] and the write digital array w 18f [1] , that is, P 18f [1]= p 18f [1]+ w 18f [1] . Among them, the printed digital array p 18f [1] is stored in the print storage array 11A, and the write digital array w 18f [1] is stored in the write storage array 13A.

On the other hand, since the storage layer 16B does not contain the write storage array, the digital array P 18f [2] stored in the data entry film 6B is only the printed digital array p 18f [2], that is, P 18f [2] = p 18f [2] . In summary, the printed digital array sequence of chip 18f can be expressed as: S 18f = (p 18f [1], p 18f [2]) .

Similarly, for the chip 18g in Fig. 26B, the digital array P 18g [1] stored in the data recording film 6A in the memory layer 16A includes the printed digital array p 18g [1] and the write digital array w 18g [1] , That is, P 18g [1] = p 18g [1] + w 18g [1] . The digital array P 18g [2] stored in the data recording film 6B in the storage layer 16B is the printed digital array p 18g [2], that is, P 18g [2] = p 18g [2]. The sequence of the printed digital array is: S 18g = (p 18g [1], p 18g [2]).

In the same 3D-wP batch, since all chips 18f and 18g are manufactured by the same mask, they store the same content data and all contain the same set of printed digital arrays, ie {S 18f }= {S 18g } . In the data entry process, if the conventional printing method is used, the printed digital array sequences S 18f and S 18g of the chips 18f and 18g should be the same. If the offset printing method is employed, the printed digital array sequences S 18f , S 18g of the chips 18f and 18g may be different.

On the other hand, in the same 3D-wP batch, chips 18f, 18g can store different custom data. Their write storage array 13A can store different write digital arrays w 18f [1] , w 18g [1] . For example, in the write storage array 13A of the chip 18f, the storage element 5aa stores '1', the storage element 5ab stores '0' (Fig. 26A), and in the write storage array 13A of the chip 18g, the storage element 5aa is stored. ' 0 ', the storage element 5ab stores ' 1 ' (Fig. 26B). Although the data stored in the write storage array 13A is different, since the mask data is not required for writing the customized data, the chips 18f and 18g still belong to the same 3D-wP batch.

Although the writing method can be used to enter custom data, its writing efficiency is very low. Even with multi-beam direct write technology, the writing efficiency is about one wafer per hour (see Kampherbeek, ' High throughput maskless lithography' ), which is slower than the print method 100 Times. In order to maintain capacity, the total amount of data for custom data should be limited. At least the time spent on writing should be no longer than the time spent on printing. That is, the total amount of data for custom data should be less than 1% of the total amount of data. .

 Figure 27A - Figure 27D are shown in Figure 26A and Figure 26B The steps of entering content data and custom data in the embodiment. It consists of two data entry steps: the print step and the write step. After forming the isolation dielectric film 3b, a photoresist 3p is formed on the surface of the wafer. . The printing step records the content data into the photoresist 3p by photolithography or imprinting (Fig. 27A). For example, photolithography will pass through a data mask in memory cells 5ad, 5af The photoresist is exposed. Then, the writing step re-records the custom data into the photoresist 3p by direct write lithography (Fig. 27B). ). Direct write lithography does not require a data mask, which uses a controllable beam (such as an electron beam, a laser beam, or a focused particle beam) to place the photoresist 3p one bit (eg, memory cell 5ab). Exposure. After the above two data entry steps are completed, the photoresist 3p is developed (Fig. 27C). At this time, in the storage elements 5af, 5ad, 5ab The photoresist at the place is cleaned up. Then, an etching step removes the exposed isolation dielectric film 3b (Fig. 27D). After these steps, the content data and the customized data are entered into the data entry film of the storage layer 16A. In 6A.

 Figure 28 shows another 3D-wP chip 18h. In this embodiment, the storage layers 16A, 16B All contain only the print storage arrays 11A, 11B. The write memory array 13 is formed in the substrate layer 0K. Its memory elements 0c1 and 0c2 are based on transistors. Substrate layer 0K Contains at least one data entry film 0V1: the presence of channel hole 0v1 indicates '1', and if it does not, it indicates '0'. By writing data in the data entry film 0V1, the memory element 0c1, 0c2 can store custom data. Note that the minimum feature size P of the channel hole 0v1 can be much larger than the minimum feature size of the data opening 6ca in the storage layer 16A p . In this way, even if the printed memory array uses more advanced memory technologies (such as p=44nm), the write storage array can still use the backward technology (such as P=2um). ). The advantage of this method is that a relatively inexpensive writing technique, such as laser beam lithography, can be used to directly write data.

 Figure 29 shows the data entry step for implementing the embodiment of Figure 28. It includes the writing steps 61, 63 and the printing step 65 67. First, the custom data is written to the data entry film 0V1 of the substrate layer 0K (step 61). ). This step does not require a data mask, which uses a controllable beam (such as an electron beam, a laser beam, or a focused particle beam) to write the data bit by bit. In forming the write storage array 13 (step 63 After that, the content data is printed to the data entry film 6A of the storage layer 16A (step 65). This printing step uses a data mask and forms the print storage array 11A (step 67 ).

 Figure 30 shows a 3D-wP 18C with good data security. It contains a printed memory array 11 , a write storage array 13 and a encryption logic 17 . They are best integrated in a 3D-wP chip. Print Storage Array 11 Store Content Data, Write Storage Array 13 Store the 3D-wP The key to the chip 18C. In order to enhance the security of data, the keys of different chips are preferably different. Although the same 3D-wP All chips in the batch store the same content. Since the output of each chip is encrypted by a different key, the output data of different 3D-wP are different. In order to prevent reverse design, at least part of the write storage array 13 is located The highest storage layer of the 3D-wP chip is below 16B, as in the lower memory layer 16A, or in the substrate layer 0K. Write storage array in addition to the key 13 It is also possible to store the chip serial number or information related to the printed digital array sequence.

Industrial applicability

 Finally, an overview of semiconductor memories suitable for mass publishing is presented here. 3D read only memory (3D-ROM) ) is the ideal medium for mass publishing. Three-dimensional electrical programming read-only memory (3D-EPROM, also known as three-dimensional write memory) has long been considered superior to 3D-P. 3D-EPROM Use 'write' to enter data. Since 'write' is a serial data entry method, 3D-EPROM write speed is very slow. For example, three-dimensional one-time programming memory developed by Sandisk (3-D OTP has a write speed of only 1.5MB/s. It takes a long time to enter a movie: ~0.5 hours to enter a DVD format movie (~4GB), or ~3 hours to enter a movie Movies in BD format (~20GB); if you want to enter 1TB of data, it takes a week! Such long entry times can result in high entry costs, resulting in 3D-EPROM Not suitable for mass publishing. This has been ignored by most people in the past.

 On the other hand, 3D-P Enter data by 'print'. 'Print' is a parallel data entry method. It includes photolithography and imprinting. These technologies are large-scale industrial printing technologies, and can record large amounts of data into a large number of chips in a short time. For example, in At 22nm, a single exposure can be entered in ~155GB Data. As a summary, similar to traditional paper media (picture books, newspapers, magazines) and plastic media (such as CDs), semiconductor memory should choose 'print' rather than 'write' to achieve mass publishing.

It is to be understood that the form and details of the invention may be modified without departing from the spirit and scope of the invention. Embodiments of the present invention are primarily directed to photolithography, which can be applied to imprint methods. Therefore, the invention should not be limited in any way by the spirit of the appended claims.

Claims (27)

  1.  A method of manufacturing a three-dimensional printing memory, comprising the steps of:
    1) forming a substrate circuit on a semiconductor substrate;
    2) forming a bottom address line above the substrate circuit;
    3 Forming a layer of data entry film on the bottom address line, and converting the data pattern from a data mask to the data entry film by printing;
    4) forming a top address line on the data entry film;
    5) repeating steps 2) - 4) forming another storage layer;
    Wherein the data pattern represents data stored in the memory, and the minimum half period of the address line is less than 45 nm The minimum feature size of the data mask is greater than a minimum half period of the address line, and the data mask carries a plurality of different mass publications.
  2. A method of manufacturing a mask programming read-only memory (mask-ROM), comprising the steps of:
    1) forming a layer of data entry film;
    2) converting the data pattern from a data mask to the data entry film by printing;
    3) forming a plurality of address lines coupled to the data entry film;
    Wherein the data pattern represents data stored in the memory, and the minimum half period of the address line is less than 45 nm The minimum feature size of the data mask is greater than a minimum half period of the address line, and the data mask carries a plurality of different mass publications.
  3. According to claims 1 and 2 The memory manufacturing method is further characterized in that all the mass publications in the data mask are not repeated.
  4. The memory manufacturing method according to claims 1 and 2, characterized in that said printing method comprises photolithography and imprinting.
  5. A three-dimensional imprinting memory, comprising:
    a semiconductor substrate;
    a plurality of storage layers stacked on and coupled to the substrate, the plurality of storage layers being stacked on each other, each storage layer containing at least one layer of data entry film, the graphics in the data entry film representing stored data, The minimum feature size of the storage layer is less than 45nm ;
    This memory stores data for a number of different mass publications.
  6. A method of manufacturing an imprint memory, comprising the steps of:
    1) forming a data entry film;
    2) converting the data pattern from a data template to the data entry film by imprinting;
    3) forming a plurality of address lines coupled to the data entry film;
    Wherein, the data graphic represents data stored in the memory, and the data pattern has a nanometer scale and does not have microscale periodicity.
  7. The memory manufacturing method according to claim 6, wherein the data pattern has a size of from 1 nm to 100 Between the nanometers.
  8. The memory manufacturing method according to claim 6, wherein the imprint memory is a three-dimensional imprint memory.
  9. The memory manufacturing method according to claim 6, wherein the imprint memory is a cross point array memory.
  10. The memory manufacturing method according to claim 6, wherein the imprint method is a nanoimprint method.
  11.  A memory manufacturing method according to claim 6, wherein said data template contains a plurality of protrusions.
  12. A three-dimensional offset printing memory, comprising:
    a semiconductor substrate;
    a plurality of storage layers stacked on and coupled to the substrate, the plurality of storage layers being stacked on each other, each storage layer comprising at least one layer of data entry film, the graphic in the data entry film representing a digital array;
    An input/output can be set, and the settable input/output sets the input of the memory according to the sequence of the digital array in the memory / Output.
  13. According to claim 12 The memory is further characterized by: a storage means for storing information related to the sequence of the digital array.
  14. A three-dimensional offset printing memory, comprising:
    a semiconductor substrate;
    a plurality of storage layers stacked on and coupled to the substrate, the plurality of storage layers being stacked on each other, each storage layer comprising at least one layer of data entry film, the graphic in the data entry film representing a digital array;
    In the same batch of the three-dimensional offset print memory, all memories contain the same set of digital arrays; in at least two memories, the digital array sequence is different.
  15. The memory of claim 14 further characterized by:
    The first and second memories are included in the batch, the first and second memories each include a first and a second storage layer, and the second storage layer is located above the first storage layer;
    The first storage layer in the first memory stores a first digital array, and the second storage layer in the first memory stores a second digital array;
    The first storage layer in the second memory stores a second data pattern, and the second storage layer in the second memory stores a first data pattern.
  16. The memory of claim 14 further characterized by:
    The batch contains first and second memories, each of the first and second memories including a storage layer containing first and second data entry films, the first data entry film being located The second data is recorded on the film; wherein
    The first data entry film in the first memory stores a first digital array, and the second data entry film in the first memory stores a second digital array;
    The first data entry film in the second memory stores a second digital array, and the second data entry film in the second memory stores a first digital array.
  17. According to claim 14 The memory is part of a three-dimensional memory package, and the three-dimensional memory package is further characterized by: a plurality of three-dimensional offset printing memories stacked on each other.
  18. A method of manufacturing a three-dimensional offset printing memory, comprising the steps of:
    1) forming a substrate circuit on a semiconductor substrate;
    2 Forming a memory layer above the substrate circuit, the memory layer comprising at least a first data entry film, the first position of the substrate and a data graphics carrier when the data pattern is formed in the first data entry film quasi;
    3 Forming a second data entry film over the first data entry film, the substrate being aligned with the second position of the data pattern carrier when the data pattern is formed in the second data entry film.
  19. According to claim 18 The memory manufacturing method is further characterized in that the number of data graphics carrying devices required for the memory is smaller than the number of data recording films in the memory.
  20. According to claim 18 The memory manufacturing method is further characterized in that the data graphics carrying device is a data mask or a data template.
  21. A three-dimensional writable print memory, characterized by comprising:
    a semiconductor substrate;
    a plurality of memory layers stacked on and coupled to the substrate, the plurality of memory layers being stacked on each other, the memory layer comprising a plurality of printed memory arrays, the graphics in the printed memory array representing content data;
    Writing a storage array, the graphics in the write storage array representing customized data;
    The total amount of data of the customized data is less than 1% of the total amount of data of the content data.
  22. The memory of claim 21 further characterized by: said 3D-wP in the same batch All of the memories store the same content data, and at least two memories store different custom data.
  23.  A memory according to claim 21, wherein said write storage array is located below said highest storage layer of said storage layer .
  24. According to claim 21 The memory is further characterized in that a minimum feature size of the data entry film in the write storage array is larger than a minimum feature size of the data entry film in the record storage array.
  25. A method of manufacturing a three-dimensional writable print memory, comprising the steps of:
    1) forming a transistor on a semiconductor substrate;
    2) Entering customized data by direct writing lithography;
    3) recording content data in a plurality of mutually stacked storage layers by a printing method, the plurality of storage layers being stacked on and coupled to the substrate;
    The total data amount of the customized data is less than 1% of the total data amount of the content data.
  26. According to claim 25 The memory manufacturing method is further characterized in that the direct write photolithography comprises electron beam lithography, laser beam lithography or focused particle beam lithography.
  27. A memory manufacturing method according to claim 25, wherein said printing method comprises photolithography and imprinting.
PCT/CN2012/080895 2011-09-01 2012-09-02 Three-dimensional recorded memory WO2013029564A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US201161529920P true 2011-09-01 2011-09-01
US201161529919P true 2011-09-01 2011-09-01
US201161529922P true 2011-09-01 2011-09-01
US61/529,922 2011-09-01
US61/529,920 2011-09-01
US61/529,919 2011-09-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201280042212.5A CN103875059B (en) 2011-09-01 2012-09-02 Three-dimensional print records reservoir

Publications (1)

Publication Number Publication Date
WO2013029564A1 true WO2013029564A1 (en) 2013-03-07

Family

ID=47755346

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/080895 WO2013029564A1 (en) 2011-09-01 2012-09-02 Three-dimensional recorded memory

Country Status (2)

Country Link
CN (1) CN103875059B (en)
WO (1) WO2013029564A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812506B1 (en) 2016-04-13 2017-11-07 Western Digital Technologies, Inc. Nano-imprinted self-aligned multi-level processing method
CN107978516A (en) * 2016-10-24 2018-05-01 杭州海存信息技术有限公司 The three-dimension packaging of reservoir is recorded based on three-dimensional biasing print

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104835822B (en) * 2012-09-02 2018-02-09 杭州海存信息技术有限公司 Three-dimensional biasing print records reservoir
CN103681679A (en) * 2012-08-30 2014-03-26 成都海存艾匹科技有限公司 Three-dimensional offset-printed memory
CN103681674A (en) * 2012-09-01 2014-03-26 成都海存艾匹科技有限公司 Three-dimensional printed memory
DE102014115253A1 (en) 2014-10-20 2016-04-21 Osram Opto Semiconductors Gmbh Process for structuring a layer sequence and semiconductor laser device
CN107357551A (en) * 2016-05-10 2017-11-17 成都海存艾匹科技有限公司 For realizing the processor of at least two class functions

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1099695C (en) * 1998-09-24 2003-01-22 张国飙 Three-dimensional read-only memory
CN1487362A (en) * 2002-09-17 2004-04-07 惠普开发有限公司 Impression mask photoetching
US20070121375A1 (en) * 2005-11-29 2007-05-31 Asml Holding N.V. System and method for forming nanodisks used in imprint lithography and nanodisk and memory disk formed thereby
CN101840996A (en) * 2009-03-20 2010-09-22 德晶电子(江苏)有限公司 Printed semiconductor transistor and forming method thereof
US20110019459A1 (en) * 2007-01-11 2011-01-27 Guobiao Zhang Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1099695C (en) * 1998-09-24 2003-01-22 张国飙 Three-dimensional read-only memory
CN1487362A (en) * 2002-09-17 2004-04-07 惠普开发有限公司 Impression mask photoetching
US20070121375A1 (en) * 2005-11-29 2007-05-31 Asml Holding N.V. System and method for forming nanodisks used in imprint lithography and nanodisk and memory disk formed thereby
US20110019459A1 (en) * 2007-01-11 2011-01-27 Guobiao Zhang Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space
CN101840996A (en) * 2009-03-20 2010-09-22 德晶电子(江苏)有限公司 Printed semiconductor transistor and forming method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812506B1 (en) 2016-04-13 2017-11-07 Western Digital Technologies, Inc. Nano-imprinted self-aligned multi-level processing method
US9929214B2 (en) 2016-04-13 2018-03-27 Western Digital Technologies, Inc. Nano-imprinted self-aligned multi-level processing method
CN107978516A (en) * 2016-10-24 2018-05-01 杭州海存信息技术有限公司 The three-dimension packaging of reservoir is recorded based on three-dimensional biasing print

Also Published As

Publication number Publication date
CN103875059A (en) 2014-06-18
CN103875059B (en) 2016-09-07

Similar Documents

Publication Publication Date Title
US20160254223A1 (en) Coarse Grid Design Methods and Structures
US9673195B2 (en) Semiconductor device having sufficient process margin and method of forming same
Neisser et al. ITRS lithography roadmap: 2015 challenges
CA1292313C (en) Electronic camera
CN101903991B (en) Methods for isolating portions of a loop of pitch-multiplied material and related structures
US7418902B2 (en) Imprint lithography including alignment
EP1688790B1 (en) Imprint lithography
US7214624B2 (en) Resist pattern forming method, magnetic recording medium manufacturing method and magnetic head manufacturing method
US6563568B2 (en) Multiple image reticle for forming layers
JP4712370B2 (en) Composite stamper for imprint lithography
US7582921B2 (en) Semiconductor device and method for patterning
RU2208267C2 (en) Data storage and processing device and its manufacturing process
JP4870810B2 (en) Imprint mold and imprint mold manufacturing method
Isaac The future of CMOS technology
US8127265B2 (en) Pattern verification method, program thereof, and manufacturing method of semiconductor device
US5657235A (en) Continuous scale optical proximity correction by mask maker dose modulation
US6426269B1 (en) Dummy feature reduction using optical proximity effect correction
CN101946282B (en) Magnetic domain patterning using plasma ion implantation
US7304364B2 (en) Embossed mask lithography
KR100378195B1 (en) Generation method of data for used in mask including dummy pattern groups having density continuously adjusted in according to density of local design pattern and recording media in which the same recorded
DE60121785T2 (en) Active tft matrix for an optical sensor with a light-sensitive semiconductor layer, and optical sensor with such a matrix
US7537866B2 (en) Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US9224851B2 (en) Planarized semiconductor particles positioned on a substrate
US20120119321A1 (en) Topography based patterning
US8187797B2 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12827140

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12827140

Country of ref document: EP

Kind code of ref document: A1