CN107978516A - Three-dimensional package based on three-dimensional offset printed memory - Google Patents
Three-dimensional package based on three-dimensional offset printed memory Download PDFInfo
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- CN107978516A CN107978516A CN201610927271.0A CN201610927271A CN107978516A CN 107978516 A CN107978516 A CN 107978516A CN 201610927271 A CN201610927271 A CN 201610927271A CN 107978516 A CN107978516 A CN 107978516A
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- 238000009825 accumulation Methods 0.000 claims description 60
- 238000005538 encapsulation Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 11
- 238000001459 lithography Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 description 41
- 238000010586 diagram Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- 239000007943 implant Substances 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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Abstract
The invention provides a three-dimensional package (3D-oP) based on a three-dimensional offset printed memory (3D-oP)2-oP). The data mask patterns in different 3D-oP chips are combined on the same data mask. The offset of the wafer relative to the data mask is different in different imprinting steps. Therefore, data patterns from the same data mask are printed into the data recording films of different 3D-oP chips.
Description
Technical field
The present invention relates to integrated circuit memory field, more precisely, being related to masking film program read-only memory（mask-
ROM）.
Background technology
Three-dimensional masking film program read-only memory（3D-MPROM）It is to realize the ideal medium that magnanimity is published.United States Patent (USP) 5,
835,396 disclose a kind of 3D-MPROM.As shown in Figure 1,3D-MPROM is a kind of monolithic integrated optical circuit, it contains semiconductor
Substrate 0 and one is stacked on the three-dimensional heap 10 on substrate.The three-dimensional heap 10 contains M（M≥2）A accumulation layer being stacked with（Such as
10A、10B）.Each accumulation layer（Such as 10A）Contain a plurality of top address line（Such as 2a）, bottom address wire（Such as 1a）With storage member（Such as
5aa）.Each storage member storage n（n≥1）Position data.Accumulation layer（Such as 16A, 16B）By contacting access opening（Such as 1av, 1 ' av）
Coupled with substrate 0.Substrate circuitry 0X in substrate 0 contains the peripheral circuit of three-dimensional heap 10.In this application, xMxn 3D-
MPROM refers to that contains a M（M≥2）A accumulation layer, and each storage member storage n（n≥1）The 3D-MPROM of position.
3D-MPROM is a kind of cross point memory based on diode.Each storage member（Such as 5aa）Typically contain one
Diode 3d.Diode can be using generalized definition as any two end device having the property that：When the size of its suffered voltage
Less than read voltage, or when the direction of its suffered voltage is different from read voltage, its resistance is more than the resistance under read voltage.Each
Accumulation layer（Such as 10A）Also at least contain a layer data typing film（Such as 6A）.Figure in data inputting film is datagraphic, its generation
Its data for being stored of table.In Fig. 1, data inputting film 6A is one layer of spacer medium 3b, it stops top address Xian Hedi addresses
Electric current flowing between line, and pass through data opening（Such as 6ca）Presence or absence come distinguish storage member（Such as 5ca）Different shapes
State.
Figure in data inputting film is got by figure conversion.Figure is changed, also known as print record（print）, will
Figure is transformed into the film of one layer of integrated circuit from one piece of mask plate.In the prior art, the datagram in different accumulation layers
Shape be by different pieces of information mask plate print record Lai.Fig. 2A-Fig. 2 B represent data mask version 4A, 4B that two conventional art uses.
Per block number according to mask plate（Such as 4A）Contain mask element array " aa "-" bd ".The bright or dark decision of figure at each mask member
The presence or absence of data opening at corresponding storage member.Such as say, the mask open 4ca on data mask version 4A causes accumulation layer
The data opening 6ca of member 5ca is stored in 10A；The aa of mask open 4 ', 4 ' da on data mask version 4B cause in accumulation layer 10B
Store 5 ' aa of member, 6 ' aa of data opening, the 6 ' da of 5 ' da.
In order to further improve storage density, 3D-MPROM can use n（n>1）Bit, i.e., each storage member storage n
Data.U.S. Patent Application Serial Number 12/785,621 discloses a kind of 3D-MPROM using more bits.As shown in figure 3, its
Storage member（Such as 5aa）It is 2 bits, i.e., it stores two figure cases：1st and the 2nd figure case.Wherein, the 1st figure case passes through
One time extra implant is realized, and the 2nd figure case is realized by one layer of resistive film.In this application, j-th of figure case represents one
N bits（The storage member of n figure case of storage, n >=j）The jth position of middle storage.
In the prior art, the datagraphic of different figure cases be by different pieces of information mask plate print record Lai.Fig. 4 A- Fig. 4 B
Represent data mask version 4C, 4D that two conventional art uses.Per block number according to mask plate（Such as 4C）Contain a mask element array
“aa”-“bd”.The presence that is bright or secretly determining extra implant film or resistive film at corresponding storage member of figure at each mask member
Whether.Such as say, the mask open 4xa* on data mask version 4C results in the extra implant film in storage member 5ca, 5da
3i；The ba* of mask open 4 ', 4 ' da* on data mask version 4D cause to remove the resistive film 3r in storage member 5ba, 5da.
In the prior art, since each accumulation layer and each figure case are required to a block number according to mask plate, xMxn 3D-
MPROM generally requires M × n block numbers according to mask plate.In 22nm nodes, a block number is 250,000 dollars according to the cost of mask plate, a set of
Data mask version needed for x8x2 3D-MPROM（Including 16 block numbers according to mask plate）It is of high cost up to 4,000,000 dollars.It is so high
Data mask version cost will greatly limit the extensive use of 3D-MPROM.
The content of the invention
The main object of the present invention is to provide a kind of 3D-MPROM with lower data typing cost.
It is a further object of the present invention to provide a kind of method of reduction data mask version number needed for 3D-MPROM.
According to these and other purpose, the present invention proposes that a kind of three-dimensional biasing print records reservoir（three-
Dimensional offset-printed memory, referred to as 3D-oP）.3D-oP is a kind of improved 3D-MPROM, it is logical
Cross biasing print record and carry out logging data.In order to realize biasing print record, it is merged corresponding to the mask pattern of different accumulation layer/figure cases
Onto a multizone data mask version.In different print steps, wafer relative to the multizone data mask version biasing
Amount is different.Therefore, the mask pattern from same data mask version is by the data inputting film of print record to different accumulation layer/figure cases
In.Biasing print record can reduce the quantity of data mask version needed for memory, so as to reduce data inputting cost.In the present invention,
Mask plate can refer to the figure bogey that any print record technique uses, including masterplate.
In same 3D-oP batches, all 3D-oP chips print record by same set of data mask version.Although chip it
Between may have different digital array sequences, but all chips are respectively provided with same digital array set.Here, digital array
It is the array being made of a datagraphic in the digital value representated by the position corresponding to each storage member；Digital array sequence
Refer to all digital arrays in a 3D-oP chip（Digital array including all accumulation layers and all figure cases）According to a bit
Sequentially（Such as according to the distance from substrate）And the sequence formed；Digital array set refers to all number battle arrays in the 3D-oP chips
The set of row.As its name suggests, set is only related with its contained element, unrelated with order.
In order not to allow user to perceive the difference of digital array sequence, 3D-oP preferably can set input/output containing one
（configurable input/output）.For different chip in same 3D-oP batches, this can set input/output according to
Its digital array sequence sets the input/output of the chip.Relative to the 3D-oP chips of a reference, if this 3D-oP core
The digital array order for having two accumulation layers in piece is exchanged with each other, then input/output can be set to need to change the 3D-oP cores
At least part input address of piece；If the digital array order for having two figure cases in this 3D-oP chip is exchanged with each other,
Input/output can be then set to change the order of at least part carry-out bit in 3D-oP chips output.
Brief description of the drawings
Fig. 1 is the sectional view of x2x1 3D-MPROM line of cut AA ' along Fig. 2A-Fig. 2 B a kind of.
Two block numbers that Fig. 2A-Fig. 2 B represent to use in conventional x2x1 3D-MPROM technologies are according to mask plate.
Fig. 3 is the sectional view of x1x2 3D-MPROM line of cut BB ' along Fig. 4 A- Fig. 4 B a kind of.
Two block numbers that Fig. 4 A- Fig. 4 B represent to use in conventional x1x2 3D-MPROM technologies are according to mask plate.
Fig. 5 A- Fig. 5 B represent a kind of two print steps for biasing and being used in print record method.
Fig. 6 is the simple case of a multizone data mask version.
Fig. 7 A- Fig. 7 B represent the digital array m that two data masked areas represent respectively in multizone data mask version
(1)、m(2)。
Fig. 8 A- Fig. 8 B are the sectional view of two 3D-oP chips 18a, 18b in same x2x1 3D-oP batches.
Fig. 9 A- Fig. 9 B represent the digital array p of two accumulation layer 16A, 16B storages in 3D-oP chips 18a18a[1]、p18a
[2]。
Figure 10 A- Figure 10 B are the sectional view of two 3D-oP chips 18c, 18d in same x1x2 3D-oP batches.
Figure 11 A- Figure 11 B represent the digital array p that the 1st and the 2nd figure case stores in 3D-oP chips 18c18c[1,1]、p18c
[1,2]。
Figure 12 represents a kind of circuit block diagram of 3D-oP.
Figure 13 A represent a kind of circuit block diagram of x2x1 3D-oP；Figure 13 B represent a kind of circuit block diagram of x1x2 3D-oP.
Figure 14 is a kind of sectional view of x2x2 3D-oP.
Figure 15 represents multizone data mask version used by a kind of x2x2 3D-oP, and the institute of an exposure on-site
There is chip.
After Figure 16 is listed in each print steps of x2x2 3D-oP, the number on each chip in each data inputting film
Array.
Figure 17 represents a kind of circuit block diagram of x2x2 3D-oP.
Figure 18 is a kind of x3x3x1 3D2The sectional view of-oP encapsulation.
Figure 19 represents a kind of 3D2The circuit block diagram of-oP encapsulation.
Figure 20 represents a kind of 3D2Multizone data mask version used by-oP is encapsulated, and the institute of an exposure on-site
There is chip.
Figure 21 is listed in 3D2After each print steps of-oP encapsulation, the number on each chip in each data inputting film
Array.
Figure 22 lists a 3D2Three kinds of 3D in-oP batches2- oP is encapsulated.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Embodiment
In order to reduce the number of data mask version, the present invention proposes that a kind of three-dimensional biasing print records reservoir（3D-oP）.It is logical
Cross biasing print record method and carry out logging data.Biasing print record method is the one kind printed in record method.Main print record method includes photoetching process
（photo-lithography）And stamped method（Imprint-lithography, also referred to as nano-imprint
Lithogrpahy, referred to as NIL）（Referring to Chinese patent application " three-dimensional print records reservoir "）：Photoetching process passes through data mask version
Carry out logging data；And imprint print record and pass through data masterplate（Template, also referred to as master, stamp or mold etc.）Carry out typing
Data.
Fig. 5 A- Fig. 5 B represent a kind of two print steps for biasing and being used in print record method.It uses one piece of multi-region numeric field data
Mask plate 8.In this embodiment, mask pattern of the multizone data mask version 8 containing two different accumulation layers 16A, 16B.It
Respectively be located at data mask version region 8a, 8b in.
Biasing print record method includes following two print steps.In the 1st print steps（See Fig. 5 A, such as the first accumulation layer of print record
The lithography step A of 16A）During beginning, the origin O of chip 18a18aWith the origin O of data mask region 8aMAlignment.In step of exposure
E1aWhen, data mask region 8a is recorded into chip 18a in the data inputting film 6A of accumulation layer 16A by print；In step of exposure E1b
When, data mask region 8b is recorded into chip 18b in the data inputting film 6A of accumulation layer 16A by print.
In the 2nd print steps（See Fig. 5 B, such as the lithography step B of the second accumulation layer 16B of print record）When, wafer 9 is relative to it
Alignment location bias in 1 print steps distance Sy.Use dyRepresent the distance between chip 18a and chip 18b.If
Sy=dy, then when the 2nd print steps start, the origin O of chip 18b18bWith origin OMAlignment.In step of exposure E2aWhen, data are covered
Diaphragm area 8a is recorded into chip 18b in the data inputting film 6B of accumulation layer 16B by print.
To next exposure place（exposure field）E2bDuring exposure, as long as step distance DyIt is dyTwice,
That is Dy=2dy, then data mask region 8b will be by print record into chip 18a in the data inputting film 6B of accumulation layer 16B.Finally, when
After completing above-mentioned two lithography step A, B, in chip 18a, data mask region 8a, 8b by print record to accumulation layer 16A,
In data inputting film 6A, 6B of 16B；In chip 18b, they are by data inputting film 6B, 6A of print record to accumulation layer 16B, 16A
In.
Fig. 6 is the simple case of a multizone data mask version 8.Each data mask region 8a, 8b contain one and cover
Membrane element array " aa "-" bd ".In the 8a of data mask region, the bright figure at mask first " ca ", " bb ", " ab " place forms mask
Be open 8ca, 8xb.In the 8b of data mask region, the bright figure at mask first " aa ", " da ", " bb " place forms mask open
8aa、8da、8bb.If using being defined as below：Dark mask pattern represents ' 0 ', and bright mask pattern represents ' 1 ', then data mask area
Digital value value in the 8a of domain representated by each mask member forms a digital array m (1)（Fig. 7 A）, it is every in the 8b of data mask region
Digital value representated by a mask member forms a digital array m (2)（Fig. 7 B）.
Fig. 8 A- Fig. 8 B represent two 3D-oP chips 18a, 18b in same x2x1 3D-oP batches.At a 3D-oP batches
In secondary, all chips are all manufactured by same a set of mask plate, they contain identical three-dimensional framework.Here, three-dimensional framework bag
All address wires in three-dimensional heap are included, but are free from data inputting film.In this embodiment, the data in chip 18a and 18b
Print and record by same data mask version 8.Fig. 8 A represent the x2x1 three-dimensional heaps 16a of chip 18a.The data inputting film of accumulation layer 16A
6A is printed by data mask region 8a to be recorded；The data inputting film 6B of accumulation layer 16B is printed by data mask region 8b to be recorded.Herein, use
It is defined as below：No data opening represents ' 0 ', has data opening to represent ' 1 '.Correspondingly, in 3D-oP chips 18a, accumulation layer
The digital value of all storage member storages forms the digital array p in Fig. 9 A in 16A18a[1], all storage members are deposited in accumulation layer 16B
The digital value of storage forms the digital array p in Fig. 9 B18a[2].As can be seen that digital array p18a[1] the digital battle array and in Fig. 7 A
It is identical to arrange m (1), i.e. p18a[1]= m(1)；Digital array p18a[2] the digital array m (2) and in Fig. 7 B is identical, i.e. p18a[2]=
m(2).On the other hand, Fig. 8 B represent the x2x1 three-dimensional heaps 16b of chip 18b.In chip 18b, the data inputting of accumulation layer 16A
Film 6A is printed by data mask region 8b to be recorded；The data inputting film 6B of accumulation layer 16B is printed by data mask region 8a to be recorded.Therefore, it is right
For chip 18b, p18b[1]= m(2)；p18b[2]= m(1)。
In the 3D-oP batches, all digital arrays of each 3D-oP chips（Including all accumulation layers and all numbers
The digital array of position）According to certain order（According to the distance from substrate, from closely to remote）One digital array sequence S of arrangement form.
The set of the digital array is referred to as digital array set { S }.According to the definition of set, set is only related with element therein,
It is unrelated with putting in order for element.For the chip 18a and 18b of Fig. 8 A- Fig. 8 B, their digital array sequence can be with table
Up to for：
S18a= (p18a[1], p18a[2]) = (m(1), m(2))；
S18b= (p18b[1], p18b[2]) = (m(2), m(1))；
Wherein, { S18a} = {S18b, but S18a ≠ S18b,
As can be seen that chip 18a and chip 18b has an identical data array set, but different data array sequences.For
Same data are read, it is necessary to different with 18b access chip 18a accumulation layer.
Biasing print record is also applied in the 3D-MPROM using n bits.Similarly, covering corresponding to different figure cases
Film pattern is integrated into a multizone data mask version.In different print steps, wafer is relative to the multi-region numeric field data
The amount of bias of mask plate is different.Therefore, the datagraphic from same data mask version is by the data of print record to different figure cases
In typing film.Figure 10 A- Figure 10 B represent two 3D-oP chips 18c, 18d in same x1x2 3D-oP batches.
Figure 10 A represent the x1x2 three-dimensional heaps 16c of chip 18c.Each storage member on accumulation layer 16C（Such as 5aa）Storage two
A figure case：1st and the 2nd figure case.1st figure case is stored by the first data inputting film 6C, it is one layer of extra implant film 3i；
2nd figure case is stored by the second data inputting film 6D, it is one layer of multigroup film 3r.The data inputting film 6C of 1st figure case is by counting
Print and record according to mask regions 8a, the data inputting film 6D of the 2nd figure case is printed by data mask area 8b to be recorded.Herein, using such as
Give a definition：There is extra implant to represent ' 0 ', no extra implant represents ' 1 '；There is resistive film to represent ' 0 ', non-resistance film represents ' 1 '.
Correspondingly, in the first accumulation layer 16C of 3D-oP chips 18c, the digital value that its 1st figure case is stored is formed in Figure 11 A
Digital array p18c[1,1], the digital value that its 2nd figure case is stored form the digital array p in Figure 11 B18a[1,2].Here,
p18c[i, j] refers to the digital array that j-th of figure case of i-th of accumulation layer in chip 18c is stored.As can be seen that digital battle array
Arrange p18c[1,1] is with the digital array m (1) in Fig. 7 A on the contrary, i.e. p18c[1,1] = - m(1)；Digital array p18c[1,2] with scheming
Digital array m (2) in 7B is identical, i.e. p18c[1,2] = m(2).Here, symbol '-' is represented on the contrary, i.e. ' 0 ' and ' 1 ' exchanges.
Since the binary value in digital array can change with the definition of binary value, the positive and negative of digital array does not have too
More meanings.In this application, as long as all binary value all sames or opposite in two digital arrays, then it is assumed that the two are digital
Array is equal.On the other hand, Figure 10 B represent the x1x2 three-dimensional heaps 16d of chip 18d.In the first accumulation layer 16C of chip 18d,
The data inputting film 6C of its 1st figure case is printed by data mask area 8b to be recorded, and the data inputting film 6D of the 2nd figure case is by data mask
Area 8a print records.Therefore, for chip 18d, p18d[1,1] = - m(2)；p18d[1,2] = -m(1)。
For the chip 18c and 18d of Figure 10 A- Figure 10 B, its digital array sequence can be expressed as：
S18c = (p18c[1,1], p18c[1,2]) = (-m(1), m(2))；
S18d = (p18d[1,1], p18d[1,2]) = (-m(2), m(1))；
Wherein, { S18c} = {S18d, but S18c ≠ S18d,
As can be seen that chip 18c and chip 18d has an identical data array set, but different data array sequences.It is right
For same input address, the order of carry-out bit needs to exchange in output.
Figure 12 represents a kind of circuit block diagram of 3D-oP.It, which contains an xMxn three-dimensionals heap 16 and one, can set input/output electric
Road 24.Three-dimensional heap 16 contains M × n digital array.Wherein, in the i-th accumulation layer j-th of figure case digital array by p [i,
j]（0≤i≤M, 0≤j≤n）Represent.Input/output circuitry 24 can be set also to contain a sequence memory 22.The memory 22
Storage and the relevant information of digital array sequence in the 3D-oP chips.One and the relevant information of digital array sequence are chips
Sequence number.Position of the chip serial number directly to chip on wafer is related, it can be used for extracting the digital array sequence of chip
Column information.Sequence memory 22 is preferably an embedded non-volatile memory.Such as say, it can write direct storage
Device, laser programmable fuse and/or electrical programming memory.For writing direct for feram memory, with digital array sequence
Relevant information writes in process of production；For laser programmable fuse, with the relevant information of digital array sequence in life
During production or rear write-in；For electrical programming memory, write with the relevant information of digital array sequence after production process
Enter.
According to the relevant information of digital array sequence, input/output circuitry 24 can be set to change external input/defeated
Go out the input in 28, the output of internal input/output 26 can also be changed, so that external input/output 26 and digital array
Sequence is unrelated.In other words, in a batch of all 3D-oP, although they may have different digital array sequences,
For a user, they have same external input/output 28.Figure 13 A- Figure 13 B disclose the more thin of 3D-oP circuits
Section.
Figure 13 A represent the circuit block diagram of x2x1 3D-oP 18 in Fig. 8 A- Fig. 8 B a kind of.The figure illustrates its input address
Decoder 20I.Accumulation layer 16A, 16B in three-dimensional heap 16 stores digital array p [1], p [2] respectively.Here, due to each
Storage member only stores a figure case, and the expression of digital array has been simplified to p [i]（0≤i≤M）.Input address decoder
20I decodes internal input address 26.For example, if the highest order of internal input address 26 were ' 0 ', digital array p
[1] it is accessed；Conversely, digital array p [2] is accessed.Can set input/output circuitry 24 can according to digital array sequence
Relevant information, changes external input address 28.For chip 18a, internal input address 26 and external input address 28
It is identical；For chip 18b, the highest order contrast of internal input address 26 and external input address 28.
Figure 13 B represent the circuit block diagram of x1x2 3D-oP 18 in Figure 10 A- Figure 10 B a kind of.The figure illustrates output to buffer
Area 20O.Three-dimensional heap 6 stores digital array p [1,1] corresponding with the 1st and the 2nd figure case and p [1,2].Output buffer 20O
Contain multiple output groups 21,21 ' ....Each output group output is stored in all figure cases in same storage member.Such as say, it is defeated
Go out group 21 and contain figure case 21a, 21b.Wherein, the 1st figure case that figure case 21a outputs are stored in some storage member is exported,
The 21b outputs of output figure case are stored in the 2nd figure case of same storage member.Can set input/output circuitry 24 can according to
The relevant information of digital array sequence, changes the output figure case order of each output group 21 in output buffer 20O.For core
For piece 18c, outside output 28 and internal output 26 are identical；For chip 18d, each output group（Such as 21）In output
Figure case order contrast.
The method of the record of biasing print to different accumulation layers can be with biasing print record in Figure 10 A- Figure 10 B to not in Fig. 8 A- Fig. 8 B
Method with figure case combines.Particularly, the mask pattern of different accumulation layers and different figure cases is merged into same more
On area data mask plate.In different print steps, wafer is different relative to the amount of bias of the multizone data mask version.
Therefore, the datagraphic from same data mask version is by print record to different accumulation layers and the data inputting film of different figure cases
In.Figure 14 discloses such a example.The x2x2 3D-oP 18e contain two accumulation layers 16A, 16B, and each storage member
Store two figure cases：1st and the 2nd figure case.The embodiment contains 4 data inputting films, they store following number respectively
Array：The 1st figure case storage p [1,1] in accumulation layer 16A；The 2nd figure case storage p [1,2] in accumulation layer 16A；Accumulation layer
The 1st figure case storage p [2,1] in 16B；The 2nd figure case storage p [2,2] in accumulation layer 16B.
Left panels in Figure 15 represent multizone data mask version 8 used by the x2x2 3D-oP 18.It contains 4
A data masked areas, its digital array are m (1)-m (4) respectively.The origin of the multizone data mask version 8 is OM.Figure 15's
Right graphic represents all chip D [1]-D [4] in an exposure place E on a 3D-oP wafer 9.These chips are each
Origin be O1-O4.Printed off since chip D [1]-D [4] is biased by a data mask version 8, they belong to same 3D-oP batches.
After Figure 16 is listed in each print steps of x2x2 3D-oP 18, each data inputting film storage on each chip
Digital array.The 3rd of the table is listed in each print steps, OMThe chip origin being aligned.4 of the present embodiment
Data inputting film needs 4 print steps.In the 1st print steps（Form p [1,1]）When, OMIt is directed at the origin O of chip D [1]1,
The digital array p [1,1] of chip D [1]-D [4] is respectively m (1)-m (4).In the 2nd print steps（Form p [1,2]）When, OMIt is right
The origin O of quasi core piece D [2]2.As long as the step distance D on y directionsyIt is chip D [1] and D [2] distance dy2 times, i.e. Dy=2dy,
Then the digital array p [1,2] of chip D [1]-D [4] is respectively m (2), m (1), m (4), m (3).In the 3rd print steps（Shape
Into p [2,1]）When, OMIt is directed at the origin O of chip D [3]3.As long as the step distance D on x directionsxIt is chip D [3] and D [1] distance
dx2 times, i.e. Dx=2dx, then the digital array p [2,1] of chip D [1]-D [4] is respectively m (3), m (4), m (1), m (2).
In the 4th print steps（Form p [2,2]）When, OMIt is directed at the origin O of chip D [4]4.As long as Dy=2dyAnd Dx=2dx, then chip D
[1] the digital array p [2,2] of-D [4] is respectively m (4), m (3), m (2), m (1).
In short, for Figure 15 chips D [1]-D [4], its digital array sequence can be expressed as：
SD[1] = (pD[1][1,1], pD[1][1,2], pD[1][2,1], pD[1][2,2]) = (m(1), m(2), m(3), m(4));
SD[2] = (pD[2][1,1], pD[2][1,2], pD[2][2,1], pD[2][2,2]) = (m(2), m(1), m(4), m(3));
SD[3] = (pD[3][1,1], pD[3][1,2], pD[3][2,1], pD[3][2,2]) = (m(3), m(4), m(1), m(2));
SD[4] = (pD[4][1,1], pD[4][1,2], pD[4][2,1], pD[4][2,2]) = (m(4), m(3), m(2), m(1));
Wherein { SM[1]} = {SM[2]} = {SM[3], but SM[1] ≠ SM[2] ≠ SM[3],
3D-oP chips D [1]-D [4], which is can be seen that, from these expression formulas is respectively provided with identical digital array set, but can be with
With different digital array sequences.
Figure 17 represents the circuit block diagram of x2x2 3D-oP 18.The figure illustrates input address decoder 20I and output to buffer
Area 20O.They and the input address decoder 20I in Figure 13 A- Figure 13 B and output buffer 20O have identical function.It is three-dimensional
Heap 16 stores 4 digital array p [1,1]-p [2,2].Input/output circuitry 24 can be set according to related to digital array sequence
Information, thus it is possible to vary external input address 28, can also change internal output 26：It is not any for chip D [1]
Change；For chip D [2], each output group in output buffer 20O（Such as 21）Output figure case order exchanged；
For chip D [3], the highest order contrast of internal input address 26 and external input address 28；For chip D [4]
For, the highest order contrast of internal input address 26 and external input address 28, and it is each defeated in output buffer 20O
Go out group（Such as 21）Output figure case order exchanged.
Biasing print record technology can be not only used in the data inputting film of one single chip, can be used for the number of multiple chips
According in typing film.Correspondingly, the present invention proposes a kind of three-dimensional storage enclosure based on 3D-oP（3D2-oP）.3D2- oP encapsulation is general
Issued in the form of storage card.Similarly, the mask pattern of multiple accumulation layer/figure cases is integrated into more than one piece in multiple chips
In area data mask plate.In different print steps, wafer is different relative to the amount of bias of the multizone data mask version.
Therefore, the datagraphic from same data mask version arrives 3D by print record2Different accumulation layer/numbers of different chips in-oP encapsulation
In code bit.
Figure 18 represents a kind of x3x3x1 3D2- oP encapsulation 38.Here, xKxMxn 3D2- oP encapsulation represents one containing K
It is stacked with the storage enclosure of xMxn 3D-oP chips.Particularly, the present embodiment contains three 3D-oP chips C1-C3.They
It is vertically stacked in package substrate 30 and forms 3D-oP heaps 36.Lead 32 is by chip C1-C3Coupled with substrate 30.In order to improve
Its Information Security, preferably in 3D2Moulding compound is filled in-oP encapsulation 38.
Figure 19 is the 3D2The circuit block diagram of-oP encapsulation 38.Its 3D-oP heap 36 contains 9 digital arrays, wherein each core
Piece C1-C3Contain 3 digital array p [1]-p [3].It can also set input/output circuitry 24 containing one, its function and figure
It is similar in 17.Input/output circuitry 24 can be set to be located in 3D-oP chips and/or in control chip.
The left side figure of Figure 20 is 3D2Multizone data mask version 8 used by-oP encapsulation 38.It contains 9 data masks
Region, and digital array m (1)-m (9) is represented respectively.The origin of the multizone data mask version 8 is OM.The right figure of Figure 20
It is all chip D [1]-D [9] in a 3D-oP wafers 9 in an exposure place E.Wherein, the origin of chip D [1]-D [3] point
Wei not O1-O3。
Figure 21 is listed in 3D2After each print steps of-oP encapsulation 38, the number on each chip in each data inputting film
Code array.The 3rd of the table is listed in each print steps, OMThe chip origin being aligned.3 data of the present embodiment
Typing film needs 3 print steps.In the 1st print steps（Form p [1]）When, OMIt is directed at the origin O of chip D [1]1, chip D
[1] the digital array p [1] of-D [9] is respectively m (1)-m (9).In the 2nd print steps（Form p [2]）When, OMIt is directed at chip D
[2] origin O2.As long as Dy=3dy1=3dy2, then the digital array p [2] of chip D [1]-D [9] is respectively m (3), m (1), m
(2), m(6), m(4), m(5), m(9), m(7), m(8).In the 3rd print steps（Form p [3]）When, OMIt is directed at chip D
[3] origin O3.As long as Dy=3dy1=3dy2, then the digital array p [3] of chip D [1]-D [9] is respectively m (2), m (3), m
(1), m(5), m(6), m(4), m(8), m(9), m(7)。
Figure 22 lists a 3D2Three kinds of 3D in-oP batches2- oP encapsulates M [1]-M [3].These three 3D2- oP encapsulates M
[1]-M [3] is made of 9 chips in Figure 20 respectively：3D2- oP encapsulation M [1] contain chip D [1], D [4], D [7];
3D2- oP encapsulation M [2] contain chip D [2], D [5], D [8]; 3D2- oP encapsulation M [3] contain chip D [3], D [6], D
[9].Because these 3D2- oP encapsulation M [1]-M [3] bias print record by same data mask version 8 and are formed, they belong to same 3D2-
OP batches.
In short, for the 3D in Figure 202- oP encapsulates M [1]-M [3], its digital array sequence can be expressed as：
SM[1] = (SD[1], SD[4], SD[7]) = (m(1), m(3), m(2); m(4), m(6), m(5); m(7), m(9), m(8));
SM[2] = (SD[2], SD[5], SD[8]) = (m(2), m(1), m(3); m(5), m(4), m(6); m(8), m(7), m(9));
SM[3] = (SD[3], SD[6], SD[9]) = (m(3), m(1), m(1); m(6), m(5), m(4); m(9), m(8), m(7));
Wherein SM[1] ≠ SM[2] ≠ SM[3] and {SM[1]} = {SM[2]} = {SM[3],
3D is can be seen that from these expression formulas2- oP encapsulation M [1]-M [3] are respectively provided with identical digital array set, but they
There can be different digital array sequences.
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be to the form and details of the present invention
It is modified, this simultaneously applies the spirit of the present invention without prejudice to them.Such as say, biasing print record can be applied not only to photoetching process,
It can also be applied to stamped method.Therefore, except the spirit according to appended claims, the present invention should not be restricted by any limit
System.
Claims (10)
1. one kind records reservoir based on three-dimensional biasing print（3D-oP）Three-dimension packaging（3D2-oP）, contain the first He being stacked with
2nd 3D-oP chips, it is characterised in that：
First 3D-oP chips contain the first and second data inputting films, and the second data inputting film is located at first data record
Enter above film, which stores the first digital array, which stores the second digital array；
2nd 3D-oP chips contain the third and fourth data inputting film, and the 4th data inputting film is located at the record of the 3rd data
Enter above film, the 3rd data inputting film stores the 3rd digital array, and the 4th data inputting film stores the 4th digital array；
With a batch of 3D2In-oP encapsulation, all 3D2- oP encapsulation contains same set digital array set；At least two
3D2The digital array sequence of-oP encapsulation is different.
2. three-dimension packaging according to claim 1, is further characterized in that：First 3D-oP chips contain first and second
Accumulation layer, and second accumulation layer is located above first accumulation layer, which contains the first data inputting film, should
Second accumulation layer contains the second data inputting film.
3. three-dimension packaging according to claim 2, be further characterized in that containing：First can set input circuit, this first
It can set output circuit that the input of the first 3D-oP chips is set according to digital array sequence in the first 3D-oP chips.
4. three-dimension packaging according to claim 1, is further characterized in that：2nd 3D-oP chips contain third and fourth
Accumulation layer, and the 4th accumulation layer is located above the 3rd accumulation layer, the 3rd accumulation layer contains the 3rd data inputting film, should
4th accumulation layer contains the 4th data inputting film.
5. three-dimension packaging according to claim 4, be further characterized in that containing：Second can set input circuit, this second
It can set output circuit that the input of the 2nd 3D-oP chips is set according to digital array sequence in the 2nd 3D-oP chips.
6. three-dimension packaging according to claim 1, is further characterized in that：First 3D-oP chips contain the first accumulation layer,
First accumulation layer contains the first and second data inputtings film.
7. three-dimension packaging according to claim 6, be further characterized in that containing：First can set output circuit, this first
It can set output circuit that the output of the first 3D-oP chips is set according to digital array sequence in the first 3D-oP chips.
8. three-dimension packaging according to claim 1, is further characterized in that：2nd 3D-oP chips contain the second accumulation layer,
Second accumulation layer contains the third and fourth data inputting film.
9. three-dimension packaging according to claim 8, be further characterized in that containing：Second can set output circuit, this second
It can set output circuit that the output of the 2nd 3D-oP chips is set according to digital array sequence in the 2nd 3D-oP chips.
10. three-dimension packaging according to claim 1, is further characterized in that：Datagraphic in the data inputting film by
Photoetching process（photo-lithography）Or stamped method（imprint-lithography）Formed.
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|---|---|---|---|
| CN201610927271.0A CN107978516A (en) | 2016-10-24 | 2016-10-24 | Three-dimensional package based on three-dimensional offset printed memory |
| US15/381,073 US9741697B2 (en) | 2011-09-01 | 2016-12-15 | Three-dimensional 3D-oP-based package |
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| CN201610927271.0A CN107978516A (en) | 2016-10-24 | 2016-10-24 | Three-dimensional package based on three-dimensional offset printed memory |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099695C (en) * | 1998-09-24 | 2003-01-22 | 张国飙 | Three-dimensional read-only memory |
| CN1487362A (en) * | 2002-09-17 | 2004-04-07 | ��������˹�����տ����� | Impression mask photoetching |
| WO2013029564A1 (en) * | 2011-09-01 | 2013-03-07 | Zhang Guobiao | Three-dimensional recorded memory |
-
2016
- 2016-10-24 CN CN201610927271.0A patent/CN107978516A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099695C (en) * | 1998-09-24 | 2003-01-22 | 张国飙 | Three-dimensional read-only memory |
| CN1487362A (en) * | 2002-09-17 | 2004-04-07 | ��������˹�����տ����� | Impression mask photoetching |
| WO2013029564A1 (en) * | 2011-09-01 | 2013-03-07 | Zhang Guobiao | Three-dimensional recorded memory |
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