CN1099695C - Three-dimensional read-only memory - Google Patents

Three-dimensional read-only memory Download PDF

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CN1099695C
CN1099695C CN 98119572 CN98119572A CN1099695C CN 1099695 C CN1099695 C CN 1099695C CN 98119572 CN98119572 CN 98119572 CN 98119572 A CN98119572 A CN 98119572A CN 1099695 C CN1099695 C CN 1099695C
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read
rom
accumulation layer
film
storage
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CN1212452A (en
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张国飙
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张国飙
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor

Abstract

The present invention provides a read only memory with memory elements arranged in a three-dimensional space. Memory elements are distributed on a plurality of memory layers. The memory layers are overlapped, and one memory layer is overlapped on the other memory layer. A plurality of addressing lines and memory elements are arranged on each memory layer. The memory elements can be mask programmable or field programmable. Memory density and memory capacity can be greatly enhanced due to the fact that the memory elements are arranged in a three-dimensional space. The access time of the three-dimensional read only memory is short, and the three-dimensional read only memory can be manufactured by a standard semiconductor production flow. The present invention can be widely applied to many fields.

Description

3 D ROM and manufacture method thereof

The present invention relates to integrated circuit fields, or rather, relate to read-only memory and manufacture method thereof in the integrated circuit.

Read-only memory is a device of depositing fix information, and its information during fabrication or programme when the user uses and write.Read-only memory in the past all is arranged in the two-dimensional array on the Semiconductor substrate.Exist a storage element on each crosspoint of this array, this storage element provides a resistive, inductive, capacitive character, diode-type or uses the coupling mechanism of active element.Each storage element is represented one-bit digital information.Simultaneously, each storage element links to each other with input and output by the signal of telecommunication, can guarantee the extremely short access time like this.Read-only memory is divided into two kinds: a kind of is mask-programmable only read memory (MPROM), and another kind is a program read-only memory (EPROM).The information of MPROM is to control by mask during fabrication, and on the other hand, the information of EPROM is write by the user.

The United States Patent (USP) 5,429,968 (July 4 nineteen ninety-five) of authorizing Koyoma belongs to an example of existing MPROM technology.Its uses field effect transistor as storage element, changes digital information in the storage element by the threshold voltage of adjusting field effect transistor.By adjusting the ion injection rate, the field effect transistor of different location becomes enhancement mode or depletion type.Under suitable voltage, the field effect transistor of enhancement mode be open and the field effect transistor of depletion type is conducting.By surveying the electric current on the corresponding lines not, can read the digital information of different location.Because these field effect transistor can only be formed on the Semiconductor substrate, so this MPROM can only be arranged to two-dimensional structure.

On the other hand, EPROM generally uses an ohmic coupling mechanism to represent digital information.Representative resistive coupling mechanism comprises fuse (fuse) and anti-fuse (antifuse).Authorize the United States Patent (USP) 4,899,205 (February 6 nineteen ninety) of Hamdy etc. and described a two-dimentional EPROM who utilizes the anti-fuse of silicon-silicon as programmed element.In this structure, the source/leakage of anti-fuse and access field effect transistor integrates the formation storage element.Because the access field effect transistor must be grown on the Semiconductor substrate, so use the EPROM of the anti-fuse of silicon-silicon can only be arranged to a two-dimensional array.When using this structure, the amount of digital information on the unit are chip is subjected to the restriction of the size of access field effect transistor.Authorize the United States Patent (USP) 4,442,507 (on April 10th, 1984) of Roesner etc. and described another kind of program read-only memory.It uses the Schottky diode heap as storage element.Its address selection line is generated by polysilicon, and another address selection line is generated by aluminium.The polysilicon that generates with common process generally can not be grown in above the aluminium.Therefore, this memory can only use one deck EPROM.That is to say that storage density is limited.

As mentioned above, because the storage element of read-only memory of the prior art is formed on the substrate of semi-conducting material formation, that is to say that prior art can only be arranged in the storage element in the integrated circuit in the two-dimensional space, thereby make the storage density of read-only memory be subjected to very big restriction.In addition, the word line that is formed by polysilicon in the prior art also exists big, the slower shortcoming of access rate of resistivity.

In order to improve the storage density of read-only memory in the integrated circuit, the inventor is from improving the angle that dimension is set of storage element, on the basis of the constituent material that changes storage element, with storage element with the three dimensional form setting, thereby can improve storage density, can improve access speed again.Will generate storage element with three dimensional form, just mean that read-only memory has the folded mutually accumulation layer of multilayer, each accumulation layer all has a plurality of storage elements and corresponding word line and bit line.A plurality of accumulation layers folded mutually requires the accumulation layer of lower floor to be necessary for the upper strata accumulation layer a well basis is provided.Along with the appearance of chemico-mechanical polishing (CMP) technology, this requirement can reach at an easy rate.

First purpose of the present invention provides a kind of read-only storage element novel, that generate with three dimensional form;

Second purpose of the present invention provides a kind of 3 D ROM;

The 3rd purpose of the present invention provides a kind of manufacture method of 3 D ROM.

In order to solve the above-mentioned problems in the prior art, the present invention proposes a kind of 3 D ROM and manufacture method thereof.

A kind of 3 D ROM of the present invention comprises that one contains transistorized Semiconductor substrate, it is characterized in that also comprising: at least two read-only accumulation layers that are stacked on the described substrate, each read-only accumulation layer comprises a plurality of read-only storage elements and a plurality of address selection line; And a plurality of interlayer interface channel mouth and/or contact channels holes that are formed between described read-only accumulation layer and the Semiconductor substrate, are used to provide the connection between described read-only accumulation layer and the described Semiconductor substrate.

Another kind of 3 D ROM of the present invention comprises that one contains transistorized Semiconductor substrate, it is characterized in that also comprising: a dielectric insulating film, this dielectric insulating film cover to this Semiconductor substrate of small part and are complanations; At least one is stacked in the read-only accumulation layer on the described dielectric insulating film, and described read-only accumulation layer comprises a plurality of read-only memorys and a plurality of address selection line; And a plurality ofly be formed between described read-only accumulation layer and the Semiconductor substrate, be used to provide the interlayer interface channel mouth and/or the contact channels hole that connect between described read-only accumulation layer and the described Semiconductor substrate.

The manufacture method of 3 D ROM of the present invention comprises the following steps: 1) on semi-conductive substrate, form transistor; 2) be formed with formation one dielectric insulating film on the transistorized Semiconductor substrate; 3) on above-mentioned dielectric insulating film, form a plurality of contact channels hole and/or interlayer interface channel mouth; 4) on the above-mentioned dielectric insulating film that is formed with contact channels hole and/or interlayer interface channel mouth, form the first read-only accumulation layer; 5) repeating step 4 forms the second read-only accumulation layer etc. on described first accumulation layer.

Read-only memory of the present invention is arranged in storage element on the three dimensions, thereby the storage density and the capacity of memory have been improved greatly, and owing to 3 D ROM of the present invention can integrate with other semiconductor circuit, thereby improved the data/commands transmission rate between them, shortened the access time.

The manufacturing process of 3 D ROM of the present invention can be compatible mutually with the semiconductor fabrication process of routine.Therefore, can make with the semiconductor production equipment and the flow process of standard.

Below with reference to accompanying drawing 3 D ROM of the present invention and manufacture method thereof are elaborated.Wherein,

Fig. 1 is perspective view that contains the 3D-ROM of two accumulation layers of expression.

Fig. 2 is the circuit diagram on 3D-MPROM chip substrate of expression.This circuit provides addressing and reads function.

Fig. 3 is the circuit diagram on 3D-EPROM chip substrate of expression.This circuit provides addressing, programmes and reads function.

Fig. 4 is the sectional drawing of a 3D-ROM storage element of expression.

Fig. 5 A~5C is the sectional drawing of the several MPROM films of expression.

Fig. 6 A~6E is the sectional drawing of the several 3D-MPROM storage elements of expression.

Fig. 7 is illustrated in one 4 * 4 a storage element array of reading under the case condition the most difficult, and zero represents 0, * represent 1.

Fig. 8 is the logical zero of expression 3D-MPROM film and the E-I characteristic of logical one.

Fig. 9 A is a sectional drawing of describing first kind of EPROM film; Fig. 9 B is a sectional drawing of describing second kind of EPROM film;

Fig. 9 C is a sectional drawing of describing the third EPROM film.

Figure 10 A is the sectional drawing of a kind of 3D-EPROM storage element of expression; Figure 10 B is the sectional drawing of the another kind of 3D-EPROM storage element of expression.

Figure 11 represents the E-I characteristic of accurate conductive membrane, anti-fuse film and EPROM film.

Figure 12 A is the vertical view that is illustrated in first kind of wiring in a kind of 3D-ROM accumulation layer;

Figure 12 B is the vertical view that is illustrated in second kind of wiring in the 3D-ROM accumulation layer;

Figure 12 C is the vertical view that is illustrated in the third wiring in the 3D-ROM accumulation layer.

Figure 13 is the sectional drawing of first kind of 3D-ROM memory construction of expression.

Figure 14 is the sectional drawing of second kind of 3D-ROM memory construction of expression.

Figure 15 A~15B is the sectional drawing of the third 3D-ROM memory construction of expression.

Figure 1 shows that one 2 * 2 * 2 3D-ROM.Here, symbol l * m * n 3D-ROM is meant a 3D-ROM who contains l accumulation layer, m bar word line and n bit lines.This 3D-ROM is grown on the Semiconductor substrate 10, and it has two accumulation layers 100,200.If substrate surface is the XY plane, each accumulation layer plane is all parallel with substrate surface.Accumulation layer 200 is stacked in above the accumulation layer 100, and is promptly stacked along the Z direction.Each accumulation layer is made up of along Y direction address selection line along directions X address selection line and two one 2 * 2 storage element array, two.Address selection line on the directions X is called word line, and they are included in word line 101,102 and the word line on accumulation layer 200 201,202 on the accumulation layer 100.Address selection line on the Y direction is called bit line, and they comprise bit line 111,112 on the accumulation layer 100 and the bit line 211,212 on the accumulation layer 200.The infall of word line and bit line is provided with storage element, as 121~124,221~224.Each storage element can be stored a binary message and a kind of coupling mechanism is provided between word line and bit line.This coupling mechanism comprises resistive, inductive, capacitive character, diode-type or uses the coupling mechanism of active element.Each storage element is represented a binary message by the size that changes coupling mechanism.To selected storage element, address selection line provides and programmes/path of reading.

Fig. 1 also shows the connected mode of the address selection line in substrate 10 and the different accumulation layers.In the accumulation layer 100, word line 101,102 is connected with substrate 10 at contact point 131,132 by contact channels hole 101a, 102a.Bit line 111,112 is connected with substrate 10 at contact point 141,142 by contact channels hole 111a, 112a on the other hand.Similarly, in the accumulation layer 200, word line 201,202 is connected with substrate 10 at contact point 231,232 by contact channels hole 201a, 202a.On the other hand, bit line 211,212 is connected with substrate 10 at contact point 241,242 by contact channels hole 211a, 212a.For allow accumulation layer 200 be connected with substrate 10, address selection line need be extended, for example, bit line 211 must extend across contact channels hole 111a until contact channels hole 211a, just unlikely like this damage bit line 111 or contact channels hole 111a.

Fig. 2 represents the circuit diagram of a kind of addressing of one 2 * 2 * 2 3D-MPROM/read.Because the function that will finish addressing and read with transistor, the circuit of this addressing/read need be built in above the Semiconductor substrate 10.It is made up of a Z address decoder 190, two 170,270 in 160,260 and two Y address decoders of X address decoder.Z address decoder 190 contains X address input 191, Y address input 192, Z address input 193.These inputs all connect together with input pin or other some circuit of semiconductor integrated package.

For the information that stores in addressing/the read storage element (for example, the storage element 121 among Fig. 1), must in X, Y and Z address input 191,192,193, add suitable voltage, so that added voltage equals to read voltage V on the storage element 121 RCan realize the connection of following two signals of telecommunication in the level signal that adds in the Z address input 193: one is between input 191 of X address and X address input 1 (161), and another is between Y address input 192 and Y address input 1 (171).Therefore, when the addressing signal in addressing signal in the X address input 191 and the Y address input 192 is input on X address decoder 1 (160) and the Y address decoder 1 (170) respectively, have only the voltage of the addressing line on the accumulation layer 100 just can correspondingly change.Simultaneously, the level signal in the Z address input 193 makes between the output 196 of the output 1 (164) of X address decoder 1 (160) and Z address decoder 190 and realizes connecting.

Addressing signal on the X address decoder 1 (160) is brought up to the voltage on the contact point 131 and is read voltage V RHalf, V R/ 2.Simultaneously, the addressing signal on the Y address decoder 1 (170) drops to negative 1/2 to the voltage on the contact point 141 and reads voltage ,-V R/ 2.By contact channels hole 101a and 111a, therefore the voltage on the word line 101 also be enhanced V R/ 2, the voltage on the bit line 111 drops to-V R/ 2.Therefore, read voltage V for one RBe added in the two ends of storage element 121.For the different state of storage element 121, different electric currents is arranged on the word line 101.Output signal passes to output 196 from exporting 1 (164), and then passes to output pin.So, can read the information that stores in the storage element 121.

Fig. 3 is the circuit diagram of an addressing/read/programme, and this circuit diagram is represented one 2 * 2 * 2 3D-EPROM.Similar with the circuit of Fig. 2, this circuit also is formed on above the Semiconductor substrate 10.It comprises Z address decoder 190, two 160,260 and two Y address decoders 170,270 of X address decoder.Except X, Y, Z address input 191,192,193, Z address decoder 190 comprises that also output 196, programming realize that PGM195, a voltage are half (V of program voltage PP/ 2) power supply 197 and a voltage are the half (V of program voltage that bears PP/ 2) power supply 198.

The read operation of 3D-EPROM and the read operation of 3D-MPROM are similar.The programming of 3D-EPROM can be carried out with following mode, and for example, for the storage element among Fig. 1 224 is programmed, Z address input 193 should make X address input 191, Y address input 192, V PP/ 2 power supplys 197 ,-V PP/ 2 power supplys 198 and PGM195 are connected with relevant terminal on the Y address decoder 2 (270) at X address decoder 2 (260) with them.Select word line 202 and bit line 212 by the signal of contact point 232,242 on X, Y addressing line then.After PGM195 was selected, the voltage of word line 202 was raised to V PP/ 2, the voltage of bit line 212 drops to-V PP/ 2, other addressing line of while is ground connection all.Because storage element 224 is positioned at the infall of word line 202 and bit line 212, added voltage is a program voltage V on it PPThereby storage element 224 is programmed.On the other hand, added voltage only is V on other storage element PP/ 2, they keep its state of not programming.

Fig. 4 represents the sectional drawing of a 3D-ROM storage element of the present invention.It has a top electrode 501, ROM film 502, a hearth electrode 503 and a place 504.Top electrode 501 is used to do an addressing line, for example, and as bit line.It preferably is made up of metal material.Here metal material refers to metallic element, metal alloy and metallic compound, for example, thickness between 0.2~2 μ m, the preferably aluminium of 0.5 μ m or copper.Between top electrode 501 and ROM film 502, one deck barrier metal film also can be arranged, for example, TiW.This layer barrier film can prevent to react between top electrode 501 and the ROM film 502.Hearth electrode 503 can be used as another addressing line, for example, and word line.It preferably comprises metal material, for example, thickness between 0.2~2 μ m, the preferably aluminium of 0.5 μ m or copper.Between hearth electrode 503 and ROM film 502, also one deck barrier film can be arranged, for example, TiW.This layer barrier film can prevent to react between hearth electrode 503 and the ROM film 502.

ROM film 502 has been represented the digital information that is stored in this storage element.The ROM film is called as the MPROM film in MPROM.If the MPROM film is reading to be in high resistance state under the voltage, then it has represented " 0 " logic.Correspondingly, the MPROM film of " 0 " logic is called as barrier film.On the other hand, if the MPROM film is reading to be in low resistance state under the voltage, then it has represented " 1 " logic.Correspondingly, the MPROM film of " 1 " logic is called as accurate conductive membrane.Use the reason of " accurate conductive membrane " in Fig. 7 and Fig. 8, to explain in more detail.

In EPROM, the ROM film is known as the EPROM film.The EPROM film contains an accurate conductive membrane and an anti-fuse film.Accurate conductive membrane has identical characteristic with accurate conductive membrane among the 3D-MPROM.Anti-fuse film was a high resistance state before programming, and it irreversibly converts low resistance state to the programming back.To an EPROM chip that just dispatches from the factory, its anti-fuse film is complete.Therefore, the EPROM film is in high resistance state, and representative " 0 " logic, and the anti-fuse film in programming back has become low resistance state, and correspondingly, the EPROM film has become an accurate conductive membrane, and representative " 1 " logic.Different storage elements is separated from each other by place 504.Place 504 is made of insulating material (for example, silica).Its thickness between 0.2~2 μ m, 0.5 μ m preferably.

Fig. 5 A~5C represents several MPROM films.

Fig. 5 A represents a kind of MPROM film that is suitable for as " 0 " logical storage unit.This MPROM film contains the dielectric 502a that a resistance shelves electric current flows through, and for example, it can be the silica that utilizes the PECVD method to generate, its thickness between 0.02~2 μ m, 0.5 μ m preferably.

Fig. 5 B~5C represents two kinds of MPROM films that are suitable for as " 1 " logic.It contains an accurate conductive membrane.Accurate conductive membrane has a nonlinear resistance property: a) it is in low resistance state under the voltage reading; B) its resistance obviously increases than reading the little or direction of voltage when reading the opposite voltage of voltage when being subjected to a size.Fig. 7 and Fig. 8 will do to explain in detail to this.

Fig. 5 B has shown an accurate conductive membrane 502b as " 1 " logic.It contains amorphous silicon, thickness between 5~500nm, 100nm preferably.Amorphous silicon can generate with following way, as: sputter, electric glow discharge method.If the addressing line can bear the heat treatment of a higher temperature, for example, to form by the refractoriness metal, so accurate conductive membrane can be used the polysilicon that is generated by common process.Amorphous silicon film can be plain or mix.Because amorphous silicon has the E-I characteristic of index shape, in general, it can satisfy the requirement of the aligning conductive membrane E-I characteristic that is proposed in the above argumentation.On the other hand, protective ceramic material, particularly protective oxide also have the E-I characteristic of index shape, and therefore, they also can be used to valid conductive membrane 502b.Here, protective ceramic material is meant that Pilling-Bedworth compares the ceramic material (J.Shackelford, " Introduction to Materials Science for Engineers ", second edition, 609-610 page or leaf, 1988) greater than 1.The example of some protective ceramic materials comprises Be, Cu, Al, Cr, Mn, Fe, Co, Pd, Pb, Ce, Sc, Zn, Zr, La, Y, Nb, the oxide of Rh and Pt.The usually available following way of protective ceramic material forms: 1. sedimentation.For example, CVD, sputter; 2. method of formation.For example, methods such as thermal oxidation method, plasma oxidation method, anode oxidation method.The thickness of protective ceramic material between 2~200nm, 10nm preferably.Other material that can be accurate conductive membrane 502b comprises amorphous germanium, carbon, carborundum or the like.

Fig. 5 C has represented another accurate conductive membrane 502b as " 1 " logical storage unit.It is made by the p-n junction diode of an amorphous silicon.If the addressing line is the infusibility metal, then can use polysilicon p-n junction diode.The thickness of p layer 502bb and n layer 502ba between 20~300nm, 60nm preferably.P-n junction positive and negative two between resistance differ greatly, therefore, the p-n junction diode can satisfy the condition of accurate conductive membrane.Correspondingly, it can be used as " 1 " logical storage unit.Except the p-n junction diode, p-i-n knot also can be with valid conductive membrane 502b.Fig. 7 and Fig. 8 will more go through the benefit of using p-n junction or p-i-n knot.

Fig. 6 A~6E has represented the structure of several 3D-MPROM storage elements.Fig. 6 A is suitable for doing " 0 " logic, and Fig. 6 B~6E is suitable for doing " 1 " logic OR " 0 " logic, preferably " 1 " logic.

Fig. 6 A has represented a kind of sectional drawing of storage element.This storage element is suitable for " 0 " logic, and correspondingly, MPROM film 502 is barrier film 502a.This barrier film can be the extension of place 504.It can be made of a thick insulating material.Because the existence of barrier film does not have electric current to pass through between top electrode 501 and the hearth electrode 503.Therefore, show high resistance between top electrode 501 and the hearth electrode 503.

Fig. 6 B~6E has represented the sectional drawing of other four kinds of 3D-MPROM storage elements.There are similar structure in they and the anti-fuse of metal-metal unit.In place 504, form an access opening 505, then MPROM film 502 access opening 505 the insides, below or above formation.According to the logic state of this storage element, the MPROM film can be barrier film of expression " 0 " logic or the accurate conductive membrane of " 1 " logic.

Fig. 6 B has represented a kind of sectional drawing of 3D-MPROM storage element.Here, MPROM film 502 is formed in 505 li of access openings.The technical process of making this storage element is as follows: at first form hearth electrode 503, deposit place film 504 then, and etching place film 504 is to form access opening 505, after this, MPROM film 502 and top electrode 501 are created on access opening 505 the insides successively, at last with top electrode 501 and MPROM film 502 etching formings.

Fig. 6 C has represented the sectional drawing of another kind of 3D-MPROM storage element.Here MPROM film 502 is formed on above the access opening 505.The technical process of making this storage element is as follows: at first form hearth electrode 503, deposition place 504, etch access opening 505, in access opening 505, fill the stopple 506 that for example constitutes then by tungsten, and with the material Throwing light of tungsten and place on every side 504, deposition and etching MPROM film 502 and top electrode 501 at last.

Fig. 6 D has represented the sectional drawing of another kind of 3D-MPROM storage element.Here MPROM film 502 is formed on below the access opening 505.The technical process of making this storage element is as follows: at first form hearth electrode 503 and MPROM film 502, deposit place film 504 then, and etch access opening 505.After access opening 505 forms, expose a part of upper surface of MPROM film 502.Deposit the top electrode film at last and etch top electrode 501.

Fig. 6 E has represented the sectional drawing of another kind of 3D-MPROM storage element.The difference of the storage element among this storage element and Fig. 6 D is to be formed with a top buffer film 508 between MPROM film 502 and top electrode 501.This top buffer film 508 contains conductor, for example, thickness between 50~500nm, the tungsten of 100nm preferably.The effect of this top buffer film is when opening access opening 505, can prevent that MPROM film 502 is by over etching.

Fig. 7 has represented a n * n storage element array that is under the most difficult read states.At this moment, the storage element that read is 600aa, and it is in " 0 " logic state, and other all storage elements all are in " 1 " logic state.As an example, when reading, the voltage on the word line 400a rises to V R/ 2, the voltage on the bit line 500a is reduced to-V R/ 2, other all addressing line suspends.Fig. 8 has represented the E-I characteristic of the ROM of the ROM of " 0 " logic state and " 1 " logic state.Concerning " 0 " logic and " 1 " logical storage unit, have non-linear relation between the current/voltage, the while reverse current is little or approximately equal than forward current.The benefit of this volt-ampere characteristic will go through below.

When reading storage element 600aa (" 0 " logic), the voltage on the word line 400a is V R/ 2, the voltage on the bit line 500a is-V R/ 2, therefore, the electric current by storage element 600aa to the contribution of the electric current on the word line 400a is

I 600aa=I " 0 " logic(V R) last other electric current in addition of word line 400a, they are from other circuit, as 600ab → 600bb → 600ba.If the amorphous silicon film that one deck is single is used as accurate conductive membrane 502b, so, its reverse E-I characteristic and forward E-I characteristic are similar.In this case, each " 1 " logical storage unit approximately is 1/3 as the voltage drop on 600ab, 600bb, the 600ba and reads voltage.Therefore, the leakage current by circuit 600ab → 600bb → 600ba approximately is I " 1 " logic(V R/ 3).Because n * n storage element arranged in this accumulation layer, read under the situation the most difficult, n the thread cast-off road as 600ab → 600bb → 600ba arranged.Therefore, read under the situation the most difficult, other electric current on word line 400a approximately is

I Other≈ I " 1 " logic(V R/ 3) * n.

Generally speaking, the electric current on word line 400a is under " 0 " logic situation

Generally speaking, the electric current on word line 400a is under " 0 " logic situation

I " 0 " logical word line≈ I 600aa+ I Other=I " 0 " logic(V R)+I " 1 " logic(V R/ 3) * n.

Read under the situation in that another kind is the most difficult, the word line current of " 1 " logic is

I " 1 " logical word line=I " 1 " logic(V R).This most difficult situation of reading is meant that our interested storage element is in " 1 " logic state, and all the other each storage elements are in " 0 " logic state.These storage elements that are in " 0 " logic state are very little to the contribution of word line current.

In order to distinguish " 0 " logic and " 1 " logic, we wish

I " 1 " logical word line>I " 0 " logical word linePromptly

I " 1 " logic(V R)>I " 0 " logic(V R)+I " 1 " logic(V R/ 3) * n. I in general " 0 " logic(V RThe I of)<< " 1 " logic(V R), therefore, as an estimation,

Because the memory capacity in accumulation layer is n 2, equation (1) has proposed an estimation to the memory capacity in the accumulation layer.

According to equation (1), the size of memory capacity depends on the nonlinear characteristic of the E-I characteristic of accurate conductive membrane.If accurate conductive membrane has the E-I characteristic of an exponential type, read-only memory can have very big capacity.

If be added in the voltage on the accurate conductive membrane and read voltage direction when opposite, accurate conductive membrane has higher resistance (Fig. 8), for example, and amorphous silicon p-n junction diode.For " 0 " logic under the most difficult read states, its electric current can be littler.This is that the last suffered voltage of 600bb is reverse voltage because for the drain circuit that resembles 600ab → 600bb → 600ba and so on, and therefore, leakage current is far smaller than I " 1 " logic(V R/ 3).Correspondingly, n can that is to say that memory capacity can be bigger much larger than by the set upper limit of equation (1).

Fig. 9 A~11st is about the description of 3D-EPROM.The difference of 3D-EPROM and 3D-MPROM is: all 3D-EPROM storage elements have identical structure, and they are at first all in " 0 " logic state, in other words, and programming state not; The user can optionally carry out the address programming, makes it convert " 1 " logic state to.The EPROM film contains an accurate conductive membrane and an anti-fuse film.Become low resistance after the accurate conducting of " 1 " logic among accurate conductive membrane and the 3D-MPROM.Fig. 9 A~9C has provided some examples.

Fig. 9 A has represented the EPROM film 502c of a 3D-EPROM storage element.It contains an accurate conductive membrane 502cb and an anti-fuse film 502ca.This accurate conductive membrane 502cb is similar to the accurate conductive membrane of using among the 3D-MPROM, as the accurate conductive membrane of representing among Fig. 5 B.Anti-fuse film 502ca is made of amorphous silicon or protectiveness pottery, for example, thickness between 3~100nm, the chromium oxide of 10nm preferably.Figure 11 has represented accurate conductive membrane 502cb, anti-fuse film 502ca and the E-I characteristic of EPROM film 502c of programming not.Anti-fuse film 502ca is at a suitable program voltage V PPWith program current I PUnder be programmed.Select suitable V PPAnd I PBe for fear of the accurate conductive membrane 502cb of damage.The anti-fuse film 502ca in programming back is converted into low resistance state, and correspondingly, the E-I characteristic of EPROM film is similar to the E-I characteristic of accurate conductive membrane 502cb.Therefore, storage element enters " 1 " logic state.

Fig. 9 B represents the EPROM film 502c of another 3D-EPROM.Here EPROM film 502c comprises a p-n junction diode 502cb and anti-fuse film 502ca.This p-n junction diode 502cb (being accurate conductive membrane) is similar to the p-n junction diode of representing among Fig. 5 C.The silicon area 502cba that silicon area 502cbb that it is mixed by p and n mix forms, thickness between 50~500nm, 60nm preferably.Anti-fuse film 502ca can be formed on the following of accurate conductive membrane or above.Except the p-n junction diode had better on state characteristic, the class of operation of this 3D-EPROM was like the 3D-EPROM among Fig. 9 A.

Fig. 9 C has represented the EPROM film 502c of another 3D-EPROM.Here an intermediate buffering film 502cc is embedded between accurate conductive membrane 502cb and the anti-fuse film 502ca.It is made of the refractoriness metal, for example, and the tungsten of thickness between 10nm~2 μ m.In the programming process of anti-fuse film 502ca, can produce local Jiao Erre.This Jiao Erre can make the temperature of anti-fuse film 502ca raise.After having added intermediate buffering film 502cc, can prevent that its aligning conductive membrane 502cb from producing fire damage.The programming of this storage element and read operation are similar to the storage element among Fig. 9 A and Fig. 9 B.

Except the accurate conductive membrane 502b among Fig. 6 A~6E was replaced with EPROM film 502c, the storage element of 3D-EPROM can use the structure of Fig. 6 A~6E fully.For the EPROM film among Fig. 9 C, Figure 10 A and Figure 10 B have represented the corresponding EPROM storage element of other structure.Concerning those those skilled in the art, the position of accurate conductive membrane 502cb among Figure 10 A and Figure 10 B and anti-fuse film 502ca can exchange.

Figure 10 A has represented the storage element of a 3D-EPROM.It has a hearth electrode 503, an accurate conductive membrane 502cb, intermediate buffering film 502cc, an anti-fuse film 502ca and a top electrode 501.Its manufacturing step comprises: deposit and etching hearth electrode 503 and accurate conductive membrane 502cb; Deposit dielectric insulating film 504; Thereby etching dielectric insulating film 504 exposes a part of accurate conductive membrane 502cb to form window 505; Excessive film 502cc forms anti-fuse film 502ca and top electrode 501 at last in the middle of filling in the middle of the window 505.Figure 10 B has represented another 3D-EPROM storage element.The manufacturing step of this storage element is: deposit hearth electrode 503, accurate conductive membrane 502cb and intermediate buffering film 502cc; Etching intermediate buffering film 502cc and accurate conductive membrane 502cb; Etching hearth electrode 503; Deposit place deielectric-coating 504; Thereby etching place deielectric-coating 504 exposes a part of intermediate buffering film 502cc to form access opening 505; Last deposit and etching anti-fuse film 502ca and top electrode 501.

Figure 12 A~12C is illustrated in several domain vertical views in the 3D-ROM accumulation layer.In these domains, word line 450a~450d is along directions X, and bit line 470a~470c is along the Y direction.Contact channels hole 460a~460d provides being connected between the transistor on word line and the substrate.

Figure 12 A has represented first kind of domain, and all here contact channels hole 460a~460d drop on the straight line.Figure 12 B has represented second kind of domain, and the contact channels hole is divided into two groups here: A group 460a and 460c; B group 460b and 460d.B set of contact access opening has a segment distance from A set of contact access opening, so all contact channels hole 460a~460d drop on two straight lines.Because it is comparatively sparse mutually that the contact channels hole becomes, it is simpler that the design of decoder can become.Figure 12 C has represented the third domain, and its contact channels hole also is divided into two groups: C group 460a and 460c; D group 460b and 460d.The contact channels hole of C group and D group is placed on the two ends of word line, so the design of addressing device becomes simpler.

Figure 13 has represented the sectional drawing of a 3D-ROM memory.Here as an example with a 3D-MPROM structure.The technical process of making this memory comprises: at first form transistor on Semiconductor substrate 10.Those those skilled in the art will be appreciated that these transistors can be by the semiconductor process flow manufacturing of standard.These transistors provide the function of addressing/read.Be formed with generation dielectric insulating film 20 on the transistorized substrate 10.This dielectric insulating film 20 can be a silica, also can be some other more advanced medium systems.These more advanced medium systems can more successfully be filled the space.Dielectric insulating film 20 can use such as the method for CMP and come complanation.After this contact channels hole 101a and interlayer interface channel mouth 201a3 form by methods such as RIE.On the surface of this complanation, form a conductor, form first word line 101 by the figure conversion then, also formed a pedestal 201a2 simultaneously.Word line 101 can contain the metal of high conductivity, for example, and aluminium or copper.Another dielectric film 30 is formed on the word line 101 and is flattened.At this moment by the figure conversion digital information is transformed on the dielectric film 30, if will produce " 0 " logic and " 1 " logic respectively on address 123 and 121, the mask figure on 123 and 121 should be respectively opaque and transparent.Therefore after the exposure only the etchant resist on 121 just can be eliminated.Form access opening by RIE, and exposed a part of word line 101.And then form accurate conductive membrane 121 and bit line 111 and 112.After this, another dielectric film 40 forms on bit line 111 and 112, and it can enough method complanations such as CMP, and provides a smooth basis for second accumulation layer 200.

Second accumulation layer 200 can form with similar method, comes interface channel mouth 201a1 between cambium layer but need to increase a step.201a1 provides word line 201 on the accumulation layer 200 and the connection between the pedestal 201a2 on the accumulation layer 100.Therefore, second accumulation layer 200 produces by contact channels hole 201a and substrate 10 and is electrically connected.After second accumulation layer generates, continue to use the smooth wafer surface of CMP polishing technology.Repeat above step, just produce a multilayer 3D-ROM.

Above description is to carry out as an example with the storage element among Fig. 6 A and Fig. 6 B, and those skilled in the art should understand above processing step and structure equally also can be used the storage element among Fig. 6 C~6E.

Figure 14 has represented the sectional drawing of another kind of 3D-ROM memory.With a 3D-MPROM as an example, as can see from Figure 2, X, Y addressing device will occupy certain area.Correspondingly, the distance between the contact point 131 and 231 must surpass certain value.In order to keep the memory capacity of 3D-ROM, can between substrate 10 and first accumulation layer 100, increase at least one wiring layer 109b.This wiring layer 109b removes the contact point on the accumulation layer 100 131 from the contact point 231 of accumulation layer 200.Therefore can save more chip area.Correspondingly, memory capacity also can increase.

Figure 15 A~15B has represented the sectional drawing of another kind of 3D-ROM memory.Here, by the address selection line on the different layers is cascaded, can reduce the contact point number between addressing line and the substrate 10.When the contact point decreased number, the complexity of addressing device also correspondingly reduces.Correspondingly, the manufacturability of 3D-ROM has also improved.The method of employing in Figure 13 and Figure 14, the 3D-ROM of a l * m * n has the individual contact point of l * (m+n).But the memory of a l * m * n, its minimum contact point number can be 2 × l × m × n , For example, one 4 * 3 * 3 3D-ROM can be only with 6 word line contact points and 6 bit line contact points.

Figure 15 A has represented the sectional drawing of this 3D-ROM memory perpendicular to bit line 482a~482d.Four accumulation layer 500a~500d are arranged in this 3D-ROM.Word line 480a~480d is divided into two groups: A group 480a and 480b; B group 480c and 480d.Word line in every group is cascaded, and uses a contact channels hole to substrate 10 jointly.For example, link together by metal closures 490b between word line 480b and the 480a, be connected with substrate 10 by contact channels hole 490a then.Similarly, word line 480d and 480c link together by metal closures 490d, are connected with substrate 10 by contact channels hole 490c then.Figure 15 B has represented the sectional drawing of this 3D-ROM memory perpendicular to word line 480a~480d.Bit line 482a~482d is divided into two groups: C group 482a and 482c; D group 482b and 482d.Bit line in every group is cascaded, and uses a contact channels hole to substrate 10 jointly.For example, link together by metal closures 492c between bit line 482c and the 482a, be connected with substrate 10 by contact channels hole 492a then.Similarly, bit line 482d and 482b link together by metal closures 492d, are connected with substrate 10 by contact channels hole 492b then.Generally speaking, make the contact point number of bit line and word line and substrate 10 is reduced by half.

Figure 13~15B is the structure that example has been described 3D-MPROM with 3D-MPROM.These structures also are suitable for concerning 3D-EPROM.Unique difference is for all storage elements of 3D-EPROM, all will etch window and form the EPROM film; This EPROM film contains accurate conductive membrane and anti-fuse film, rather than contains accurate conductive membrane as 3D-MPROM.In addition, all manufacturing technology steps are all applicable.

Because the 3D-ROM memory has great memory capacity, so can be applied in a lot of fields.For example, nowadays computer uses its most of hard drive space to come storing software, and these softwares seldom are changed, and therefore a lot of hard disk resources have been wasted.Use CD-ROM can partly relax this problem, but the time for reading of CD-ROM is very long.The 3D-ROM memory has big memory capacity and very fast time for reading, is the device of a desirable storing software therefore.A computer that uses 3D-ROM to come storing software can relax the requirement to hard-disk capacity.When the 3D-ROM memory is used as the memory element of computer software, can use independent 3D-ROM storage chip also can be integrated in 3D-ROM on the central processing unit (CPU).The application of another 3D-ROM memory is sensitive card, also is called safety card.Sensitive card can be stored a large amount of personal information, and can replace identity card in the near future, phonecard, credit card or the like.Some informational needs forever keeps in the sensitivity card, and other informational needs are replaced at any time, therefore can be MPROM of the present invention, EPROM and some other nonvolatile memory, for example, E 2PROM is integrated on the single 3D-ROM chip, and uses it to block as sensitivity.For example, E 2PROM and addressing device of the present invention can be created on the Semiconductor substrate, then, can generate MPROM of the present invention and EPROM on them.Because the MPROM of the present invention and EPROM cost is low, integrated level is high is E 2The sensitivity that PROM, MPROM and EPROM integrate with three dimensional form is stuck in the market that can find them in the near future.

Though above specification has specifically described examples more of the present invention, those skilled in the art should understand, under prerequisite not away from the spirit and scope of the present invention, can change form of the present invention and details, for example, in the above specification to the description of each embodiment based on positive logic, be familiar with this professional those of ordinary skill and all know, if " 0 " logic and " 1 " logic are exchanged, the present invention also can be used for negative logic.Therefore, except the spirit according to additional claims, the present invention should not be subjected to any restriction.

Claims (26)

1. a 3 D ROM comprises that one contains transistorized Semiconductor substrate, it is characterized in that comprising:
At least two read-only accumulation layers that are stacked on the described substrate, wherein, each read-only accumulation layer comprises a plurality of read-only storage elements and a plurality of address selection line; And
A plurality ofly be formed between described read-only accumulation layer and the Semiconductor substrate, be used to provide the interlayer interface channel mouth and/or the contact channels hole that connect between described read-only accumulation layer and the described Semiconductor substrate.
2. 3 D ROM according to claim 1 is characterized in that also having: an interlayer dielectric film, this interlayer dielectric in described read-only accumulation layer to the small part first read-only accumulation layer with between the small part second read-only accumulation layer.
3. 3 D ROM according to claim 1, its feature also is: the described first read-only accumulation layer contains first address selection line, the second read-only accumulation layer contains second address selection line, and first address selection line and second address selection line interconnect.
4. according to the described 3 D ROM of claim 1-3, it is characterized in that also having: the address decoder of described read-only accumulation layer wherein, is made of the transistor that is positioned on the described Semiconductor substrate of part to the described address decoder of small part.
5. 3 D ROM according to claim 4 is characterized in that also having: a wiring layer, this wiring layer make the below that can be positioned at least one read-only accumulation layer to the described address decoder of small part.
6. according to the described 3 D ROM of claim 1-3, it is characterized in that also having: at least one described read-only accumulation layer contains a plurality of first kind address selection line and a plurality of second class address selection lines of arranging and being parallel to each other along second direction of arranging and being parallel to each other along first direction, described first kind address selection line is connected with described Semiconductor substrate by the contact channels hole, and described contact channels hole is dropped on two straight lines in the projection on this Semiconductor substrate at least.
7. according to the described 3 D ROM of claim 1-3, its feature also is: the circuit on this Semiconductor substrate contains conventional memory and/or conventional processors.
8. according to the described 3 D ROM of claim 1-3, it is characterized in that: described read-only storage element contains first electrode, the accurate conductive membrane of second electrode and between this two electrode, and is wherein, less at the resistance of reading described accurate conductive membrane under the voltage; When the voltage on the described read-only storage element when reading voltage, its resistance is bigger.
9. 3 D ROM according to claim 8, its feature also is: described first electrode, second electrode all contain metal material.
10. 3 D ROM according to claim 8, its feature also is: described accurate conductive membrane contains semi-conducting material.
11. 3 D ROM according to claim 8, its feature also is: when the direction of the voltage on the described read-only storage element was opposite with the direction of reading voltage, the resistance of described accurate conductive membrane was bigger.
12. 3 D ROM according to claim 11, its feature also is: described accurate conductive membrane contains first semiconductor film and second semiconductor film, and wherein, first semiconductor film and second semiconductor film are counter-dopings.
13. 3 D ROM according to claim 8, its feature also is: described accurate conductive membrane has the on-monocrystalline structure.
14. 3 D ROM according to claim 8 is characterized in that: described read-only storage element has an anti-fuse film between described first electrode and described second electrode.
15. 3 D ROM according to claim 14 is characterized in that also having: a buffer film between described anti-fuse film and accurate conductive membrane.
16. a 3 D ROM comprises that one contains transistorized Semiconductor substrate, it is characterized in that comprising:
One dielectric insulating film, this dielectric insulating film cover to this Semiconductor substrate of small part and are complanations;
At least one is stacked in the read-only accumulation layer on the described dielectric insulating film, and described read-only accumulation layer comprises a plurality of read-only storage elements and a plurality of address selection line; And
A plurality ofly be formed between described read-only accumulation layer and the Semiconductor substrate, be used to provide the interlayer interface channel mouth and/or the contact channels hole that connect between described read-only accumulation layer and the described Semiconductor substrate.
17. 3 D ROM according to claim 16 is characterized in that also having: the address decoder of described read-only accumulation layer wherein, is made of the transistor that is positioned on the described Semiconductor substrate of part to the described address decoder of small part.
18. 3 D ROM according to claim 17 is characterized in that also having: a wiring layer, this wiring layer make the below that can be positioned at least one read-only accumulation layer to the described address decoder of small part.
19. 3 D ROM according to claim 16, it is characterized in that also having: at least one described read-only accumulation layer contains a plurality of first kind address selection line and a plurality of second class address selection lines of arranging and being parallel to each other along second direction of arranging and being parallel to each other along first direction, described first kind address selection line is connected with described Semiconductor substrate by the contact channels hole, and described contact channels hole is dropped on two straight lines in the projection on this Semiconductor substrate at least.
20. 3 D ROM according to claim 16, its feature also is: the circuit on this Semiconductor substrate contains conventional memory and/or conventional processors.
21. according to the described 3 D ROM of claim 16-20, it is characterized in that: described read-only storage element contains first electrode, the accurate conductive membrane of second electrode and between this two electrode, wherein, less at the resistance of reading described accurate conductive membrane under the voltage; When the voltage on the storage element when reading voltage, its resistance is bigger.
22. 3 D ROM according to claim 21, its feature also is: described first electrode, second electrode all contain metal material.
23. 3 D ROM according to claim 21, its feature also is: when the direction of the voltage on the described read-only storage element was opposite with the direction of reading voltage, the resistance of described accurate conductive membrane was bigger.
24. 3 D ROM according to claim 21 is characterized in that: described read-only storage element also has an anti-fuse film between described first electrode and described second electrode.
25. the manufacture method of a 3 D ROM comprises the following steps:
1) on semi-conductive substrate, forms transistor circuit;
2) form dielectric insulating film being formed with on the transistorized Semiconductor substrate;
3) on above-mentioned dielectric insulating film, form contact channels hole and/or interlayer interface channel mouth;
4) on the above-mentioned dielectric insulating film that is formed with contact channels hole and interlayer interface channel mouth, form the first read-only accumulation layer;
5) forming one on the first read-only accumulation layer covers to the interlayer dielectric of the small part first read-only accumulation layer;
Repeating step 3)-5) to form a plurality of read-only accumulation layers.
At least one during 26. the manufacture method of a kind of 3 D ROM according to claim 25 also comprises the following steps:
2 ') in step 2) after with the dielectric insulating film complanation;
5 ') after step 5) with the interlayer dielectric complanation.
CN 98119572 1998-09-24 1998-09-24 Three-dimensional read-only memory CN1099695C (en)

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